Project import generated by Copybara. GitOrigin-RevId: ceda9993b5e33a3605cf30ca3862478abb29e23f
diff --git a/Kconfig b/Kconfig index 9278e59..2cc272b 100644 --- a/Kconfig +++ b/Kconfig
@@ -70,11 +70,11 @@ bool "Select defaults suitable for booting general purpose Linux distributions" select AUTO_COMPLETE select CMDLINE_EDITING - select CMD_BOOTI if ARM64 - select CMD_BOOTZ if ARM && !ARM64 + select CMD_BOOTI if ARM64 && !AML_DISABLE_DEV_CMDS + select CMD_BOOTZ if ARM && !ARM64 && !AML_DISABLE_DEV_CMDS select CMD_DHCP if CMD_NET - select CMD_PING if CMD_NET select CMD_ENV_EXISTS + select CMD_EXT2 select CMD_EXT4 select CMD_FAT select CMD_FS_GENERIC @@ -275,20 +275,10 @@ SHA256 variant is supported: SHA512 and others are not currently supported in U-Boot. -config FIT_FULL_CHECK - bool "Do a full check of the FIT before using it" - default y - help - Enable this do a full check of the FIT to make sure it is valid. This - helps to protect against carefully crafted FITs which take advantage - of bugs or omissions in the code. This includes a bad structure, - multiple root nodes and the like. - config FIT_SIGNATURE bool "Enable signature verification of FIT uImages" depends on DM select HASH - select FIT_FULL_CHECK select RSA help This option enables signature verification of FIT uImages, @@ -365,21 +355,11 @@ help Support printing the content of the fitImage in a verbose manner in SPL. -config SPL_FIT_FULL_CHECK - bool "Do a full check of the FIT before using it" - help - Enable this do a full check of the FIT to make sure it is valid. This - helps to protect against carefully crafted FITs which take advantage - of bugs or omissions in the code. This includes a bad structure, - multiple root nodes and the like. - - config SPL_FIT_SIGNATURE bool "Enable signature verification of FIT firmware within SPL" depends on SPL_DM select SPL_FIT select SPL_RSA - select SPL_FIT_FULL_CHECK config SPL_LOAD_FIT bool "Enable SPL loading U-Boot as a FIT" @@ -541,4 +521,3 @@ source "lib/Kconfig" source "test/Kconfig" -
diff --git a/Makefile b/Makefile index 6dbe24c..6087d06 100644 --- a/Makefile +++ b/Makefile
@@ -42,16 +42,6 @@ # descending is started. They are now explicitly listed as the # prepare rule. -# We use U_BOOT_DATE and U_BOOT_TIME to record u-boot build timestamp. -# make T=0 or by default to use local time (date) as build timestamp. -# make T=1 to use latest git commit time as build timestamp. -ifeq ("$(origin T)", "command line") - KBUILD_TIME_STAMP = $(T) -endif -ifndef KBUILD_TIME_STAMP - KBUILD_TIME_STAMP = 0 -endif - # Beautify output # --------------------------------------------------------------------------- # @@ -131,6 +121,8 @@ # Do we want to locate output files in a separate directory? ifeq ("$(origin O)", "command line") KBUILD_OUTPUT := $(O) +else + KBUILD_OUTPUT := build endif # That's our default target when none is given on the command line @@ -228,7 +220,7 @@ buildsrc := $(abspath $(srctree)) buildtree := $(abspath $(CURDIR)/$(KBUILD_OUTPUT)) -export srctree objtree VPATH buildsrc buildtree +export srctree objtree VPATH buildsrc buildtree KBUILD_OUTPUT # Make sure CDPATH settings don't interfere unexport CDPATH @@ -257,6 +249,9 @@ CROSS_COMPILE ?= endif +CROSS_COMPILE ?=/opt/gcc-linaro-7.3.1-2018.05-i686_aarch64-elf/bin/aarch64-elf- +export CROSS_COMPILE + KCONFIG_CONFIG ?= .config export KCONFIG_CONFIG @@ -345,7 +340,6 @@ export KBUILD_MODULES KBUILD_BUILTIN export KBUILD_CHECKSRC KBUILD_SRC KBUILD_EXTMOD -export BL33_DEBUG # We need some generic definitions (do not try to remake the file). scripts/Kbuild.include: ; @@ -383,14 +377,11 @@ KBUILD_CPPFLAGS := -D__KERNEL__ -D__UBOOT__ -KBUILD_CFLAGS := -Wall -Wstrict-prototypes \ +KBUILD_CFLAGS := -Wall -Wstrict-prototypes -Werror \ -Wno-format-security \ -fno-builtin -ffreestanding $(CSTD_FLAG) KBUILD_CFLAGS += -fshort-wchar -fno-strict-aliasing KBUILD_AFLAGS := -D__ASSEMBLY__ -ifeq ($(BL33_DEBUG), 1) - KBUILD_CFLAGS+=-DBL33_DEBUG_PRINT -endif # Don't generate position independent code KBUILD_CFLAGS += $(call cc-option,-fno-PIE) @@ -400,7 +391,9 @@ UBOOTRELEASE = $(shell cat include/config/uboot.release 2> /dev/null) UBOOTVERSION = $(VERSION)$(if $(PATCHLEVEL),.$(PATCHLEVEL)$(if $(SUBLEVEL),.$(SUBLEVEL)))$(EXTRAVERSION) -export VERSION PATCHLEVEL SUBLEVEL UBOOTRELEASE UBOOTVERSION +ACSRELEASE = $(shell cat include/config/acs.release 2> /dev/null) + +export VERSION PATCHLEVEL SUBLEVEL UBOOTRELEASE UBOOTVERSION ACSRELEASE export ARCH CPU BOARD VENDOR SOC CPUDIR BOARDDIR export CONFIG_SHELL HOSTCC HOSTCFLAGS HOSTLDFLAGS CROSS_COMPILE AS LD CC export CPP AR NM LDR STRIP OBJCOPY OBJDUMP @@ -431,6 +424,13 @@ scripts_basic: $(Q)$(MAKE) $(build)=scripts/basic $(Q)rm -f .tmp_quiet_recordmcount + $(Q)if [ -d $(srctree)/.git/hooks ]; then \ + if [ ! -f $(srctree)/.git/hooks/pre-commit-old -a -f $(srctree)/.git/hooks/pre-commit ]; then \ + cp $(srctree)/.git/hooks/pre-commit $(srctree)/.git/hooks/pre-commit-old; \ + fi; \ + cp $(srctree)/scripts/amlogic/coding_style/pre-commit $(srctree)/.git/hooks/; \ + chmod +x $(srctree)/.git/hooks/pre-commit; \ + fi # To avoid any implicit rule to kick in, define an empty command. scripts/basic/%: scripts_basic ; @@ -457,7 +457,6 @@ version_h := include/generated/version_autogenerated.h timestamp_h := include/generated/timestamp_autogenerated.h defaultenv_h := include/generated/defaultenv_autogenerated.h -timestamp_git_h := include/generated/timestamp_autogenerated.h no-dot-config-targets := clean clobber mrproper distclean \ help %docs check% coccicheck \ @@ -482,10 +481,6 @@ endif endif -ifneq ($(ENABLE_UBOOT_UPDATE),1) - KBUILD_CFLAGS += -DAML_DISABLE_UPDATE_MODE -endif - ifeq ($(mixed-targets),1) # =========================================================================== # We're called with mixed targets (*config and build targets). @@ -630,7 +625,8 @@ KBUILD_CFLAGS += -O2 endif -KBUILD_CFLAGS += $(call cc-option,-fno-stack-protector) +STACK_CFLAGS := $(call cc-option,-fstack-protector-strong) +KBUILD_CFLAGS += $(STACK_CFLAGS) KBUILD_CFLAGS += $(call cc-option,-fno-delete-null-pointer-checks) # change __FILE__ to the relative path from the srctree @@ -676,10 +672,6 @@ KBUILD_AFLAGS += $(KAFLAGS) KBUILD_CFLAGS += $(KCFLAGS) -ifdef BOARD_NAME -KBUILD_CFLAGS += -DBOARD_NAME='"$(BOARD_NAME)"' -endif - # Use UBOOTINCLUDE when you must reference the include/ directory. # Needed to be compatible with the O= option UBOOTINCLUDE := \ @@ -767,7 +759,6 @@ u-boot-init := $(head-y) u-boot-main := $(libs-y) - # Add GCC lib ifeq ($(CONFIG_USE_PRIVATE_LIBGCC),y) PLATFORM_LIBGCC = arch/$(ARCH)/lib/lib.a @@ -1566,10 +1557,17 @@ echo "$(UBOOTVERSION)$$($(CONFIG_SHELL) $(srctree)/scripts/setlocalversion $(srctree))" endef +define filechk_acs.release + echo "$(BOARD)$$($(CONFIG_SHELL) $(srctree)/scripts/setlocalversion $(srctree))" +endef + # Store (new) UBOOTRELEASE string in include/config/uboot.release include/config/uboot.release: include/config/auto.conf FORCE $(call filechk,uboot.release) +include/config/acs.release: include/config/auto.conf FORCE + $(call filechk,acs.release) + # Things we need to do before we recursively start building the kernel # or the modules are listed in "prepare". @@ -1583,7 +1581,7 @@ # prepare3 is used to check if we are building in a separate output directory, # and if so do: # 1) Check that make has not been executed in the kernel src $(srctree) -prepare3: include/config/uboot.release +prepare3: include/config/uboot.release include/config/acs.release ifneq ($(KBUILD_SRC),) @$(kecho) ' Using $(srctree) as source for U-Boot' $(Q)if [ -f $(srctree)/.config -o -d $(srctree)/include/config ]; then \ @@ -1620,9 +1618,11 @@ define filechk_version.h (echo \#define PLAIN_VERSION \"$(UBOOTRELEASE)\"; \ + echo \#define ACS_VERSION \"$(ACSRELEASE)\"; \ echo \#define U_BOOT_VERSION \"U-Boot \" PLAIN_VERSION; \ echo \#define CONFIG_SYSTEM_AS_ROOT \"${SYSTEMMODE}\"; \ echo \#define CONFIG_AVB2 \"${AVBMODE}\"; \ + echo \#define CONFIG_CMD_BOOTCTOL_VAB \"${BOOTCTRLMODE}\"; \ echo \#define CC_VERSION_STRING \"$$(LC_ALL=C $(CC) --version | head -n 1)\"; \ echo \#define LD_VERSION_STRING \"$$(LC_ALL=C $(LD) --version | head -n 1)\"; ) endef @@ -1644,6 +1644,7 @@ LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_TZ "%z"'; \ LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_DMI_DATE "%m/%d/%Y"'; \ LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_BUILD_DATE 0x%Y%m%d'; \ + LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_DATE_TIME "%y%m%d.%H%M%S"'; \ else \ return 42; \ fi; \ @@ -1653,6 +1654,7 @@ LC_ALL=C date +'#define U_BOOT_TZ "%z"'; \ LC_ALL=C date +'#define U_BOOT_DMI_DATE "%m/%d/%Y"'; \ LC_ALL=C date +'#define U_BOOT_BUILD_DATE 0x%Y%m%d'; \ + LC_ALL=C date +'#define U_BOOT_DATE_TIME "%y%m%d.%H%M%S"'; \ fi) endef @@ -1664,28 +1666,11 @@ xxd -i ; echo ", 0x00" ; ) endef -define filechk_timestamp_git.h - (echo \#define U_BOOT_DATE \"$(shell git log -1 --format=%cd --date=format:"%b %d %C%y")\"; \ - echo \#define U_BOOT_TIME \"$(shell git log -1 --format=%cd --date=format:"%T")\"; \ - echo \#define U_BOOT_TZ \"$(shell git log -1 --format=%cd --date=format:"%Z")\"; \ - echo \#define U_BOOT_DMI_DATE \"$(shell git log -1 --format=%cd --date=format:"%m/%d/%Y")\"; \ - echo \#define U_BOOT_BUILD_DATE \"$(shell git log -1 --format=%cd --date=format:"0x%Y%m%d")\";) -endef - -export U_BOOT_TIME_GIT=$(shell git log -1 --format=%cd --date=format:"%T") -export U_BOOT_DATE_GIT=$(shell git log -1 --format=%cd --date=format:"%b %d %C%y") - -$(version_h): include/config/uboot.release FORCE +$(version_h): include/config/uboot.release include/config/acs.release FORCE $(call filechk,version.h) - -ifeq ($(KBUILD_TIME_STAMP),0) $(timestamp_h): $(srctree)/Makefile FORCE $(call filechk,timestamp.h) -else -$(timestamp_git_h): $(srctree)/Makefile FORCE - $(call filechk,timestamp_git.h) -endif $(defaultenv_h): $(CONFIG_DEFAULT_ENV_FILE:"%"=%) FORCE $(call filechk,defaultenv.h) @@ -1791,13 +1776,13 @@ $(filter-out include, $(shell ls -1 $d 2>/dev/null)))) CLEAN_FILES += include/bmp_logo.h include/bmp_logo_data.h \ - u-boot.* MLO* SPL System.map fit-dtb.blob + boot* u-boot* MLO* SPL System.map fit-dtb.blob # Directories & files removed with 'make mrproper' MRPROPER_DIRS += include/config include/generated spl tpl \ .tmp_objdiff MRPROPER_FILES += .config .config.old include/autoconf.mk* include/config.h \ - ctags etags tags + ctags etags tags TAGS cscope* GPATH GTAGS GRTAGS GSYMS # clean - Delete most, but leave enough to build external modules # @@ -1853,6 +1838,7 @@ -o -name '*.pyc' \) \ -type f -print | xargs rm -f @rm -f boards.cfg + @rm -rf $(srctree)/build backup: F=`basename $(srctree)` ; cd .. ; \ @@ -1906,8 +1892,6 @@ @echo ' 2: warnings which occur quite often but may still be relevant' @echo ' 3: more obscure warnings, can most likely be ignored' @echo ' Multiple levels can be combined with W=12 or W=123' - @echo ' make T=0 [targets] 0 => use local time (date) as build timestamp' - @echo ' make T=1 [targets] 1 => use latest git commit time as build timestamp' @echo '' @echo 'Execute "make" or "make all" to build all targets marked with [*] ' @echo 'For further info see the ./README file'
diff --git a/api/Kconfig b/api/Kconfig index e418adc..16731d3 100644 --- a/api/Kconfig +++ b/api/Kconfig
@@ -7,4 +7,3 @@ This option enables the U-Boot API. See api/README for more information. endmenu -
diff --git a/arch/Kconfig b/arch/Kconfig index 11e7713..35e2712 100644 --- a/arch/Kconfig +++ b/arch/Kconfig
@@ -237,4 +237,3 @@ source "arch/x86/Kconfig" source "arch/xtensa/Kconfig" source "arch/riscv/Kconfig" -
diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig index 38b6ffe..fa6b344 100644 --- a/arch/arc/Kconfig +++ b/arch/arc/Kconfig
@@ -171,4 +171,3 @@ source "board/synopsys/iot_devkit/Kconfig" endmenu -
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/Kconfig b/arch/arm/cpu/arm926ejs/lpc32xx/Kconfig index 1db1262..986ad73 100644 --- a/arch/arm/cpu/arm926ejs/lpc32xx/Kconfig +++ b/arch/arm/cpu/arm926ejs/lpc32xx/Kconfig
@@ -18,4 +18,3 @@ source "board/work-microwave/work_92105/Kconfig" endif -
diff --git a/arch/arm/cpu/armv7/Kconfig b/arch/arm/cpu/armv7/Kconfig index 4d0dcee..73d57a2 100644 --- a/arch/arm/cpu/armv7/Kconfig +++ b/arch/arm/cpu/armv7/Kconfig
@@ -59,4 +59,3 @@ required if U-Boot runs in HYP mode. endif -
diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index 4ffde9a..5d6a711 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -107,4 +107,3 @@ bool endmenu -
diff --git a/arch/arm/cpu/armv7/vf610/Kconfig b/arch/arm/cpu/armv7/vf610/Kconfig index 764d1fb..13905b5 100644 --- a/arch/arm/cpu/armv7/vf610/Kconfig +++ b/arch/arm/cpu/armv7/vf610/Kconfig
@@ -34,4 +34,3 @@ source "board/toradex/colibri_vf/Kconfig" endif -
diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig index d5a9158..1c12bbd 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig
@@ -95,7 +95,7 @@ config PSCI_RESET bool "Use PSCI for reset and shutdown" - default n + default y select ARM_SMCCC if OF_CONTROL depends on !ARCH_EXYNOS7 && !ARCH_BCM283X && \ !TARGET_LS2080A_SIMU && !TARGET_LS2080AQDS && \ @@ -166,4 +166,3 @@ endif endif -
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index b55b36c..2b086da 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -571,4 +571,3 @@ help Enabling this will make a U-Boot binary that is capable of being booted via TFA. -
diff --git a/arch/arm/cpu/armv8/sec_firmware.c b/arch/arm/cpu/armv8/sec_firmware.c index 3c52495..8dc0ac9 100644 --- a/arch/arm/cpu/armv8/sec_firmware.c +++ b/arch/arm/cpu/armv8/sec_firmware.c
@@ -310,7 +310,7 @@ return false; } - if (fit_check_format(sec_firmware_img, IMAGE_SIZE_INVAL)) { + if (!fit_check_format(sec_firmware_img)) { printf("SEC Firmware: Bad firmware image (bad FIT header)\n"); return false; }
diff --git a/arch/arm/cpu/armv8/zynqmp/Kconfig b/arch/arm/cpu/armv8/zynqmp/Kconfig index 91b017a..8a311e1 100644 --- a/arch/arm/cpu/armv8/zynqmp/Kconfig +++ b/arch/arm/cpu/armv8/zynqmp/Kconfig
@@ -154,4 +154,3 @@ endchoice endif -
diff --git a/arch/arm/dts/elaine-b1-panel.dtsi b/arch/arm/dts/elaine-b1-panel.dtsi deleted file mode 100755 index 5d6b445..0000000 --- a/arch/arm/dts/elaine-b1-panel.dtsi +++ /dev/null
@@ -1,973 +0,0 @@ -/* - * arch/arm/dts/elaine-b1-panel.dtsi - * - * Copyright (C) 2016 Amlogic, Inc. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - */ - -/ { - lcd{ - compatible = "amlogic, lcd-sm1"; - mode = "tablet"; - status = "okay"; - key_valid = <0>; - clocks = <&clkc CLKID_MIPI_DSI_HOST - &clkc CLKID_MIPI_DSI_PHY - &clkc CLKID_DSI_MEAS_COMP - &clkc CLKID_VCLK2_ENCL - &clkc CLKID_VCLK2_VENCL - &clkc CLKID_GP0_PLL>; - clock-names = "dsi_host_gate", - "dsi_phy_gate", - "dsi_meas", - "encl_top_gate", - "encl_int_gate", - "gp0_pll"; - reg = <0x0 0xffd07000 0x0 0x400 /* dsi_host */ - 0x0 0xff644000 0x0 0x200>; /* dsi_phy */ - interrupts = <0 3 1 - 0 56 1>; - interrupt-names = "vsync","vsync2"; - pinctrl_version = <2>; /* for uboot */ - - /* power type: - * (0=cpu_gpio, 1=pmu_gpio, 2=signal,3=extern, 0xff=ending) - * power index: - * (point gpios_index, or extern_index,0xff=invalid) - * power value:(0=output low, 1=output high, 2=input) - * power delay:(unit in ms) - */ - lcd_cpu-gpios = <&gpio GPIOZ_13 GPIO_ACTIVE_HIGH>; - lcd_cpu_gpio_names = "GPIOZ_13"; - - boe_fiti9364_7{ - model_name = "TV070WSM_FT9364"; - interface = "mipi"; - basic_setting = <600 1024 /*h_active, v_active*/ - 700 1053 /*h_period, v_period*/ - 8 /*lcd_bits*/ - 95 163>; /*screen_widht, screen_height*/ - lcd_timing = <24 36 0 /*hs_width,hs_bp,hs_pol*/ - 2 8 0>; /*vs_width,vs_bp,vs_pol*/ - clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/ - 0 /*clk_ss_level*/ - 1 /*clk_auto_generate*/ - 44226000>; /*pixel_clk(unit in Hz)*/ - mipi_attr = <4 /*lane_num*/ - 400 /*bit_rate_max(MHz)*/ - 0 /*factor(*100, default 0 for auto)*/ - 1 /*operation_mode_init(0=video, 1=command)*/ - 0 /*operation_mode_display(0=video, 1=command)*/ - 2 /* - *video_mode_type - *(0=sync_pulse,1=sync_event,2=burst) - */ - 0 /*clk_always_hs(0=disable,1=enable)*/ - 0>; /*phy_switch(0=auto,1=standard,2=slow)*/ - /* dsi_init: data_type, num, data... */ - dsi_init_on = < - 0xff 10 - 0xf0 3 0 1 30 /* reset high, delay 30ms */ - 0xf0 3 0 0 10 /* reset low, delay 10ms */ - 0xf0 3 0 1 30 /* reset high, delay 30ms */ - 0xfc 2 0x04 3 /* check_reg, check_cnt */ - 0xff 0xff>; /* ending flag */ - dsi_init_off = < - 0xff 5 /* delay 5ms */ - 0xff 0xff>; /* ending flag */ - /* extern_init: 0xff for invalid */ - extern_init = <1>; - /* power step: type,index,value,delay(ms) */ - power_on_step = < - 0 1 0 200 - 2 0 0 0 - 0xff 0 0 0>; - power_off_step = < - 2 0 0 5 /* delay 5ms after mipi off */ - 0 0 0 20 /* reset low */ - 0 1 1 100 /* panel power off */ - 0xff 0 0 0>; - backlight_index = <0>; - }; - - inx_fiti9364_7{ - model_name = "P070ACB_FT9364"; - interface = "mipi"; - basic_setting = <600 1024 /*h_active, v_active*/ - 770 1070 /*h_period, v_period*/ - 8 /*lcd_bits*/ - 3 5>; /*screen_widht, screen_height*/ - lcd_timing = <10 80 0 /*hs_width,hs_bp,hs_pol*/ - 6 20 0>; /*vs_width,vs_bp,vs_pol*/ - clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/ - 0 /*clk_ss_level*/ - 1 /*clk_auto_generate*/ - 49434000>; /*pixel_clk(unit in Hz)*/ - mipi_attr = <4 /*lane_num*/ - 400 /*bit_rate_max(MHz)*/ - 0 /*factor(*100, default 0 for auto)*/ - 1 /*operation_mode_init(0=video, 1=command)*/ - 0 /*operation_mode_display(0=video, 1=command)*/ - 2 /* - *video_mode_type - *(0=sync_pulse,1=sync_event,2=burst) - */ - 0 /*clk_always_hs(0=disable,1=enable)*/ - 0>; /*phy_switch(0=auto,1=standard,2=slow)*/ - /* dsi_init: data_type, num, data... */ - dsi_init_on = < - 0xff 10 - 0xf0 3 0 1 30 /* reset high, delay 30ms */ - 0xf0 3 0 0 10 /* reset low, delay 10ms */ - 0xf0 3 0 1 30 /* reset high, delay 30ms */ - 0xfc 2 0x04 3 /* check_reg, check_cnt */ - 0xff 0xff>; /* ending flag */ - dsi_init_off = < - 0xff 5 /* delay 5ms */ - 0xff 0xff>; /* ending flag */ - /* extern_init: 0xff for invalid */ - extern_init = <2>; - /* power step: type,index,value,delay(ms) */ - power_on_step = < - 0 1 0 200 /* panel power on */ - 2 0 0 0 - 0xff 0 0 0>; - power_off_step = < - 2 0 0 5 /* delay 5ms after mipi off */ - 0 0 0 20 /* reset low */ - 0 1 1 100 /* panel power off */ - 0xff 0 0 0>; - backlight_index = <0>; - }; - - kd_fiti9364_7{ - model_name = "KD070D82_FT9364"; - interface = "mipi"; - basic_setting = <600 1024 /*h_active, v_active*/ - 770 1070 /*h_period, v_period*/ - 8 /*lcd_bits*/ - 3 5>; /*screen_widht, screen_height*/ - lcd_timing = <10 80 0 /*hs_width,hs_bp,hs_pol*/ - 6 20 0>; /*vs_width,vs_bp,vs_pol*/ - clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/ - 0 /*clk_ss_level*/ - 1 /*clk_auto_generate*/ - 49434000>; /*pixel_clk(unit in Hz)*/ - mipi_attr = <4 /*lane_num*/ - 400 /*bit_rate_max(MHz)*/ - 0 /*factor(*100, default 0 for auto)*/ - 1 /*operation_mode_init(0=video, 1=command)*/ - 0 /*operation_mode_display(0=video, 1=command)*/ - 2 /* - *video_mode_type - *(0=sync_pulse,1=sync_event,2=burst) - */ - 0 /*clk_always_hs(0=disable,1=enable)*/ - 0>; /*phy_switch(0=auto,1=standard,2=slow)*/ - /* dsi_init: data_type, num, data... */ - dsi_init_on = < - 0xff 10 - 0xf0 3 0 1 30 /* reset high, delay 30ms */ - 0xf0 3 0 0 10 /* reset low, delay 10ms */ - 0xf0 3 0 1 30 /* reset high, delay 30ms */ - 0xfc 2 0x04 3 /* check_reg, check_cnt */ - 0xff 0xff>; /* ending flag */ - dsi_init_off = < - 0xff 5 /* delay 5ms */ - 0xff 0xff>; /* ending flag */ - /* extern_init: 0xff for invalid */ - extern_init = <3>; - /* power step: type,index,value,delay(ms) */ - power_on_step = < - 0 1 0 200 /* panel power on */ - 2 0 0 0 - 0xff 0 0 0>; - power_off_step = < - 2 0 0 5 /* delay 5ms after mipi off */ - 0 0 0 20 /* reset low */ - 0 1 1 100 /* panel power off */ - 0xff 0 0 0>; - backlight_index = <0>; - }; - - }; - - lcd_extern{ - compatible = "amlogic, lcd_extern"; - dev_name = "lcd_extern"; - status = "okay"; - key_valid = <0>; - - extern_1{ - index = <1>; - extern_name = "mipi_default"; // TV070WSM_FT9364 - status = "okay"; - type = <2>; /* 0=i2c, 1=spi, 2=mipi */ - cmd_size = <0xff>; - init_on = < - 0x23 2 0xE0 0x00 - 0x23 2 0xE1 0x93 - 0x23 2 0xE2 0x65 - 0x23 2 0xE3 0xF8 - 0x23 2 0xE0 0x01 - 0x23 2 0x00 0x00 - 0x23 2 0x01 0x90 - 0x23 2 0x03 0x00 - 0x23 2 0x04 0x90 - 0x23 2 0x17 0x00 - 0x23 2 0x18 0xB0 - 0x23 2 0x19 0x01 - 0x23 2 0x1A 0x00 - 0x23 2 0x1B 0xB0 - 0x23 2 0x1C 0x01 - 0x23 2 0x1F 0x3E - 0x23 2 0x20 0x2F - 0x23 2 0x21 0x2F - 0x23 2 0x22 0x0E - 0x23 2 0x37 0x69 - 0x23 2 0x38 0x05 - 0x23 2 0x39 0x00 - 0x23 2 0x3A 0x01 - 0x23 2 0x3C 0x90 - 0x23 2 0x3D 0xFF - 0x23 2 0x3E 0xFF - 0x23 2 0x3F 0xFF - 0x23 2 0x40 0x02 - 0x23 2 0x41 0x80 - 0x23 2 0x42 0x99 - 0x23 2 0x43 0x06 - 0x23 2 0x44 0x09 - 0x23 2 0x45 0x3C - 0x23 2 0x4B 0x04 - 0x23 2 0x55 0x0D - 0x23 2 0x56 0x01 - 0x23 2 0x57 0x89 - 0x23 2 0x58 0x0A - 0x23 2 0x59 0x0A - 0x23 2 0x5A 0x27 - 0x23 2 0x5B 0x15 - 0x23 2 0x5D 0x7C - 0x23 2 0x5E 0x67 - 0x23 2 0x5F 0x58 - 0x23 2 0x60 0x4C - 0x23 2 0x61 0x48 - 0x23 2 0x62 0x38 - 0x23 2 0x63 0x3C - 0x23 2 0x64 0x24 - 0x23 2 0x65 0x3B - 0x23 2 0x66 0x38 - 0x23 2 0x67 0x36 - 0x23 2 0x68 0x53 - 0x23 2 0x69 0x3F - 0x23 2 0x6A 0x44 - 0x23 2 0x6B 0x35 - 0x23 2 0x6C 0x2E - 0x23 2 0x6D 0x1F - 0x23 2 0x6E 0x0C - 0x23 2 0x6F 0x00 - 0x23 2 0x70 0x7C - 0x23 2 0x71 0x67 - 0x23 2 0x72 0x58 - 0x23 2 0x73 0x4C - 0x23 2 0x74 0x48 - 0x23 2 0x75 0x38 - 0x23 2 0x76 0x3C - 0x23 2 0x77 0x24 - 0x23 2 0x78 0x3B - 0x23 2 0x79 0x38 - 0x23 2 0x7A 0x36 - 0x23 2 0x7B 0x53 - 0x23 2 0x7C 0x3F - 0x23 2 0x7D 0x44 - 0x23 2 0x7E 0x35 - 0x23 2 0x7F 0x2E - 0x23 2 0x80 0x1F - 0x23 2 0x81 0x0C - 0x23 2 0x82 0x00 - 0x23 2 0xE0 0x02 - 0x23 2 0x00 0x45 - 0x23 2 0x01 0x45 - 0x23 2 0x02 0x47 - 0x23 2 0x03 0x47 - 0x23 2 0x04 0x41 - 0x23 2 0x05 0x41 - 0x23 2 0x06 0x1F - 0x23 2 0x07 0x1F - 0x23 2 0x08 0x1F - 0x23 2 0x09 0x1F - 0x23 2 0x0A 0x1F - 0x23 2 0x0B 0x1F - 0x23 2 0x0C 0x1F - 0x23 2 0x0D 0x1D - 0x23 2 0x0E 0x1D - 0x23 2 0x0F 0x1D - 0x23 2 0x10 0x1F - 0x23 2 0x11 0x1F - 0x23 2 0x12 0x1F - 0x23 2 0x13 0x1F - 0x23 2 0x14 0x1F - 0x23 2 0x15 0x1F - 0x23 2 0x16 0x44 - 0x23 2 0x17 0x44 - 0x23 2 0x18 0x46 - 0x23 2 0x19 0x46 - 0x23 2 0x1A 0x40 - 0x23 2 0x1B 0x40 - 0x23 2 0x1C 0x1F - 0x23 2 0x1D 0x1F - 0x23 2 0x1E 0x1F - 0x23 2 0x1F 0x1F - 0x23 2 0x20 0x1F - 0x23 2 0x21 0x1F - 0x23 2 0x22 0x1F - 0x23 2 0x23 0x1D - 0x23 2 0x24 0x1D - 0x23 2 0x25 0x1D - 0x23 2 0x26 0x1F - 0x23 2 0x27 0x1F - 0x23 2 0x28 0x1F - 0x23 2 0x29 0x1F - 0x23 2 0x2A 0x1F - 0x23 2 0x2B 0x1F - 0x23 2 0x58 0x40 - 0x23 2 0x59 0x00 - 0x23 2 0x5A 0x00 - 0x23 2 0x5B 0x10 - 0x23 2 0x5C 0x07 - 0x23 2 0x5D 0x20 - 0x23 2 0x5E 0x00 - 0x23 2 0x5F 0x00 - 0x23 2 0x61 0x00 - 0x23 2 0x62 0x00 - 0x23 2 0x63 0x7A - 0x23 2 0x64 0x7A - 0x23 2 0x65 0x00 - 0x23 2 0x66 0x00 - 0x23 2 0x67 0x32 - 0x23 2 0x68 0x08 - 0x23 2 0x69 0x7A - 0x23 2 0x6A 0x7A - 0x23 2 0x6B 0x00 - 0x23 2 0x6C 0x00 - 0x23 2 0x6D 0x00 - 0x23 2 0x6E 0x00 - 0x23 2 0x6F 0x89 - 0x23 2 0x70 0x00 - 0x23 2 0x71 0x00 - 0x23 2 0x72 0x06 - 0x23 2 0x73 0x7B - 0x23 2 0x74 0x00 - 0x23 2 0x75 0x07 - 0x23 2 0x76 0x00 - 0x23 2 0x77 0x5D - 0x23 2 0x78 0x17 - 0x23 2 0x79 0x1F - 0x23 2 0x7A 0x00 - 0x23 2 0x7B 0x00 - 0x23 2 0x7C 0x00 - 0x23 2 0x7D 0x03 - 0x23 2 0x7E 0x7B - 0x23 2 0xE0 0x03 - 0x23 2 0xAF 0x20 - 0x23 2 0xE0 0x04 - 0x23 2 0x09 0x11 - 0x23 2 0x0E 0x48 - 0x23 2 0x2B 0x2B - 0x23 2 0x2E 0x44 - 0x23 2 0x41 0xFF - 0x23 2 0xE0 0x00 - 0x23 2 0xE6 0x02 - 0x23 2 0xE7 0x0C - 0x23 2 0x51 0xFF - 0x23 2 0x53 0x2C - 0x23 2 0x55 0x00 - 0x05 1 0x11 - 0xFF 125 /* Delay 125ms */ - 0x05 1 0x29 - 0xFF 0xFF /* Ending Flag */ - >; - init_off = < - 0xff 5 - 0x05 1 0x28 /* display off */ - 0xff 60 /* delay 60ms */ - 0x05 1 0x10 /* sleep in */ - 0xff 110 /* delay 110ms */ - 0xff 0xff>; /* ending */ - }; - - extern_2{ - index = <2>; - extern_name = "mipi_default"; // P070ACB_FT9364 - status = "okay"; - type = <2>; /* 0=i2c, 1=spi, 2=mipi */ - cmd_size = <0xff>; - init_on = < - 0x23 2 0xE0 0x00 /* Page 0 */ - 0x23 2 0xE1 0x93 /* PASSWORD */ - 0x23 2 0xE2 0x65 - 0x23 2 0xE3 0xF8 - 0x23 2 0x80 0x03 /* DSI 4 lane */ - 0x23 2 0xE0 0x01 /* Page 01 */ - 0x23 2 0x0C 0x74 /* Set PWRIC */ - 0x23 2 0x17 0x00 /* Set Gamma Power */ - 0x23 2 0x18 0xEF /* VGMP=5.1V */ - 0x23 2 0x19 0x00 /* VGSP=0V */ - 0x23 2 0x1A 0x00 - 0x23 2 0x1B 0xEF /* VGMN=-5.1V */ - 0x23 2 0x1C 0x00 /* VGSN=0V */ - 0x23 2 0x1F 0x70 /* VGH_REG=16.2V */ - 0x23 2 0x20 0x2D /* VGL_REG=-12V */ - 0x23 2 0x21 0x2D /* VGL_REG2=-12V */ - 0x23 2 0x22 0x7E /* VGH_REG short to VGH VGL_REG short to VGL */ - 0x23 2 0x26 0xF3 /* VDDD from IOVCC/VCI */ - 0x23 2 0x37 0x09 /* SS=1 BGR=1 */ - 0x23 2 0x38 0x04 /* JDT=100 column inversion */ - 0x23 2 0x39 0x00 /* Source EQ Setting EQ1 */ - 0x23 2 0x3A 0x01 /* Source EQ Setting EQ2 */ - 0x23 2 0x3C 0x90 /* Source EQ Setting EQ3 */ - 0x23 2 0x3D 0xFF /* SET Source OP on time */ - 0x23 2 0x3E 0xFF /* SET Source OP off time */ - 0x23 2 0x3F 0xFF /* SET Source OP off time */ - 0x23 2 0x40 0x02 /* RSO=640 RGB */ - 0x23 2 0x41 0x80 /* LN=512->1024 line */ - 0x23 2 0x42 0x99 /* SLT internal line period */ - 0x23 2 0x43 0x14 /* VFP */ - 0x23 2 0x44 0x19 /* VBP */ - 0x23 2 0x45 0x5A /* HBP */ - 0x23 2 0x4B 0x04 - 0x23 2 0x55 0x02 /* DCDCM=0010 FP7721BX2 */ - 0x23 2 0x56 0x01 /* No auto Ratio function */ - 0x23 2 0x57 0x69 /* VGH_RT=3'b011 2*AVDD-AVEE VGL_RT=3'b010=AVEE+VCL-AVDD VCL_RT=2'b00 0.5*VCIP */ - 0x23 2 0x58 0x0A /* AVDD_S */ - 0x23 2 0x59 0x0A /* VCL = -2.5V */ - 0x23 2 0x5A 0x2E /* VGH = 16.2V */ - 0x23 2 0x5B 0x19 /* VGL = -12V */ - 0x23 2 0x5C 0x15 /* pump clk */ - 0x23 2 0x5D 0x71 /* V255 positive voltage from 4.888V to 4.888V */ - 0x23 2 0x5E 0x65 /* V251 positive voltage from 4.533V to 4.718V */ - 0x23 2 0x5F 0x55 /* V247 positive voltage from 4.349V to 4.491V */ - 0x23 2 0x60 0x49 /* V243 positive voltage from 4.179V to 4.321V */ - 0x23 2 0x61 0x46 /* V235 positive voltage from 3.910V to 4.052V */ - 0x23 2 0x62 0x38 /* V227 positive voltage from 3.726V to 3.853V */ - 0x23 2 0x63 0x3D /* V211 positive voltage from 3.428V to 3.528V */ - 0x23 2 0x64 0x29 /* V191 positive voltage from 3.159V to 3.244V */ - 0x23 2 0x65 0x43 /* V159 positive voltage from 2.805V to 2.876V */ - 0x23 2 0x66 0x42 /* V128 positive voltage from 2.522V to 2.578V */ - 0x23 2 0x67 0x44 /* V96 positive voltage from 2.267V to 2.323V */ - 0x23 2 0x68 0x63 /* V64 positive voltage from 1.941V to 2.026V */ - 0x23 2 0x69 0x53 /* V44 positive voltage from 1.686V to 1.799V */ - 0x23 2 0x6A 0x5B /* V28 positive voltage from 1.431V to 1.516V */ - 0x23 2 0x6B 0x4E /* V20 positive voltage from 1.275V to 1.322V */ - 0x23 2 0x6C 0x4C /* V12 positive voltage from 1.077V to 1.077V */ - 0x23 2 0x6D 0x41 /* V8 positive voltage from 0.949V to 0.921V */ - 0x23 2 0x6E 0x2D /* V4 positive voltage from 0.723V to 0.638V */ - 0x23 2 0x6F 0x23 /* V0 positive voltage from 0.496V to 0.496V */ - 0x23 2 0x70 0x71 /* V255 negative voltage from -4.888V to -4.888V */ - 0x23 2 0x71 0x4C /* V251 negative voltage from -4.179V to -4.363V */ - 0x23 2 0x72 0x3B /* V247 negative voltage from -3.995V to -4.123V */ - 0x23 2 0x73 0x30 /* V243 negative voltage from -3.825V to -3.967V */ - 0x23 2 0x74 0x2D /* V233 negative voltage from -3.556V to -3.698V */ - 0x23 2 0x75 0x1F /* V227 negative voltage from -3.372V to -3.499V */ - 0x23 2 0x76 0x25 /* V211 negative voltage from -3.088V to -3.188V */ - 0x23 2 0x77 0x10 /* V191 negative voltage from -2.805V to -2.890V */ - 0x23 2 0x78 0x2A /* V159 negative voltage from -2.451V to -2.522V */ - 0x23 2 0x79 0x2A /* V128 negative voltage from -2.182V to -2.238V */ - 0x23 2 0x7A 0x2B /* V96 negative voltage from -1.913V to -1.969V */ - 0x23 2 0x7B 0x4A /* V64 negative voltage from -1.587V to -1.672V */ - 0x23 2 0x7C 0x3A /* V44 negative voltage from -1.332V to -1.445V */ - 0x23 2 0x7D 0x43 /* V28 negative voltage from -1.091V to -1.176V */ - 0x23 2 0x7E 0x36 /* V20 negative voltage from -0.935V to -0.992V */ - 0x23 2 0x7F 0x33 /* V12 negative voltage from -0.723V to -0.723V */ - 0x23 2 0x80 0x28 /* V8 negative voltage from -0.595V to -0.567V */ - 0x23 2 0x81 0x14 /* V4 negative voltage from -0.368V to -0.283V */ - 0x23 2 0x82 0x0B /* V0 negative voltage from -0.156V to -0.156V */ - 0x23 2 0xE0 0x02 /* Page2 */ - 0x23 2 0x00 0x53 /* GIP_L Pin mapping RESET_EVEN */ - 0x23 2 0x01 0x55 /* VSSG_EVEN */ - 0x23 2 0x02 0x55 /* VSSA_EVEN */ - 0x23 2 0x03 0x51 /* STV2_EVEN */ - 0x23 2 0x04 0x77 /* VDD2_EVEN */ - 0x23 2 0x05 0x57 /* VDD1_EVEN */ - 0x23 2 0x06 0x1F /* VGL */ - 0x23 2 0x07 0x4F /* CK12 */ - 0x23 2 0x08 0x4D /* CK10 */ - 0x23 2 0x09 0x1F /* VGL */ - 0x23 2 0x0A 0x4B /* CK8 */ - 0x23 2 0x0B 0x49 /* CK6 */ - 0x23 2 0x0C 0x1F /* VGL */ - 0x23 2 0x0D 0x47 /* CK4 */ - 0x23 2 0x0E 0x45 /* CK2 */ - 0x23 2 0x0F 0x41 /* STV1_EVEN */ - 0x23 2 0x10 0x1F /* VGL */ - 0x23 2 0x11 0x1F /* VGL */ - 0x23 2 0x12 0x1F /* VGL */ - 0x23 2 0x13 0x55 /* VGG */ - 0x23 2 0x14 0x1F /* VGL */ - 0x23 2 0x15 0x1F /* VGL */ - 0x23 2 0x16 0x52 /* GIP_R Pin mapping RESET_ODD */ - 0x23 2 0x17 0x55 /* VSSG_ODD */ - 0x23 2 0x18 0x55 /* VSSA_ODD */ - 0x23 2 0x19 0x50 /* STV2_ODD */ - 0x23 2 0x1A 0x77 /* VDD2_ODD */ - 0x23 2 0x1B 0x57 /* VDD1_ODD */ - 0x23 2 0x1C 0x1F /* VGL */ - 0x23 2 0x1D 0x4E /* CK11 */ - 0x23 2 0x1E 0x4C /* CK9 */ - 0x23 2 0x1F 0x1F /* VGL */ - 0x23 2 0x20 0x4A /* CK7 */ - 0x23 2 0x21 0x48 /* CK5 */ - 0x23 2 0x22 0x1F /* VGL */ - 0x23 2 0x23 0x46 /* CK3 */ - 0x23 2 0x24 0x44 /* CK1 */ - 0x23 2 0x25 0x40 /* STV1_ODD */ - 0x23 2 0x26 0x1F /* VGL */ - 0x23 2 0x27 0x1F /* VGL */ - 0x23 2 0x28 0x1F /* VGL */ - 0x23 2 0x29 0x1F /* VGL */ - 0x23 2 0x2A 0x1F /* VGL */ - 0x23 2 0x2B 0x55 /* VGG */ - 0x23 2 0x2C 0x12 /* GIP_L_GS Pin mapping RESET_EVEN */ - 0x23 2 0x2D 0x15 /* VSSG_EVEN */ - 0x23 2 0x2E 0x15 /* VSSA_EVEN */ - 0x23 2 0x2F 0x00 /* STV2_EVEN */ - 0x23 2 0x30 0x17 /* VDD2_EVEN */ - 0x23 2 0x31 0x17 /* VDD1_EVEN */ - 0x23 2 0x32 0x1F /* VGL */ - 0x23 2 0x33 0x08 /* CK12 */ - 0x23 2 0x34 0x0A /* CK10 */ - 0x23 2 0x35 0x1F /* VGL */ - 0x23 2 0x36 0x0C /* CK8 */ - 0x23 2 0x37 0x0E /* CK6 */ - 0x23 2 0x38 0x1F /* VGL */ - 0x23 2 0x39 0x04 /* CK4 */ - 0x23 2 0x3A 0x06 /* CK2 */ - 0x23 2 0x3B 0x10 /* STV1_EVEN */ - 0x23 2 0x3C 0x1F /* VGL */ - 0x23 2 0x3D 0x1F /* VGL */ - 0x23 2 0x3E 0x1F /* VGL */ - 0x23 2 0x3F 0x15 /* VGG */ - 0x23 2 0x40 0x1F /* VGL */ - 0x23 2 0x41 0x1F /* VGL */ - 0x23 2 0x42 0x13 /* GIP_R_GS Pin mapping RESET_ODD */ - 0x23 2 0x43 0x15 /* VSSG_ODD */ - 0x23 2 0x44 0x15 /* VSSA_ODD */ - 0x23 2 0x45 0x01 /* STV2_ODD */ - 0x23 2 0x46 0x37 /* VDD2_ODD */ - 0x23 2 0x47 0x17 /* VDD1_ODD */ - 0x23 2 0x48 0x1F /* VGL */ - 0x23 2 0x49 0x09 /* CK11 */ - 0x23 2 0x4A 0x0B /* CK9 */ - 0x23 2 0x4B 0x1F /* VGL */ - 0x23 2 0x4C 0x0D /* CK7 */ - 0x23 2 0x4D 0x0F /* CK5 */ - 0x23 2 0x4E 0x1F /* VGL */ - 0x23 2 0x4F 0x05 /* CK3 */ - 0x23 2 0x50 0x07 /* CK1 */ - 0x23 2 0x51 0x11 /* STV1_ODD */ - 0x23 2 0x52 0x1F /* VGL */ - 0x23 2 0x53 0x1F /* VGL */ - 0x23 2 0x54 0x1F /* VGL */ - 0x23 2 0x55 0x1F /* VGL */ - 0x23 2 0x56 0x1F /* VGL */ - 0x23 2 0x57 0x15 /* VGG */ - 0x23 2 0x58 0x40 /* GAS OPT=1 for abnormal power off */ - 0x23 2 0x59 0x00 /* INIT_W */ - 0x23 2 0x5A 0x00 /* INIT[7:0] */ - 0x23 2 0x5B 0x10 /* STV_NUM STV_S0[10:8] */ - 0x23 2 0x5C 0x14 /* STV_S0[7:0] */ - 0x23 2 0x5D 0x40 /* STV_W STV_S1 */ - 0x23 2 0x5E 0x01 /* STV_S2 */ - 0x23 2 0x5F 0x02 /* STV_S3 */ - 0x23 2 0x60 0x40 /* ETV_W ETV_S1 */ - 0x23 2 0x61 0x03 /* ETV_S2 */ - 0x23 2 0x62 0x04 /* ETV_S3 */ - 0x23 2 0x63 0x7A /* SETV_ON for STV/ETV on time */ - 0x23 2 0x64 0x7A /* SETV_OFF for STV/ETV off time */ - 0x23 2 0x65 0x74 /* ETV_EN ETV_NUM ETV_S0 */ - 0x23 2 0x66 0x16 /* ETV_S0 */ - 0x23 2 0x67 0xB4 /* CKV0_NUM CKV0_W */ - 0x23 2 0x68 0x16 /* CKV0_S0 */ - 0x23 2 0x69 0x7A /* CKV0_on */ - 0x23 2 0x6A 0x7A /* CKV0_off time */ - 0x23 2 0x6B 0x0C /* CKV0_DUM */ - 0x23 2 0x6C 0x00 /* GIP Line EQ option */ - 0x23 2 0x6D 0x04 /* GIP rising EQ */ - 0x23 2 0x6E 0x04 /* GIP fallig EQ */ - 0x23 2 0x6F 0x88 /* GIP_DR CKV0_CON CKV1_CON */ - 0x23 2 0x70 0x00 /* CKV1_NUM CKV0_W */ - 0x23 2 0x71 0x00 /* CKV1_S0 */ - 0x23 2 0x72 0x06 /* CKV1_on */ - 0x23 2 0x73 0x7B /* CKV1_off time */ - 0x23 2 0x74 0x00 /* CKV1_DUM */ - 0x23 2 0x75 0xBC /* FLM_EN FLM_W */ - 0x23 2 0x76 0x00 /* FLM on time */ - 0x23 2 0x77 0x04 /* VEN_EN VEN_W FLM_NUM FLM_OFF */ - 0x23 2 0x78 0x2C /* FLM_OFF */ - 0x23 2 0x79 0x00 /* VEN_W */ - 0x23 2 0x7A 0x00 /* VEN_S0 */ - 0x23 2 0x7B 0x00 /* VEN_S1 */ - 0x23 2 0x7C 0x00 /* VEN_DUM */ - 0x23 2 0x7D 0x03 /* VEN on time */ - 0x23 2 0x7E 0x7B /* VEN off time */ - 0x23 2 0xE0 0x03 /* Page3 */ - 0x23 2 0xAF 0x20 /* Set CABC */ - 0x23 2 0xE0 0x04 /* Page4 */ - 0x23 2 0x09 0x11 /* Source level at blanking period */ - 0x23 2 0x0E 0x48 /* Source EQ option */ - 0x23 2 0x2B 0x2B /* ESD Protect */ - 0x23 2 0x2E 0x44 /* Special Packet disable */ - 0x23 2 0x41 0xFF /* Set CABC */ - 0x23 2 0xE0 0x00 /* Page0 */ - 0x23 2 0xE6 0x02 /* Enable Watch Dog */ - 0x23 2 0xE7 0x0C /* Watch Dog timer setting */ - 0x23 2 0x51 0xFF /* CABC Option 0x80=50% duty 0xFF=100% */ - 0x23 2 0x53 0x2C - 0x23 2 0x55 0x00 - 0x05 1 0x11 /* Sleep Out */ - 0xFF 125 /* Delay 125ms */ - 0x05 1 0x29 /* Display On */ - 0xFF 0xFF /* Ending */ - >; - init_off = < - 0xff 5 - 0x05 1 0x28 /* display off */ - 0xff 60 /* delay 60ms */ - 0x05 1 0x10 /* sleep in */ - 0xff 110 /* delay 110ms */ - 0xff 0xff>; /* ending */ - }; - - extern_3{ - index = <3>; - extern_name = "mipi_default"; // KD070D82_FT9364 - status = "okay"; - type = <2>; /* 0=i2c, 1=spi, 2=mipi */ - cmd_size = <0xff>; - init_on = < - 0x23 2 0xE0 0x00 /* Register setting change to Page 0 */ - 0x23 2 0xE1 0x93 /* PASSWORD, setting as 93-65-F8 to enable page1-4 command access */ - 0x23 2 0xE2 0x65 - 0x23 2 0xE3 0xF8 - 0x23 2 0x80 0x03 /* Setting DSI lane number, 0x03 is DSI 4 lane */ - 0x23 2 0xE0 0x01 /* Register setting change to Page 1 */ - 0x23 2 0x00 0x00 /* Set VCOM_Forward */ - 0x23 2 0x01 0x9E /* VCOM=0x09F */ - 0x23 2 0x03 0x00 /* Set VCOM_Reverse */ - 0x23 2 0x04 0xAA /* VCOMR=0x0AA, -1.40V */ - 0x23 2 0x0C 0x74 /* Set PWRIC pumping frequency,=8 HCLK, about 512KHz */ - 0x23 2 0x17 0x00 /* Set Gamma Power, VGMP[8]=0, VGSP[8]=0 */ - 0x23 2 0x18 0xEF /* VGMP[8:0]=0x0EF=5.1V */ - 0x23 2 0x19 0x00 /* VGSP[8:0]=0x000=0V */ - 0x23 2 0x1A 0x00 /* VGMN[8]=0, VGSN[8]=0 */ - 0x23 2 0x1B 0xEF /* VGMN[8:0]=0x0EF=-5.1V */ - 0x23 2 0x1C 0x00 /* VGSN[8:0]=0x000=0V */ - 0x23 2 0x1F 0x70 /* VGH_REG=16.2V */ - 0x23 2 0x20 0x2D /* VGL_REG=-12V */ - 0x23 2 0x21 0x2D /* VGL_REG2=-12V */ - 0x23 2 0x22 0x7E /* VGH_REG short to VGH, VGL_REG short to VGL, */ - 0x23 2 0x26 0xF3 /* VDDD from IOVCC&VCI */ - 0x23 2 0x37 0x09 /* SS=1, source scan from S2400 to S1;BGR=1 CF type is (S1,S2,S3) align to (B,G,R) */ - 0x23 2 0x38 0x04 /* JDT=100, display inversion type is column inversion */ - 0x23 2 0x39 0x00 /* Source EQ Setting, EQ1, 0x00=0us */ - 0x23 2 0x3A 0x01 /* Source EQ Setting, EQ2, 0x01 =0.1us */ - 0x23 2 0x3C 0x90 /* Source EQ Setting, EQ3, EQ3 start at 14.4us */ - 0x23 2 0x3D 0xFF /* SET Source OP on time, 0xFF means source op always on */ - 0x23 2 0x3E 0xFF /* SET Source OP off time, 0xFF means source op always on */ - 0x23 2 0x3F 0xFF /* SET Source OP off time, 0xFF means source op always on */ - 0x23 2 0x40 0x02 /* horizontal resolution setting,RSO[2:0]= 0x02 =600RGB, LN[1:0]=2'b00 */ - 0x23 2 0x41 0x80 /* LN[9:0]=0x200=512, vertical resolution is 512*2=1024 line */ - 0x23 2 0x42 0x99 /* SLT, internal line period=0x99->15.3us */ - 0x23 2 0x43 0x14 /* Internal VFP=Ext_VFP=20(0x14) */ - 0x23 2 0x44 0x19 /* Internal _VBP=Ext_VS+Ext_VBP-1=6+20-1=25(0x19) */ - 0x23 2 0x45 0x5A /* Internal_HBP=Ext_HS+Ext_HBP=90(0x5A) */ - 0x23 2 0x55 0x02 /* Seting PWRIC mode, DCDCM=0010-> FP7721BX2 */ - 0x23 2 0x56 0x01 /* No auto Ratio function */ - 0x23 2 0x57 0x69 /* VGH_RT=3'b011,2*AVDD-AVEE,VGL_RT=3'b010=AVEE+VCL-AVDD,VCL_RT=2'b00,0.5*VCIP */ - 0x23 2 0x58 0x0A /* AVDD_S, not use internal AVDD in this model */ - 0x23 2 0x59 0x0A /* VCL = -2.5V */ - 0x23 2 0x5A 0x2E /* VGH = 16.2V */ - 0x23 2 0x5B 0x19 /* VGL = -12V */ - 0x23 2 0x5C 0x15 /* pump clk, VCL_CLK[1:0]=2'b01=HCLK/2=32KHz, VGHVGL_CLK[1:0]=2'b01=HCLK/2=32KHz */ - 0x23 2 0x5D 0x77 /* Gamma voltage setting, VP255-4.793V */ - 0x23 2 0x5E 0x5C /* VP251 */ - 0x23 2 0x5F 0x4D /* VP247 */ - 0x23 2 0x60 0x40 /* VP243 */ - 0x23 2 0x61 0x3D /* VP235 */ - 0x23 2 0x62 0x2F /* VP227 */ - 0x23 2 0x63 0x34 /* VP211 */ - 0x23 2 0x64 0x1F /* VP191 */ - 0x23 2 0x65 0x38 /* VP159 */ - 0x23 2 0x66 0x38 /* VP128 */ - 0x23 2 0x67 0x39 /* VP96 */ - 0x23 2 0x68 0x58 /* VP64 */ - 0x23 2 0x69 0x48 /* VP44 */ - 0x23 2 0x6A 0x51 /* VP28 */ - 0x23 2 0x6B 0x44 /* VP20 */ - 0x23 2 0x6C 0x41 /* VP12 */ - 0x23 2 0x6D 0x35 /* VP8 */ - 0x23 2 0x6E 0x24 /* VP4 */ - 0x23 2 0x6F 0x02 /* VP0 */ - 0x23 2 0x70 0x77 /* VN255 */ - 0x23 2 0x71 0x5C /* VN251 */ - 0x23 2 0x72 0x4D /* VN247 */ - 0x23 2 0x73 0x40 /* VN243 */ - 0x23 2 0x74 0x3D /* VN235 */ - 0x23 2 0x75 0x2F /* VN227 */ - 0x23 2 0x76 0x34 /* VN211 */ - 0x23 2 0x77 0x1F /* VN191 */ - 0x23 2 0x78 0x38 /* VN159 */ - 0x23 2 0x79 0x38 /* VN128 */ - 0x23 2 0x7A 0x39 /* VN96 */ - 0x23 2 0x7B 0x58 /* VN64 */ - 0x23 2 0x7C 0x48 /* VN44 */ - 0x23 2 0x7D 0x51 /* VN28 */ - 0x23 2 0x7E 0x44 /* VN20 */ - 0x23 2 0x7F 0x41 /* VN12 */ - 0x23 2 0x80 0x35 /* VN8 */ - 0x23 2 0x81 0x24 /* VN4 */ - 0x23 2 0x82 0x02 /* VN0 */ - 0x23 2 0xE0 0x02 /* Register setting change to Page 2 */ - 0x23 2 0x00 0x53 /* GIP_L_Forward scan mapping, assign as RESET_EVEN */ - 0x23 2 0x01 0x55 /* assign as VSSG_EVEN */ - 0x23 2 0x02 0x55 /* assign as VSSA_EVEN */ - 0x23 2 0x03 0x51 /* assign as STV2_EVEN */ - 0x23 2 0x04 0x77 /* assign as VDD2_EVEN */ - 0x23 2 0x05 0x57 /* assign as VDD1_EVEN */ - 0x23 2 0x06 0x1F /* assign as VGL */ - 0x23 2 0x07 0x4F /* assign as CK12 */ - 0x23 2 0x08 0x4D /* assign as CK10 */ - 0x23 2 0x09 0x1F /* assign as VGL */ - 0x23 2 0x0A 0x4B /* assign as CK8 */ - 0x23 2 0x0B 0x49 /* assign as CK6 */ - 0x23 2 0x0C 0x1F /* assign as VGL */ - 0x23 2 0x0D 0x47 /* assign as CK4 */ - 0x23 2 0x0E 0x45 /* assign as CK2 */ - 0x23 2 0x0F 0x41 /* assign as STV1_EVEN */ - 0x23 2 0x10 0x1F /* assign as VGL */ - 0x23 2 0x11 0x1F /* assign as VGL */ - 0x23 2 0x12 0x1F /* assign as VGL */ - 0x23 2 0x13 0x55 /* assign as VGG */ - 0x23 2 0x14 0x1F /* assign as VGL */ - 0x23 2 0x15 0x1F /* assign as VGL */ - 0x23 2 0x16 0x52 /* GIP_R_Forward scan mapping, assign as RESET_ODD */ - 0x23 2 0x17 0x55 /* assign as VSSG_ODD */ - 0x23 2 0x18 0x55 /* assign as VSSA_ODD */ - 0x23 2 0x19 0x50 /* assign as STV2_ODD */ - 0x23 2 0x1A 0x77 /* assign as VDD2_ODD */ - 0x23 2 0x1B 0x57 /* assign as VDD1_ODD */ - 0x23 2 0x1C 0x1F /* assign as VGL */ - 0x23 2 0x1D 0x4E /* assign as CK11 */ - 0x23 2 0x1E 0x4C /* assign as CK9 */ - 0x23 2 0x1F 0x1F /* assign as VGL */ - 0x23 2 0x20 0x4A /* assign as CK7 */ - 0x23 2 0x21 0x48 /* assign as CK5 */ - 0x23 2 0x22 0x1F /* assign as VGL */ - 0x23 2 0x23 0x46 /* assign as CK3 */ - 0x23 2 0x24 0x44 /* assign as CK1 */ - 0x23 2 0x25 0x40 /* assign as STV1_ODD */ - 0x23 2 0x26 0x1F /* assign as VGL */ - 0x23 2 0x27 0x1F /* assign as VGL */ - 0x23 2 0x28 0x1F /* assign as VGL */ - 0x23 2 0x29 0x1F /* assign as VGL */ - 0x23 2 0x2A 0x1F /* assign as VGL */ - 0x23 2 0x2B 0x55 /* assign as VGG */ - 0x23 2 0x2C 0x12 /* GIP_L_Reverse Scan mapping, assign as RESET_EVEN */ - 0x23 2 0x2D 0x15 /* assign as VSSG_EVEN */ - 0x23 2 0x2E 0x15 /* assign as VSSA_EVEN */ - 0x23 2 0x2F 0x00 /* assign as STV2_EVEN */ - 0x23 2 0x30 0x17 /* assign as VDD2_EVEN */ - 0x23 2 0x31 0x17 /* assign as VDD1_EVEN */ - 0x23 2 0x32 0x1F /* assign as VGL */ - 0x23 2 0x33 0x08 /* assign as CK12 */ - 0x23 2 0x34 0x0A /* assign as CK10 */ - 0x23 2 0x35 0x1F /* assign as VGL */ - 0x23 2 0x36 0x0C /* assign as CK8 */ - 0x23 2 0x37 0x0E /* assign as CK6 */ - 0x23 2 0x38 0x1F /* assign as VGL */ - 0x23 2 0x39 0x04 /* assign as CK4 */ - 0x23 2 0x3A 0x06 /* assign as CK2 */ - 0x23 2 0x3B 0x10 /* assign as STV1_EVEN */ - 0x23 2 0x3C 0x1F /* assign as VGL */ - 0x23 2 0x3D 0x1F /* assign as VGL */ - 0x23 2 0x3E 0x1F /* assign as VGL */ - 0x23 2 0x3F 0x15 /* assign as VGG */ - 0x23 2 0x40 0x1F /* assign as VGL */ - 0x23 2 0x41 0x1F /* assign as VGL */ - 0x23 2 0x42 0x13 /* GIP_R_Reverse Scan mapping, assign as RESET_ODD */ - 0x23 2 0x43 0x15 /* assign as VSSG_ODD */ - 0x23 2 0x44 0x15 /* assign as VSSA_ODD */ - 0x23 2 0x45 0x01 /* assign as STV2_ODD */ - 0x23 2 0x46 0x17 /* assign as VDD2_ODD */ - 0x23 2 0x47 0x17 /* assign as VDD1_ODD */ - 0x23 2 0x48 0x1F /* assign as VGL */ - 0x23 2 0x49 0x09 /* assign as CK11 */ - 0x23 2 0x4A 0x0B /* assign as CK9 */ - 0x23 2 0x4B 0x1F /* assign as VGL */ - 0x23 2 0x4C 0x0D /* assign as CK7 */ - 0x23 2 0x4D 0x0F /* assign as CK5 */ - 0x23 2 0x4E 0x1F /* assign as VGL */ - 0x23 2 0x4F 0x05 /* assign as CK3 */ - 0x23 2 0x50 0x07 /* assign as CK1 */ - 0x23 2 0x51 0x11 /* assign as STV1_ODD */ - 0x23 2 0x52 0x1F /* assign as VGL */ - 0x23 2 0x53 0x1F /* assign as VGL */ - 0x23 2 0x54 0x1F /* assign as VGL */ - 0x23 2 0x55 0x1F /* assign as VGL */ - 0x23 2 0x56 0x1F /* assign as VGL */ - 0x23 2 0x57 0x15 /* assign as VGG */ - 0x23 2 0x58 0x40 /* GAS OPT=1, When abnormal power off, GIP will pull to VGH */ - 0x23 2 0x59 0x00 /* INIT_W=0, no INIT function in this panel */ - 0x23 2 0x5A 0x00 /* INIT[10:0], no INIT function in this panel */ - 0x23 2 0x5B 0x10 /* STV_NUM,STV_S0[10:8], 2 STV pulses */ - 0x23 2 0x5C 0x14 /* STV_S0[7:0], STV start from 21th hsync after vsync */ - 0x23 2 0x5D 0x40 /* STV_W=4, STV width is 4 Hline; STV1 delay 1 hline with STV0 */ - 0x23 2 0x5E 0x01 /* STV_S2, STV2 delay 2 hline with STV0 */ - 0x23 2 0x5F 0x02 /* STV_S3, STV3 delay 3 hline with STV0 */ - 0x23 2 0x60 0x40 /* ETV_W=4, ETV witdh is 4 hline; ETV1 delay 1 hilne from ETV0 */ - 0x23 2 0x61 0x03 /* ETV_S2, ETV2 delay 4 hline with ETV0 */ - 0x23 2 0x62 0x04 /* ETV_S3, ETV3 delay 5 hline with ETV0 */ - 0x23 2 0x63 0x7A /* SETV_ON for STV/ETV on time, rising at 12.2us after hsync */ - 0x23 2 0x64 0x7A /* SETV_OFF for STV/ETV off time , falling at 12.2us after hsync */ - 0x23 2 0x65 0x74 /* ETV_EN=1, enable ETV function; ETV_NUM=3, using 4 ETV pulse, */ - 0x23 2 0x66 0x16 /* ETV_S0=0x416, EVT start at 1046th hsync fater vaync */ - 0x23 2 0x67 0xB4 /* CKV_NUM=2'b1011, using 12 CKV pulse; CKV0_W=4. CKV width is 4 hline */ - 0x23 2 0x68 0x16 /* CKV0_S0 , CKV start from 23th hsync after vsync */ - 0x23 2 0x69 0x7A /* CKV0_on ,for CKV on time, rising at 12.2us after hsync */ - 0x23 2 0x6A 0x7A /* CKV0_off ,for CKV off time, falling at 12.2us after hsync */ - 0x23 2 0x6B 0x0C /* CKV0_DUM, total CKV pulse number=1024+12=1036 */ - 0x23 2 0x6C 0x00 /* GIP Line EQ option , disable GEQ_Line function */ - 0x23 2 0x6D 0x04 /* GIP rising EQ, period is 0.4us */ - 0x23 2 0x6E 0x04 /* GIP fallig EQ, period is 0.4us */ - 0x23 2 0x6F 0x88 /* GIP_DR; CKV0_CON, no continuous CKV0; CKV1_CON, no continuous CKV1 */ - 0x23 2 0x70 0x00 /* CKV1_NUM, CKV0_W , no CKV group 1 function in this panel, don't care */ - 0x23 2 0x71 0x00 /* CKV1_S0, no CKV group 1 function in this panel, don't care */ - 0x23 2 0x72 0x06 /* CKV1_on , no CKV group 1 function in this panel, don't care */ - 0x23 2 0x73 0x7B /* CKV1_off time, no CKV group 1 function in this panel, don't care */ - 0x23 2 0x74 0x00 /* CKV1_DUM, no CKV group 1 function in this panel, don't care */ - 0x23 2 0x75 0xBC /* FLM_EN, enable FLM function; FLM_W=0x3C, FLM toggle period is 60 frame */ - 0x23 2 0x76 0x00 /* FLM on time , FLM on(rising) at 1st hsync after vsync */ - 0x23 2 0x77 0x04 /* VEN_EN, VEN_W, no VEN function in this panel, don't care */ - 0x23 2 0x78 0x2C /* FLM_OFF, FLM off(falling) at 1068th hsync after vsync */ - 0x23 2 0x79 0x00 /* VEN_W , no VEN function in this panel, don't care */ - 0x23 2 0x7A 0x00 /* VEN_S0 , no VEN function in this panel, don't care */ - 0x23 2 0x7B 0x00 /* VEN_S1 , no VEN function in this panel, don't care */ - 0x23 2 0x7C 0x00 /* VEN_DUM , no VEN function in this panel, don't care */ - 0x23 2 0x7D 0x03 /* VEN on time , no VEN function in this panel, don't care */ - 0x23 2 0x7E 0x7B /* VEN off time , no VEN function in this panel, don't care */ - 0x23 2 0xE0 0x03 /* Register setting change to Page 3 */ - 0x23 2 0xAF 0x20 /* Set CABC, disable CABC TP detect, for CABC pattern change more smooth */ - 0x23 2 0xE0 0x04 /* Register setting change to Page 4 */ - 0x23 2 0x09 0x11 /* Source level at blanking period, sweeping V0 level */ - 0x23 2 0x0E 0x48 /* Source EQ option, EQ to PCAP,NCAP */ - 0x23 2 0x2B 0x2B /* ESD Protect, clock lane op behavior follow data lane, improve ESD performance */ - 0x23 2 0x2E 0x44 /* ESD protect, disable special packet */ - 0x23 2 0x41 0xFF /* Set CABC, for CABC pattern change more smooth */ - 0x23 2 0xE0 0x00 /* Register setting change to Page 0 */ - 0x23 2 0xE6 0x02 /* Enable Watch Dog */ - 0x23 2 0xE7 0x0C /* Watch Dog timer setting, WD alarm time is 12*512osc after hsync stop */ - 0x23 2 0x51 0xFF /* CABC Option, 0x80=50% duty, 0xFF=100% */ - 0x23 2 0x53 0x2C /* enable dimming, BCTRL, BL */ - 0x23 2 0x55 0x00 /* CABC mode, 0x00 is manual mode */ - 0x05 1 0x11 /* SLPOUT */ - 0xFF 125 /* Delay 125ms */ - 0x05 1 0x29 /* Display On */ - 0xFF 0xFF /* Ending */ - >; - init_off = < - 0xff 5 - 0x05 1 0x28 /* display off */ - 0xff 60 /* delay 60ms */ - 0x05 1 0x10 /* sleep in */ - 0xff 110 /* delay 110ms */ - 0xff 0xff>; /* ending */ - }; - }; - - backlight{ - compatible = "amlogic, backlight-g12a"; - status = "okay"; - key_valid = <0>; - pinctrl-names = "pwm_on","pwm_off"; - pinctrl-0 = <&pwm_f_pins2>; - pinctrl-1 = <&bl_pwm_off_pins>; - pinctrl_version = <2>; /* for uboot */ - bl_pwm_config = <&bl_pwm_conf>; - bl-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_HIGH - &gpio GPIOH_5 GPIO_ACTIVE_HIGH>; - bl_gpio_names = "GPIOH_4","GPIOH_5"; - - /* pwm port: PWM_A, PWM_B, PWM_C, PWM_D, PWM_E, PWM_F, PWM_VS*/ - /* power index:(point gpios_index, 0xff=invalid) - * power value:(0=output low, 1=output high, 2=input) - * power delay:(unit in ms) - */ - - backlight_0{ - index = <0>; - bl_name = "backlight_pwm"; - bl_level_default_uboot_kernel = <100 100>; - bl_level_attr = <255 10 /*max, min*/ - 128 128>; /*mid, mid_mapping*/ - bl_ctrl_method = <1>; /* 1=pwm, 2=pwm_combo, 4=extern */ - bl_power_attr = <0 /*en_gpio_index*/ - 1 0 /*on_value, off_value*/ - 200 200>; /*on_delay(ms), off_delay(ms)*/ - bl_pwm_port = "PWM_F"; - bl_pwm_attr = <0 /*pwm_method*/ - 180 /*pwm_freq(pwm:Hz, pwm_vs:multiple of vs)*/ - 100 25>; /*duty_max(%), duty_min(%)*/ - bl_pwm_power = <1 1 /*pwm_gpio_index, pwm_gpio_off*/ - 10 10>; /*pwm_on_delay(ms), pwm_off_delay(ms)*/ - bl_pwm_en_sequence_reverse = <0>; /* 1 for reverse */ - }; - backlight_1{ - index = <1>; - bl_name = "bl_extern"; - bl_level_default_uboot_kernel = <100 100>; - bl_level_attr = <255 10 /*max, min*/ - 128 128>; /*mid, mid_mapping*/ - bl_ctrl_method = <4>; /*1=pwm, 2=pwm_combo, 4=extern*/ - bl_power_attr = <1 /*en_gpio_index*/ - 1 0 /*on_value, off_value*/ - 200 200>; /*on_delay(ms), off_delay(ms)*/ - bl_extern_index = <0>; - }; - }; - bl_pwm_conf:bl_pwm_conf{ - pwm_channel_0 { - pwm_port_index = <5>; - pwms = <&pwm_ef MESON_PWM_1 30040 0>; - }; - }; - - bl_extern{ - compatible = "amlogic, bl_extern"; - status = "disabled"; - i2c_bus = "i2c_bus_3"; - - extern_0{ - index = <0>; - extern_name = "i2c_lp8556"; - type = <0>; /*0=i2c, 1=spi, 2=mipi*/ - i2c_address = <0x2c>; /*7bit i2c address*/ - dim_max_min = <255 10>; - }; - - extern_1{ - index = <1>; - extern_name = "mipi_lt070me05"; - type = <2>; /*0=i2c, 1=spi, 2=mipi*/ - dim_max_min = <255 10>; - }; - }; -};/* end of panel */
diff --git a/arch/arm/dts/elaine-bx-panel.dtsi b/arch/arm/dts/elaine-bx-panel.dtsi deleted file mode 100755 index 8cada5e..0000000 --- a/arch/arm/dts/elaine-bx-panel.dtsi +++ /dev/null
@@ -1,1313 +0,0 @@ -/* - * arch/arm/dts/elaine-bx-panel.dtsi - * - * Copyright (C) 2016 Amlogic, Inc. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - */ - -/ { - lcd{ - compatible = "amlogic, lcd-sm1"; - mode = "tablet"; - status = "okay"; - key_valid = <0>; - clocks = <&clkc CLKID_MIPI_DSI_HOST - &clkc CLKID_MIPI_DSI_PHY - &clkc CLKID_DSI_MEAS_COMP - &clkc CLKID_VCLK2_ENCL - &clkc CLKID_VCLK2_VENCL - &clkc CLKID_GP0_PLL>; - clock-names = "dsi_host_gate", - "dsi_phy_gate", - "dsi_meas", - "encl_top_gate", - "encl_int_gate", - "gp0_pll"; - reg = <0x0 0xffd07000 0x0 0x400 /* dsi_host */ - 0x0 0xff644000 0x0 0x200>; /* dsi_phy */ - interrupts = <0 3 1 - 0 56 1>; - interrupt-names = "vsync","vsync2"; - pinctrl_version = <2>; /* for uboot */ - - /* power type: - * (0=cpu_gpio, 1=pmu_gpio, 2=signal,3=extern, 0xff=ending) - * power index: - * (point gpios_index, or extern_index,0xff=invalid) - * power value:(0=output low, 1=output high, 2=input) - * power delay:(unit in ms) - */ - lcd_cpu-gpios = <&gpio GPIOZ_13 GPIO_ACTIVE_HIGH>; - lcd_cpu_gpio_names = "GPIOZ_13"; - - boe_fiti9364_7{ - model_name = "TV070WSM_FT9364"; - interface = "mipi"; - basic_setting = <600 1024 /*h_active, v_active*/ - 700 1053 /*h_period, v_period*/ - 8 /*lcd_bits*/ - 95 163>; /*screen_widht, screen_height*/ - lcd_timing = <24 36 0 /*hs_width,hs_bp,hs_pol*/ - 2 8 0>; /*vs_width,vs_bp,vs_pol*/ - clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/ - 0 /*clk_ss_level*/ - 1 /*clk_auto_generate*/ - 44226000>; /*pixel_clk(unit in Hz)*/ - mipi_attr = <4 /*lane_num*/ - 400 /*bit_rate_max(MHz)*/ - 0 /*factor(*100, default 0 for auto)*/ - 1 /*operation_mode_init(0=video, 1=command)*/ - 0 /*operation_mode_display(0=video, 1=command)*/ - 2 /* - *video_mode_type - *(0=sync_pulse,1=sync_event,2=burst) - */ - 0 /*clk_always_hs(0=disable,1=enable)*/ - 0>; /*phy_switch(0=auto,1=standard,2=slow)*/ - /* dsi_init: data_type, num, data... */ - dsi_init_on = < - 0xff 10 - 0xf0 3 0 1 30 /* reset high, delay 30ms */ - 0xf0 3 0 0 10 /* reset low, delay 10ms */ - 0xf0 3 0 1 30 /* reset high, delay 30ms */ - 0xfc 2 0x04 3 /* check_reg, check_cnt */ - 0xff 0xff>; /* ending flag */ - dsi_init_off = < - 0xff 5 /* delay 5ms */ - 0xff 0xff>; /* ending flag */ - /* extern_init: 0xff for invalid */ - extern_init = <1>; - /* power step: type,index,value,delay(ms) */ - power_on_step = < - 0 1 0 200 - 2 0 0 0 - 0xff 0 0 0>; - power_off_step = < - 2 0 0 5 /* delay 5ms after mipi off */ - 0 0 0 20 /* reset low */ - 0 1 1 100 /* panel power off */ - 0xff 0 0 0>; - backlight_index = <0>; - }; - - boe_fiti9365_7{ - model_name = "TV070WSM_FT9365"; - interface = "mipi"; - basic_setting = <600 1024 /*h_active, v_active*/ - 700 1053 /*h_period, v_period*/ - 8 /*lcd_bits*/ - 95 163>; /*screen_widht, screen_height*/ - lcd_timing = <24 36 0 /*hs_width,hs_bp,hs_pol*/ - 2 8 0>; /*vs_width,vs_bp,vs_pol*/ - clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/ - 0 /*clk_ss_level*/ - 1 /*clk_auto_generate*/ - 44226000>; /*pixel_clk(unit in Hz)*/ - mipi_attr = <4 /*lane_num*/ - 400 /*bit_rate_max(MHz)*/ - 0 /*factor(*100, default 0 for auto)*/ - 1 /*operation_mode_init(0=video, 1=command)*/ - 0 /*operation_mode_display(0=video, 1=command)*/ - 2 /* - *video_mode_type - *(0=sync_pulse,1=sync_event,2=burst) - */ - 0 /*clk_always_hs(0=disable,1=enable)*/ - 0>; /*phy_switch(0=auto,1=standard,2=slow)*/ - /* dsi_init: data_type, num, data... */ - dsi_init_on = < - 0xff 10 - 0xf0 3 0 1 30 /* reset high, delay 30ms */ - 0xf0 3 0 0 10 /* reset low, delay 10ms */ - 0xf0 3 0 1 30 /* reset high, delay 30ms */ - 0xfc 2 0x04 3 /* check_reg, check_cnt */ - 0xff 0xff>; /* ending flag */ - dsi_init_off = < - 0xff 5 /* delay 5ms */ - 0xff 0xff>; /* ending flag */ - /* extern_init: 0xff for invalid */ - extern_init = <2>; - /* power step: type,index,value,delay(ms) */ - power_on_step = < - 0 1 0 200 - 2 0 0 0 - 0xff 0 0 0>; - power_off_step = < - 2 0 0 5 /* delay 5ms after mipi off */ - 0 0 0 20 /* reset low */ - 0 1 1 100 /* panel power off */ - 0xff 0 0 0>; - backlight_index = <0>; - }; - - kd_fiti9364_7{ - model_name = "KD070D82_FT9364"; - interface = "mipi"; - basic_setting = <600 1024 /*h_active, v_active*/ - 770 1070 /*h_period, v_period*/ - 8 /*lcd_bits*/ - 3 5>; /*screen_widht, screen_height*/ - lcd_timing = <10 80 0 /*hs_width,hs_bp,hs_pol*/ - 6 20 0>; /*vs_width,vs_bp,vs_pol*/ - clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/ - 0 /*clk_ss_level*/ - 1 /*clk_auto_generate*/ - 49434000>; /*pixel_clk(unit in Hz)*/ - mipi_attr = <4 /*lane_num*/ - 400 /*bit_rate_max(MHz)*/ - 0 /*factor(*100, default 0 for auto)*/ - 1 /*operation_mode_init(0=video, 1=command)*/ - 0 /*operation_mode_display(0=video, 1=command)*/ - 2 /* - *video_mode_type - *(0=sync_pulse,1=sync_event,2=burst) - */ - 0 /*clk_always_hs(0=disable,1=enable)*/ - 0>; /*phy_switch(0=auto,1=standard,2=slow)*/ - /* dsi_init: data_type, num, data... */ - dsi_init_on = < - 0xff 10 - 0xf0 3 0 1 30 /* reset high, delay 30ms */ - 0xf0 3 0 0 10 /* reset low, delay 10ms */ - 0xf0 3 0 1 30 /* reset high, delay 30ms */ - 0xfc 2 0x04 3 /* check_reg, check_cnt */ - 0xff 0xff>; /* ending flag */ - dsi_init_off = < - 0xff 5 /* delay 5ms */ - 0xff 0xff>; /* ending flag */ - /* extern_init: 0xff for invalid */ - extern_init = <3>; - /* power step: type,index,value,delay(ms) */ - power_on_step = < - 0 1 0 200 /* panel power on */ - 2 0 0 0 - 0xff 0 0 0>; - power_off_step = < - 2 0 0 5 /* delay 5ms after mipi off */ - 0 0 0 20 /* reset low */ - 0 1 1 100 /* panel power off */ - 0xff 0 0 0>; - backlight_index = <0>; - }; - - kd_fiti9365_7{ - model_name = "KD070D82_FT9365"; - interface = "mipi"; - basic_setting = <600 1024 /*h_active, v_active*/ - 770 1070 /*h_period, v_period*/ - 8 /*lcd_bits*/ - 3 5>; /*screen_widht, screen_height*/ - lcd_timing = <10 80 0 /*hs_width,hs_bp,hs_pol*/ - 6 20 0>; /*vs_width,vs_bp,vs_pol*/ - clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/ - 0 /*clk_ss_level*/ - 1 /*clk_auto_generate*/ - 49434000>; /*pixel_clk(unit in Hz)*/ - mipi_attr = <4 /*lane_num*/ - 400 /*bit_rate_max(MHz)*/ - 0 /*factor(*100, default 0 for auto)*/ - 1 /*operation_mode_init(0=video, 1=command)*/ - 0 /*operation_mode_display(0=video, 1=command)*/ - 2 /* - *video_mode_type - *(0=sync_pulse,1=sync_event,2=burst) - */ - 0 /*clk_always_hs(0=disable,1=enable)*/ - 0>; /*phy_switch(0=auto,1=standard,2=slow)*/ - /* dsi_init: data_type, num, data... */ - dsi_init_on = < - 0xff 10 - 0xf0 3 0 1 30 /* reset high, delay 30ms */ - 0xf0 3 0 0 10 /* reset low, delay 10ms */ - 0xf0 3 0 1 30 /* reset high, delay 30ms */ - 0xfc 2 0x04 3 /* check_reg, check_cnt */ - 0xff 0xff>; /* ending flag */ - dsi_init_off = < - 0xff 5 /* delay 5ms */ - 0xff 0xff>; /* ending flag */ - /* extern_init: 0xff for invalid */ - extern_init = <4>; - /* power step: type,index,value,delay(ms) */ - power_on_step = < - 0 1 0 200 /* panel power on */ - 2 0 0 0 - 0xff 0 0 0>; - power_off_step = < - 2 0 0 5 /* delay 5ms after mipi off */ - 0 0 0 20 /* reset low */ - 0 1 1 100 /* panel power off */ - 0xff 0 0 0>; - backlight_index = <0>; - }; - - boe_sit7703_7{ - model_name = "TV070WSM_ST7703I"; - interface = "mipi"; - basic_setting = <600 1024 /*h_active, v_active*/ - 700 1053 /*h_period, v_period*/ - 8 /*lcd_bits*/ - 95 63>; /*screen_widht, screen_height*/ - lcd_timing = <24 36 0 /*hs_width,hs_bp,hs_pol*/ - 2 8 0>; /*vs_width,vs_bp,vs_pol*/ - clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/ - 0 /*clk_ss_level*/ - 1 /*clk_auto_generate*/ - 44226000>; /*pixel_clk(unit in Hz)*/ - mipi_attr = <4 /*lane_num*/ - 400 /*bit_rate_max(MHz)*/ - 0 /*factor(*100, default 0 for auto)*/ - 1 /*operation_mode_init(0=video, 1=command)*/ - 0 /*operation_mode_display(0=video, 1=command)*/ - 2 /* - *video_mode_type - *(0=sync_pulse,1=sync_event,2=burst) - */ - 0 /*clk_always_hs(0=disable,1=enable)*/ - 0>; /*phy_switch(0=auto,1=standard,2=slow)*/ - /* dsi_init: data_type, num, data... */ - dsi_init_on = < - 0xff 10 - 0xf0 3 0 1 100 /* reset high, delay 100ms */ - 0xf0 3 0 0 10 /* reset low, delay 10ms */ - 0xf0 3 0 1 220 /* reset high, delay 220ms */ - 0xfc 2 0xda 1 /*check_reg, check_cnt */ - 0xfc 2 0xdb 1 /*check_reg, check_cnt */ - 0xfc 2 0xdc 1 /*check_reg, check_cnt */ - 0xff 0xff>; /* ending flag */ - dsi_init_off = < - 0xff 5 /* delay 5ms */ - 0xff 0xff>; /* ending flag */ - /* extern_init: 0xff for invalid */ - extern_init = <5>; - /* power step: type,index,value,delay(ms) */ - power_on_step = < - 0 1 0 200 /* panel power on */ - 2 0 0 0 - 0xff 0 0 0>; - power_off_step = < - 2 0 0 5 /* delay 5ms after mipi off */ - 0 0 0 20 /* reset low */ - 0 1 1 100 /* panel power off */ - 0xff 0 0 0>; - backlight_index = <0>; - }; - }; - - lcd_extern{ - compatible = "amlogic, lcd_extern"; - dev_name = "lcd_extern"; - status = "okay"; - key_valid = <0>; - - extern_1{ - index = <1>; - extern_name = "mipi_default"; // TV070WSM_FT9364 - status = "okay"; - type = <2>; /* 0=i2c, 1=spi, 2=mipi */ - cmd_size = <0xff>; - init_on = < - 0x23 2 0xE0 0x00 - 0x23 2 0xE1 0x93 - 0x23 2 0xE2 0x65 - 0x23 2 0xE3 0xF8 - 0x23 2 0xE0 0x01 - 0x23 2 0x00 0x00 - 0x23 2 0x01 0x90 - 0x23 2 0x03 0x00 - 0x23 2 0x04 0x90 - 0x23 2 0x17 0x00 - 0x23 2 0x18 0xB0 - 0x23 2 0x19 0x01 - 0x23 2 0x1A 0x00 - 0x23 2 0x1B 0xB0 - 0x23 2 0x1C 0x01 - 0x23 2 0x1F 0x3E - 0x23 2 0x20 0x2F - 0x23 2 0x21 0x2F - 0x23 2 0x22 0x0E - 0x23 2 0x37 0x69 - 0x23 2 0x38 0x05 - 0x23 2 0x39 0x00 - 0x23 2 0x3A 0x01 - 0x23 2 0x3C 0x90 - 0x23 2 0x3D 0xFF - 0x23 2 0x3E 0xFF - 0x23 2 0x3F 0xFF - 0x23 2 0x40 0x02 - 0x23 2 0x41 0x80 - 0x23 2 0x42 0x99 - 0x23 2 0x43 0x06 - 0x23 2 0x44 0x09 - 0x23 2 0x45 0x3C - 0x23 2 0x4B 0x04 - 0x23 2 0x55 0x0D - 0x23 2 0x56 0x01 - 0x23 2 0x57 0x89 - 0x23 2 0x58 0x0A - 0x23 2 0x59 0x0A - 0x23 2 0x5A 0x27 - 0x23 2 0x5B 0x15 - 0x23 2 0x5D 0x7C - 0x23 2 0x5E 0x67 - 0x23 2 0x5F 0x58 - 0x23 2 0x60 0x4C - 0x23 2 0x61 0x48 - 0x23 2 0x62 0x38 - 0x23 2 0x63 0x3C - 0x23 2 0x64 0x24 - 0x23 2 0x65 0x3B - 0x23 2 0x66 0x38 - 0x23 2 0x67 0x36 - 0x23 2 0x68 0x53 - 0x23 2 0x69 0x3F - 0x23 2 0x6A 0x44 - 0x23 2 0x6B 0x35 - 0x23 2 0x6C 0x2E - 0x23 2 0x6D 0x1F - 0x23 2 0x6E 0x0C - 0x23 2 0x6F 0x00 - 0x23 2 0x70 0x7C - 0x23 2 0x71 0x67 - 0x23 2 0x72 0x58 - 0x23 2 0x73 0x4C - 0x23 2 0x74 0x48 - 0x23 2 0x75 0x38 - 0x23 2 0x76 0x3C - 0x23 2 0x77 0x24 - 0x23 2 0x78 0x3B - 0x23 2 0x79 0x38 - 0x23 2 0x7A 0x36 - 0x23 2 0x7B 0x53 - 0x23 2 0x7C 0x3F - 0x23 2 0x7D 0x44 - 0x23 2 0x7E 0x35 - 0x23 2 0x7F 0x2E - 0x23 2 0x80 0x1F - 0x23 2 0x81 0x0C - 0x23 2 0x82 0x00 - 0x23 2 0xE0 0x02 - 0x23 2 0x00 0x45 - 0x23 2 0x01 0x45 - 0x23 2 0x02 0x47 - 0x23 2 0x03 0x47 - 0x23 2 0x04 0x41 - 0x23 2 0x05 0x41 - 0x23 2 0x06 0x1F - 0x23 2 0x07 0x1F - 0x23 2 0x08 0x1F - 0x23 2 0x09 0x1F - 0x23 2 0x0A 0x1F - 0x23 2 0x0B 0x1F - 0x23 2 0x0C 0x1F - 0x23 2 0x0D 0x1D - 0x23 2 0x0E 0x1D - 0x23 2 0x0F 0x1D - 0x23 2 0x10 0x1F - 0x23 2 0x11 0x1F - 0x23 2 0x12 0x1F - 0x23 2 0x13 0x1F - 0x23 2 0x14 0x1F - 0x23 2 0x15 0x1F - 0x23 2 0x16 0x44 - 0x23 2 0x17 0x44 - 0x23 2 0x18 0x46 - 0x23 2 0x19 0x46 - 0x23 2 0x1A 0x40 - 0x23 2 0x1B 0x40 - 0x23 2 0x1C 0x1F - 0x23 2 0x1D 0x1F - 0x23 2 0x1E 0x1F - 0x23 2 0x1F 0x1F - 0x23 2 0x20 0x1F - 0x23 2 0x21 0x1F - 0x23 2 0x22 0x1F - 0x23 2 0x23 0x1D - 0x23 2 0x24 0x1D - 0x23 2 0x25 0x1D - 0x23 2 0x26 0x1F - 0x23 2 0x27 0x1F - 0x23 2 0x28 0x1F - 0x23 2 0x29 0x1F - 0x23 2 0x2A 0x1F - 0x23 2 0x2B 0x1F - 0x23 2 0x58 0x40 - 0x23 2 0x59 0x00 - 0x23 2 0x5A 0x00 - 0x23 2 0x5B 0x10 - 0x23 2 0x5C 0x07 - 0x23 2 0x5D 0x20 - 0x23 2 0x5E 0x00 - 0x23 2 0x5F 0x00 - 0x23 2 0x61 0x00 - 0x23 2 0x62 0x00 - 0x23 2 0x63 0x7A - 0x23 2 0x64 0x7A - 0x23 2 0x65 0x00 - 0x23 2 0x66 0x00 - 0x23 2 0x67 0x32 - 0x23 2 0x68 0x08 - 0x23 2 0x69 0x7A - 0x23 2 0x6A 0x7A - 0x23 2 0x6B 0x00 - 0x23 2 0x6C 0x00 - 0x23 2 0x6D 0x00 - 0x23 2 0x6E 0x00 - 0x23 2 0x6F 0x89 - 0x23 2 0x70 0x00 - 0x23 2 0x71 0x00 - 0x23 2 0x72 0x06 - 0x23 2 0x73 0x7B - 0x23 2 0x74 0x00 - 0x23 2 0x75 0x07 - 0x23 2 0x76 0x00 - 0x23 2 0x77 0x5D - 0x23 2 0x78 0x17 - 0x23 2 0x79 0x1F - 0x23 2 0x7A 0x00 - 0x23 2 0x7B 0x00 - 0x23 2 0x7C 0x00 - 0x23 2 0x7D 0x03 - 0x23 2 0x7E 0x7B - 0x23 2 0xE0 0x03 - 0x23 2 0xAF 0x20 - 0x23 2 0xE0 0x04 - 0x23 2 0x09 0x11 - 0x23 2 0x0E 0x48 - 0x23 2 0x2B 0x2B - 0x23 2 0x2E 0x44 - 0x23 2 0x41 0xFF - 0x23 2 0xE0 0x00 - 0x23 2 0xE6 0x02 - 0x23 2 0xE7 0x0C - 0x23 2 0x51 0xFF - 0x23 2 0x53 0x2C - 0x23 2 0x55 0x00 - 0x05 1 0x11 - 0xFF 125 /* Delay 125ms */ - 0x05 1 0x29 - 0xFF 0xFF /* Ending Flag */ - >; - init_off = < - 0xff 5 - 0x05 1 0x28 /* display off */ - 0xff 60 /* delay 60ms */ - 0x05 1 0x10 /* sleep in */ - 0xff 110 /* delay 110ms */ - 0xff 0xff>; /* ending */ - }; - - extern_2{ - index = <2>; - extern_name = "mipi_default"; // TV070WSM_FT9365 - status = "okay"; - type = <2>; /* 0=i2c, 1=spi, 2=mipi */ - cmd_size = <0xff>; - init_on = < - 0x23 2 0xE0 0x00 /*Page 0*/ - 0x23 2 0xE1 0x93 - 0x23 2 0xE2 0x65 - 0x23 2 0xE3 0xF8 - 0x23 2 0xE0 0x01 /*Page 1*/ - 0x23 2 0x00 0x00 - 0x23 2 0x01 0x90 - 0x23 2 0x03 0x00 - 0x23 2 0x04 0x90 - 0x23 2 0x17 0x00 - 0x23 2 0x18 0xB0 - 0x23 2 0x19 0x01 - 0x23 2 0x1A 0x00 - 0x23 2 0x1B 0xB0 - 0x23 2 0x1C 0x01 - 0x23 2 0x35 0x28 /*Set SAP = 8*/ - 0x23 2 0x37 0x69 /*SET panel_ctrl*/ - 0x23 2 0x38 0x05 /*SET RGBCYC*/ - 0x23 2 0x39 0x00 - 0x23 2 0x3A 0x01 - 0x23 2 0x3C 0x90 - 0x23 2 0x3D 0xFF - 0x23 2 0x3E 0xFF - 0x23 2 0x3F 0xFF - 0x23 2 0x40 0x02 /*SET_TCON*/ - 0x23 2 0x41 0x80 - 0x23 2 0x42 0x99 - 0x23 2 0x43 0x06 - 0x23 2 0x44 0x09 - 0x23 2 0x45 0x3C - 0x23 2 0x4B 0x04 - 0x23 2 0x55 0x02 /*Power Voltage*/ - 0x23 2 0x56 0x01 - 0x23 2 0x57 0x89 - 0x23 2 0x58 0x0A - 0x23 2 0x59 0x0A - 0x23 2 0x5A 0x27 - 0x23 2 0x5B 0x15 - 0x23 2 0x5D 0x7C /*Gamma*/ - 0x23 2 0x5E 0x65 - 0x23 2 0x5F 0x53 - 0x23 2 0x60 0x46 - 0x23 2 0x61 0x41 - 0x23 2 0x62 0x33 - 0x23 2 0x63 0x35 - 0x23 2 0x64 0x1E - 0x23 2 0x65 0x36 - 0x23 2 0x66 0x34 - 0x23 2 0x67 0x34 - 0x23 2 0x68 0x51 - 0x23 2 0x69 0x3E - 0x23 2 0x6A 0x44 - 0x23 2 0x6B 0x35 - 0x23 2 0x6C 0x2E - 0x23 2 0x6D 0x1F - 0x23 2 0x6E 0x0C - 0x23 2 0x6F 0x00 - 0x23 2 0x70 0x7C - 0x23 2 0x71 0x65 - 0x23 2 0x72 0x53 - 0x23 2 0x73 0x46 - 0x23 2 0x74 0x41 - 0x23 2 0x75 0x33 - 0x23 2 0x76 0x35 - 0x23 2 0x77 0x1E - 0x23 2 0x78 0x36 - 0x23 2 0x79 0x34 - 0x23 2 0x7A 0x34 - 0x23 2 0x7B 0x51 - 0x23 2 0x7C 0x3E - 0x23 2 0x7D 0x44 - 0x23 2 0x7E 0x35 - 0x23 2 0x7F 0x2E - 0x23 2 0x80 0x1F - 0x23 2 0x81 0x0C - 0x23 2 0x82 0x00 - 0x23 2 0xE0 0x02 /*Page 2*/ - 0x23 2 0x00 0x45 /*GIP_L*/ - 0x23 2 0x01 0x45 - 0x23 2 0x02 0x47 - 0x23 2 0x03 0x47 - 0x23 2 0x04 0x41 - 0x23 2 0x05 0x41 - 0x23 2 0x06 0x1F - 0x23 2 0x07 0x1F - 0x23 2 0x08 0x1F - 0x23 2 0x09 0x1F - 0x23 2 0x0A 0x1F - 0x23 2 0x0B 0x1F - 0x23 2 0x0C 0x1F - 0x23 2 0x0D 0x1D - 0x23 2 0x0E 0x1D - 0x23 2 0x0F 0x1D - 0x23 2 0x10 0x1F - 0x23 2 0x11 0x1F - 0x23 2 0x12 0x1F - 0x23 2 0x13 0x1F - 0x23 2 0x14 0x1F - 0x23 2 0x15 0x1F - 0x23 2 0x16 0x44 /*GIP_R*/ - 0x23 2 0x17 0x44 - 0x23 2 0x18 0x46 - 0x23 2 0x19 0x46 - 0x23 2 0x1A 0x40 - 0x23 2 0x1B 0x40 - 0x23 2 0x1C 0x1F - 0x23 2 0x1D 0x1F - 0x23 2 0x1E 0x1F - 0x23 2 0x1F 0x1F - 0x23 2 0x20 0x1F - 0x23 2 0x21 0x1F - 0x23 2 0x22 0x1F - 0x23 2 0x23 0x1D - 0x23 2 0x24 0x1D - 0x23 2 0x25 0x1D - 0x23 2 0x26 0x1F - 0x23 2 0x27 0x1F - 0x23 2 0x28 0x1F - 0x23 2 0x29 0x1F - 0x23 2 0x2A 0x1F - 0x23 2 0x2B 0x1F - 0x23 2 0x58 0x40 /*GIP Timing*/ - 0x23 2 0x59 0x00 - 0x23 2 0x5A 0x00 - 0x23 2 0x5B 0x10 - 0x23 2 0x5C 0x07 - 0x23 2 0x5D 0x20 - 0x23 2 0x5E 0x00 - 0x23 2 0x5F 0x00 - 0x23 2 0x61 0x00 - 0x23 2 0x62 0x00 - 0x23 2 0x63 0x7A - 0x23 2 0x64 0x7A - 0x23 2 0x65 0x00 - 0x23 2 0x66 0x00 - 0x23 2 0x67 0x32 - 0x23 2 0x68 0x08 - 0x23 2 0x69 0x7A - 0x23 2 0x6A 0x7A - 0x23 2 0x6B 0x00 - 0x23 2 0x6C 0x00 - 0x23 2 0x6D 0x04 - 0x23 2 0x6E 0x04 - 0x23 2 0x6F 0x89 - 0x23 2 0x70 0x00 - 0x23 2 0x71 0x00 - 0x23 2 0x72 0x06 - 0x23 2 0x73 0x7B - 0x23 2 0x74 0x00 - 0x23 2 0x75 0x07 - 0x23 2 0x76 0x00 - 0x23 2 0x77 0x5D - 0x23 2 0x78 0x17 - 0x23 2 0x79 0x1F - 0x23 2 0x7A 0x00 - 0x23 2 0x7B 0x00 - 0x23 2 0x7C 0x00 - 0x23 2 0x7D 0x03 - 0x23 2 0x7E 0x7B - 0x23 2 0xE0 0x03 /*Page 3*/ - 0x23 2 0xA9 0x02 - 0x23 2 0xAC 0x4D - 0x23 2 0xE0 0x04 /*Page 4*/ - 0x23 2 0x00 0x0E - 0x23 2 0x02 0xB3 - 0x23 2 0x09 0x60 - 0x23 2 0x0E 0x48 - 0x23 2 0xE0 0x00 /*Page 0*/ - 0x23 2 0x51 0xFF - 0x23 2 0x53 0x2C - 0xFF 5 /*Delay 5ms*/ - 0x05 1 0x11 - 0xFF 125 /*Delay 125ms*/ - 0x05 1 0x29 - 0xFF 20 /*Delay 20ms*/ - 0xFF 0xFF /*Ending Flag*/ - >; - init_off = < - 0xff 5 - 0x05 1 0x28 /* display off */ - 0xff 60 /* delay 60ms */ - 0x05 1 0x10 /* sleep in */ - 0xff 110 /* delay 110ms */ - 0xff 0xff>; /* ending */ - }; - - extern_3{ - index = <3>; - extern_name = "mipi_default"; // KD070D82_FT9364 - status = "okay"; - type = <2>; /* 0=i2c, 1=spi, 2=mipi */ - cmd_size = <0xff>; - init_on = < - 0x23 2 0xE0 0x00 /* Register setting change to Page 0 */ - 0x23 2 0xE1 0x93 /* PASSWORD, setting as 93-65-F8 to enable page1-4 command access */ - 0x23 2 0xE2 0x65 - 0x23 2 0xE3 0xF8 - 0x23 2 0x80 0x03 /* Setting DSI lane number, 0x03 is DSI 4 lane */ - 0x23 2 0xE0 0x01 /* Register setting change to Page 1 */ - 0x23 2 0x00 0x00 /* Set VCOM_Forward */ - 0x23 2 0x01 0x9E /* VCOM=0x09F */ - 0x23 2 0x03 0x00 /* Set VCOM_Reverse */ - 0x23 2 0x04 0xAA /* VCOMR=0x0AA, -1.40V */ - 0x23 2 0x0C 0x74 /* Set PWRIC pumping frequency,=8 HCLK, about 512KHz */ - 0x23 2 0x17 0x00 /* Set Gamma Power, VGMP[8]=0, VGSP[8]=0 */ - 0x23 2 0x18 0xEF /* VGMP[8:0]=0x0EF=5.1V */ - 0x23 2 0x19 0x00 /* VGSP[8:0]=0x000=0V */ - 0x23 2 0x1A 0x00 /* VGMN[8]=0, VGSN[8]=0 */ - 0x23 2 0x1B 0xEF /* VGMN[8:0]=0x0EF=-5.1V */ - 0x23 2 0x1C 0x00 /* VGSN[8:0]=0x000=0V */ - 0x23 2 0x1F 0x70 /* VGH_REG=16.2V */ - 0x23 2 0x20 0x2D /* VGL_REG=-12V */ - 0x23 2 0x21 0x2D /* VGL_REG2=-12V */ - 0x23 2 0x22 0x7E /* VGH_REG short to VGH, VGL_REG short to VGL, */ - 0x23 2 0x26 0xF3 /* VDDD from IOVCC&VCI */ - 0x23 2 0x37 0x09 /* SS=1, source scan from S2400 to S1;BGR=1 CF type is (S1,S2,S3) align to (B,G,R) */ - 0x23 2 0x38 0x04 /* JDT=100, display inversion type is column inversion */ - 0x23 2 0x39 0x00 /* Source EQ Setting, EQ1, 0x00=0us */ - 0x23 2 0x3A 0x01 /* Source EQ Setting, EQ2, 0x01 =0.1us */ - 0x23 2 0x3C 0x90 /* Source EQ Setting, EQ3, EQ3 start at 14.4us */ - 0x23 2 0x3D 0xFF /* SET Source OP on time, 0xFF means source op always on */ - 0x23 2 0x3E 0xFF /* SET Source OP off time, 0xFF means source op always on */ - 0x23 2 0x3F 0xFF /* SET Source OP off time, 0xFF means source op always on */ - 0x23 2 0x40 0x02 /* horizontal resolution setting,RSO[2:0]= 0x02 =600RGB, LN[1:0]=2'b00 */ - 0x23 2 0x41 0x80 /* LN[9:0]=0x200=512, vertical resolution is 512*2=1024 line */ - 0x23 2 0x42 0x99 /* SLT, internal line period=0x99->15.3us */ - 0x23 2 0x43 0x14 /* Internal VFP=Ext_VFP=20(0x14) */ - 0x23 2 0x44 0x19 /* Internal _VBP=Ext_VS+Ext_VBP-1=6+20-1=25(0x19) */ - 0x23 2 0x45 0x5A /* Internal_HBP=Ext_HS+Ext_HBP=90(0x5A) */ - 0x23 2 0x55 0x02 /* Seting PWRIC mode, DCDCM=0010-> FP7721BX2 */ - 0x23 2 0x56 0x01 /* No auto Ratio function */ - 0x23 2 0x57 0x69 /* VGH_RT=3'b011,2*AVDD-AVEE,VGL_RT=3'b010=AVEE+VCL-AVDD,VCL_RT=2'b00,0.5*VCIP */ - 0x23 2 0x58 0x0A /* AVDD_S, not use internal AVDD in this model */ - 0x23 2 0x59 0x0A /* VCL = -2.5V */ - 0x23 2 0x5A 0x2E /* VGH = 16.2V */ - 0x23 2 0x5B 0x19 /* VGL = -12V */ - 0x23 2 0x5C 0x15 /* pump clk, VCL_CLK[1:0]=2'b01=HCLK/2=32KHz, VGHVGL_CLK[1:0]=2'b01=HCLK/2=32KHz */ - 0x23 2 0x5D 0x77 /* Gamma voltage setting, VP255-4.793V */ - 0x23 2 0x5E 0x5C /* VP251 */ - 0x23 2 0x5F 0x4D /* VP247 */ - 0x23 2 0x60 0x40 /* VP243 */ - 0x23 2 0x61 0x3D /* VP235 */ - 0x23 2 0x62 0x2F /* VP227 */ - 0x23 2 0x63 0x34 /* VP211 */ - 0x23 2 0x64 0x1F /* VP191 */ - 0x23 2 0x65 0x38 /* VP159 */ - 0x23 2 0x66 0x38 /* VP128 */ - 0x23 2 0x67 0x39 /* VP96 */ - 0x23 2 0x68 0x58 /* VP64 */ - 0x23 2 0x69 0x48 /* VP44 */ - 0x23 2 0x6A 0x51 /* VP28 */ - 0x23 2 0x6B 0x44 /* VP20 */ - 0x23 2 0x6C 0x41 /* VP12 */ - 0x23 2 0x6D 0x35 /* VP8 */ - 0x23 2 0x6E 0x24 /* VP4 */ - 0x23 2 0x6F 0x02 /* VP0 */ - 0x23 2 0x70 0x77 /* VN255 */ - 0x23 2 0x71 0x5C /* VN251 */ - 0x23 2 0x72 0x4D /* VN247 */ - 0x23 2 0x73 0x40 /* VN243 */ - 0x23 2 0x74 0x3D /* VN235 */ - 0x23 2 0x75 0x2F /* VN227 */ - 0x23 2 0x76 0x34 /* VN211 */ - 0x23 2 0x77 0x1F /* VN191 */ - 0x23 2 0x78 0x38 /* VN159 */ - 0x23 2 0x79 0x38 /* VN128 */ - 0x23 2 0x7A 0x39 /* VN96 */ - 0x23 2 0x7B 0x58 /* VN64 */ - 0x23 2 0x7C 0x48 /* VN44 */ - 0x23 2 0x7D 0x51 /* VN28 */ - 0x23 2 0x7E 0x44 /* VN20 */ - 0x23 2 0x7F 0x41 /* VN12 */ - 0x23 2 0x80 0x35 /* VN8 */ - 0x23 2 0x81 0x24 /* VN4 */ - 0x23 2 0x82 0x02 /* VN0 */ - 0x23 2 0xE0 0x02 /* Register setting change to Page 2 */ - 0x23 2 0x00 0x53 /* GIP_L_Forward scan mapping, assign as RESET_EVEN */ - 0x23 2 0x01 0x55 /* assign as VSSG_EVEN */ - 0x23 2 0x02 0x55 /* assign as VSSA_EVEN */ - 0x23 2 0x03 0x51 /* assign as STV2_EVEN */ - 0x23 2 0x04 0x77 /* assign as VDD2_EVEN */ - 0x23 2 0x05 0x57 /* assign as VDD1_EVEN */ - 0x23 2 0x06 0x1F /* assign as VGL */ - 0x23 2 0x07 0x4F /* assign as CK12 */ - 0x23 2 0x08 0x4D /* assign as CK10 */ - 0x23 2 0x09 0x1F /* assign as VGL */ - 0x23 2 0x0A 0x4B /* assign as CK8 */ - 0x23 2 0x0B 0x49 /* assign as CK6 */ - 0x23 2 0x0C 0x1F /* assign as VGL */ - 0x23 2 0x0D 0x47 /* assign as CK4 */ - 0x23 2 0x0E 0x45 /* assign as CK2 */ - 0x23 2 0x0F 0x41 /* assign as STV1_EVEN */ - 0x23 2 0x10 0x1F /* assign as VGL */ - 0x23 2 0x11 0x1F /* assign as VGL */ - 0x23 2 0x12 0x1F /* assign as VGL */ - 0x23 2 0x13 0x55 /* assign as VGG */ - 0x23 2 0x14 0x1F /* assign as VGL */ - 0x23 2 0x15 0x1F /* assign as VGL */ - 0x23 2 0x16 0x52 /* GIP_R_Forward scan mapping, assign as RESET_ODD */ - 0x23 2 0x17 0x55 /* assign as VSSG_ODD */ - 0x23 2 0x18 0x55 /* assign as VSSA_ODD */ - 0x23 2 0x19 0x50 /* assign as STV2_ODD */ - 0x23 2 0x1A 0x77 /* assign as VDD2_ODD */ - 0x23 2 0x1B 0x57 /* assign as VDD1_ODD */ - 0x23 2 0x1C 0x1F /* assign as VGL */ - 0x23 2 0x1D 0x4E /* assign as CK11 */ - 0x23 2 0x1E 0x4C /* assign as CK9 */ - 0x23 2 0x1F 0x1F /* assign as VGL */ - 0x23 2 0x20 0x4A /* assign as CK7 */ - 0x23 2 0x21 0x48 /* assign as CK5 */ - 0x23 2 0x22 0x1F /* assign as VGL */ - 0x23 2 0x23 0x46 /* assign as CK3 */ - 0x23 2 0x24 0x44 /* assign as CK1 */ - 0x23 2 0x25 0x40 /* assign as STV1_ODD */ - 0x23 2 0x26 0x1F /* assign as VGL */ - 0x23 2 0x27 0x1F /* assign as VGL */ - 0x23 2 0x28 0x1F /* assign as VGL */ - 0x23 2 0x29 0x1F /* assign as VGL */ - 0x23 2 0x2A 0x1F /* assign as VGL */ - 0x23 2 0x2B 0x55 /* assign as VGG */ - 0x23 2 0x2C 0x12 /* GIP_L_Reverse Scan mapping, assign as RESET_EVEN */ - 0x23 2 0x2D 0x15 /* assign as VSSG_EVEN */ - 0x23 2 0x2E 0x15 /* assign as VSSA_EVEN */ - 0x23 2 0x2F 0x00 /* assign as STV2_EVEN */ - 0x23 2 0x30 0x17 /* assign as VDD2_EVEN */ - 0x23 2 0x31 0x17 /* assign as VDD1_EVEN */ - 0x23 2 0x32 0x1F /* assign as VGL */ - 0x23 2 0x33 0x08 /* assign as CK12 */ - 0x23 2 0x34 0x0A /* assign as CK10 */ - 0x23 2 0x35 0x1F /* assign as VGL */ - 0x23 2 0x36 0x0C /* assign as CK8 */ - 0x23 2 0x37 0x0E /* assign as CK6 */ - 0x23 2 0x38 0x1F /* assign as VGL */ - 0x23 2 0x39 0x04 /* assign as CK4 */ - 0x23 2 0x3A 0x06 /* assign as CK2 */ - 0x23 2 0x3B 0x10 /* assign as STV1_EVEN */ - 0x23 2 0x3C 0x1F /* assign as VGL */ - 0x23 2 0x3D 0x1F /* assign as VGL */ - 0x23 2 0x3E 0x1F /* assign as VGL */ - 0x23 2 0x3F 0x15 /* assign as VGG */ - 0x23 2 0x40 0x1F /* assign as VGL */ - 0x23 2 0x41 0x1F /* assign as VGL */ - 0x23 2 0x42 0x13 /* GIP_R_Reverse Scan mapping, assign as RESET_ODD */ - 0x23 2 0x43 0x15 /* assign as VSSG_ODD */ - 0x23 2 0x44 0x15 /* assign as VSSA_ODD */ - 0x23 2 0x45 0x01 /* assign as STV2_ODD */ - 0x23 2 0x46 0x17 /* assign as VDD2_ODD */ - 0x23 2 0x47 0x17 /* assign as VDD1_ODD */ - 0x23 2 0x48 0x1F /* assign as VGL */ - 0x23 2 0x49 0x09 /* assign as CK11 */ - 0x23 2 0x4A 0x0B /* assign as CK9 */ - 0x23 2 0x4B 0x1F /* assign as VGL */ - 0x23 2 0x4C 0x0D /* assign as CK7 */ - 0x23 2 0x4D 0x0F /* assign as CK5 */ - 0x23 2 0x4E 0x1F /* assign as VGL */ - 0x23 2 0x4F 0x05 /* assign as CK3 */ - 0x23 2 0x50 0x07 /* assign as CK1 */ - 0x23 2 0x51 0x11 /* assign as STV1_ODD */ - 0x23 2 0x52 0x1F /* assign as VGL */ - 0x23 2 0x53 0x1F /* assign as VGL */ - 0x23 2 0x54 0x1F /* assign as VGL */ - 0x23 2 0x55 0x1F /* assign as VGL */ - 0x23 2 0x56 0x1F /* assign as VGL */ - 0x23 2 0x57 0x15 /* assign as VGG */ - 0x23 2 0x58 0x40 /* GAS OPT=1, When abnormal power off, GIP will pull to VGH */ - 0x23 2 0x59 0x00 /* INIT_W=0, no INIT function in this panel */ - 0x23 2 0x5A 0x00 /* INIT[10:0], no INIT function in this panel */ - 0x23 2 0x5B 0x10 /* STV_NUM,STV_S0[10:8], 2 STV pulses */ - 0x23 2 0x5C 0x14 /* STV_S0[7:0], STV start from 21th hsync after vsync */ - 0x23 2 0x5D 0x40 /* STV_W=4, STV width is 4 Hline; STV1 delay 1 hline with STV0 */ - 0x23 2 0x5E 0x01 /* STV_S2, STV2 delay 2 hline with STV0 */ - 0x23 2 0x5F 0x02 /* STV_S3, STV3 delay 3 hline with STV0 */ - 0x23 2 0x60 0x40 /* ETV_W=4, ETV witdh is 4 hline; ETV1 delay 1 hilne from ETV0 */ - 0x23 2 0x61 0x03 /* ETV_S2, ETV2 delay 4 hline with ETV0 */ - 0x23 2 0x62 0x04 /* ETV_S3, ETV3 delay 5 hline with ETV0 */ - 0x23 2 0x63 0x7A /* SETV_ON for STV/ETV on time, rising at 12.2us after hsync */ - 0x23 2 0x64 0x7A /* SETV_OFF for STV/ETV off time , falling at 12.2us after hsync */ - 0x23 2 0x65 0x74 /* ETV_EN=1, enable ETV function; ETV_NUM=3, using 4 ETV pulse, */ - 0x23 2 0x66 0x16 /* ETV_S0=0x416, EVT start at 1046th hsync fater vaync */ - 0x23 2 0x67 0xB4 /* CKV_NUM=2'b1011, using 12 CKV pulse; CKV0_W=4. CKV width is 4 hline */ - 0x23 2 0x68 0x16 /* CKV0_S0 , CKV start from 23th hsync after vsync */ - 0x23 2 0x69 0x7A /* CKV0_on ,for CKV on time, rising at 12.2us after hsync */ - 0x23 2 0x6A 0x7A /* CKV0_off ,for CKV off time, falling at 12.2us after hsync */ - 0x23 2 0x6B 0x0C /* CKV0_DUM, total CKV pulse number=1024+12=1036 */ - 0x23 2 0x6C 0x00 /* GIP Line EQ option , disable GEQ_Line function */ - 0x23 2 0x6D 0x04 /* GIP rising EQ, period is 0.4us */ - 0x23 2 0x6E 0x04 /* GIP fallig EQ, period is 0.4us */ - 0x23 2 0x6F 0x88 /* GIP_DR; CKV0_CON, no continuous CKV0; CKV1_CON, no continuous CKV1 */ - 0x23 2 0x70 0x00 /* CKV1_NUM, CKV0_W , no CKV group 1 function in this panel, don't care */ - 0x23 2 0x71 0x00 /* CKV1_S0, no CKV group 1 function in this panel, don't care */ - 0x23 2 0x72 0x06 /* CKV1_on , no CKV group 1 function in this panel, don't care */ - 0x23 2 0x73 0x7B /* CKV1_off time, no CKV group 1 function in this panel, don't care */ - 0x23 2 0x74 0x00 /* CKV1_DUM, no CKV group 1 function in this panel, don't care */ - 0x23 2 0x75 0xBC /* FLM_EN, enable FLM function; FLM_W=0x3C, FLM toggle period is 60 frame */ - 0x23 2 0x76 0x00 /* FLM on time , FLM on(rising) at 1st hsync after vsync */ - 0x23 2 0x77 0x04 /* VEN_EN, VEN_W, no VEN function in this panel, don't care */ - 0x23 2 0x78 0x2C /* FLM_OFF, FLM off(falling) at 1068th hsync after vsync */ - 0x23 2 0x79 0x00 /* VEN_W , no VEN function in this panel, don't care */ - 0x23 2 0x7A 0x00 /* VEN_S0 , no VEN function in this panel, don't care */ - 0x23 2 0x7B 0x00 /* VEN_S1 , no VEN function in this panel, don't care */ - 0x23 2 0x7C 0x00 /* VEN_DUM , no VEN function in this panel, don't care */ - 0x23 2 0x7D 0x03 /* VEN on time , no VEN function in this panel, don't care */ - 0x23 2 0x7E 0x7B /* VEN off time , no VEN function in this panel, don't care */ - 0x23 2 0xE0 0x03 /* Register setting change to Page 3 */ - 0x23 2 0xAF 0x20 /* Set CABC, disable CABC TP detect, for CABC pattern change more smooth */ - 0x23 2 0xE0 0x04 /* Register setting change to Page 4 */ - 0x23 2 0x09 0x11 /* Source level at blanking period, sweeping V0 level */ - 0x23 2 0x0E 0x48 /* Source EQ option, EQ to PCAP,NCAP */ - 0x23 2 0x2B 0x2B /* ESD Protect, clock lane op behavior follow data lane, improve ESD performance */ - 0x23 2 0x2E 0x44 /* ESD protect, disable special packet */ - 0x23 2 0x41 0xFF /* Set CABC, for CABC pattern change more smooth */ - 0x23 2 0xE0 0x00 /* Register setting change to Page 0 */ - 0x23 2 0xE6 0x02 /* Enable Watch Dog */ - 0x23 2 0xE7 0x0C /* Watch Dog timer setting, WD alarm time is 12*512osc after hsync stop */ - 0x23 2 0x51 0xFF /* CABC Option, 0x80=50% duty, 0xFF=100% */ - 0x23 2 0x53 0x2C /* enable dimming, BCTRL, BL */ - 0x23 2 0x55 0x00 /* CABC mode, 0x00 is manual mode */ - 0x05 1 0x11 /* SLPOUT */ - 0xFF 125 /* Delay 125ms */ - 0x05 1 0x29 /* Display On */ - 0xFF 0xFF /* Ending */ - >; - init_off = < - 0xff 5 - 0x05 1 0x28 /* display off */ - 0xff 60 /* delay 60ms */ - 0x05 1 0x10 /* sleep in */ - 0xff 110 /* delay 110ms */ - 0xff 0xff>; /* ending */ - }; - - extern_4{ - index = <4>; - extern_name = "mipi_default"; // KD070D82_FT9365 - status = "okay"; - type = <2>; /* 0=i2c, 1=spi, 2=mipi */ - cmd_size = <0xff>; - init_on = < - 0x23 2 0xE0 0x00 - 0x23 2 0xE1 0x93 - 0x23 2 0xE2 0x65 - 0x23 2 0xE3 0xF8 - 0x23 2 0x80 0x03 - 0x23 2 0xE0 0x01 - 0x23 2 0x00 0x00 - 0x23 2 0x01 0x9E - 0x23 2 0x03 0x00 - 0x23 2 0x04 0xAA - 0x23 2 0x0C 0x74 - 0x23 2 0x17 0x00 - 0x23 2 0x18 0xEF - 0x23 2 0x19 0x00 - 0x23 2 0x1A 0x00 - 0x23 2 0x1B 0xEF - 0x23 2 0x1C 0x00 - 0x23 2 0x37 0x09 - 0x23 2 0x38 0x04 - 0x23 2 0x39 0x00 - 0x23 2 0x3A 0x01 - 0x23 2 0x3C 0x90 - 0x23 2 0x3D 0xFF - 0x23 2 0x3E 0xFF - 0x23 2 0x3F 0xFF - 0x23 2 0x40 0x02 - 0x23 2 0x41 0x80 - 0x23 2 0x42 0x99 - 0x23 2 0x43 0x14 - 0x23 2 0x44 0x19 - 0x23 2 0x45 0x5A - 0x23 2 0x55 0x02 - 0x23 2 0x56 0x01 - 0x23 2 0x57 0x69 - 0x23 2 0x58 0x0A - 0x23 2 0x59 0x0A - 0x23 2 0x5A 0x2E - 0x23 2 0x5B 0x19 - 0x23 2 0x5C 0x15 - 0x23 2 0x5D 0x77 - 0x23 2 0x5E 0x5C - 0x23 2 0x5F 0x4D - 0x23 2 0x60 0x40 - 0x23 2 0x61 0x3D - 0x23 2 0x62 0x2F - 0x23 2 0x63 0x34 - 0x23 2 0x64 0x1F - 0x23 2 0x65 0x38 - 0x23 2 0x66 0x38 - 0x23 2 0x67 0x39 - 0x23 2 0x68 0x58 - 0x23 2 0x69 0x48 - 0x23 2 0x6A 0x51 - 0x23 2 0x6B 0x44 - 0x23 2 0x6C 0x41 - 0x23 2 0x6D 0x35 - 0x23 2 0x6E 0x24 - 0x23 2 0x6F 0x02 - 0x23 2 0x70 0x77 - 0x23 2 0x71 0x5C - 0x23 2 0x72 0x4D - 0x23 2 0x73 0x40 - 0x23 2 0x74 0x3D - 0x23 2 0x75 0x2F - 0x23 2 0x76 0x34 - 0x23 2 0x77 0x1F - 0x23 2 0x78 0x38 - 0x23 2 0x79 0x38 - 0x23 2 0x7A 0x39 - 0x23 2 0x7B 0x58 - 0x23 2 0x7C 0x48 - 0x23 2 0x7D 0x51 - 0x23 2 0x7E 0x44 - 0x23 2 0x7F 0x41 - 0x23 2 0x80 0x35 - 0x23 2 0x81 0x24 - 0x23 2 0x82 0x02 - 0x23 2 0xE0 0x02 - 0x23 2 0x00 0x53 - 0x23 2 0x01 0x55 - 0x23 2 0x02 0x55 - 0x23 2 0x03 0x51 - 0x23 2 0x04 0x77 - 0x23 2 0x05 0x57 - 0x23 2 0x06 0x1F - 0x23 2 0x07 0x4F - 0x23 2 0x08 0x4D - 0x23 2 0x09 0x1F - 0x23 2 0x0A 0x4B - 0x23 2 0x0B 0x49 - 0x23 2 0x0C 0x1F - 0x23 2 0x0D 0x47 - 0x23 2 0x0E 0x45 - 0x23 2 0x0F 0x41 - 0x23 2 0x10 0x1F - 0x23 2 0x11 0x1F - 0x23 2 0x12 0x1F - 0x23 2 0x13 0x55 - 0x23 2 0x14 0x1F - 0x23 2 0x15 0x1F - 0x23 2 0x16 0x52 - 0x23 2 0x17 0x55 - 0x23 2 0x18 0x55 - 0x23 2 0x19 0x50 - 0x23 2 0x1A 0x77 - 0x23 2 0x1B 0x57 - 0x23 2 0x1C 0x1F - 0x23 2 0x1D 0x4E - 0x23 2 0x1E 0x4C - 0x23 2 0x1F 0x1F - 0x23 2 0x20 0x4A - 0x23 2 0x21 0x48 - 0x23 2 0x22 0x1F - 0x23 2 0x23 0x46 - 0x23 2 0x24 0x44 - 0x23 2 0x25 0x40 - 0x23 2 0x26 0x1F - 0x23 2 0x27 0x1F - 0x23 2 0x28 0x1F - 0x23 2 0x29 0x1F - 0x23 2 0x2A 0x1F - 0x23 2 0x2B 0x55 - 0x23 2 0x2C 0x12 - 0x23 2 0x2D 0x15 - 0x23 2 0x2E 0x15 - 0x23 2 0x2F 0x00 - 0x23 2 0x30 0x17 - 0x23 2 0x31 0x17 - 0x23 2 0x32 0x1F - 0x23 2 0x33 0x08 - 0x23 2 0x34 0x0A - 0x23 2 0x35 0x1F - 0x23 2 0x36 0x0C - 0x23 2 0x37 0x0E - 0x23 2 0x38 0x1F - 0x23 2 0x39 0x04 - 0x23 2 0x3A 0x06 - 0x23 2 0x3B 0x10 - 0x23 2 0x3C 0x1F - 0x23 2 0x3D 0x1F - 0x23 2 0x3E 0x1F - 0x23 2 0x3F 0x15 - 0x23 2 0x40 0x1F - 0x23 2 0x41 0x1F - 0x23 2 0x42 0x13 - 0x23 2 0x43 0x15 - 0x23 2 0x44 0x15 - 0x23 2 0x45 0x01 - 0x23 2 0x46 0x17 - 0x23 2 0x47 0x17 - 0x23 2 0x48 0x1F - 0x23 2 0x49 0x09 - 0x23 2 0x4A 0x0B - 0x23 2 0x4B 0x1F - 0x23 2 0x4C 0x0D - 0x23 2 0x4D 0x0F - 0x23 2 0x4E 0x1F - 0x23 2 0x4F 0x05 - 0x23 2 0x50 0x07 - 0x23 2 0x51 0x11 - 0x23 2 0x52 0x1F - 0x23 2 0x53 0x1F - 0x23 2 0x54 0x1F - 0x23 2 0x55 0x1F - 0x23 2 0x56 0x1F - 0x23 2 0x57 0x15 - 0x23 2 0x58 0x40 - 0x23 2 0x59 0x00 - 0x23 2 0x5A 0x00 - 0x23 2 0x5B 0x10 - 0x23 2 0x5C 0x14 - 0x23 2 0x5D 0x40 - 0x23 2 0x5E 0x01 - 0x23 2 0x5F 0x02 - 0x23 2 0x60 0x40 - 0x23 2 0x61 0x03 - 0x23 2 0x62 0x04 - 0x23 2 0x63 0x7A - 0x23 2 0x64 0x7A - 0x23 2 0x65 0x74 - 0x23 2 0x66 0x16 - 0x23 2 0x67 0xB4 - 0x23 2 0x68 0x16 - 0x23 2 0x69 0x7A - 0x23 2 0x6A 0x7A - 0x23 2 0x6B 0x0C - 0x23 2 0x6C 0x00 - 0x23 2 0x6D 0x04 - 0x23 2 0x6E 0x04 - 0x23 2 0x6F 0x88 - 0x23 2 0x70 0x00 - 0x23 2 0x71 0x00 - 0x23 2 0x72 0x06 - 0x23 2 0x73 0x7B - 0x23 2 0x74 0x00 - 0x23 2 0x75 0xBC - 0x23 2 0x76 0x00 - 0x23 2 0x77 0x04 - 0x23 2 0x78 0x2C - 0x23 2 0x79 0x00 - 0x23 2 0x7A 0x00 - 0x23 2 0x7B 0x00 - 0x23 2 0x7C 0x00 - 0x23 2 0x7D 0x03 - 0x23 2 0x7E 0x7B - 0x23 2 0xE0 0x03 - 0x23 2 0xA9 0x02 - 0x23 2 0xAC 0x4D - 0x23 2 0xE0 0x04 - 0x23 2 0x00 0x0E - 0x23 2 0x02 0xB3 - 0x23 2 0x09 0x60 - 0x23 2 0x0E 0x48 - 0x23 2 0xE0 0x00 - 0x23 2 0x51 0xFF - 0x23 2 0x53 0x2C - 0x23 2 0x55 0x00 - 0x05 1 0x11 - 0xFF 125 /* Delay 125ms */ - 0x23 2 0xE0 0x01 - 0x23 2 0x35 0x24 - 0x23 2 0xE0 0x04 - 0x23 2 0x09 0x61 - 0x23 2 0xE0 0x00 - 0x05 1 0x29 - 0xFF 20 /* Delay 20ms */ - 0x23 2 0x35 0x00 - 0xFF 0xFF /* Ending */ - >; - init_off = < - 0xff 5 - 0x05 1 0x28 /* display off */ - 0xff 60 /* delay 60ms */ - 0x05 1 0x10 /* sleep in */ - 0xff 110 /* delay 110ms */ - 0xff 0xff>; /* ending */ - }; - - extern_5{ - index = <5>; - extern_name = "mipi_default"; // TV070WSM_ST7703I - status = "okay"; - type = <2>; /* 0=i2c, 1=spi, 2=mipi */ - cmd_size = <0xff>; - init_on = < - 0x29 4 0xB9 0xF1 0x12 0x83 - 0x29 4 0xB2 0x88 0x04 0xF0 - 0x29 11 0xB3 0x0C 0x0C 0x28 0x28 0x03 0xFF 0x00 0x00 0x00 0x00 - 0x23 2 0xB4 0xE0 - 0x29 3 0xB5 0x08 0x08 - 0x29 5 0xB8 0x25 0x22 0xF0 0x63 - 0x29 28 0xBA 0x33 0x81 0x05 0xF9 0x0E 0x0E 0x20 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x44 0x25 0x00 0x90 0x0A 0x00 0x00 0x01 0x4F 0x01 0x00 0x00 0x37 - 0x23 2 0xBC 0x47 - 0x29 4 0xBF 0x02 0x11 0x00 - 0x29 10 0xC0 0xFF 0xFF 0x50 0x50 0xA0 0x00 0x12 0xF0 0x00 - 0x29 13 0xC1 0x54 0xC0 0x32 0x32 0x77 0xF1 0xEF 0xEF 0xAE 0xAE 0x9E 0x9E - 0x29 7 0xC6 0x02 0x00 0xFF 0xFF 0x08 0xFF - 0x29 7 0xC7 0x10 0x00 0x0A 0x00 0x00 0x07 - 0x23 2 0xCC 0x0B - 0x29 35 0xE0 0x00 0x09 0x0E 0x27 0x39 0x3F 0x41 0x37 0x06 0x0C 0x0E 0x12 0x14 0x12 0x13 0x10 0x18 0x00 0x09 0x0E 0x27 0x39 0x3F 0x41 0x37 0x06 0x0C 0x0E 0x12 0x14 0x12 0x13 0x10 0x18 - 0x29 35 0xCD 0x07 0x80 0x81 0x84 0x83 0x81 0x84 0x82 0x81 0x82 0x80 0x7F 0x80 0x80 0x80 0x81 0x81 0x80 0x7F 0x7E 0x7F 0x80 0x82 0x84 0x84 0x83 0x84 0x81 0x7E 0x83 0x7E 0x7C 0x80 0x83 - 0x29 34 0xCE 0x80 0x81 0x84 0x83 0x81 0x84 0x82 0x81 0x82 0x80 0x7F 0x80 0x80 0x80 0x81 0x81 0x80 0x7F 0x7E 0x7F 0x80 0x82 0x84 0x84 0x83 0x84 0x81 0x7E 0x83 0x7E 0x7C 0x80 0x83 - 0x29 34 0xCF 0x80 0x81 0x84 0x83 0x81 0x84 0x82 0x81 0x82 0x80 0x7F 0x80 0x80 0x80 0x81 0x81 0x80 0x7F 0x7E 0x7F 0x80 0x82 0x84 0x84 0x83 0x84 0x81 0x7E 0x83 0x7E 0x7C 0x80 0x83 - 0x29 15 0xE3 0x03 0x03 0x03 0x03 0x10 0x10 0x00 0x00 0x00 0x00 0x28 0x00 0xC0 0x10 - 0x29 64 0xE9 0xC2 0x10 0x01 0x00 0x00 0x80 0x81 0x12 0x31 0x23 0x21 0x80 0x80 0x81 0x23 0x24 0x00 0x00 0x30 0x00 0x00 0x00 0x00 0x00 0x30 0x00 0x00 0x00 0x11 0x33 0x11 0x88 0x88 0x88 0x88 0x88 0x88 0x88 0x88 0x00 0x22 0x00 0x88 0x88 0x88 0x88 0x88 0x88 0x88 0x88 0x00 0x00 0x00 0x01 0x0D 0x80 0x81 0x14 0x00 0x00 0x00 0x00 0x00 - 0x29 62 0xEA 0x96 0x0C 0x02 0x02 0x02 0xB4 0x00 0x00 0x00 0x00 0x00 0x00 0x22 0x00 0x00 0x88 0x88 0x88 0x88 0x88 0x88 0x88 0x88 0x11 0x33 0x11 0x88 0x88 0x88 0x88 0x88 0x88 0x88 0x88 0x23 0x07 0x00 0x00 0xD6 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x10 0x00 0x01 0x10 0x00 0x00 0x00 - 0x05 1 0x11 - 0xff 150 /* Delay 150ms */ - 0x05 1 0x29 - 0xff 50 /* Delay 50ms */ - 0xff 0xff /* Ending */ - >; - init_off = < - 0xff 5 - 0x05 1 0x28 /* display off */ - 0xff 60 /* delay 60ms */ - 0x05 1 0x10 /* sleep in */ - 0xff 110 /* delay 110ms */ - 0xff 0xff>; /* ending */ - }; - }; - - backlight{ - compatible = "amlogic, backlight-g12a"; - status = "okay"; - key_valid = <0>; - pinctrl-names = "pwm_on","pwm_off"; - pinctrl-0 = <&pwm_f_pins2>; - pinctrl-1 = <&bl_pwm_off_pins>; - pinctrl_version = <2>; /* for uboot */ - bl_pwm_config = <&bl_pwm_conf>; - bl-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_HIGH - &gpio GPIOH_5 GPIO_ACTIVE_HIGH>; - bl_gpio_names = "GPIOH_4","GPIOH_5"; - - /* pwm port: PWM_A, PWM_B, PWM_C, PWM_D, PWM_E, PWM_F, PWM_VS*/ - /* power index:(point gpios_index, 0xff=invalid) - * power value:(0=output low, 1=output high, 2=input) - * power delay:(unit in ms) - */ - - backlight_0{ - index = <0>; - bl_name = "backlight_pwm"; - bl_level_default_uboot_kernel = <100 100>; - bl_level_attr = <255 10 /*max, min*/ - 128 128>; /*mid, mid_mapping*/ - bl_ctrl_method = <1>; /* 1=pwm, 2=pwm_combo, 4=extern */ - bl_power_attr = <0 /*en_gpio_index*/ - 1 0 /*on_value, off_value*/ - 200 200>; /*on_delay(ms), off_delay(ms)*/ - bl_pwm_port = "PWM_F"; - bl_pwm_attr = <0 /*pwm_method*/ - 180 /*pwm_freq(pwm:Hz, pwm_vs:multiple of vs)*/ - 100 25>; /*duty_max(%), duty_min(%)*/ - bl_pwm_power = <1 1 /*pwm_gpio_index, pwm_gpio_off*/ - 10 10>; /*pwm_on_delay(ms), pwm_off_delay(ms)*/ - bl_pwm_en_sequence_reverse = <0>; /* 1 for reverse */ - }; - backlight_1{ - index = <1>; - bl_name = "bl_extern"; - bl_level_default_uboot_kernel = <100 100>; - bl_level_attr = <255 10 /*max, min*/ - 128 128>; /*mid, mid_mapping*/ - bl_ctrl_method = <4>; /*1=pwm, 2=pwm_combo, 4=extern*/ - bl_power_attr = <1 /*en_gpio_index*/ - 1 0 /*on_value, off_value*/ - 200 200>; /*on_delay(ms), off_delay(ms)*/ - bl_extern_index = <0>; - }; - }; - bl_pwm_conf:bl_pwm_conf{ - pwm_channel_0 { - pwm_port_index = <5>; - pwms = <&pwm_ef MESON_PWM_1 30040 0>; - }; - }; - - bl_extern{ - compatible = "amlogic, bl_extern"; - status = "disabled"; - i2c_bus = "i2c_bus_3"; - - extern_0{ - index = <0>; - extern_name = "i2c_lp8556"; - type = <0>; /*0=i2c, 1=spi, 2=mipi*/ - i2c_address = <0x2c>; /*7bit i2c address*/ - dim_max_min = <255 10>; - }; - - extern_1{ - index = <1>; - extern_name = "mipi_lt070me05"; - type = <2>; /*0=i2c, 1=spi, 2=mipi*/ - dim_max_min = <255 10>; - }; - }; -};/* end of panel */
diff --git a/arch/arm/dts/elaine-p0-panel.dtsi b/arch/arm/dts/elaine-p0-panel.dtsi deleted file mode 100755 index dbbbf62..0000000 --- a/arch/arm/dts/elaine-p0-panel.dtsi +++ /dev/null
@@ -1,1169 +0,0 @@ -/* - * arch/arm64/boot/dts/amlogic/estelle-sm1-panel.dtsi - * - * Copyright (C) 2016 Amlogic, Inc. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - */ - -/ { - lcd{ - compatible = "amlogic, lcd-sm1"; - mode = "tablet"; - status = "okay"; - key_valid = <0>; - clocks = <&clkc CLKID_MIPI_DSI_HOST - &clkc CLKID_MIPI_DSI_PHY - &clkc CLKID_DSI_MEAS_COMP - &clkc CLKID_VCLK2_ENCL - &clkc CLKID_VCLK2_VENCL - &clkc CLKID_GP0_PLL>; - clock-names = "dsi_host_gate", - "dsi_phy_gate", - "dsi_meas", - "encl_top_gate", - "encl_int_gate", - "gp0_pll"; - reg = <0x0 0xffd07000 0x0 0x400 /* dsi_host */ - 0x0 0xff644000 0x0 0x200>; /* dsi_phy */ - interrupts = <0 3 1 - 0 56 1>; - interrupt-names = "vsync","vsync2"; - pinctrl_version = <2>; /* for uboot */ - - /* power type: - * (0=cpu_gpio, 1=pmu_gpio, 2=signal,3=extern, 0xff=ending) - * power index: - * (point gpios_index, or extern_index,0xff=invalid) - * power value:(0=output low, 1=output high, 2=input) - * power delay:(unit in ms) - */ - lcd_cpu-gpios = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>; - lcd_cpu_gpio_names = "GPIOH_6"; - - lcd_1{ - model_name = "TV070WSM"; - interface = "mipi"; - basic_setting = <600 1024 /*h_active, v_active*/ - 700 1053 /*h_period, v_period*/ - 8 /*lcd_bits*/ - 95 163>; /*screen_widht, screen_height*/ - lcd_timing = <24 36 0 /*hs_width,hs_bp,hs_pol*/ - 2 8 0>; /*vs_width,vs_bp,vs_pol*/ - clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/ - 0 /*clk_ss_level*/ - 1 /*clk_auto_generate*/ - 44250000>; /*pixel_clk(unit in Hz)*/ - mipi_attr = <4 /*lane_num*/ - 360 /*bit_rate_max(MHz)*/ - 0 /*factor(*100, default 0 for auto)*/ - 1 /*operation_mode_init(0=video, 1=command)*/ - 0 /*operation_mode_display(0=video, 1=command)*/ - 2 /* - *video_mode_type - *(0=sync_pulse,1=sync_event,2=burst) - */ - 0 /*clk_always_hs(0=disable,1=enable)*/ - 0>; /*phy_switch(0=auto,1=standard,2=slow)*/ - /* dsi_init: data_type, num, data... */ - dsi_init_on = < - 0xff 10 /* delay 10 ms */ - 0xf0 3 0 1 30 /* reset high, delay 30ms */ - 0xf0 3 0 0 10 /* reset low, delay 10ms */ - 0xf0 3 0 1 30 /* reset high, delay 30ms */ - 0xfc 2 4 3 /* mipi state check */ - 0xff 10 /* delay 10 ms */ - 0xff 0xff>; /* ending flag */ - dsi_init_off = <0xff 0xff>; /* ending flag */ - /* extern_init: 0xff for invalid */ - extern_init = <1>; - /* power step: type,index,value,delay(ms) */ - power_on_step = < - 2 0 0 0 - 0xff 0 0 0>; - power_off_step = < - 2 0 0 50 - 0 0 0 100 - 0xff 0 0 0>; - backlight_index = <0>; - }; - - lcd_2{ - model_name = "P070ACB"; - interface = "mipi"; - basic_setting = <600 1024 /*h_active, v_active*/ - 680 1194 /*h_period, v_period*/ - 8 /*lcd_bits*/ - 3 5>; /*screen_widht, screen_height*/ - lcd_timing = <24 36 0 /*hs_width,hs_bp,hs_pol*/ - 10 80 0>; /*vs_width,vs_bp,vs_pol*/ - clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/ - 0 /*clk_ss_level*/ - 1 /*clk_auto_generate*/ - 48715200>; /*pixel_clk(unit in Hz)*/ - mipi_attr = <4 /*lane_num*/ - 400 /*bit_rate_max(MHz)*/ - 0 /*factor(*100, default 0 for auto)*/ - 1 /*operation_mode_init(0=video, 1=command)*/ - 0 /*operation_mode_display(0=video, 1=command)*/ - 2 /* - *video_mode_type - *(0=sync_pulse,1=sync_event,2=burst) - */ - 0 /*clk_always_hs(0=disable,1=enable)*/ - 0>; /*phy_switch(0=auto,1=standard,2=slow)*/ - /* dsi_init: data_type, num, data... */ - dsi_init_on = < - 0xff 10 /* delay 10ms */ - 0xf0 3 0 1 30 /* reset high, delay 30ms */ - 0xf0 3 0 0 10 /* reset low, delay 10ms */ - 0xf0 3 0 1 30 /* reset high, delay 30ms */ - 0xfc 2 4 3 /* mipi state check */ - 0xff 10 /* delay 10 ms */ - 0xff 0xff>; /* ending flag */ - dsi_init_off = <0xff 0xff>; /* ending flag */ - /* extern_init: 0xff for invalid */ - extern_init = <2>; - /* power step: type,index,value,delay(ms) */ - power_on_step = < - 2 0 0 0 - 0xff 0 0 0>; - power_off_step = < - 2 0 0 50 - 0 0 0 100 - 0xff 0 0 0>; - backlight_index = <1>; - }; - - lcd_3{ - model_name = "TV070WSM_FT"; - interface = "mipi"; - basic_setting = <600 1024 /*h_active, v_active*/ - 700 1053 /*h_period, v_period*/ - 8 /*lcd_bits*/ - 95 163>; /*screen_widht, screen_height*/ - lcd_timing = <24 36 0 /*hs_width,hs_bp,hs_pol*/ - 2 8 0>; /*vs_width,vs_bp,vs_pol*/ - clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/ - 0 /*clk_ss_level*/ - 1 /*clk_auto_generate*/ - 48715200>; /*pixel_clk(unit in Hz)*/ - mipi_attr = <4 /*lane_num*/ - 400 /*bit_rate_max(MHz)*/ - 0 /*factor(*100, default 0 for auto)*/ - 1 /*operation_mode_init(0=video, 1=command)*/ - 0 /*operation_mode_display(0=video, 1=command)*/ - 2 /* - *video_mode_type - *(0=sync_pulse,1=sync_event,2=burst) - */ - 0 /*clk_always_hs(0=disable,1=enable)*/ - 0>; /*phy_switch(0=auto,1=standard,2=slow)*/ - /* dsi_init: data_type, num, data... */ - dsi_init_on = < - 0xff 10 - 0xf0 3 0 1 30 /* reset high, delay 30ms */ - 0xf0 3 0 0 10 /* reset low, delay 10ms */ - 0xf0 3 0 1 30 /* reset high, delay 30ms */ - 0xfc 2 0x04 3 /* check_reg, check_cnt */ - 0xff 0xff>; /* ending flag */ - dsi_init_off = <0xff 0xff>; /* ending flag */ - /* extern_init: 0xff for invalid */ - extern_init = <3>; - /* power step: type,index,value,delay(ms) */ - power_on_step = < - 0 1 0 200 - 2 0 0 0 - 0xff 0 0 0>; - power_off_step = < - 2 0 0 0 - 0 0 0 20 - 0 1 1 100 - 0xff 0 0 0>; - backlight_index = <0>; - }; - - lcd_4{ - model_name = "P070ACB_FT"; - interface = "mipi"; - basic_setting = <600 1024 /*h_active, v_active*/ - 770 1070 /*h_period, v_period*/ - 8 /*lcd_bits*/ - 3 5>; /*screen_widht, screen_height*/ - lcd_timing = <10 80 0 /*hs_width,hs_bp,hs_pol*/ - 6 20 0>; /*vs_width,vs_bp,vs_pol*/ - clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/ - 0 /*clk_ss_level*/ - 1 /*clk_auto_generate*/ - 49434000>; /*pixel_clk(unit in Hz)*/ - mipi_attr = <4 /*lane_num*/ - 400 /*bit_rate_max(MHz)*/ - 0 /*factor(*100, default 0 for auto)*/ - 1 /*operation_mode_init(0=video, 1=command)*/ - 0 /*operation_mode_display(0=video, 1=command)*/ - 2 /* - *video_mode_type - *(0=sync_pulse,1=sync_event,2=burst) - */ - 0 /*clk_always_hs(0=disable,1=enable)*/ - 0>; /*phy_switch(0=auto,1=standard,2=slow)*/ - /* dsi_init: data_type, num, data... */ - dsi_init_on = < - 0xff 10 - 0xf0 3 0 1 30 /* reset high, delay 30ms */ - 0xf0 3 0 0 10 /* reset low, delay 10ms */ - 0xf0 3 0 1 30 /* reset high, delay 30ms */ - 0xfc 2 0x04 3 /* check_reg, check_cnt */ - 0xff 0xff>; /* ending flag */ - dsi_init_off = <0xff 0xff>; /* ending flag */ - /* extern_init: 0xff for invalid */ - extern_init = <4>; - /* power step: type,index,value,delay(ms) */ - power_on_step = < - 0 1 0 200 /* panel power on */ - 2 0 0 0 - 0xff 0 0 0>; - power_off_step = < - 2 0 0 0 - 0 0 0 20 /* reset low */ - 0 1 1 100 /* panel power off */ - 0xff 0 0 0>; - backlight_index = <0>; - }; - }; - - lcd_extern{ - compatible = "amlogic, lcd_extern"; - dev_name = "lcd_extern"; - status = "okay"; - key_valid = <0>; - - extern_1{ - index = <1>; - extern_name = "mipi_default"; //TV070WSM - status = "okay"; - type = <2>; /* 0=i2c, 1=spi, 2=mipi */ - cmd_size = <0xff>; - init_on = < - 0xfd 1 100 /* delay */ - 0x15 2 0x62 0x01 - 0x39 5 0xff 0xaa 0x55 0x25 0x01 - 0x15 2 0xfc 0x08 - 0xff 1 /* delay */ - 0x15 2 0xfc 0x00 - 0x39 5 0xff 0xaa 0x55 0x25 0x00 - 0xff 20 /* delay */ - 0x39 6 0xf0 0x55 0xaa 0x52 0x08 0x00 - 0x39 3 0xb1 0x68 0x41 - 0x15 2 0xb5 0x88 - 0x15 2 0xb6 0x0f - 0x39 5 0xb8 0x01 0x01 0x12 0x01 - 0x39 3 0xbb 0x11 0x11 - 0x39 3 0xbc 0x05 0x05 - 0x15 2 0xc7 0x03 - 0x39 6 0xbd 0x03 0x02 0x19 0x17 0x00 - 0x15 2 0xc8 0x80 - 0x39 6 0xf0 0x55 0xaa 0x52 0x08 0x01 - 0x39 3 0xB2 0x01 0x01 - 0x39 3 0xB3 0x28 0x28 - 0x39 3 0xB4 0x14 0x14 - 0x39 3 0xB8 0x05 0x05 - 0x39 3 0xB9 0x45 0x45 - 0x39 3 0xBA 0x25 0x25 - 0x39 3 0xBC 0x88 0x00 - 0x39 3 0xBD 0x88 0x00 - 0x39 6 0xF0 0x55 0xAA 0x52 0x08 0x02 - 0x15 2 0xEE 0x00 - 0x39 17 0xB0 0x00 0x4B 0x00 0x5C 0x00 0x79 0x00 0x94 0x00 0xA6 0x00 0xD8 0x00 0xF2 0x01 0x19 - 0x39 17 0xB1 0x01 0x39 0x01 0x77 0x01 0xA2 0x01 0xF2 0x02 0x32 0x02 0x34 0x02 0x6D 0x02 0xA2 - 0x39 17 0xB2 0x02 0xC7 0x02 0xF2 0x03 0x18 0x03 0x43 0x03 0x65 0x03 0x86 0x03 0x8F 0x03 0x94 - 0x39 5 0xB3 0x03 0x96 0x03 0x98 - 0x39 17 0xB4 0x00 0x84 0x00 0x91 0x00 0xA4 0x00 0xB6 0x00 0xCA 0x00 0xE9 0x01 0x02 0x01 0x2A - 0x39 17 0xB5 0x01 0x49 0x01 0x82 0x01 0xAF 0x01 0xF7 0x02 0x36 0x02 0x38 0x02 0x70 0x02 0xA6 - 0x39 17 0xB6 0x02 0xC8 0x02 0xF5 0x03 0x1A 0x03 0x43 0x03 0x62 0x03 0x82 0x03 0x8F 0x03 0x94 - 0x39 5 0xB7 0x03 0x96 0x03 0x98 - 0x39 17 0xB8 0x01 0x22 0x01 0x27 0x01 0x2E 0x01 0x38 0x01 0x40 0x01 0x53 0x01 0x60 0x01 0x7B - 0x39 17 0xB9 0x01 0x8C 0x01 0xB5 0x01 0xD3 0x02 0x11 0x02 0x49 0x02 0x4A 0x02 0x7F 0x02 0xB1 - 0x39 17 0xBA 0x02 0xD1 0x03 0x00 0x03 0x22 0x03 0x49 0x03 0x60 0x03 0x7A 0x03 0x8B 0x03 0x8F - 0x39 5 0xBB 0x03 0x93 0x03 0x9A - 0x39 17 0xBC 0x00 0x37 0x00 0x48 0x00 0x65 0x00 0x80 0x00 0x92 0x00 0xC4 0x00 0xDE 0x01 0x05 - 0x39 17 0xBD 0x01 0x31 0x01 0x6F 0x01 0x9E 0x01 0xEE 0x02 0x32 0x02 0x34 0x02 0x71 0x02 0xA7 - 0x39 17 0xBE 0x02 0xD3 0x02 0xFE 0x03 0x24 0x03 0x4F 0x03 0x71 0x03 0x92 0x03 0x9B 0x03 0xA0 - 0x39 5 0xBF 0x03 0xA6 0x03 0xA8 - 0x39 17 0xC0 0x00 0x70 0x00 0x7D 0x00 0x90 0x00 0xA4 0x00 0xB6 0x00 0xD5 0x00 0xEE 0x01 0x16 - 0x39 17 0xC1 0x01 0x41 0x01 0x7A 0x01 0xAB 0x01 0xF3 0x02 0x36 0x02 0x38 0x02 0x74 0x02 0xAA - 0x39 17 0xC2 0x02 0xD4 0x03 0x01 0x03 0x26 0x03 0x4F 0x03 0x6E 0x03 0x8E 0x03 0x9B 0x03 0xA0 - 0x39 5 0xC3 0x03 0xA6 0x03 0xA8 - 0x39 17 0xC4 0x01 0x0E 0x01 0x13 0x01 0x1A 0x01 0x24 0x01 0x2C 0x01 0x3F 0x01 0x4C 0x01 0x67 - 0x39 17 0xC5 0x01 0x84 0x01 0xAD 0x01 0xCF 0x02 0x0D 0x02 0x49 0x02 0x4A 0x02 0x83 0x02 0xB5 - 0x39 17 0xC6 0x02 0xDD 0x03 0x0C 0x03 0x2E 0x03 0x55 0x03 0x6B 0x03 0x86 0x03 0x97 0x03 0x9B - 0x39 5 0xC7 0x03 0xA1 0x03 0xA8 - 0x39 6 0xF0 0x55 0xAA 0x52 0x08 0x04 - 0x39 6 0xB1 0x03 0x02 0x02 0x02 0x00 - 0x39 6 0xF0 0x55 0xAA 0x52 0x08 0x06 - 0x39 3 0xB0 0x11 0x11 - 0x39 3 0xB1 0x13 0x13 - 0x39 3 0xB2 0x03 0x03 - 0x39 3 0xB3 0x34 0x34 - 0x39 3 0xB4 0x34 0x34 - 0x39 3 0xB5 0x34 0x34 - 0x39 3 0xB6 0x34 0x34 - 0x39 3 0xB7 0x34 0x34 - 0x39 3 0xB8 0x34 0x34 - 0x39 3 0xB9 0x34 0x34 - 0x39 3 0xBA 0x34 0x34 - 0x39 3 0xBB 0x34 0x34 - 0x39 3 0xBC 0x34 0x34 - 0x39 3 0xBD 0x34 0x34 - 0x39 3 0xBE 0x34 0x34 - 0x39 3 0xBF 0x34 0x34 - 0x39 3 0xC0 0x34 0x34 - 0x39 3 0xC1 0x02 0x02 - 0x39 3 0xC2 0x12 0x12 - 0x39 3 0xC3 0x10 0x10 - 0x39 3 0xE5 0x34 0x34 - 0x39 6 0xD8 0x00 0x00 0x00 0x00 0x00 - 0x39 6 0xD9 0x00 0x00 0x00 0x00 0x00 - 0x39 6 0xF0 0x55 0xAA 0x52 0x08 0x05 - 0x15 2 0xC0 0x03 - 0x15 2 0xC1 0x02 - 0x39 3 0xC8 0x01 0x20 - 0x15 2 0xE5 0x03 - 0x15 2 0xE6 0x03 - 0x15 2 0xE7 0x03 - 0x15 2 0xE8 0x03 - 0x15 2 0xE9 0x03 - 0x39 5 0xD1 0x03 0x00 0x3D 0x00 - 0x39 6 0xF0 0x55 0xAA 0x52 0x08 0x03 - 0x39 3 0xB0 0x11 0x00 - 0x39 3 0xB1 0x11 0x00 - 0x39 6 0xB2 0x03 0x00 0x00 0x00 0x00 - 0x39 6 0xB3 0x03 0x00 0x00 0x00 0x00 - 0x39 6 0xBA 0x31 0x00 0x00 0x00 0x00 - 0x15 2 0x35 0x00 - 0x15 2 0x51 0xFF - 0x15 2 0x53 0x2C - 0x15 2 0x55 0x03 - 0x05 1 0x11 - 0xfd 1 120 /* delay 120ms */ - 0x05 1 0x29 - 0xff 0xff /* ending */ - >; - init_off = < - 0x05 1 0x28 /* display off */ - 0xff 10 /* delay 10ms */ - 0x05 1 0x10 /* sleep in */ - 0xff 150 /* delay 150ms */ - 0xff 0xff>; /*ending*/ - }; - - extern_2{ - index = <2>; - extern_name = "mipi_default"; //P070ACB - status = "okay"; - type = <2>; /* 0=i2c, 1=spi, 2=mipi */ - cmd_size = <0xff>; - init_on = < - 0xfd 1 100 /* delay */ - 0x15 2 0x62 0x01 - 0x29 5 0xFF 0xAA 0x55 0x25 0x01 - 0x23 2 0xFC 0x08 - 0xfd 1 1 /* delay(ms) */ - 0x23 2 0xFC 0x00 - - 0xfd 1 1 /* delay(ms) */ - 0x23 2 0x6F 0x21 - 0x23 2 0xF7 0x01 - 0xfd 1 1 /* delay(ms) */ - 0x23 2 0x6F 0x21 - 0x23 2 0xF7 0x00 - 0xfd 1 1 /* delay(ms) */ - - 0x23 2 0x6F 0x1A - 0x23 2 0xF7 0x05 - 0xfd 1 1 /* delay(ms) */ - - 0x29 5 0xFF 0xAA 0x55 0x25 0x00 - - 0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x00 - 0x29 3 0xB1 0x68 0x41 - 0x23 2 0xB5 0x88 - 0x29 6 0xBD 0x02 0xB0 0x0C 0x14 0x00 - 0x23 2 0xC8 0x80 - - 0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x01 - 0x29 3 0xB3 0x2D 0x2D - 0x29 3 0xB4 0x19 0x19 - 0x23 2 0xB5 0x06 - - 0x29 3 0xB9 0x36 0x36 - 0x29 3 0xBA 0x26 0x26 - 0x29 3 0xBC 0xA8 0x01 - 0x29 3 0xBD 0xAB 0x01 - 0x23 2 0xC0 0x0C - - 0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x02 - 0x23 2 0xEE 0x02 - 0x29 7 0xB0 0x00 0x50 0x00 0x52 0x00 0x73 - 0x23 2 0x6F 0x06 - 0x29 7 0xB0 0x00 0x8F 0x00 0xA5 0x00 0xCA - 0x23 2 0x6F 0x0C - 0x29 5 0xB0 0x00 0xEA 0x01 0x1B - 0x29 7 0xB1 0x01 0x42 0x01 0x82 0x01 0xB3 - 0x23 2 0x6F 0x06 - 0x29 7 0xB1 0x02 0x00 0x02 0x41 0x02 0x42 - 0x23 2 0x6F 0x0C - 0x29 5 0xB1 0x02 0x78 0x02 0xB5 - 0x29 7 0xB2 0x02 0xDA 0x03 0x12 0x03 0x3A - 0x23 2 0x6F 0x06 - 0x29 7 0xB2 0x03 0x6E 0x03 0x8D 0x03 0xB1 - 0x23 2 0x6F 0x0C - 0x29 5 0xB2 0x03 0xCA 0x03 0xE8 - 0x29 5 0xB3 0x03 0xF4 0x03 0xFF - - 0x29 7 0xBC 0x00 0x05 0x00 0x52 0x00 0x73 - 0x23 2 0x6F 0x06 - 0x29 7 0xBC 0x00 0x8F 0x00 0xA5 0x00 0xCA - 0x23 2 0x6F 0x0C - 0x29 5 0xBC 0x00 0xEA 0x01 0x1B - 0x29 7 0xBD 0x01 0x42 0x01 0x82 0x01 0xB3 - 0x23 2 0x6F 0x06 - 0x29 7 0xBD 0x02 0x00 0x02 0x41 0x02 0x42 - 0x23 2 0x6F 0x0C - 0x29 5 0xBD 0x02 0x78 0x02 0xB5 - 0x29 7 0xBE 0x02 0xDA 0x03 0x12 0x03 0x3A - 0x23 2 0x6F 0x06 - 0x29 7 0xBE 0x03 0x6E 0x03 0x8D 0x03 0xB1 - 0x23 2 0x6F 0x0C - 0x29 5 0xBE 0x03 0xCA 0x03 0xE8 - 0x29 5 0xBF 0x03 0xF4 0x03 0xFF - - 0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x03 - 0x29 6 0xB2 0x05 0x00 0x00 0x00 0x00 - 0x29 6 0xB6 0x05 0x00 0x00 0x00 0x00 - 0x29 6 0xB7 0x05 0x00 0x00 0x00 0x00 - 0x29 6 0xBA 0x57 0x00 0x00 0x00 0x00 - 0x29 6 0xBB 0x57 0x00 0x00 0x00 0x00 - 0x29 5 0xC0 0x00 0x34 0x00 0x00 - 0x29 5 0xC1 0x00 0x00 0x34 0x00 - 0x23 2 0xC4 0x40 - - 0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x05 - 0x29 3 0xB0 0x17 0x06 - 0x29 3 0xB1 0x17 0x06 - 0x29 3 0xB2 0x17 0x06 - 0x29 3 0xB3 0x17 0x06 - 0x29 3 0xB4 0x17 0x06 - - 0x29 6 0xBD 0x03 0x01 0x03 0x03 0x01 - 0x23 2 0xC0 0x05 - 0x23 2 0xC4 0x82 - 0x23 2 0xC5 0xA2 - 0x29 3 0xC8 0x03 0x30 - 0x29 3 0xC9 0x03 0x31 - 0x29 4 0xCC 0x00 0x00 0x3C - 0x29 4 0xCD 0x00 0x00 0x3C - 0x29 6 0xD1 0x00 0x44 0x09 0x00 0x00 - 0x29 6 0xD2 0x00 0x04 0x0B 0x00 0x00 - - 0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x06 - 0x29 3 0xB0 0x0B 0x2D - 0x29 3 0xB1 0x2D 0x09 - 0x29 3 0xB2 0x2A 0x29 - 0x29 3 0xB3 0x34 0x1B - 0x29 3 0xB4 0x19 0x17 - 0x29 3 0xB5 0x15 0x13 - 0x29 3 0xB6 0x11 0x01 - 0x29 3 0xB7 0x34 0x34 - 0x29 3 0xB8 0x34 0x2D - 0x29 3 0xB9 0x2D 0x34 - 0x29 3 0xBA 0x2D 0x2D - 0x29 3 0xBB 0x34 0x34 - 0x29 3 0xBC 0x34 0x34 - 0x29 3 0xBD 0x00 0x10 - 0x29 3 0xBE 0x12 0x14 - 0x29 3 0xBF 0x16 0x18 - - 0x29 3 0xC0 0x1A 0x34 - 0x29 3 0xC1 0x29 0x2A - 0x29 3 0xC2 0x08 0x2D - 0x29 3 0xC3 0x2D 0x0A - 0x29 3 0xC4 0x0A 0x2D - 0x29 3 0xC5 0x2D 0x00 - 0x29 3 0xC6 0x2A 0x29 - 0x29 3 0xC7 0x34 0x14 - 0x29 3 0xC8 0x16 0x18 - 0x29 3 0xC9 0x1A 0x10 - 0x29 3 0xCA 0x12 0x08 - 0x29 3 0xCB 0x34 0x34 - 0x29 3 0xCC 0x34 0x2D - 0x29 3 0xCD 0x2D 0x34 - 0x29 3 0xCE 0x2D 0x2D - 0x29 3 0xCF 0x34 0x34 - - 0x29 3 0xD0 0x34 0x34 - 0x29 3 0xD1 0x09 0x13 - 0x29 3 0xD2 0x11 0x1B - 0x29 3 0xD3 0x19 0x17 - 0x29 3 0xD4 0x15 0x34 - 0x29 3 0xD5 0x29 0x2A - 0x29 3 0xD6 0x01 0x2D - 0x29 3 0xD7 0x2D 0x0B - 0x29 6 0xD8 0x00 0x00 0x00 0x00 0x00 - 0x29 6 0xD9 0x00 0x00 0x00 0x00 0x00 - - 0x29 3 0xE5 0x34 0x34 - 0x29 3 0xE6 0x34 0x34 - 0x23 2 0xE7 0x00 - 0x29 3 0xE8 0x34 0x34 - 0x29 3 0xE9 0x34 0x34 - 0x23 2 0xEA 0x00 - - 0x29 6 0xF0 0x55 0xAA 0x52 0x00 0x00 - - 0x13 1 0x35 - 0x13 1 0x11 - 0xfd 1 120 /* delay(ms) */ - 0x13 1 0x29 - 0xfd 1 20 /* delay(ms) */ - 0xff 0 /* ending */ - >; - init_off = < - 0x05 1 0x28 /* display off */ - 0xff 10 /* delay 10ms */ - 0x05 1 0x10 /* sleep in */ - 0xff 150 /* delay 150ms */ - 0xff 0xff>; /*ending*/ - }; - - extern_3{ - index = <3>; - extern_name = "mipi_default"; //TV070WSM_FT - status = "okay"; - type = <2>; /* 0=i2c, 1=spi, 2=mipi */ - cmd_size = <0xff>; - init_on = < - 0x23 2 0xE0 0x00 - 0x23 2 0xE1 0x93 - 0x23 2 0xE2 0x65 - 0x23 2 0xE3 0xF8 - 0x23 2 0xE0 0x01 - 0x23 2 0x00 0x00 - 0x23 2 0x01 0x90 - 0x23 2 0x03 0x00 - 0x23 2 0x04 0x90 - 0x23 2 0x17 0x00 - 0x23 2 0x18 0xB0 - 0x23 2 0x19 0x01 - 0x23 2 0x1A 0x00 - 0x23 2 0x1B 0xB0 - 0x23 2 0x1C 0x01 - 0x23 2 0x1F 0x3E - 0x23 2 0x20 0x2F - 0x23 2 0x21 0x2F - 0x23 2 0x22 0x0E - 0x23 2 0x37 0x69 - 0x23 2 0x38 0x05 - 0x23 2 0x39 0x00 - 0x23 2 0x3A 0x01 - 0x23 2 0x3C 0x90 - 0x23 2 0x3D 0xFF - 0x23 2 0x3E 0xFF - 0x23 2 0x3F 0xFF - 0x23 2 0x40 0x02 - 0x23 2 0x41 0x80 - 0x23 2 0x42 0x99 - 0x23 2 0x43 0x06 - 0x23 2 0x44 0x09 - 0x23 2 0x45 0x3C - 0x23 2 0x4B 0x04 - 0x23 2 0x55 0x0D - 0x23 2 0x56 0x01 - 0x23 2 0x57 0x89 - 0x23 2 0x58 0x0A - 0x23 2 0x59 0x0A - 0x23 2 0x5A 0x27 - 0x23 2 0x5B 0x15 - 0x23 2 0x5D 0x7C - 0x23 2 0x5E 0x67 - 0x23 2 0x5F 0x58 - 0x23 2 0x60 0x4C - 0x23 2 0x61 0x48 - 0x23 2 0x62 0x38 - 0x23 2 0x63 0x3C - 0x23 2 0x64 0x24 - 0x23 2 0x65 0x3B - 0x23 2 0x66 0x38 - 0x23 2 0x67 0x36 - 0x23 2 0x68 0x53 - 0x23 2 0x69 0x3F - 0x23 2 0x6A 0x44 - 0x23 2 0x6B 0x35 - 0x23 2 0x6C 0x2E - 0x23 2 0x6D 0x1F - 0x23 2 0x6E 0x0C - 0x23 2 0x6F 0x00 - 0x23 2 0x70 0x7C - 0x23 2 0x71 0x67 - 0x23 2 0x72 0x58 - 0x23 2 0x73 0x4C - 0x23 2 0x74 0x48 - 0x23 2 0x75 0x38 - 0x23 2 0x76 0x3C - 0x23 2 0x77 0x24 - 0x23 2 0x78 0x3B - 0x23 2 0x79 0x38 - 0x23 2 0x7A 0x36 - 0x23 2 0x7B 0x53 - 0x23 2 0x7C 0x3F - 0x23 2 0x7D 0x44 - 0x23 2 0x7E 0x35 - 0x23 2 0x7F 0x2E - 0x23 2 0x80 0x1F - 0x23 2 0x81 0x0C - 0x23 2 0x82 0x00 - 0x23 2 0xE0 0x02 - 0x23 2 0x00 0x45 - 0x23 2 0x01 0x45 - 0x23 2 0x02 0x47 - 0x23 2 0x03 0x47 - 0x23 2 0x04 0x41 - 0x23 2 0x05 0x41 - 0x23 2 0x06 0x1F - 0x23 2 0x07 0x1F - 0x23 2 0x08 0x1F - 0x23 2 0x09 0x1F - 0x23 2 0x0A 0x1F - 0x23 2 0x0B 0x1F - 0x23 2 0x0C 0x1F - 0x23 2 0x0D 0x1D - 0x23 2 0x0E 0x1D - 0x23 2 0x0F 0x1D - 0x23 2 0x10 0x1F - 0x23 2 0x11 0x1F - 0x23 2 0x12 0x1F - 0x23 2 0x13 0x1F - 0x23 2 0x14 0x1F - 0x23 2 0x15 0x1F - 0x23 2 0x16 0x44 - 0x23 2 0x17 0x44 - 0x23 2 0x18 0x46 - 0x23 2 0x19 0x46 - 0x23 2 0x1A 0x40 - 0x23 2 0x1B 0x40 - 0x23 2 0x1C 0x1F - 0x23 2 0x1D 0x1F - 0x23 2 0x1E 0x1F - 0x23 2 0x1F 0x1F - 0x23 2 0x20 0x1F - 0x23 2 0x21 0x1F - 0x23 2 0x22 0x1F - 0x23 2 0x23 0x1D - 0x23 2 0x24 0x1D - 0x23 2 0x25 0x1D - 0x23 2 0x26 0x1F - 0x23 2 0x27 0x1F - 0x23 2 0x28 0x1F - 0x23 2 0x29 0x1F - 0x23 2 0x2A 0x1F - 0x23 2 0x2B 0x1F - 0x23 2 0x58 0x40 - 0x23 2 0x59 0x00 - 0x23 2 0x5A 0x00 - 0x23 2 0x5B 0x10 - 0x23 2 0x5C 0x06 - 0x23 2 0x5D 0x20 - 0x23 2 0x5E 0x00 - 0x23 2 0x5F 0x00 - 0x23 2 0x61 0x00 - 0x23 2 0x62 0x00 - 0x23 2 0x63 0x7A - 0x23 2 0x64 0x7A - 0x23 2 0x65 0x00 - 0x23 2 0x66 0x00 - 0x23 2 0x67 0x32 - 0x23 2 0x68 0x08 - 0x23 2 0x69 0x7A - 0x23 2 0x6A 0x7A - 0x23 2 0x6B 0x00 - 0x23 2 0x6C 0x00 - 0x23 2 0x6D 0x04 - 0x23 2 0x6E 0x04 - 0x23 2 0x6F 0x88 - 0x23 2 0x70 0x00 - 0x23 2 0x71 0x00 - 0x23 2 0x72 0x06 - 0x23 2 0x73 0x7B - 0x23 2 0x74 0x00 - 0x23 2 0x75 0x07 - 0x23 2 0x76 0x00 - 0x23 2 0x77 0x5D - 0x23 2 0x78 0x17 - 0x23 2 0x79 0x1F - 0x23 2 0x7A 0x00 - 0x23 2 0x7B 0x00 - 0x23 2 0x7C 0x00 - 0x23 2 0x7D 0x03 - 0x23 2 0x7E 0x7B - 0x23 2 0xE0 0x03 - 0x23 2 0xAF 0x20 - 0x23 2 0xE0 0x04 - 0x23 2 0x09 0x11 - 0x23 2 0x0E 0x48 - 0x23 2 0x2B 0x2B - 0x23 2 0x2E 0x44 - 0x23 2 0x41 0xFF - 0x23 2 0xE0 0x00 - 0x23 2 0xE6 0x02 - 0x23 2 0xE7 0x0C - 0x05 1 0x11 - 0xff 120 /* delay 120ms */ - - 0x23 2 0xE0 0x03 - 0x23 2 0x2B 0x01 - 0x23 2 0x2C 0x00 - 0x23 2 0x30 0x03 - 0x23 2 0x31 0xCC - 0x23 2 0x32 0x03 - 0x23 2 0x33 0xC9 - 0x23 2 0x34 0x03 - 0x23 2 0x35 0xC0 - 0x23 2 0x36 0x03 - 0x23 2 0x37 0xB3 - 0x23 2 0x38 0x03 - 0x23 2 0x39 0xAB - 0x23 2 0x3A 0x03 - 0x23 2 0x3B 0x9D - 0x23 2 0x3C 0x03 - 0x23 2 0x3D 0x8F - 0x23 2 0x3E 0x03 - 0x23 2 0x3F 0x6D - 0x23 2 0x40 0x03 - 0x23 2 0x41 0x51 - 0x23 2 0x42 0x03 - 0x23 2 0x43 0x17 - 0x23 2 0x44 0x02 - 0x23 2 0x45 0xD8 - 0x23 2 0x46 0x02 - 0x23 2 0x47 0x60 - 0x23 2 0x48 0x01 - 0x23 2 0x49 0xEB - 0x23 2 0x4A 0x01 - 0x23 2 0x4B 0xE5 - 0x23 2 0x4C 0x01 - 0x23 2 0x4D 0x6C - 0x23 2 0x4E 0x00 - 0x23 2 0x4F 0xF2 - 0x23 2 0x50 0x00 - 0x23 2 0x51 0xB4 - 0x23 2 0x52 0x00 - 0x23 2 0x53 0x74 - 0x23 2 0x54 0x00 - 0x23 2 0x55 0x54 - 0x23 2 0x56 0x00 - 0x23 2 0x57 0x34 - 0x23 2 0x58 0x00 - 0x23 2 0x59 0x26 - 0x23 2 0x5A 0x00 - 0x23 2 0x5B 0x18 - 0x23 2 0x5C 0x00 - 0x23 2 0x5D 0x11 - 0x23 2 0x5E 0x00 - 0x23 2 0x5F 0x0A - 0x23 2 0x60 0x00 - 0x23 2 0x61 0x03 - 0x23 2 0x62 0x00 - 0x23 2 0x63 0x00 - 0x23 2 0x64 0x03 - 0x23 2 0x65 0x9E - 0x23 2 0x66 0x03 - 0x23 2 0x67 0x9B - 0x23 2 0x68 0x03 - 0x23 2 0x69 0x94 - 0x23 2 0x6A 0x03 - 0x23 2 0x6B 0x8C - 0x23 2 0x6C 0x03 - 0x23 2 0x6D 0x85 - 0x23 2 0x6E 0x03 - 0x23 2 0x6F 0x76 - 0x23 2 0x70 0x03 - 0x23 2 0x71 0x67 - 0x23 2 0x72 0x03 - 0x23 2 0x73 0x4B - 0x23 2 0x74 0x03 - 0x23 2 0x75 0x2E - 0x23 2 0x76 0x02 - 0x23 2 0x77 0xF7 - 0x23 2 0x78 0x02 - 0x23 2 0x79 0xB8 - 0x23 2 0x7A 0x02 - 0x23 2 0x7B 0x46 - 0x23 2 0x7C 0x01 - 0x23 2 0x7D 0xD6 - 0x23 2 0x7E 0x01 - 0x23 2 0x7F 0xD0 - 0x23 2 0x80 0x01 - 0x23 2 0x81 0x5C - 0x23 2 0x82 0x00 - 0x23 2 0x83 0xE7 - 0x23 2 0x84 0x00 - 0x23 2 0x85 0xAA - 0x23 2 0x86 0x00 - 0x23 2 0x87 0x74 - 0x23 2 0x88 0x00 - 0x23 2 0x89 0x5A - 0x23 2 0x8A 0x00 - 0x23 2 0x8B 0x3C - 0x23 2 0x8C 0x00 - 0x23 2 0x8D 0x2C - 0x23 2 0x8E 0x00 - 0x23 2 0x8F 0x1C - 0x23 2 0x90 0x00 - 0x23 2 0x91 0x14 - 0x23 2 0x92 0x00 - 0x23 2 0x93 0x0C - 0x23 2 0x94 0x00 - 0x23 2 0x95 0x04 - 0x23 2 0x96 0x00 - 0x23 2 0x97 0x00 - 0x23 2 0xE0 0x00 - 0x05 1 0x29 - 0xff 5 - 0xff 0xff /* ending flag */ - >; - init_off = < - 0xff 5 - 0x05 1 0x28 /* display off */ - 0xff 30 /* delay 10ms */ - 0x05 1 0x10 /* sleep in */ - 0xff 10 /* delay 150ms */ - 0xff 0xff>; /*ending*/ - }; - - extern_4{ - index = <4>; - extern_name = "mipi_default";/*P070ACB_FT*/ - status = "okay"; - type = <2>; /* 0=i2c, 1=spi, 2=mipi */ - cmd_size = <0xff>; - init_on = < - 0x23 2 0xE0 0x00 /* Page 0 */ - 0x23 2 0xE1 0x93 /* PASSWORD */ - 0x23 2 0xE2 0x65 - 0x23 2 0xE3 0xF8 - 0x23 2 0x80 0x03 - 0x23 2 0xE0 0x01 /* Page 01 */ - 0x23 2 0x0C 0x74 /* Set PWRIC */ - 0x23 2 0x17 0x00 /* Set Gamma Power */ - 0x23 2 0x18 0xEF /* VGMP=5.1V */ - 0x23 2 0x19 0x00 - 0x23 2 0x1A 0x00 - 0x23 2 0x1B 0xEF /* VGMN=-5.1V */ - 0x23 2 0x1C 0x00 - 0x23 2 0x1F 0x70 /* Set Gate Power */ - 0x23 2 0x20 0x2D - 0x23 2 0x21 0x2D - 0x23 2 0x22 0x7E - 0x23 2 0x26 0xF3 /* VDDD from IOVCC */ - 0x23 2 0x37 0x09 /* SetPanel */ - 0x23 2 0x38 0x04 /* SET RGBCYC */ - 0x23 2 0x39 0x00 - 0x23 2 0x3A 0x01 - 0x23 2 0x3C 0x90 - 0x23 2 0x3D 0xFF - 0x23 2 0x3E 0xFF - 0x23 2 0x3F 0xFF - 0x23 2 0x40 0x02 /* Set TCON */ - 0x23 2 0x41 0x80 - 0x23 2 0x42 0x99 - 0x23 2 0x43 0x14 - 0x23 2 0x44 0x19 - 0x23 2 0x45 0x5A - 0x23 2 0x4B 0x04 - 0x23 2 0x55 0x02 /* power voltage */ - 0x23 2 0x56 0x01 - 0x23 2 0x57 0x69 - 0x23 2 0x58 0x0A - 0x23 2 0x59 0x0A - 0x23 2 0x5A 0x2E /* VGH = 16.2V */ - 0x23 2 0x5B 0x19 /* VGL = -12V */ - 0x23 2 0x5C 0x15 - 0x23 2 0x5D 0x77 /* Gamma */ - 0x23 2 0x5E 0x56 - 0x23 2 0x5F 0x45 - 0x23 2 0x60 0x38 - 0x23 2 0x61 0x35 - 0x23 2 0x62 0x27 - 0x23 2 0x63 0x2D - 0x23 2 0x64 0x18 - 0x23 2 0x65 0x33 - 0x23 2 0x66 0x34 - 0x23 2 0x67 0x35 - 0x23 2 0x68 0x56 - 0x23 2 0x69 0x45 - 0x23 2 0x6A 0x4F - 0x23 2 0x6B 0x42 - 0x23 2 0x6C 0x40 - 0x23 2 0x6D 0x34 - 0x23 2 0x6E 0x25 - 0x23 2 0x6F 0x02 - 0x23 2 0x70 0x77 - 0x23 2 0x71 0x56 - 0x23 2 0x72 0x45 - 0x23 2 0x73 0x38 - 0x23 2 0x74 0x35 - 0x23 2 0x75 0x27 - 0x23 2 0x76 0x2D - 0x23 2 0x77 0x18 - 0x23 2 0x78 0x33 - 0x23 2 0x79 0x34 - 0x23 2 0x7A 0x35 - 0x23 2 0x7B 0x56 - 0x23 2 0x7C 0x45 - 0x23 2 0x7D 0x4F - 0x23 2 0x7E 0x42 - 0x23 2 0x7F 0x40 - 0x23 2 0x80 0x34 - 0x23 2 0x81 0x25 - 0x23 2 0x82 0x02 - 0x23 2 0xE0 0x02 /* Page2 */ - 0x23 2 0x00 0x53 - /* GIP_L Pin mapping RESET_EVEN */ - 0x23 2 0x01 0x55 /* VSSG_EVEN */ - 0x23 2 0x02 0x55 /* VSSA_EVEN */ - 0x23 2 0x03 0x51 /* STV2_EVEN */ - 0x23 2 0x04 0x77 /* VDD2_EVEN */ - 0x23 2 0x05 0x57 /* VDD1_EVEN */ - 0x23 2 0x06 0x1F - 0x23 2 0x07 0x4F /* CK12 */ - 0x23 2 0x08 0x4D /* CK10 */ - 0x23 2 0x09 0x1F - 0x23 2 0x0A 0x4B /* CK8 */ - 0x23 2 0x0B 0x49 /* CK6 */ - 0x23 2 0x0C 0x1F - 0x23 2 0x0D 0x47 /* CK4 */ - 0x23 2 0x0E 0x45 /* CK2 */ - 0x23 2 0x0F 0x41 /* STV1_EVEN */ - 0x23 2 0x10 0x1F - 0x23 2 0x11 0x1F - 0x23 2 0x12 0x1F - 0x23 2 0x13 0x55 /* VGG */ - 0x23 2 0x14 0x1F - 0x23 2 0x15 0x1F - 0x23 2 0x16 0x52 - /* GIP_R Pin mapping RESET_ODD */ - 0x23 2 0x17 0x55 /* VSSG_ODD */ - 0x23 2 0x18 0x55 /* VSSA_ODD */ - 0x23 2 0x19 0x50 /* STV2_ODD */ - 0x23 2 0x1A 0x77 /* VDD2_ODD */ - 0x23 2 0x1B 0x57 /* VDD1_ODD */ - 0x23 2 0x1C 0x1F - 0x23 2 0x1D 0x4E /* CK11 */ - 0x23 2 0x1E 0x4C /* CK9 */ - 0x23 2 0x1F 0x1F - 0x23 2 0x20 0x4A /* CK7 */ - 0x23 2 0x21 0x48 /* CK5 */ - 0x23 2 0x22 0x1F - 0x23 2 0x23 0x46 /* CK3 */ - 0x23 2 0x24 0x44 /* CK1 */ - 0x23 2 0x25 0x40 /* STV1_ODD */ - 0x23 2 0x26 0x1F - 0x23 2 0x27 0x1F - 0x23 2 0x28 0x1F - 0x23 2 0x29 0x1F - 0x23 2 0x2A 0x1F - 0x23 2 0x2B 0x55 /* VGG */ - 0x23 2 0x2C 0x12 /* GIP_L_GS Pin mapping */ - 0x23 2 0x2D 0x15 - 0x23 2 0x2E 0x15 - 0x23 2 0x2F 0x00 - 0x23 2 0x30 0x37 - 0x23 2 0x31 0x17 - 0x23 2 0x32 0x1F - 0x23 2 0x33 0x08 - 0x23 2 0x34 0x0A - 0x23 2 0x35 0x1F - 0x23 2 0x36 0x0C - 0x23 2 0x37 0x0E - 0x23 2 0x38 0x1F - 0x23 2 0x39 0x04 - 0x23 2 0x3A 0x06 - 0x23 2 0x3B 0x10 - 0x23 2 0x3C 0x1F - 0x23 2 0x3D 0x1F - 0x23 2 0x3E 0x1F - 0x23 2 0x3F 0x15 - 0x23 2 0x40 0x1F - 0x23 2 0x41 0x1F - 0x23 2 0x42 0x13 /* GIP_R_GS Pin mapping */ - 0x23 2 0x43 0x15 - 0x23 2 0x44 0x15 - 0x23 2 0x45 0x01 - 0x23 2 0x46 0x37 - 0x23 2 0x47 0x17 - 0x23 2 0x48 0x1F - 0x23 2 0x49 0x09 - 0x23 2 0x4A 0x0B - 0x23 2 0x4B 0x1F - 0x23 2 0x4C 0x0D - 0x23 2 0x4D 0x0F - 0x23 2 0x4E 0x1F - 0x23 2 0x4F 0x05 - 0x23 2 0x50 0x07 - 0x23 2 0x51 0x11 - 0x23 2 0x52 0x1F - 0x23 2 0x53 0x1F - 0x23 2 0x54 0x1F - 0x23 2 0x55 0x1F - 0x23 2 0x56 0x1F - 0x23 2 0x57 0x15 - 0x23 2 0x58 0x40 /* GIP Timing */ - 0x23 2 0x59 0x00 - 0x23 2 0x5A 0x00 - 0x23 2 0x5B 0x10 - 0x23 2 0x5C 0x14 - 0x23 2 0x5D 0x40 - 0x23 2 0x5E 0x01 - 0x23 2 0x5F 0x02 - 0x23 2 0x60 0x40 - 0x23 2 0x61 0x03 - 0x23 2 0x62 0x04 - 0x23 2 0x63 0x7A - 0x23 2 0x64 0x7A - 0x23 2 0x65 0x74 - 0x23 2 0x66 0x16 - 0x23 2 0x67 0xB4 - 0x23 2 0x68 0x16 - 0x23 2 0x69 0x7A - 0x23 2 0x6A 0x7A - 0x23 2 0x6B 0x0C - 0x23 2 0x6C 0x00 - 0x23 2 0x6D 0x04 - 0x23 2 0x6E 0x04 - 0x23 2 0x6F 0x88 - 0x23 2 0x70 0x00 - 0x23 2 0x71 0x00 - 0x23 2 0x72 0x06 - 0x23 2 0x73 0x7B - 0x23 2 0x74 0x00 - 0x23 2 0x75 0xBC - 0x23 2 0x76 0x00 - 0x23 2 0x77 0x04 - 0x23 2 0x78 0x2C - 0x23 2 0x79 0x00 - 0x23 2 0x7A 0x00 - 0x23 2 0x7B 0x00 - 0x23 2 0x7C 0x00 - 0x23 2 0x7D 0x03 - 0x23 2 0x7E 0x7B - 0x23 2 0xE0 0x04 /* Page4 */ - 0x23 2 0x09 0x11 /* Set RGBCYC2 */ - 0x23 2 0x0E 0x48 - 0x23 2 0x2B 0x2B /* ESD Protect */ - 0x23 2 0x2E 0x44 - 0x23 2 0xE0 0x00 /* Page0 */ - 0x23 2 0xE6 0x02 /* Watch dog */ - 0x23 2 0xE7 0x0C - 0x05 1 0x11 /* sleep out */ - 0xfd 1 120 - 0x05 1 0x29 /* display on */ - 0x05 1 0x35 - 0xfd 1 20 /* delay(ms) */ - 0xFF 0>; /*ending*/ - init_off = < - 0x05 1 0x28 /* display off */ - 0xff 10 /* delay 10ms */ - 0x05 1 0x10 /* sleep in */ - 0xff 150 /* delay 150ms */ - 0xff 0xff>; /*ending*/ - }; - }; - - backlight{ - compatible = "amlogic, backlight-g12a"; - status = "okay"; - key_valid = <0>; - pinctrl-names = "pwm_on","pwm_off"; - pinctrl-0 = <&pwm_f_pins2>; - pinctrl-1 = <&bl_pwm_off_pins>; - pinctrl_version = <2>; /* for uboot */ - bl_pwm_config = <&bl_pwm_conf>; - bl-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_HIGH - &gpio GPIOH_5 GPIO_ACTIVE_HIGH>; - bl_gpio_names = "GPIOH_4","GPIOH_5"; - - /* pwm port: PWM_A, PWM_B, PWM_C, PWM_D, PWM_E, PWM_F, PWM_VS*/ - /* power index:(point gpios_index, 0xff=invalid) - * power value:(0=output low, 1=output high, 2=input) - * power delay:(unit in ms) - */ - - backlight_0{ - index = <0>; - bl_name = "backlight_pwm"; - bl_level_default_uboot_kernel = <100 100>; - bl_level_attr = <255 10 /*max, min*/ - 128 128>; /*mid, mid_mapping*/ - bl_ctrl_method = <1>; /* 1=pwm, 2=pwm_combo, 4=extern */ - bl_power_attr = <0 /*en_gpio_index*/ - 1 0 /*on_value, off_value*/ - 200 200>; /*on_delay(ms), off_delay(ms)*/ - bl_pwm_port = "PWM_F"; - bl_pwm_attr = <0 /*pwm_method*/ - 180 /*pwm_freq(pwm:Hz, pwm_vs:multiple of vs)*/ - 100 25>; /*duty_max(%), duty_min(%)*/ - bl_pwm_power = <1 1 /*pwm_gpio_index, pwm_gpio_off*/ - 10 10>; /*pwm_on_delay(ms), pwm_off_delay(ms)*/ - bl_pwm_en_sequence_reverse = <0>; /* 1 for reverse */ - }; - backlight_1{ - index = <1>; - bl_name = "bl_extern"; - bl_level_default_uboot_kernel = <100 100>; - bl_level_attr = <255 10 /*max, min*/ - 128 128>; /*mid, mid_mapping*/ - bl_ctrl_method = <4>; /*1=pwm, 2=pwm_combo, 4=extern*/ - bl_power_attr = <1 /*en_gpio_index*/ - 1 0 /*on_value, off_value*/ - 200 200>; /*on_delay(ms), off_delay(ms)*/ - bl_extern_index = <0>; - }; - }; - bl_pwm_conf:bl_pwm_conf{ - pwm_channel_0 { - pwm_port_index = <5>; - pwms = <&pwm_ef MESON_PWM_1 30040 0>; - }; - }; - - bl_extern{ - compatible = "amlogic, bl_extern"; - status = "disabled"; - i2c_bus = "i2c_bus_3"; - - extern_0{ - index = <0>; - extern_name = "i2c_lp8556"; - type = <0>; /*0=i2c, 1=spi, 2=mipi*/ - i2c_address = <0x2c>; /*7bit i2c address*/ - dim_max_min = <255 10>; - }; - - extern_1{ - index = <1>; - extern_name = "mipi_lt070me05"; - type = <2>; /*0=i2c, 1=spi, 2=mipi*/ - dim_max_min = <255 10>; - }; - }; -};/* end of panel */ -
diff --git a/arch/arm/dts/elaine-p1-panel.dtsi b/arch/arm/dts/elaine-p1-panel.dtsi deleted file mode 100755 index 75f93db..0000000 --- a/arch/arm/dts/elaine-p1-panel.dtsi +++ /dev/null
@@ -1,973 +0,0 @@ -/* - * arch/arm/dts/elaine-p1-panel.dtsi - * - * Copyright (C) 2016 Amlogic, Inc. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - */ - -/ { - lcd{ - compatible = "amlogic, lcd-sm1"; - mode = "tablet"; - status = "okay"; - key_valid = <0>; - clocks = <&clkc CLKID_MIPI_DSI_HOST - &clkc CLKID_MIPI_DSI_PHY - &clkc CLKID_DSI_MEAS_COMP - &clkc CLKID_VCLK2_ENCL - &clkc CLKID_VCLK2_VENCL - &clkc CLKID_GP0_PLL>; - clock-names = "dsi_host_gate", - "dsi_phy_gate", - "dsi_meas", - "encl_top_gate", - "encl_int_gate", - "gp0_pll"; - reg = <0x0 0xffd07000 0x0 0x400 /* dsi_host */ - 0x0 0xff644000 0x0 0x200>; /* dsi_phy */ - interrupts = <0 3 1 - 0 56 1>; - interrupt-names = "vsync","vsync2"; - pinctrl_version = <2>; /* for uboot */ - - /* power type: - * (0=cpu_gpio, 1=pmu_gpio, 2=signal,3=extern, 0xff=ending) - * power index: - * (point gpios_index, or extern_index,0xff=invalid) - * power value:(0=output low, 1=output high, 2=input) - * power delay:(unit in ms) - */ - lcd_cpu-gpios = <&gpio GPIOZ_13 GPIO_ACTIVE_HIGH>; - lcd_cpu_gpio_names = "GPIOZ_13"; - - boe_fiti_7{ - model_name = "TV070WSM_FT"; - interface = "mipi"; - basic_setting = <600 1024 /*h_active, v_active*/ - 700 1053 /*h_period, v_period*/ - 8 /*lcd_bits*/ - 95 163>; /*screen_widht, screen_height*/ - lcd_timing = <24 36 0 /*hs_width,hs_bp,hs_pol*/ - 2 8 0>; /*vs_width,vs_bp,vs_pol*/ - clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/ - 0 /*clk_ss_level*/ - 1 /*clk_auto_generate*/ - 44226000>; /*pixel_clk(unit in Hz)*/ - mipi_attr = <4 /*lane_num*/ - 400 /*bit_rate_max(MHz)*/ - 0 /*factor(*100, default 0 for auto)*/ - 1 /*operation_mode_init(0=video, 1=command)*/ - 0 /*operation_mode_display(0=video, 1=command)*/ - 2 /* - *video_mode_type - *(0=sync_pulse,1=sync_event,2=burst) - */ - 0 /*clk_always_hs(0=disable,1=enable)*/ - 0>; /*phy_switch(0=auto,1=standard,2=slow)*/ - /* dsi_init: data_type, num, data... */ - dsi_init_on = < - 0xff 10 - 0xf0 3 0 1 30 /* reset high, delay 30ms */ - 0xf0 3 0 0 10 /* reset low, delay 10ms */ - 0xf0 3 0 1 30 /* reset high, delay 30ms */ - 0xfc 2 0x04 3 /* check_reg, check_cnt */ - 0xff 0xff>; /* ending flag */ - dsi_init_off = < - 0xff 5 /* delay 5ms */ - 0xff 0xff>; /* ending flag */ - /* extern_init: 0xff for invalid */ - extern_init = <1>; - /* power step: type,index,value,delay(ms) */ - power_on_step = < - 0 1 0 200 - 2 0 0 0 - 0xff 0 0 0>; - power_off_step = < - 2 0 0 5 /* delay 5ms after mipi off */ - 0 0 0 20 /* reset low */ - 0 1 1 100 /* panel power off */ - 0xff 0 0 0>; - backlight_index = <0>; - }; - - inx_fiti_7{ - model_name = "P070ACB_FT"; - interface = "mipi"; - basic_setting = <600 1024 /*h_active, v_active*/ - 770 1070 /*h_period, v_period*/ - 8 /*lcd_bits*/ - 3 5>; /*screen_widht, screen_height*/ - lcd_timing = <10 80 0 /*hs_width,hs_bp,hs_pol*/ - 6 20 0>; /*vs_width,vs_bp,vs_pol*/ - clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/ - 0 /*clk_ss_level*/ - 1 /*clk_auto_generate*/ - 49434000>; /*pixel_clk(unit in Hz)*/ - mipi_attr = <4 /*lane_num*/ - 400 /*bit_rate_max(MHz)*/ - 0 /*factor(*100, default 0 for auto)*/ - 1 /*operation_mode_init(0=video, 1=command)*/ - 0 /*operation_mode_display(0=video, 1=command)*/ - 2 /* - *video_mode_type - *(0=sync_pulse,1=sync_event,2=burst) - */ - 0 /*clk_always_hs(0=disable,1=enable)*/ - 0>; /*phy_switch(0=auto,1=standard,2=slow)*/ - /* dsi_init: data_type, num, data... */ - dsi_init_on = < - 0xff 10 - 0xf0 3 0 1 30 /* reset high, delay 30ms */ - 0xf0 3 0 0 10 /* reset low, delay 10ms */ - 0xf0 3 0 1 30 /* reset high, delay 30ms */ - 0xfc 2 0x04 3 /* check_reg, check_cnt */ - 0xff 0xff>; /* ending flag */ - dsi_init_off = < - 0xff 5 /* delay 5ms */ - 0xff 0xff>; /* ending flag */ - /* extern_init: 0xff for invalid */ - extern_init = <2>; - /* power step: type,index,value,delay(ms) */ - power_on_step = < - 0 1 0 200 /* panel power on */ - 2 0 0 0 - 0xff 0 0 0>; - power_off_step = < - 2 0 0 5 /* delay 5ms after mipi off */ - 0 0 0 20 /* reset low */ - 0 1 1 100 /* panel power off */ - 0xff 0 0 0>; - backlight_index = <0>; - }; - - kd_fiti_7{ - model_name = "KD070D82_FT"; - interface = "mipi"; - basic_setting = <600 1024 /*h_active, v_active*/ - 770 1070 /*h_period, v_period*/ - 8 /*lcd_bits*/ - 3 5>; /*screen_widht, screen_height*/ - lcd_timing = <10 80 0 /*hs_width,hs_bp,hs_pol*/ - 6 20 0>; /*vs_width,vs_bp,vs_pol*/ - clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/ - 0 /*clk_ss_level*/ - 1 /*clk_auto_generate*/ - 49434000>; /*pixel_clk(unit in Hz)*/ - mipi_attr = <4 /*lane_num*/ - 400 /*bit_rate_max(MHz)*/ - 0 /*factor(*100, default 0 for auto)*/ - 1 /*operation_mode_init(0=video, 1=command)*/ - 0 /*operation_mode_display(0=video, 1=command)*/ - 2 /* - *video_mode_type - *(0=sync_pulse,1=sync_event,2=burst) - */ - 0 /*clk_always_hs(0=disable,1=enable)*/ - 0>; /*phy_switch(0=auto,1=standard,2=slow)*/ - /* dsi_init: data_type, num, data... */ - dsi_init_on = < - 0xff 10 - 0xf0 3 0 1 30 /* reset high, delay 30ms */ - 0xf0 3 0 0 10 /* reset low, delay 10ms */ - 0xf0 3 0 1 30 /* reset high, delay 30ms */ - 0xfc 2 0x04 3 /* check_reg, check_cnt */ - 0xff 0xff>; /* ending flag */ - dsi_init_off = < - 0xff 5 /* delay 5ms */ - 0xff 0xff>; /* ending flag */ - /* extern_init: 0xff for invalid */ - extern_init = <3>; - /* power step: type,index,value,delay(ms) */ - power_on_step = < - 0 1 0 200 /* panel power on */ - 2 0 0 0 - 0xff 0 0 0>; - power_off_step = < - 2 0 0 5 /* delay 5ms after mipi off */ - 0 0 0 20 /* reset low */ - 0 1 1 100 /* panel power off */ - 0xff 0 0 0>; - backlight_index = <0>; - }; - - }; - - lcd_extern{ - compatible = "amlogic, lcd_extern"; - dev_name = "lcd_extern"; - status = "okay"; - key_valid = <0>; - - extern_1{ - index = <1>; - extern_name = "mipi_default"; //TV070WSM_FT - status = "okay"; - type = <2>; /* 0=i2c, 1=spi, 2=mipi */ - cmd_size = <0xff>; - init_on = < - 0x23 2 0xE0 0x00 - 0x23 2 0xE1 0x93 - 0x23 2 0xE2 0x65 - 0x23 2 0xE3 0xF8 - 0x23 2 0xE0 0x01 - 0x23 2 0x00 0x00 - 0x23 2 0x01 0x90 - 0x23 2 0x03 0x00 - 0x23 2 0x04 0x90 - 0x23 2 0x17 0x00 - 0x23 2 0x18 0xB0 - 0x23 2 0x19 0x01 - 0x23 2 0x1A 0x00 - 0x23 2 0x1B 0xB0 - 0x23 2 0x1C 0x01 - 0x23 2 0x1F 0x3E - 0x23 2 0x20 0x2F - 0x23 2 0x21 0x2F - 0x23 2 0x22 0x0E - 0x23 2 0x37 0x69 - 0x23 2 0x38 0x05 - 0x23 2 0x39 0x00 - 0x23 2 0x3A 0x01 - 0x23 2 0x3C 0x90 - 0x23 2 0x3D 0xFF - 0x23 2 0x3E 0xFF - 0x23 2 0x3F 0xFF - 0x23 2 0x40 0x02 - 0x23 2 0x41 0x80 - 0x23 2 0x42 0x99 - 0x23 2 0x43 0x06 - 0x23 2 0x44 0x09 - 0x23 2 0x45 0x3C - 0x23 2 0x4B 0x04 - 0x23 2 0x55 0x0D - 0x23 2 0x56 0x01 - 0x23 2 0x57 0x89 - 0x23 2 0x58 0x0A - 0x23 2 0x59 0x0A - 0x23 2 0x5A 0x27 - 0x23 2 0x5B 0x15 - 0x23 2 0x5D 0x7C - 0x23 2 0x5E 0x67 - 0x23 2 0x5F 0x58 - 0x23 2 0x60 0x4C - 0x23 2 0x61 0x48 - 0x23 2 0x62 0x38 - 0x23 2 0x63 0x3C - 0x23 2 0x64 0x24 - 0x23 2 0x65 0x3B - 0x23 2 0x66 0x38 - 0x23 2 0x67 0x36 - 0x23 2 0x68 0x53 - 0x23 2 0x69 0x3F - 0x23 2 0x6A 0x44 - 0x23 2 0x6B 0x35 - 0x23 2 0x6C 0x2E - 0x23 2 0x6D 0x1F - 0x23 2 0x6E 0x0C - 0x23 2 0x6F 0x00 - 0x23 2 0x70 0x7C - 0x23 2 0x71 0x67 - 0x23 2 0x72 0x58 - 0x23 2 0x73 0x4C - 0x23 2 0x74 0x48 - 0x23 2 0x75 0x38 - 0x23 2 0x76 0x3C - 0x23 2 0x77 0x24 - 0x23 2 0x78 0x3B - 0x23 2 0x79 0x38 - 0x23 2 0x7A 0x36 - 0x23 2 0x7B 0x53 - 0x23 2 0x7C 0x3F - 0x23 2 0x7D 0x44 - 0x23 2 0x7E 0x35 - 0x23 2 0x7F 0x2E - 0x23 2 0x80 0x1F - 0x23 2 0x81 0x0C - 0x23 2 0x82 0x00 - 0x23 2 0xE0 0x02 - 0x23 2 0x00 0x45 - 0x23 2 0x01 0x45 - 0x23 2 0x02 0x47 - 0x23 2 0x03 0x47 - 0x23 2 0x04 0x41 - 0x23 2 0x05 0x41 - 0x23 2 0x06 0x1F - 0x23 2 0x07 0x1F - 0x23 2 0x08 0x1F - 0x23 2 0x09 0x1F - 0x23 2 0x0A 0x1F - 0x23 2 0x0B 0x1F - 0x23 2 0x0C 0x1F - 0x23 2 0x0D 0x1D - 0x23 2 0x0E 0x1D - 0x23 2 0x0F 0x1D - 0x23 2 0x10 0x1F - 0x23 2 0x11 0x1F - 0x23 2 0x12 0x1F - 0x23 2 0x13 0x1F - 0x23 2 0x14 0x1F - 0x23 2 0x15 0x1F - 0x23 2 0x16 0x44 - 0x23 2 0x17 0x44 - 0x23 2 0x18 0x46 - 0x23 2 0x19 0x46 - 0x23 2 0x1A 0x40 - 0x23 2 0x1B 0x40 - 0x23 2 0x1C 0x1F - 0x23 2 0x1D 0x1F - 0x23 2 0x1E 0x1F - 0x23 2 0x1F 0x1F - 0x23 2 0x20 0x1F - 0x23 2 0x21 0x1F - 0x23 2 0x22 0x1F - 0x23 2 0x23 0x1D - 0x23 2 0x24 0x1D - 0x23 2 0x25 0x1D - 0x23 2 0x26 0x1F - 0x23 2 0x27 0x1F - 0x23 2 0x28 0x1F - 0x23 2 0x29 0x1F - 0x23 2 0x2A 0x1F - 0x23 2 0x2B 0x1F - 0x23 2 0x58 0x40 - 0x23 2 0x59 0x00 - 0x23 2 0x5A 0x00 - 0x23 2 0x5B 0x10 - 0x23 2 0x5C 0x07 - 0x23 2 0x5D 0x20 - 0x23 2 0x5E 0x00 - 0x23 2 0x5F 0x00 - 0x23 2 0x61 0x00 - 0x23 2 0x62 0x00 - 0x23 2 0x63 0x7A - 0x23 2 0x64 0x7A - 0x23 2 0x65 0x00 - 0x23 2 0x66 0x00 - 0x23 2 0x67 0x32 - 0x23 2 0x68 0x08 - 0x23 2 0x69 0x7A - 0x23 2 0x6A 0x7A - 0x23 2 0x6B 0x00 - 0x23 2 0x6C 0x00 - 0x23 2 0x6D 0x00 - 0x23 2 0x6E 0x00 - 0x23 2 0x6F 0x89 - 0x23 2 0x70 0x00 - 0x23 2 0x71 0x00 - 0x23 2 0x72 0x06 - 0x23 2 0x73 0x7B - 0x23 2 0x74 0x00 - 0x23 2 0x75 0x07 - 0x23 2 0x76 0x00 - 0x23 2 0x77 0x5D - 0x23 2 0x78 0x17 - 0x23 2 0x79 0x1F - 0x23 2 0x7A 0x00 - 0x23 2 0x7B 0x00 - 0x23 2 0x7C 0x00 - 0x23 2 0x7D 0x03 - 0x23 2 0x7E 0x7B - 0x23 2 0xE0 0x03 - 0x23 2 0xAF 0x20 - 0x23 2 0xE0 0x04 - 0x23 2 0x09 0x11 - 0x23 2 0x0E 0x48 - 0x23 2 0x2B 0x2B - 0x23 2 0x2E 0x44 - 0x23 2 0x41 0xFF - 0x23 2 0xE0 0x00 - 0x23 2 0xE6 0x02 - 0x23 2 0xE7 0x0C - 0x23 2 0x51 0xFF - 0x23 2 0x53 0x2C - 0x23 2 0x55 0x00 - 0x05 1 0x11 - 0xFF 125 /* Delay 125ms */ - 0x05 1 0x29 - 0xFF 0xFF /* Ending Flag */ - >; - init_off = < - 0xff 5 - 0x05 1 0x28 /* display off */ - 0xff 60 /* delay 60ms */ - 0x05 1 0x10 /* sleep in */ - 0xff 110 /* delay 110ms */ - 0xff 0xff>; /* ending */ - }; - - extern_2{ - index = <2>; - extern_name = "mipi_default"; /*P070ACB_FT*/ - status = "okay"; - type = <2>; /* 0=i2c, 1=spi, 2=mipi */ - cmd_size = <0xff>; - init_on = < - 0x23 2 0xE0 0x00 /* Page 0 */ - 0x23 2 0xE1 0x93 /* PASSWORD */ - 0x23 2 0xE2 0x65 - 0x23 2 0xE3 0xF8 - 0x23 2 0x80 0x03 /* DSI 4 lane */ - 0x23 2 0xE0 0x01 /* Page 01 */ - 0x23 2 0x0C 0x74 /* Set PWRIC */ - 0x23 2 0x17 0x00 /* Set Gamma Power */ - 0x23 2 0x18 0xEF /* VGMP=5.1V */ - 0x23 2 0x19 0x00 /* VGSP=0V */ - 0x23 2 0x1A 0x00 - 0x23 2 0x1B 0xEF /* VGMN=-5.1V */ - 0x23 2 0x1C 0x00 /* VGSN=0V */ - 0x23 2 0x1F 0x70 /* VGH_REG=16.2V */ - 0x23 2 0x20 0x2D /* VGL_REG=-12V */ - 0x23 2 0x21 0x2D /* VGL_REG2=-12V */ - 0x23 2 0x22 0x7E /* VGH_REG short to VGH VGL_REG short to VGL */ - 0x23 2 0x26 0xF3 /* VDDD from IOVCC/VCI */ - 0x23 2 0x37 0x09 /* SS=1 BGR=1 */ - 0x23 2 0x38 0x04 /* JDT=100 column inversion */ - 0x23 2 0x39 0x00 /* Source EQ Setting EQ1 */ - 0x23 2 0x3A 0x01 /* Source EQ Setting EQ2 */ - 0x23 2 0x3C 0x90 /* Source EQ Setting EQ3 */ - 0x23 2 0x3D 0xFF /* SET Source OP on time */ - 0x23 2 0x3E 0xFF /* SET Source OP off time */ - 0x23 2 0x3F 0xFF /* SET Source OP off time */ - 0x23 2 0x40 0x02 /* RSO=640 RGB */ - 0x23 2 0x41 0x80 /* LN=512->1024 line */ - 0x23 2 0x42 0x99 /* SLT internal line period */ - 0x23 2 0x43 0x14 /* VFP */ - 0x23 2 0x44 0x19 /* VBP */ - 0x23 2 0x45 0x5A /* HBP */ - 0x23 2 0x4B 0x04 - 0x23 2 0x55 0x02 /* DCDCM=0010 FP7721BX2 */ - 0x23 2 0x56 0x01 /* No auto Ratio function */ - 0x23 2 0x57 0x69 /* VGH_RT=3'b011 2*AVDD-AVEE VGL_RT=3'b010=AVEE+VCL-AVDD VCL_RT=2'b00 0.5*VCIP */ - 0x23 2 0x58 0x0A /* AVDD_S */ - 0x23 2 0x59 0x0A /* VCL = -2.5V */ - 0x23 2 0x5A 0x2E /* VGH = 16.2V */ - 0x23 2 0x5B 0x19 /* VGL = -12V */ - 0x23 2 0x5C 0x15 /* pump clk */ - 0x23 2 0x5D 0x71 /* V255 positive voltage from 4.888V to 4.888V */ - 0x23 2 0x5E 0x65 /* V251 positive voltage from 4.533V to 4.718V */ - 0x23 2 0x5F 0x55 /* V247 positive voltage from 4.349V to 4.491V */ - 0x23 2 0x60 0x49 /* V243 positive voltage from 4.179V to 4.321V */ - 0x23 2 0x61 0x46 /* V235 positive voltage from 3.910V to 4.052V */ - 0x23 2 0x62 0x38 /* V227 positive voltage from 3.726V to 3.853V */ - 0x23 2 0x63 0x3D /* V211 positive voltage from 3.428V to 3.528V */ - 0x23 2 0x64 0x29 /* V191 positive voltage from 3.159V to 3.244V */ - 0x23 2 0x65 0x43 /* V159 positive voltage from 2.805V to 2.876V */ - 0x23 2 0x66 0x42 /* V128 positive voltage from 2.522V to 2.578V */ - 0x23 2 0x67 0x44 /* V96 positive voltage from 2.267V to 2.323V */ - 0x23 2 0x68 0x63 /* V64 positive voltage from 1.941V to 2.026V */ - 0x23 2 0x69 0x53 /* V44 positive voltage from 1.686V to 1.799V */ - 0x23 2 0x6A 0x5B /* V28 positive voltage from 1.431V to 1.516V */ - 0x23 2 0x6B 0x4E /* V20 positive voltage from 1.275V to 1.322V */ - 0x23 2 0x6C 0x4C /* V12 positive voltage from 1.077V to 1.077V */ - 0x23 2 0x6D 0x41 /* V8 positive voltage from 0.949V to 0.921V */ - 0x23 2 0x6E 0x2D /* V4 positive voltage from 0.723V to 0.638V */ - 0x23 2 0x6F 0x23 /* V0 positive voltage from 0.496V to 0.496V */ - 0x23 2 0x70 0x71 /* V255 negative voltage from -4.888V to -4.888V */ - 0x23 2 0x71 0x4C /* V251 negative voltage from -4.179V to -4.363V */ - 0x23 2 0x72 0x3B /* V247 negative voltage from -3.995V to -4.123V */ - 0x23 2 0x73 0x30 /* V243 negative voltage from -3.825V to -3.967V */ - 0x23 2 0x74 0x2D /* V233 negative voltage from -3.556V to -3.698V */ - 0x23 2 0x75 0x1F /* V227 negative voltage from -3.372V to -3.499V */ - 0x23 2 0x76 0x25 /* V211 negative voltage from -3.088V to -3.188V */ - 0x23 2 0x77 0x10 /* V191 negative voltage from -2.805V to -2.890V */ - 0x23 2 0x78 0x2A /* V159 negative voltage from -2.451V to -2.522V */ - 0x23 2 0x79 0x2A /* V128 negative voltage from -2.182V to -2.238V */ - 0x23 2 0x7A 0x2B /* V96 negative voltage from -1.913V to -1.969V */ - 0x23 2 0x7B 0x4A /* V64 negative voltage from -1.587V to -1.672V */ - 0x23 2 0x7C 0x3A /* V44 negative voltage from -1.332V to -1.445V */ - 0x23 2 0x7D 0x43 /* V28 negative voltage from -1.091V to -1.176V */ - 0x23 2 0x7E 0x36 /* V20 negative voltage from -0.935V to -0.992V */ - 0x23 2 0x7F 0x33 /* V12 negative voltage from -0.723V to -0.723V */ - 0x23 2 0x80 0x28 /* V8 negative voltage from -0.595V to -0.567V */ - 0x23 2 0x81 0x14 /* V4 negative voltage from -0.368V to -0.283V */ - 0x23 2 0x82 0x0B /* V0 negative voltage from -0.156V to -0.156V */ - 0x23 2 0xE0 0x02 /* Page2 */ - 0x23 2 0x00 0x53 /* GIP_L Pin mapping RESET_EVEN */ - 0x23 2 0x01 0x55 /* VSSG_EVEN */ - 0x23 2 0x02 0x55 /* VSSA_EVEN */ - 0x23 2 0x03 0x51 /* STV2_EVEN */ - 0x23 2 0x04 0x77 /* VDD2_EVEN */ - 0x23 2 0x05 0x57 /* VDD1_EVEN */ - 0x23 2 0x06 0x1F /* VGL */ - 0x23 2 0x07 0x4F /* CK12 */ - 0x23 2 0x08 0x4D /* CK10 */ - 0x23 2 0x09 0x1F /* VGL */ - 0x23 2 0x0A 0x4B /* CK8 */ - 0x23 2 0x0B 0x49 /* CK6 */ - 0x23 2 0x0C 0x1F /* VGL */ - 0x23 2 0x0D 0x47 /* CK4 */ - 0x23 2 0x0E 0x45 /* CK2 */ - 0x23 2 0x0F 0x41 /* STV1_EVEN */ - 0x23 2 0x10 0x1F /* VGL */ - 0x23 2 0x11 0x1F /* VGL */ - 0x23 2 0x12 0x1F /* VGL */ - 0x23 2 0x13 0x55 /* VGG */ - 0x23 2 0x14 0x1F /* VGL */ - 0x23 2 0x15 0x1F /* VGL */ - 0x23 2 0x16 0x52 /* GIP_R Pin mapping RESET_ODD */ - 0x23 2 0x17 0x55 /* VSSG_ODD */ - 0x23 2 0x18 0x55 /* VSSA_ODD */ - 0x23 2 0x19 0x50 /* STV2_ODD */ - 0x23 2 0x1A 0x77 /* VDD2_ODD */ - 0x23 2 0x1B 0x57 /* VDD1_ODD */ - 0x23 2 0x1C 0x1F /* VGL */ - 0x23 2 0x1D 0x4E /* CK11 */ - 0x23 2 0x1E 0x4C /* CK9 */ - 0x23 2 0x1F 0x1F /* VGL */ - 0x23 2 0x20 0x4A /* CK7 */ - 0x23 2 0x21 0x48 /* CK5 */ - 0x23 2 0x22 0x1F /* VGL */ - 0x23 2 0x23 0x46 /* CK3 */ - 0x23 2 0x24 0x44 /* CK1 */ - 0x23 2 0x25 0x40 /* STV1_ODD */ - 0x23 2 0x26 0x1F /* VGL */ - 0x23 2 0x27 0x1F /* VGL */ - 0x23 2 0x28 0x1F /* VGL */ - 0x23 2 0x29 0x1F /* VGL */ - 0x23 2 0x2A 0x1F /* VGL */ - 0x23 2 0x2B 0x55 /* VGG */ - 0x23 2 0x2C 0x12 /* GIP_L_GS Pin mapping RESET_EVEN */ - 0x23 2 0x2D 0x15 /* VSSG_EVEN */ - 0x23 2 0x2E 0x15 /* VSSA_EVEN */ - 0x23 2 0x2F 0x00 /* STV2_EVEN */ - 0x23 2 0x30 0x17 /* VDD2_EVEN */ - 0x23 2 0x31 0x17 /* VDD1_EVEN */ - 0x23 2 0x32 0x1F /* VGL */ - 0x23 2 0x33 0x08 /* CK12 */ - 0x23 2 0x34 0x0A /* CK10 */ - 0x23 2 0x35 0x1F /* VGL */ - 0x23 2 0x36 0x0C /* CK8 */ - 0x23 2 0x37 0x0E /* CK6 */ - 0x23 2 0x38 0x1F /* VGL */ - 0x23 2 0x39 0x04 /* CK4 */ - 0x23 2 0x3A 0x06 /* CK2 */ - 0x23 2 0x3B 0x10 /* STV1_EVEN */ - 0x23 2 0x3C 0x1F /* VGL */ - 0x23 2 0x3D 0x1F /* VGL */ - 0x23 2 0x3E 0x1F /* VGL */ - 0x23 2 0x3F 0x15 /* VGG */ - 0x23 2 0x40 0x1F /* VGL */ - 0x23 2 0x41 0x1F /* VGL */ - 0x23 2 0x42 0x13 /* GIP_R_GS Pin mapping RESET_ODD */ - 0x23 2 0x43 0x15 /* VSSG_ODD */ - 0x23 2 0x44 0x15 /* VSSA_ODD */ - 0x23 2 0x45 0x01 /* STV2_ODD */ - 0x23 2 0x46 0x37 /* VDD2_ODD */ - 0x23 2 0x47 0x17 /* VDD1_ODD */ - 0x23 2 0x48 0x1F /* VGL */ - 0x23 2 0x49 0x09 /* CK11 */ - 0x23 2 0x4A 0x0B /* CK9 */ - 0x23 2 0x4B 0x1F /* VGL */ - 0x23 2 0x4C 0x0D /* CK7 */ - 0x23 2 0x4D 0x0F /* CK5 */ - 0x23 2 0x4E 0x1F /* VGL */ - 0x23 2 0x4F 0x05 /* CK3 */ - 0x23 2 0x50 0x07 /* CK1 */ - 0x23 2 0x51 0x11 /* STV1_ODD */ - 0x23 2 0x52 0x1F /* VGL */ - 0x23 2 0x53 0x1F /* VGL */ - 0x23 2 0x54 0x1F /* VGL */ - 0x23 2 0x55 0x1F /* VGL */ - 0x23 2 0x56 0x1F /* VGL */ - 0x23 2 0x57 0x15 /* VGG */ - 0x23 2 0x58 0x40 /* GAS OPT=1 for abnormal power off */ - 0x23 2 0x59 0x00 /* INIT_W */ - 0x23 2 0x5A 0x00 /* INIT[7:0] */ - 0x23 2 0x5B 0x10 /* STV_NUM STV_S0[10:8] */ - 0x23 2 0x5C 0x14 /* STV_S0[7:0] */ - 0x23 2 0x5D 0x40 /* STV_W STV_S1 */ - 0x23 2 0x5E 0x01 /* STV_S2 */ - 0x23 2 0x5F 0x02 /* STV_S3 */ - 0x23 2 0x60 0x40 /* ETV_W ETV_S1 */ - 0x23 2 0x61 0x03 /* ETV_S2 */ - 0x23 2 0x62 0x04 /* ETV_S3 */ - 0x23 2 0x63 0x7A /* SETV_ON for STV/ETV on time */ - 0x23 2 0x64 0x7A /* SETV_OFF for STV/ETV off time */ - 0x23 2 0x65 0x74 /* ETV_EN ETV_NUM ETV_S0 */ - 0x23 2 0x66 0x16 /* ETV_S0 */ - 0x23 2 0x67 0xB4 /* CKV0_NUM CKV0_W */ - 0x23 2 0x68 0x16 /* CKV0_S0 */ - 0x23 2 0x69 0x7A /* CKV0_on */ - 0x23 2 0x6A 0x7A /* CKV0_off time */ - 0x23 2 0x6B 0x0C /* CKV0_DUM */ - 0x23 2 0x6C 0x00 /* GIP Line EQ option */ - 0x23 2 0x6D 0x04 /* GIP rising EQ */ - 0x23 2 0x6E 0x04 /* GIP fallig EQ */ - 0x23 2 0x6F 0x88 /* GIP_DR CKV0_CON CKV1_CON */ - 0x23 2 0x70 0x00 /* CKV1_NUM CKV0_W */ - 0x23 2 0x71 0x00 /* CKV1_S0 */ - 0x23 2 0x72 0x06 /* CKV1_on */ - 0x23 2 0x73 0x7B /* CKV1_off time */ - 0x23 2 0x74 0x00 /* CKV1_DUM */ - 0x23 2 0x75 0xBC /* FLM_EN FLM_W */ - 0x23 2 0x76 0x00 /* FLM on time */ - 0x23 2 0x77 0x04 /* VEN_EN VEN_W FLM_NUM FLM_OFF */ - 0x23 2 0x78 0x2C /* FLM_OFF */ - 0x23 2 0x79 0x00 /* VEN_W */ - 0x23 2 0x7A 0x00 /* VEN_S0 */ - 0x23 2 0x7B 0x00 /* VEN_S1 */ - 0x23 2 0x7C 0x00 /* VEN_DUM */ - 0x23 2 0x7D 0x03 /* VEN on time */ - 0x23 2 0x7E 0x7B /* VEN off time */ - 0x23 2 0xE0 0x03 /* Page3 */ - 0x23 2 0xAF 0x20 /* Set CABC */ - 0x23 2 0xE0 0x04 /* Page4 */ - 0x23 2 0x09 0x11 /* Source level at blanking period */ - 0x23 2 0x0E 0x48 /* Source EQ option */ - 0x23 2 0x2B 0x2B /* ESD Protect */ - 0x23 2 0x2E 0x44 /* Special Packet disable */ - 0x23 2 0x41 0xFF /* Set CABC */ - 0x23 2 0xE0 0x00 /* Page0 */ - 0x23 2 0xE6 0x02 /* Enable Watch Dog */ - 0x23 2 0xE7 0x0C /* Watch Dog timer setting */ - 0x23 2 0x51 0xFF /* CABC Option 0x80=50% duty 0xFF=100% */ - 0x23 2 0x53 0x2C - 0x23 2 0x55 0x00 - 0x05 1 0x11 /* Sleep Out */ - 0xFF 125 /* Delay 125ms */ - 0x05 1 0x29 /* Display On */ - 0xFF 0xFF /* Ending */ - >; - init_off = < - 0xff 5 - 0x05 1 0x28 /* display off */ - 0xff 60 /* delay 60ms */ - 0x05 1 0x10 /* sleep in */ - 0xff 110 /* delay 110ms */ - 0xff 0xff>; /* ending */ - }; - - extern_3{ - index = <3>; - extern_name = "mipi_default"; /*KD070D82_FT*/ - status = "okay"; - type = <2>; /* 0=i2c, 1=spi, 2=mipi */ - cmd_size = <0xff>; - init_on = < - 0x23 2 0xE0 0x00 /* Register setting change to Page 0 */ - 0x23 2 0xE1 0x93 /* PASSWORD, setting as 93-65-F8 to enable page1-4 command access */ - 0x23 2 0xE2 0x65 - 0x23 2 0xE3 0xF8 - 0x23 2 0x80 0x03 /* Setting DSI lane number, 0x03 is DSI 4 lane */ - 0x23 2 0xE0 0x01 /* Register setting change to Page 1 */ - 0x23 2 0x00 0x00 /* Set VCOM_Forward */ - 0x23 2 0x01 0x9E /* VCOM=0x09F */ - 0x23 2 0x03 0x00 /* Set VCOM_Reverse */ - 0x23 2 0x04 0xAA /* VCOMR=0x0AA, -1.40V */ - 0x23 2 0x0C 0x74 /* Set PWRIC pumping frequency,=8 HCLK, about 512KHz */ - 0x23 2 0x17 0x00 /* Set Gamma Power, VGMP[8]=0, VGSP[8]=0 */ - 0x23 2 0x18 0xEF /* VGMP[8:0]=0x0EF=5.1V */ - 0x23 2 0x19 0x00 /* VGSP[8:0]=0x000=0V */ - 0x23 2 0x1A 0x00 /* VGMN[8]=0, VGSN[8]=0 */ - 0x23 2 0x1B 0xEF /* VGMN[8:0]=0x0EF=-5.1V */ - 0x23 2 0x1C 0x00 /* VGSN[8:0]=0x000=0V */ - 0x23 2 0x1F 0x70 /* VGH_REG=16.2V */ - 0x23 2 0x20 0x2D /* VGL_REG=-12V */ - 0x23 2 0x21 0x2D /* VGL_REG2=-12V */ - 0x23 2 0x22 0x7E /* VGH_REG short to VGH, VGL_REG short to VGL, */ - 0x23 2 0x26 0xF3 /* VDDD from IOVCC&VCI */ - 0x23 2 0x37 0x09 /* SS=1, source scan from S2400 to S1;BGR=1 CF type is (S1,S2,S3) align to (B,G,R) */ - 0x23 2 0x38 0x04 /* JDT=100, display inversion type is column inversion */ - 0x23 2 0x39 0x00 /* Source EQ Setting, EQ1, 0x00=0us */ - 0x23 2 0x3A 0x01 /* Source EQ Setting, EQ2, 0x01 =0.1us */ - 0x23 2 0x3C 0x90 /* Source EQ Setting, EQ3, EQ3 start at 14.4us */ - 0x23 2 0x3D 0xFF /* SET Source OP on time, 0xFF means source op always on */ - 0x23 2 0x3E 0xFF /* SET Source OP off time, 0xFF means source op always on */ - 0x23 2 0x3F 0xFF /* SET Source OP off time, 0xFF means source op always on */ - 0x23 2 0x40 0x02 /* horizontal resolution setting,RSO[2:0]= 0x02 =600RGB, LN[1:0]=2'b00 */ - 0x23 2 0x41 0x80 /* LN[9:0]=0x200=512, vertical resolution is 512*2=1024 line */ - 0x23 2 0x42 0x99 /* SLT, internal line period=0x99->15.3us */ - 0x23 2 0x43 0x14 /* Internal VFP=Ext_VFP=20(0x14) */ - 0x23 2 0x44 0x19 /* Internal _VBP=Ext_VS+Ext_VBP-1=6+20-1=25(0x19) */ - 0x23 2 0x45 0x5A /* Internal_HBP=Ext_HS+Ext_HBP=90(0x5A) */ - 0x23 2 0x55 0x02 /* Seting PWRIC mode, DCDCM=0010-> FP7721BX2 */ - 0x23 2 0x56 0x01 /* No auto Ratio function */ - 0x23 2 0x57 0x69 /* VGH_RT=3'b011,2*AVDD-AVEE,VGL_RT=3'b010=AVEE+VCL-AVDD,VCL_RT=2'b00,0.5*VCIP */ - 0x23 2 0x58 0x0A /* AVDD_S, not use internal AVDD in this model */ - 0x23 2 0x59 0x0A /* VCL = -2.5V */ - 0x23 2 0x5A 0x2E /* VGH = 16.2V */ - 0x23 2 0x5B 0x19 /* VGL = -12V */ - 0x23 2 0x5C 0x15 /* pump clk, VCL_CLK[1:0]=2'b01=HCLK/2=32KHz, VGHVGL_CLK[1:0]=2'b01=HCLK/2=32KHz */ - 0x23 2 0x5D 0x77 /* Gamma voltage setting, VP255-4.793V */ - 0x23 2 0x5E 0x5C /* VP251 */ - 0x23 2 0x5F 0x4D /* VP247 */ - 0x23 2 0x60 0x40 /* VP243 */ - 0x23 2 0x61 0x3D /* VP235 */ - 0x23 2 0x62 0x2F /* VP227 */ - 0x23 2 0x63 0x34 /* VP211 */ - 0x23 2 0x64 0x1F /* VP191 */ - 0x23 2 0x65 0x38 /* VP159 */ - 0x23 2 0x66 0x38 /* VP128 */ - 0x23 2 0x67 0x39 /* VP96 */ - 0x23 2 0x68 0x58 /* VP64 */ - 0x23 2 0x69 0x48 /* VP44 */ - 0x23 2 0x6A 0x51 /* VP28 */ - 0x23 2 0x6B 0x44 /* VP20 */ - 0x23 2 0x6C 0x41 /* VP12 */ - 0x23 2 0x6D 0x35 /* VP8 */ - 0x23 2 0x6E 0x24 /* VP4 */ - 0x23 2 0x6F 0x02 /* VP0 */ - 0x23 2 0x70 0x77 /* VN255 */ - 0x23 2 0x71 0x5C /* VN251 */ - 0x23 2 0x72 0x4D /* VN247 */ - 0x23 2 0x73 0x40 /* VN243 */ - 0x23 2 0x74 0x3D /* VN235 */ - 0x23 2 0x75 0x2F /* VN227 */ - 0x23 2 0x76 0x34 /* VN211 */ - 0x23 2 0x77 0x1F /* VN191 */ - 0x23 2 0x78 0x38 /* VN159 */ - 0x23 2 0x79 0x38 /* VN128 */ - 0x23 2 0x7A 0x39 /* VN96 */ - 0x23 2 0x7B 0x58 /* VN64 */ - 0x23 2 0x7C 0x48 /* VN44 */ - 0x23 2 0x7D 0x51 /* VN28 */ - 0x23 2 0x7E 0x44 /* VN20 */ - 0x23 2 0x7F 0x41 /* VN12 */ - 0x23 2 0x80 0x35 /* VN8 */ - 0x23 2 0x81 0x24 /* VN4 */ - 0x23 2 0x82 0x02 /* VN0 */ - 0x23 2 0xE0 0x02 /* Register setting change to Page 2 */ - 0x23 2 0x00 0x53 /* GIP_L_Forward scan mapping, assign as RESET_EVEN */ - 0x23 2 0x01 0x55 /* assign as VSSG_EVEN */ - 0x23 2 0x02 0x55 /* assign as VSSA_EVEN */ - 0x23 2 0x03 0x51 /* assign as STV2_EVEN */ - 0x23 2 0x04 0x77 /* assign as VDD2_EVEN */ - 0x23 2 0x05 0x57 /* assign as VDD1_EVEN */ - 0x23 2 0x06 0x1F /* assign as VGL */ - 0x23 2 0x07 0x4F /* assign as CK12 */ - 0x23 2 0x08 0x4D /* assign as CK10 */ - 0x23 2 0x09 0x1F /* assign as VGL */ - 0x23 2 0x0A 0x4B /* assign as CK8 */ - 0x23 2 0x0B 0x49 /* assign as CK6 */ - 0x23 2 0x0C 0x1F /* assign as VGL */ - 0x23 2 0x0D 0x47 /* assign as CK4 */ - 0x23 2 0x0E 0x45 /* assign as CK2 */ - 0x23 2 0x0F 0x41 /* assign as STV1_EVEN */ - 0x23 2 0x10 0x1F /* assign as VGL */ - 0x23 2 0x11 0x1F /* assign as VGL */ - 0x23 2 0x12 0x1F /* assign as VGL */ - 0x23 2 0x13 0x55 /* assign as VGG */ - 0x23 2 0x14 0x1F /* assign as VGL */ - 0x23 2 0x15 0x1F /* assign as VGL */ - 0x23 2 0x16 0x52 /* GIP_R_Forward scan mapping, assign as RESET_ODD */ - 0x23 2 0x17 0x55 /* assign as VSSG_ODD */ - 0x23 2 0x18 0x55 /* assign as VSSA_ODD */ - 0x23 2 0x19 0x50 /* assign as STV2_ODD */ - 0x23 2 0x1A 0x77 /* assign as VDD2_ODD */ - 0x23 2 0x1B 0x57 /* assign as VDD1_ODD */ - 0x23 2 0x1C 0x1F /* assign as VGL */ - 0x23 2 0x1D 0x4E /* assign as CK11 */ - 0x23 2 0x1E 0x4C /* assign as CK9 */ - 0x23 2 0x1F 0x1F /* assign as VGL */ - 0x23 2 0x20 0x4A /* assign as CK7 */ - 0x23 2 0x21 0x48 /* assign as CK5 */ - 0x23 2 0x22 0x1F /* assign as VGL */ - 0x23 2 0x23 0x46 /* assign as CK3 */ - 0x23 2 0x24 0x44 /* assign as CK1 */ - 0x23 2 0x25 0x40 /* assign as STV1_ODD */ - 0x23 2 0x26 0x1F /* assign as VGL */ - 0x23 2 0x27 0x1F /* assign as VGL */ - 0x23 2 0x28 0x1F /* assign as VGL */ - 0x23 2 0x29 0x1F /* assign as VGL */ - 0x23 2 0x2A 0x1F /* assign as VGL */ - 0x23 2 0x2B 0x55 /* assign as VGG */ - 0x23 2 0x2C 0x12 /* GIP_L_Reverse Scan mapping, assign as RESET_EVEN */ - 0x23 2 0x2D 0x15 /* assign as VSSG_EVEN */ - 0x23 2 0x2E 0x15 /* assign as VSSA_EVEN */ - 0x23 2 0x2F 0x00 /* assign as STV2_EVEN */ - 0x23 2 0x30 0x17 /* assign as VDD2_EVEN */ - 0x23 2 0x31 0x17 /* assign as VDD1_EVEN */ - 0x23 2 0x32 0x1F /* assign as VGL */ - 0x23 2 0x33 0x08 /* assign as CK12 */ - 0x23 2 0x34 0x0A /* assign as CK10 */ - 0x23 2 0x35 0x1F /* assign as VGL */ - 0x23 2 0x36 0x0C /* assign as CK8 */ - 0x23 2 0x37 0x0E /* assign as CK6 */ - 0x23 2 0x38 0x1F /* assign as VGL */ - 0x23 2 0x39 0x04 /* assign as CK4 */ - 0x23 2 0x3A 0x06 /* assign as CK2 */ - 0x23 2 0x3B 0x10 /* assign as STV1_EVEN */ - 0x23 2 0x3C 0x1F /* assign as VGL */ - 0x23 2 0x3D 0x1F /* assign as VGL */ - 0x23 2 0x3E 0x1F /* assign as VGL */ - 0x23 2 0x3F 0x15 /* assign as VGG */ - 0x23 2 0x40 0x1F /* assign as VGL */ - 0x23 2 0x41 0x1F /* assign as VGL */ - 0x23 2 0x42 0x13 /* GIP_R_Reverse Scan mapping, assign as RESET_ODD */ - 0x23 2 0x43 0x15 /* assign as VSSG_ODD */ - 0x23 2 0x44 0x15 /* assign as VSSA_ODD */ - 0x23 2 0x45 0x01 /* assign as STV2_ODD */ - 0x23 2 0x46 0x17 /* assign as VDD2_ODD */ - 0x23 2 0x47 0x17 /* assign as VDD1_ODD */ - 0x23 2 0x48 0x1F /* assign as VGL */ - 0x23 2 0x49 0x09 /* assign as CK11 */ - 0x23 2 0x4A 0x0B /* assign as CK9 */ - 0x23 2 0x4B 0x1F /* assign as VGL */ - 0x23 2 0x4C 0x0D /* assign as CK7 */ - 0x23 2 0x4D 0x0F /* assign as CK5 */ - 0x23 2 0x4E 0x1F /* assign as VGL */ - 0x23 2 0x4F 0x05 /* assign as CK3 */ - 0x23 2 0x50 0x07 /* assign as CK1 */ - 0x23 2 0x51 0x11 /* assign as STV1_ODD */ - 0x23 2 0x52 0x1F /* assign as VGL */ - 0x23 2 0x53 0x1F /* assign as VGL */ - 0x23 2 0x54 0x1F /* assign as VGL */ - 0x23 2 0x55 0x1F /* assign as VGL */ - 0x23 2 0x56 0x1F /* assign as VGL */ - 0x23 2 0x57 0x15 /* assign as VGG */ - 0x23 2 0x58 0x40 /* GAS OPT=1, When abnormal power off, GIP will pull to VGH */ - 0x23 2 0x59 0x00 /* INIT_W=0, no INIT function in this panel */ - 0x23 2 0x5A 0x00 /* INIT[10:0], no INIT function in this panel */ - 0x23 2 0x5B 0x10 /* STV_NUM,STV_S0[10:8], 2 STV pulses */ - 0x23 2 0x5C 0x14 /* STV_S0[7:0], STV start from 21th hsync after vsync */ - 0x23 2 0x5D 0x40 /* STV_W=4, STV width is 4 Hline; STV1 delay 1 hline with STV0 */ - 0x23 2 0x5E 0x01 /* STV_S2, STV2 delay 2 hline with STV0 */ - 0x23 2 0x5F 0x02 /* STV_S3, STV3 delay 3 hline with STV0 */ - 0x23 2 0x60 0x40 /* ETV_W=4, ETV witdh is 4 hline; ETV1 delay 1 hilne from ETV0 */ - 0x23 2 0x61 0x03 /* ETV_S2, ETV2 delay 4 hline with ETV0 */ - 0x23 2 0x62 0x04 /* ETV_S3, ETV3 delay 5 hline with ETV0 */ - 0x23 2 0x63 0x7A /* SETV_ON for STV/ETV on time, rising at 12.2us after hsync */ - 0x23 2 0x64 0x7A /* SETV_OFF for STV/ETV off time , falling at 12.2us after hsync */ - 0x23 2 0x65 0x74 /* ETV_EN=1, enable ETV function; ETV_NUM=3, using 4 ETV pulse, */ - 0x23 2 0x66 0x16 /* ETV_S0=0x416, EVT start at 1046th hsync fater vaync */ - 0x23 2 0x67 0xB4 /* CKV_NUM=2'b1011, using 12 CKV pulse; CKV0_W=4. CKV width is 4 hline */ - 0x23 2 0x68 0x16 /* CKV0_S0 , CKV start from 23th hsync after vsync */ - 0x23 2 0x69 0x7A /* CKV0_on ,for CKV on time, rising at 12.2us after hsync */ - 0x23 2 0x6A 0x7A /* CKV0_off ,for CKV off time, falling at 12.2us after hsync */ - 0x23 2 0x6B 0x0C /* CKV0_DUM, total CKV pulse number=1024+12=1036 */ - 0x23 2 0x6C 0x00 /* GIP Line EQ option , disable GEQ_Line function */ - 0x23 2 0x6D 0x04 /* GIP rising EQ, period is 0.4us */ - 0x23 2 0x6E 0x04 /* GIP fallig EQ, period is 0.4us */ - 0x23 2 0x6F 0x88 /* GIP_DR; CKV0_CON, no continuous CKV0; CKV1_CON, no continuous CKV1 */ - 0x23 2 0x70 0x00 /* CKV1_NUM, CKV0_W , no CKV group 1 function in this panel, don't care */ - 0x23 2 0x71 0x00 /* CKV1_S0, no CKV group 1 function in this panel, don't care */ - 0x23 2 0x72 0x06 /* CKV1_on , no CKV group 1 function in this panel, don't care */ - 0x23 2 0x73 0x7B /* CKV1_off time, no CKV group 1 function in this panel, don't care */ - 0x23 2 0x74 0x00 /* CKV1_DUM, no CKV group 1 function in this panel, don't care */ - 0x23 2 0x75 0xBC /* FLM_EN, enable FLM function; FLM_W=0x3C, FLM toggle period is 60 frame */ - 0x23 2 0x76 0x00 /* FLM on time , FLM on(rising) at 1st hsync after vsync */ - 0x23 2 0x77 0x04 /* VEN_EN, VEN_W, no VEN function in this panel, don't care */ - 0x23 2 0x78 0x2C /* FLM_OFF, FLM off(falling) at 1068th hsync after vsync */ - 0x23 2 0x79 0x00 /* VEN_W , no VEN function in this panel, don't care */ - 0x23 2 0x7A 0x00 /* VEN_S0 , no VEN function in this panel, don't care */ - 0x23 2 0x7B 0x00 /* VEN_S1 , no VEN function in this panel, don't care */ - 0x23 2 0x7C 0x00 /* VEN_DUM , no VEN function in this panel, don't care */ - 0x23 2 0x7D 0x03 /* VEN on time , no VEN function in this panel, don't care */ - 0x23 2 0x7E 0x7B /* VEN off time , no VEN function in this panel, don't care */ - 0x23 2 0xE0 0x03 /* Register setting change to Page 3 */ - 0x23 2 0xAF 0x20 /* Set CABC, disable CABC TP detect, for CABC pattern change more smooth */ - 0x23 2 0xE0 0x04 /* Register setting change to Page 4 */ - 0x23 2 0x09 0x11 /* Source level at blanking period, sweeping V0 level */ - 0x23 2 0x0E 0x48 /* Source EQ option, EQ to PCAP,NCAP */ - 0x23 2 0x2B 0x2B /* ESD Protect, clock lane op behavior follow data lane, improve ESD performance */ - 0x23 2 0x2E 0x44 /* ESD protect, disable special packet */ - 0x23 2 0x41 0xFF /* Set CABC, for CABC pattern change more smooth */ - 0x23 2 0xE0 0x00 /* Register setting change to Page 0 */ - 0x23 2 0xE6 0x02 /* Enable Watch Dog */ - 0x23 2 0xE7 0x0C /* Watch Dog timer setting, WD alarm time is 12*512osc after hsync stop */ - 0x23 2 0x51 0xFF /* CABC Option, 0x80=50% duty, 0xFF=100% */ - 0x23 2 0x53 0x2C /* enable dimming, BCTRL, BL */ - 0x23 2 0x55 0x00 /* CABC mode, 0x00 is manual mode */ - 0x05 1 0x11 /* SLPOUT */ - 0xFF 125 /* Delay 125ms */ - 0x05 1 0x29 /* Display On */ - 0xFF 0xFF /* Ending */ - >; - init_off = < - 0xff 5 - 0x05 1 0x28 /* display off */ - 0xff 60 /* delay 60ms */ - 0x05 1 0x10 /* sleep in */ - 0xff 110 /* delay 110ms */ - 0xff 0xff>; /* ending */ - }; - }; - - backlight{ - compatible = "amlogic, backlight-g12a"; - status = "okay"; - key_valid = <0>; - pinctrl-names = "pwm_on","pwm_off"; - pinctrl-0 = <&pwm_f_pins2>; - pinctrl-1 = <&bl_pwm_off_pins>; - pinctrl_version = <2>; /* for uboot */ - bl_pwm_config = <&bl_pwm_conf>; - bl-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_HIGH - &gpio GPIOH_5 GPIO_ACTIVE_HIGH>; - bl_gpio_names = "GPIOH_4","GPIOH_5"; - - /* pwm port: PWM_A, PWM_B, PWM_C, PWM_D, PWM_E, PWM_F, PWM_VS*/ - /* power index:(point gpios_index, 0xff=invalid) - * power value:(0=output low, 1=output high, 2=input) - * power delay:(unit in ms) - */ - - backlight_0{ - index = <0>; - bl_name = "backlight_pwm"; - bl_level_default_uboot_kernel = <100 100>; - bl_level_attr = <255 10 /*max, min*/ - 128 128>; /*mid, mid_mapping*/ - bl_ctrl_method = <1>; /* 1=pwm, 2=pwm_combo, 4=extern */ - bl_power_attr = <0 /*en_gpio_index*/ - 1 0 /*on_value, off_value*/ - 200 200>; /*on_delay(ms), off_delay(ms)*/ - bl_pwm_port = "PWM_F"; - bl_pwm_attr = <0 /*pwm_method*/ - 180 /*pwm_freq(pwm:Hz, pwm_vs:multiple of vs)*/ - 100 25>; /*duty_max(%), duty_min(%)*/ - bl_pwm_power = <1 1 /*pwm_gpio_index, pwm_gpio_off*/ - 10 10>; /*pwm_on_delay(ms), pwm_off_delay(ms)*/ - bl_pwm_en_sequence_reverse = <0>; /* 1 for reverse */ - }; - backlight_1{ - index = <1>; - bl_name = "bl_extern"; - bl_level_default_uboot_kernel = <100 100>; - bl_level_attr = <255 10 /*max, min*/ - 128 128>; /*mid, mid_mapping*/ - bl_ctrl_method = <4>; /*1=pwm, 2=pwm_combo, 4=extern*/ - bl_power_attr = <1 /*en_gpio_index*/ - 1 0 /*on_value, off_value*/ - 200 200>; /*on_delay(ms), off_delay(ms)*/ - bl_extern_index = <0>; - }; - }; - bl_pwm_conf:bl_pwm_conf{ - pwm_channel_0 { - pwm_port_index = <5>; - pwms = <&pwm_ef MESON_PWM_1 30040 0>; - }; - }; - - bl_extern{ - compatible = "amlogic, bl_extern"; - status = "disabled"; - i2c_bus = "i2c_bus_3"; - - extern_0{ - index = <0>; - extern_name = "i2c_lp8556"; - type = <0>; /*0=i2c, 1=spi, 2=mipi*/ - i2c_address = <0x2c>; /*7bit i2c address*/ - dim_max_min = <255 10>; - }; - - extern_1{ - index = <1>; - extern_name = "mipi_lt070me05"; - type = <2>; /*0=i2c, 1=spi, 2=mipi*/ - dim_max_min = <255 10>; - }; - }; -};/* end of panel */
diff --git a/arch/arm/dts/elaine-p2-panel.dtsi b/arch/arm/dts/elaine-p2-panel.dtsi deleted file mode 100755 index 8b7cb25..0000000 --- a/arch/arm/dts/elaine-p2-panel.dtsi +++ /dev/null
@@ -1,973 +0,0 @@ -/* - * arch/arm/dts/elaine-p2-panel.dtsi - * - * Copyright (C) 2016 Amlogic, Inc. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - */ - -/ { - lcd{ - compatible = "amlogic, lcd-sm1"; - mode = "tablet"; - status = "okay"; - key_valid = <0>; - clocks = <&clkc CLKID_MIPI_DSI_HOST - &clkc CLKID_MIPI_DSI_PHY - &clkc CLKID_DSI_MEAS_COMP - &clkc CLKID_VCLK2_ENCL - &clkc CLKID_VCLK2_VENCL - &clkc CLKID_GP0_PLL>; - clock-names = "dsi_host_gate", - "dsi_phy_gate", - "dsi_meas", - "encl_top_gate", - "encl_int_gate", - "gp0_pll"; - reg = <0x0 0xffd07000 0x0 0x400 /* dsi_host */ - 0x0 0xff644000 0x0 0x200>; /* dsi_phy */ - interrupts = <0 3 1 - 0 56 1>; - interrupt-names = "vsync","vsync2"; - pinctrl_version = <2>; /* for uboot */ - - /* power type: - * (0=cpu_gpio, 1=pmu_gpio, 2=signal,3=extern, 0xff=ending) - * power index: - * (point gpios_index, or extern_index,0xff=invalid) - * power value:(0=output low, 1=output high, 2=input) - * power delay:(unit in ms) - */ - lcd_cpu-gpios = <&gpio GPIOZ_13 GPIO_ACTIVE_HIGH>; - lcd_cpu_gpio_names = "GPIOZ_13"; - - boe_fiti9364_7{ - model_name = "TV070WSM_FT9364"; - interface = "mipi"; - basic_setting = <600 1024 /*h_active, v_active*/ - 700 1053 /*h_period, v_period*/ - 8 /*lcd_bits*/ - 95 163>; /*screen_widht, screen_height*/ - lcd_timing = <24 36 0 /*hs_width,hs_bp,hs_pol*/ - 2 8 0>; /*vs_width,vs_bp,vs_pol*/ - clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/ - 0 /*clk_ss_level*/ - 1 /*clk_auto_generate*/ - 44226000>; /*pixel_clk(unit in Hz)*/ - mipi_attr = <4 /*lane_num*/ - 400 /*bit_rate_max(MHz)*/ - 0 /*factor(*100, default 0 for auto)*/ - 1 /*operation_mode_init(0=video, 1=command)*/ - 0 /*operation_mode_display(0=video, 1=command)*/ - 2 /* - *video_mode_type - *(0=sync_pulse,1=sync_event,2=burst) - */ - 0 /*clk_always_hs(0=disable,1=enable)*/ - 0>; /*phy_switch(0=auto,1=standard,2=slow)*/ - /* dsi_init: data_type, num, data... */ - dsi_init_on = < - 0xff 10 - 0xf0 3 0 1 30 /* reset high, delay 30ms */ - 0xf0 3 0 0 10 /* reset low, delay 10ms */ - 0xf0 3 0 1 30 /* reset high, delay 30ms */ - 0xfc 2 0x04 3 /* check_reg, check_cnt */ - 0xff 0xff>; /* ending flag */ - dsi_init_off = < - 0xff 5 /* delay 5ms */ - 0xff 0xff>; /* ending flag */ - /* extern_init: 0xff for invalid */ - extern_init = <1>; - /* power step: type,index,value,delay(ms) */ - power_on_step = < - 0 1 0 200 - 2 0 0 0 - 0xff 0 0 0>; - power_off_step = < - 2 0 0 5 /* delay 5ms after mipi off */ - 0 0 0 20 /* reset low */ - 0 1 1 100 /* panel power off */ - 0xff 0 0 0>; - backlight_index = <0>; - }; - - inx_fiti9364_7{ - model_name = "P070ACB_FT9364"; - interface = "mipi"; - basic_setting = <600 1024 /*h_active, v_active*/ - 770 1070 /*h_period, v_period*/ - 8 /*lcd_bits*/ - 3 5>; /*screen_widht, screen_height*/ - lcd_timing = <10 80 0 /*hs_width,hs_bp,hs_pol*/ - 6 20 0>; /*vs_width,vs_bp,vs_pol*/ - clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/ - 0 /*clk_ss_level*/ - 1 /*clk_auto_generate*/ - 49434000>; /*pixel_clk(unit in Hz)*/ - mipi_attr = <4 /*lane_num*/ - 400 /*bit_rate_max(MHz)*/ - 0 /*factor(*100, default 0 for auto)*/ - 1 /*operation_mode_init(0=video, 1=command)*/ - 0 /*operation_mode_display(0=video, 1=command)*/ - 2 /* - *video_mode_type - *(0=sync_pulse,1=sync_event,2=burst) - */ - 0 /*clk_always_hs(0=disable,1=enable)*/ - 0>; /*phy_switch(0=auto,1=standard,2=slow)*/ - /* dsi_init: data_type, num, data... */ - dsi_init_on = < - 0xff 10 - 0xf0 3 0 1 30 /* reset high, delay 30ms */ - 0xf0 3 0 0 10 /* reset low, delay 10ms */ - 0xf0 3 0 1 30 /* reset high, delay 30ms */ - 0xfc 2 0x04 3 /* check_reg, check_cnt */ - 0xff 0xff>; /* ending flag */ - dsi_init_off = < - 0xff 5 /* delay 5ms */ - 0xff 0xff>; /* ending flag */ - /* extern_init: 0xff for invalid */ - extern_init = <2>; - /* power step: type,index,value,delay(ms) */ - power_on_step = < - 0 1 0 200 /* panel power on */ - 2 0 0 0 - 0xff 0 0 0>; - power_off_step = < - 2 0 0 5 /* delay 5ms after mipi off */ - 0 0 0 20 /* reset low */ - 0 1 1 100 /* panel power off */ - 0xff 0 0 0>; - backlight_index = <0>; - }; - - kd_fiti9364_7{ - model_name = "KD070D82_FT9364"; - interface = "mipi"; - basic_setting = <600 1024 /*h_active, v_active*/ - 770 1070 /*h_period, v_period*/ - 8 /*lcd_bits*/ - 3 5>; /*screen_widht, screen_height*/ - lcd_timing = <10 80 0 /*hs_width,hs_bp,hs_pol*/ - 6 20 0>; /*vs_width,vs_bp,vs_pol*/ - clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/ - 0 /*clk_ss_level*/ - 1 /*clk_auto_generate*/ - 49434000>; /*pixel_clk(unit in Hz)*/ - mipi_attr = <4 /*lane_num*/ - 400 /*bit_rate_max(MHz)*/ - 0 /*factor(*100, default 0 for auto)*/ - 1 /*operation_mode_init(0=video, 1=command)*/ - 0 /*operation_mode_display(0=video, 1=command)*/ - 2 /* - *video_mode_type - *(0=sync_pulse,1=sync_event,2=burst) - */ - 0 /*clk_always_hs(0=disable,1=enable)*/ - 0>; /*phy_switch(0=auto,1=standard,2=slow)*/ - /* dsi_init: data_type, num, data... */ - dsi_init_on = < - 0xff 10 - 0xf0 3 0 1 30 /* reset high, delay 30ms */ - 0xf0 3 0 0 10 /* reset low, delay 10ms */ - 0xf0 3 0 1 30 /* reset high, delay 30ms */ - 0xfc 2 0x04 3 /* check_reg, check_cnt */ - 0xff 0xff>; /* ending flag */ - dsi_init_off = < - 0xff 5 /* delay 5ms */ - 0xff 0xff>; /* ending flag */ - /* extern_init: 0xff for invalid */ - extern_init = <3>; - /* power step: type,index,value,delay(ms) */ - power_on_step = < - 0 1 0 200 /* panel power on */ - 2 0 0 0 - 0xff 0 0 0>; - power_off_step = < - 2 0 0 5 /* delay 5ms after mipi off */ - 0 0 0 20 /* reset low */ - 0 1 1 100 /* panel power off */ - 0xff 0 0 0>; - backlight_index = <0>; - }; - - }; - - lcd_extern{ - compatible = "amlogic, lcd_extern"; - dev_name = "lcd_extern"; - status = "okay"; - key_valid = <0>; - - extern_1{ - index = <1>; - extern_name = "mipi_default"; // TV070WSM_FT9364 - status = "okay"; - type = <2>; /* 0=i2c, 1=spi, 2=mipi */ - cmd_size = <0xff>; - init_on = < - 0x23 2 0xE0 0x00 - 0x23 2 0xE1 0x93 - 0x23 2 0xE2 0x65 - 0x23 2 0xE3 0xF8 - 0x23 2 0xE0 0x01 - 0x23 2 0x00 0x00 - 0x23 2 0x01 0x90 - 0x23 2 0x03 0x00 - 0x23 2 0x04 0x90 - 0x23 2 0x17 0x00 - 0x23 2 0x18 0xB0 - 0x23 2 0x19 0x01 - 0x23 2 0x1A 0x00 - 0x23 2 0x1B 0xB0 - 0x23 2 0x1C 0x01 - 0x23 2 0x1F 0x3E - 0x23 2 0x20 0x2F - 0x23 2 0x21 0x2F - 0x23 2 0x22 0x0E - 0x23 2 0x37 0x69 - 0x23 2 0x38 0x05 - 0x23 2 0x39 0x00 - 0x23 2 0x3A 0x01 - 0x23 2 0x3C 0x90 - 0x23 2 0x3D 0xFF - 0x23 2 0x3E 0xFF - 0x23 2 0x3F 0xFF - 0x23 2 0x40 0x02 - 0x23 2 0x41 0x80 - 0x23 2 0x42 0x99 - 0x23 2 0x43 0x06 - 0x23 2 0x44 0x09 - 0x23 2 0x45 0x3C - 0x23 2 0x4B 0x04 - 0x23 2 0x55 0x0D - 0x23 2 0x56 0x01 - 0x23 2 0x57 0x89 - 0x23 2 0x58 0x0A - 0x23 2 0x59 0x0A - 0x23 2 0x5A 0x27 - 0x23 2 0x5B 0x15 - 0x23 2 0x5D 0x7C - 0x23 2 0x5E 0x67 - 0x23 2 0x5F 0x58 - 0x23 2 0x60 0x4C - 0x23 2 0x61 0x48 - 0x23 2 0x62 0x38 - 0x23 2 0x63 0x3C - 0x23 2 0x64 0x24 - 0x23 2 0x65 0x3B - 0x23 2 0x66 0x38 - 0x23 2 0x67 0x36 - 0x23 2 0x68 0x53 - 0x23 2 0x69 0x3F - 0x23 2 0x6A 0x44 - 0x23 2 0x6B 0x35 - 0x23 2 0x6C 0x2E - 0x23 2 0x6D 0x1F - 0x23 2 0x6E 0x0C - 0x23 2 0x6F 0x00 - 0x23 2 0x70 0x7C - 0x23 2 0x71 0x67 - 0x23 2 0x72 0x58 - 0x23 2 0x73 0x4C - 0x23 2 0x74 0x48 - 0x23 2 0x75 0x38 - 0x23 2 0x76 0x3C - 0x23 2 0x77 0x24 - 0x23 2 0x78 0x3B - 0x23 2 0x79 0x38 - 0x23 2 0x7A 0x36 - 0x23 2 0x7B 0x53 - 0x23 2 0x7C 0x3F - 0x23 2 0x7D 0x44 - 0x23 2 0x7E 0x35 - 0x23 2 0x7F 0x2E - 0x23 2 0x80 0x1F - 0x23 2 0x81 0x0C - 0x23 2 0x82 0x00 - 0x23 2 0xE0 0x02 - 0x23 2 0x00 0x45 - 0x23 2 0x01 0x45 - 0x23 2 0x02 0x47 - 0x23 2 0x03 0x47 - 0x23 2 0x04 0x41 - 0x23 2 0x05 0x41 - 0x23 2 0x06 0x1F - 0x23 2 0x07 0x1F - 0x23 2 0x08 0x1F - 0x23 2 0x09 0x1F - 0x23 2 0x0A 0x1F - 0x23 2 0x0B 0x1F - 0x23 2 0x0C 0x1F - 0x23 2 0x0D 0x1D - 0x23 2 0x0E 0x1D - 0x23 2 0x0F 0x1D - 0x23 2 0x10 0x1F - 0x23 2 0x11 0x1F - 0x23 2 0x12 0x1F - 0x23 2 0x13 0x1F - 0x23 2 0x14 0x1F - 0x23 2 0x15 0x1F - 0x23 2 0x16 0x44 - 0x23 2 0x17 0x44 - 0x23 2 0x18 0x46 - 0x23 2 0x19 0x46 - 0x23 2 0x1A 0x40 - 0x23 2 0x1B 0x40 - 0x23 2 0x1C 0x1F - 0x23 2 0x1D 0x1F - 0x23 2 0x1E 0x1F - 0x23 2 0x1F 0x1F - 0x23 2 0x20 0x1F - 0x23 2 0x21 0x1F - 0x23 2 0x22 0x1F - 0x23 2 0x23 0x1D - 0x23 2 0x24 0x1D - 0x23 2 0x25 0x1D - 0x23 2 0x26 0x1F - 0x23 2 0x27 0x1F - 0x23 2 0x28 0x1F - 0x23 2 0x29 0x1F - 0x23 2 0x2A 0x1F - 0x23 2 0x2B 0x1F - 0x23 2 0x58 0x40 - 0x23 2 0x59 0x00 - 0x23 2 0x5A 0x00 - 0x23 2 0x5B 0x10 - 0x23 2 0x5C 0x07 - 0x23 2 0x5D 0x20 - 0x23 2 0x5E 0x00 - 0x23 2 0x5F 0x00 - 0x23 2 0x61 0x00 - 0x23 2 0x62 0x00 - 0x23 2 0x63 0x7A - 0x23 2 0x64 0x7A - 0x23 2 0x65 0x00 - 0x23 2 0x66 0x00 - 0x23 2 0x67 0x32 - 0x23 2 0x68 0x08 - 0x23 2 0x69 0x7A - 0x23 2 0x6A 0x7A - 0x23 2 0x6B 0x00 - 0x23 2 0x6C 0x00 - 0x23 2 0x6D 0x00 - 0x23 2 0x6E 0x00 - 0x23 2 0x6F 0x89 - 0x23 2 0x70 0x00 - 0x23 2 0x71 0x00 - 0x23 2 0x72 0x06 - 0x23 2 0x73 0x7B - 0x23 2 0x74 0x00 - 0x23 2 0x75 0x07 - 0x23 2 0x76 0x00 - 0x23 2 0x77 0x5D - 0x23 2 0x78 0x17 - 0x23 2 0x79 0x1F - 0x23 2 0x7A 0x00 - 0x23 2 0x7B 0x00 - 0x23 2 0x7C 0x00 - 0x23 2 0x7D 0x03 - 0x23 2 0x7E 0x7B - 0x23 2 0xE0 0x03 - 0x23 2 0xAF 0x20 - 0x23 2 0xE0 0x04 - 0x23 2 0x09 0x11 - 0x23 2 0x0E 0x48 - 0x23 2 0x2B 0x2B - 0x23 2 0x2E 0x44 - 0x23 2 0x41 0xFF - 0x23 2 0xE0 0x00 - 0x23 2 0xE6 0x02 - 0x23 2 0xE7 0x0C - 0x23 2 0x51 0xFF - 0x23 2 0x53 0x2C - 0x23 2 0x55 0x00 - 0x05 1 0x11 - 0xFF 125 /* Delay 125ms */ - 0x05 1 0x29 - 0xFF 0xFF /* Ending Flag */ - >; - init_off = < - 0xff 5 - 0x05 1 0x28 /* display off */ - 0xff 60 /* delay 60ms */ - 0x05 1 0x10 /* sleep in */ - 0xff 110 /* delay 110ms */ - 0xff 0xff>; /* ending */ - }; - - extern_2{ - index = <2>; - extern_name = "mipi_default"; // P070ACB_FT9364 - status = "okay"; - type = <2>; /* 0=i2c, 1=spi, 2=mipi */ - cmd_size = <0xff>; - init_on = < - 0x23 2 0xE0 0x00 /* Page 0 */ - 0x23 2 0xE1 0x93 /* PASSWORD */ - 0x23 2 0xE2 0x65 - 0x23 2 0xE3 0xF8 - 0x23 2 0x80 0x03 /* DSI 4 lane */ - 0x23 2 0xE0 0x01 /* Page 01 */ - 0x23 2 0x0C 0x74 /* Set PWRIC */ - 0x23 2 0x17 0x00 /* Set Gamma Power */ - 0x23 2 0x18 0xEF /* VGMP=5.1V */ - 0x23 2 0x19 0x00 /* VGSP=0V */ - 0x23 2 0x1A 0x00 - 0x23 2 0x1B 0xEF /* VGMN=-5.1V */ - 0x23 2 0x1C 0x00 /* VGSN=0V */ - 0x23 2 0x1F 0x70 /* VGH_REG=16.2V */ - 0x23 2 0x20 0x2D /* VGL_REG=-12V */ - 0x23 2 0x21 0x2D /* VGL_REG2=-12V */ - 0x23 2 0x22 0x7E /* VGH_REG short to VGH VGL_REG short to VGL */ - 0x23 2 0x26 0xF3 /* VDDD from IOVCC/VCI */ - 0x23 2 0x37 0x09 /* SS=1 BGR=1 */ - 0x23 2 0x38 0x04 /* JDT=100 column inversion */ - 0x23 2 0x39 0x00 /* Source EQ Setting EQ1 */ - 0x23 2 0x3A 0x01 /* Source EQ Setting EQ2 */ - 0x23 2 0x3C 0x90 /* Source EQ Setting EQ3 */ - 0x23 2 0x3D 0xFF /* SET Source OP on time */ - 0x23 2 0x3E 0xFF /* SET Source OP off time */ - 0x23 2 0x3F 0xFF /* SET Source OP off time */ - 0x23 2 0x40 0x02 /* RSO=640 RGB */ - 0x23 2 0x41 0x80 /* LN=512->1024 line */ - 0x23 2 0x42 0x99 /* SLT internal line period */ - 0x23 2 0x43 0x14 /* VFP */ - 0x23 2 0x44 0x19 /* VBP */ - 0x23 2 0x45 0x5A /* HBP */ - 0x23 2 0x4B 0x04 - 0x23 2 0x55 0x02 /* DCDCM=0010 FP7721BX2 */ - 0x23 2 0x56 0x01 /* No auto Ratio function */ - 0x23 2 0x57 0x69 /* VGH_RT=3'b011 2*AVDD-AVEE VGL_RT=3'b010=AVEE+VCL-AVDD VCL_RT=2'b00 0.5*VCIP */ - 0x23 2 0x58 0x0A /* AVDD_S */ - 0x23 2 0x59 0x0A /* VCL = -2.5V */ - 0x23 2 0x5A 0x2E /* VGH = 16.2V */ - 0x23 2 0x5B 0x19 /* VGL = -12V */ - 0x23 2 0x5C 0x15 /* pump clk */ - 0x23 2 0x5D 0x71 /* V255 positive voltage from 4.888V to 4.888V */ - 0x23 2 0x5E 0x65 /* V251 positive voltage from 4.533V to 4.718V */ - 0x23 2 0x5F 0x55 /* V247 positive voltage from 4.349V to 4.491V */ - 0x23 2 0x60 0x49 /* V243 positive voltage from 4.179V to 4.321V */ - 0x23 2 0x61 0x46 /* V235 positive voltage from 3.910V to 4.052V */ - 0x23 2 0x62 0x38 /* V227 positive voltage from 3.726V to 3.853V */ - 0x23 2 0x63 0x3D /* V211 positive voltage from 3.428V to 3.528V */ - 0x23 2 0x64 0x29 /* V191 positive voltage from 3.159V to 3.244V */ - 0x23 2 0x65 0x43 /* V159 positive voltage from 2.805V to 2.876V */ - 0x23 2 0x66 0x42 /* V128 positive voltage from 2.522V to 2.578V */ - 0x23 2 0x67 0x44 /* V96 positive voltage from 2.267V to 2.323V */ - 0x23 2 0x68 0x63 /* V64 positive voltage from 1.941V to 2.026V */ - 0x23 2 0x69 0x53 /* V44 positive voltage from 1.686V to 1.799V */ - 0x23 2 0x6A 0x5B /* V28 positive voltage from 1.431V to 1.516V */ - 0x23 2 0x6B 0x4E /* V20 positive voltage from 1.275V to 1.322V */ - 0x23 2 0x6C 0x4C /* V12 positive voltage from 1.077V to 1.077V */ - 0x23 2 0x6D 0x41 /* V8 positive voltage from 0.949V to 0.921V */ - 0x23 2 0x6E 0x2D /* V4 positive voltage from 0.723V to 0.638V */ - 0x23 2 0x6F 0x23 /* V0 positive voltage from 0.496V to 0.496V */ - 0x23 2 0x70 0x71 /* V255 negative voltage from -4.888V to -4.888V */ - 0x23 2 0x71 0x4C /* V251 negative voltage from -4.179V to -4.363V */ - 0x23 2 0x72 0x3B /* V247 negative voltage from -3.995V to -4.123V */ - 0x23 2 0x73 0x30 /* V243 negative voltage from -3.825V to -3.967V */ - 0x23 2 0x74 0x2D /* V233 negative voltage from -3.556V to -3.698V */ - 0x23 2 0x75 0x1F /* V227 negative voltage from -3.372V to -3.499V */ - 0x23 2 0x76 0x25 /* V211 negative voltage from -3.088V to -3.188V */ - 0x23 2 0x77 0x10 /* V191 negative voltage from -2.805V to -2.890V */ - 0x23 2 0x78 0x2A /* V159 negative voltage from -2.451V to -2.522V */ - 0x23 2 0x79 0x2A /* V128 negative voltage from -2.182V to -2.238V */ - 0x23 2 0x7A 0x2B /* V96 negative voltage from -1.913V to -1.969V */ - 0x23 2 0x7B 0x4A /* V64 negative voltage from -1.587V to -1.672V */ - 0x23 2 0x7C 0x3A /* V44 negative voltage from -1.332V to -1.445V */ - 0x23 2 0x7D 0x43 /* V28 negative voltage from -1.091V to -1.176V */ - 0x23 2 0x7E 0x36 /* V20 negative voltage from -0.935V to -0.992V */ - 0x23 2 0x7F 0x33 /* V12 negative voltage from -0.723V to -0.723V */ - 0x23 2 0x80 0x28 /* V8 negative voltage from -0.595V to -0.567V */ - 0x23 2 0x81 0x14 /* V4 negative voltage from -0.368V to -0.283V */ - 0x23 2 0x82 0x0B /* V0 negative voltage from -0.156V to -0.156V */ - 0x23 2 0xE0 0x02 /* Page2 */ - 0x23 2 0x00 0x53 /* GIP_L Pin mapping RESET_EVEN */ - 0x23 2 0x01 0x55 /* VSSG_EVEN */ - 0x23 2 0x02 0x55 /* VSSA_EVEN */ - 0x23 2 0x03 0x51 /* STV2_EVEN */ - 0x23 2 0x04 0x77 /* VDD2_EVEN */ - 0x23 2 0x05 0x57 /* VDD1_EVEN */ - 0x23 2 0x06 0x1F /* VGL */ - 0x23 2 0x07 0x4F /* CK12 */ - 0x23 2 0x08 0x4D /* CK10 */ - 0x23 2 0x09 0x1F /* VGL */ - 0x23 2 0x0A 0x4B /* CK8 */ - 0x23 2 0x0B 0x49 /* CK6 */ - 0x23 2 0x0C 0x1F /* VGL */ - 0x23 2 0x0D 0x47 /* CK4 */ - 0x23 2 0x0E 0x45 /* CK2 */ - 0x23 2 0x0F 0x41 /* STV1_EVEN */ - 0x23 2 0x10 0x1F /* VGL */ - 0x23 2 0x11 0x1F /* VGL */ - 0x23 2 0x12 0x1F /* VGL */ - 0x23 2 0x13 0x55 /* VGG */ - 0x23 2 0x14 0x1F /* VGL */ - 0x23 2 0x15 0x1F /* VGL */ - 0x23 2 0x16 0x52 /* GIP_R Pin mapping RESET_ODD */ - 0x23 2 0x17 0x55 /* VSSG_ODD */ - 0x23 2 0x18 0x55 /* VSSA_ODD */ - 0x23 2 0x19 0x50 /* STV2_ODD */ - 0x23 2 0x1A 0x77 /* VDD2_ODD */ - 0x23 2 0x1B 0x57 /* VDD1_ODD */ - 0x23 2 0x1C 0x1F /* VGL */ - 0x23 2 0x1D 0x4E /* CK11 */ - 0x23 2 0x1E 0x4C /* CK9 */ - 0x23 2 0x1F 0x1F /* VGL */ - 0x23 2 0x20 0x4A /* CK7 */ - 0x23 2 0x21 0x48 /* CK5 */ - 0x23 2 0x22 0x1F /* VGL */ - 0x23 2 0x23 0x46 /* CK3 */ - 0x23 2 0x24 0x44 /* CK1 */ - 0x23 2 0x25 0x40 /* STV1_ODD */ - 0x23 2 0x26 0x1F /* VGL */ - 0x23 2 0x27 0x1F /* VGL */ - 0x23 2 0x28 0x1F /* VGL */ - 0x23 2 0x29 0x1F /* VGL */ - 0x23 2 0x2A 0x1F /* VGL */ - 0x23 2 0x2B 0x55 /* VGG */ - 0x23 2 0x2C 0x12 /* GIP_L_GS Pin mapping RESET_EVEN */ - 0x23 2 0x2D 0x15 /* VSSG_EVEN */ - 0x23 2 0x2E 0x15 /* VSSA_EVEN */ - 0x23 2 0x2F 0x00 /* STV2_EVEN */ - 0x23 2 0x30 0x17 /* VDD2_EVEN */ - 0x23 2 0x31 0x17 /* VDD1_EVEN */ - 0x23 2 0x32 0x1F /* VGL */ - 0x23 2 0x33 0x08 /* CK12 */ - 0x23 2 0x34 0x0A /* CK10 */ - 0x23 2 0x35 0x1F /* VGL */ - 0x23 2 0x36 0x0C /* CK8 */ - 0x23 2 0x37 0x0E /* CK6 */ - 0x23 2 0x38 0x1F /* VGL */ - 0x23 2 0x39 0x04 /* CK4 */ - 0x23 2 0x3A 0x06 /* CK2 */ - 0x23 2 0x3B 0x10 /* STV1_EVEN */ - 0x23 2 0x3C 0x1F /* VGL */ - 0x23 2 0x3D 0x1F /* VGL */ - 0x23 2 0x3E 0x1F /* VGL */ - 0x23 2 0x3F 0x15 /* VGG */ - 0x23 2 0x40 0x1F /* VGL */ - 0x23 2 0x41 0x1F /* VGL */ - 0x23 2 0x42 0x13 /* GIP_R_GS Pin mapping RESET_ODD */ - 0x23 2 0x43 0x15 /* VSSG_ODD */ - 0x23 2 0x44 0x15 /* VSSA_ODD */ - 0x23 2 0x45 0x01 /* STV2_ODD */ - 0x23 2 0x46 0x37 /* VDD2_ODD */ - 0x23 2 0x47 0x17 /* VDD1_ODD */ - 0x23 2 0x48 0x1F /* VGL */ - 0x23 2 0x49 0x09 /* CK11 */ - 0x23 2 0x4A 0x0B /* CK9 */ - 0x23 2 0x4B 0x1F /* VGL */ - 0x23 2 0x4C 0x0D /* CK7 */ - 0x23 2 0x4D 0x0F /* CK5 */ - 0x23 2 0x4E 0x1F /* VGL */ - 0x23 2 0x4F 0x05 /* CK3 */ - 0x23 2 0x50 0x07 /* CK1 */ - 0x23 2 0x51 0x11 /* STV1_ODD */ - 0x23 2 0x52 0x1F /* VGL */ - 0x23 2 0x53 0x1F /* VGL */ - 0x23 2 0x54 0x1F /* VGL */ - 0x23 2 0x55 0x1F /* VGL */ - 0x23 2 0x56 0x1F /* VGL */ - 0x23 2 0x57 0x15 /* VGG */ - 0x23 2 0x58 0x40 /* GAS OPT=1 for abnormal power off */ - 0x23 2 0x59 0x00 /* INIT_W */ - 0x23 2 0x5A 0x00 /* INIT[7:0] */ - 0x23 2 0x5B 0x10 /* STV_NUM STV_S0[10:8] */ - 0x23 2 0x5C 0x14 /* STV_S0[7:0] */ - 0x23 2 0x5D 0x40 /* STV_W STV_S1 */ - 0x23 2 0x5E 0x01 /* STV_S2 */ - 0x23 2 0x5F 0x02 /* STV_S3 */ - 0x23 2 0x60 0x40 /* ETV_W ETV_S1 */ - 0x23 2 0x61 0x03 /* ETV_S2 */ - 0x23 2 0x62 0x04 /* ETV_S3 */ - 0x23 2 0x63 0x7A /* SETV_ON for STV/ETV on time */ - 0x23 2 0x64 0x7A /* SETV_OFF for STV/ETV off time */ - 0x23 2 0x65 0x74 /* ETV_EN ETV_NUM ETV_S0 */ - 0x23 2 0x66 0x16 /* ETV_S0 */ - 0x23 2 0x67 0xB4 /* CKV0_NUM CKV0_W */ - 0x23 2 0x68 0x16 /* CKV0_S0 */ - 0x23 2 0x69 0x7A /* CKV0_on */ - 0x23 2 0x6A 0x7A /* CKV0_off time */ - 0x23 2 0x6B 0x0C /* CKV0_DUM */ - 0x23 2 0x6C 0x00 /* GIP Line EQ option */ - 0x23 2 0x6D 0x04 /* GIP rising EQ */ - 0x23 2 0x6E 0x04 /* GIP fallig EQ */ - 0x23 2 0x6F 0x88 /* GIP_DR CKV0_CON CKV1_CON */ - 0x23 2 0x70 0x00 /* CKV1_NUM CKV0_W */ - 0x23 2 0x71 0x00 /* CKV1_S0 */ - 0x23 2 0x72 0x06 /* CKV1_on */ - 0x23 2 0x73 0x7B /* CKV1_off time */ - 0x23 2 0x74 0x00 /* CKV1_DUM */ - 0x23 2 0x75 0xBC /* FLM_EN FLM_W */ - 0x23 2 0x76 0x00 /* FLM on time */ - 0x23 2 0x77 0x04 /* VEN_EN VEN_W FLM_NUM FLM_OFF */ - 0x23 2 0x78 0x2C /* FLM_OFF */ - 0x23 2 0x79 0x00 /* VEN_W */ - 0x23 2 0x7A 0x00 /* VEN_S0 */ - 0x23 2 0x7B 0x00 /* VEN_S1 */ - 0x23 2 0x7C 0x00 /* VEN_DUM */ - 0x23 2 0x7D 0x03 /* VEN on time */ - 0x23 2 0x7E 0x7B /* VEN off time */ - 0x23 2 0xE0 0x03 /* Page3 */ - 0x23 2 0xAF 0x20 /* Set CABC */ - 0x23 2 0xE0 0x04 /* Page4 */ - 0x23 2 0x09 0x11 /* Source level at blanking period */ - 0x23 2 0x0E 0x48 /* Source EQ option */ - 0x23 2 0x2B 0x2B /* ESD Protect */ - 0x23 2 0x2E 0x44 /* Special Packet disable */ - 0x23 2 0x41 0xFF /* Set CABC */ - 0x23 2 0xE0 0x00 /* Page0 */ - 0x23 2 0xE6 0x02 /* Enable Watch Dog */ - 0x23 2 0xE7 0x0C /* Watch Dog timer setting */ - 0x23 2 0x51 0xFF /* CABC Option 0x80=50% duty 0xFF=100% */ - 0x23 2 0x53 0x2C - 0x23 2 0x55 0x00 - 0x05 1 0x11 /* Sleep Out */ - 0xFF 125 /* Delay 125ms */ - 0x05 1 0x29 /* Display On */ - 0xFF 0xFF /* Ending */ - >; - init_off = < - 0xff 5 - 0x05 1 0x28 /* display off */ - 0xff 60 /* delay 60ms */ - 0x05 1 0x10 /* sleep in */ - 0xff 110 /* delay 110ms */ - 0xff 0xff>; /* ending */ - }; - - extern_3{ - index = <3>; - extern_name = "mipi_default"; // KD070D82_FT9364 - status = "okay"; - type = <2>; /* 0=i2c, 1=spi, 2=mipi */ - cmd_size = <0xff>; - init_on = < - 0x23 2 0xE0 0x00 /* Register setting change to Page 0 */ - 0x23 2 0xE1 0x93 /* PASSWORD, setting as 93-65-F8 to enable page1-4 command access */ - 0x23 2 0xE2 0x65 - 0x23 2 0xE3 0xF8 - 0x23 2 0x80 0x03 /* Setting DSI lane number, 0x03 is DSI 4 lane */ - 0x23 2 0xE0 0x01 /* Register setting change to Page 1 */ - 0x23 2 0x00 0x00 /* Set VCOM_Forward */ - 0x23 2 0x01 0x9E /* VCOM=0x09F */ - 0x23 2 0x03 0x00 /* Set VCOM_Reverse */ - 0x23 2 0x04 0xAA /* VCOMR=0x0AA, -1.40V */ - 0x23 2 0x0C 0x74 /* Set PWRIC pumping frequency,=8 HCLK, about 512KHz */ - 0x23 2 0x17 0x00 /* Set Gamma Power, VGMP[8]=0, VGSP[8]=0 */ - 0x23 2 0x18 0xEF /* VGMP[8:0]=0x0EF=5.1V */ - 0x23 2 0x19 0x00 /* VGSP[8:0]=0x000=0V */ - 0x23 2 0x1A 0x00 /* VGMN[8]=0, VGSN[8]=0 */ - 0x23 2 0x1B 0xEF /* VGMN[8:0]=0x0EF=-5.1V */ - 0x23 2 0x1C 0x00 /* VGSN[8:0]=0x000=0V */ - 0x23 2 0x1F 0x70 /* VGH_REG=16.2V */ - 0x23 2 0x20 0x2D /* VGL_REG=-12V */ - 0x23 2 0x21 0x2D /* VGL_REG2=-12V */ - 0x23 2 0x22 0x7E /* VGH_REG short to VGH, VGL_REG short to VGL, */ - 0x23 2 0x26 0xF3 /* VDDD from IOVCC&VCI */ - 0x23 2 0x37 0x09 /* SS=1, source scan from S2400 to S1;BGR=1 CF type is (S1,S2,S3) align to (B,G,R) */ - 0x23 2 0x38 0x04 /* JDT=100, display inversion type is column inversion */ - 0x23 2 0x39 0x00 /* Source EQ Setting, EQ1, 0x00=0us */ - 0x23 2 0x3A 0x01 /* Source EQ Setting, EQ2, 0x01 =0.1us */ - 0x23 2 0x3C 0x90 /* Source EQ Setting, EQ3, EQ3 start at 14.4us */ - 0x23 2 0x3D 0xFF /* SET Source OP on time, 0xFF means source op always on */ - 0x23 2 0x3E 0xFF /* SET Source OP off time, 0xFF means source op always on */ - 0x23 2 0x3F 0xFF /* SET Source OP off time, 0xFF means source op always on */ - 0x23 2 0x40 0x02 /* horizontal resolution setting,RSO[2:0]= 0x02 =600RGB, LN[1:0]=2'b00 */ - 0x23 2 0x41 0x80 /* LN[9:0]=0x200=512, vertical resolution is 512*2=1024 line */ - 0x23 2 0x42 0x99 /* SLT, internal line period=0x99->15.3us */ - 0x23 2 0x43 0x14 /* Internal VFP=Ext_VFP=20(0x14) */ - 0x23 2 0x44 0x19 /* Internal _VBP=Ext_VS+Ext_VBP-1=6+20-1=25(0x19) */ - 0x23 2 0x45 0x5A /* Internal_HBP=Ext_HS+Ext_HBP=90(0x5A) */ - 0x23 2 0x55 0x02 /* Seting PWRIC mode, DCDCM=0010-> FP7721BX2 */ - 0x23 2 0x56 0x01 /* No auto Ratio function */ - 0x23 2 0x57 0x69 /* VGH_RT=3'b011,2*AVDD-AVEE,VGL_RT=3'b010=AVEE+VCL-AVDD,VCL_RT=2'b00,0.5*VCIP */ - 0x23 2 0x58 0x0A /* AVDD_S, not use internal AVDD in this model */ - 0x23 2 0x59 0x0A /* VCL = -2.5V */ - 0x23 2 0x5A 0x2E /* VGH = 16.2V */ - 0x23 2 0x5B 0x19 /* VGL = -12V */ - 0x23 2 0x5C 0x15 /* pump clk, VCL_CLK[1:0]=2'b01=HCLK/2=32KHz, VGHVGL_CLK[1:0]=2'b01=HCLK/2=32KHz */ - 0x23 2 0x5D 0x77 /* Gamma voltage setting, VP255-4.793V */ - 0x23 2 0x5E 0x5C /* VP251 */ - 0x23 2 0x5F 0x4D /* VP247 */ - 0x23 2 0x60 0x40 /* VP243 */ - 0x23 2 0x61 0x3D /* VP235 */ - 0x23 2 0x62 0x2F /* VP227 */ - 0x23 2 0x63 0x34 /* VP211 */ - 0x23 2 0x64 0x1F /* VP191 */ - 0x23 2 0x65 0x38 /* VP159 */ - 0x23 2 0x66 0x38 /* VP128 */ - 0x23 2 0x67 0x39 /* VP96 */ - 0x23 2 0x68 0x58 /* VP64 */ - 0x23 2 0x69 0x48 /* VP44 */ - 0x23 2 0x6A 0x51 /* VP28 */ - 0x23 2 0x6B 0x44 /* VP20 */ - 0x23 2 0x6C 0x41 /* VP12 */ - 0x23 2 0x6D 0x35 /* VP8 */ - 0x23 2 0x6E 0x24 /* VP4 */ - 0x23 2 0x6F 0x02 /* VP0 */ - 0x23 2 0x70 0x77 /* VN255 */ - 0x23 2 0x71 0x5C /* VN251 */ - 0x23 2 0x72 0x4D /* VN247 */ - 0x23 2 0x73 0x40 /* VN243 */ - 0x23 2 0x74 0x3D /* VN235 */ - 0x23 2 0x75 0x2F /* VN227 */ - 0x23 2 0x76 0x34 /* VN211 */ - 0x23 2 0x77 0x1F /* VN191 */ - 0x23 2 0x78 0x38 /* VN159 */ - 0x23 2 0x79 0x38 /* VN128 */ - 0x23 2 0x7A 0x39 /* VN96 */ - 0x23 2 0x7B 0x58 /* VN64 */ - 0x23 2 0x7C 0x48 /* VN44 */ - 0x23 2 0x7D 0x51 /* VN28 */ - 0x23 2 0x7E 0x44 /* VN20 */ - 0x23 2 0x7F 0x41 /* VN12 */ - 0x23 2 0x80 0x35 /* VN8 */ - 0x23 2 0x81 0x24 /* VN4 */ - 0x23 2 0x82 0x02 /* VN0 */ - 0x23 2 0xE0 0x02 /* Register setting change to Page 2 */ - 0x23 2 0x00 0x53 /* GIP_L_Forward scan mapping, assign as RESET_EVEN */ - 0x23 2 0x01 0x55 /* assign as VSSG_EVEN */ - 0x23 2 0x02 0x55 /* assign as VSSA_EVEN */ - 0x23 2 0x03 0x51 /* assign as STV2_EVEN */ - 0x23 2 0x04 0x77 /* assign as VDD2_EVEN */ - 0x23 2 0x05 0x57 /* assign as VDD1_EVEN */ - 0x23 2 0x06 0x1F /* assign as VGL */ - 0x23 2 0x07 0x4F /* assign as CK12 */ - 0x23 2 0x08 0x4D /* assign as CK10 */ - 0x23 2 0x09 0x1F /* assign as VGL */ - 0x23 2 0x0A 0x4B /* assign as CK8 */ - 0x23 2 0x0B 0x49 /* assign as CK6 */ - 0x23 2 0x0C 0x1F /* assign as VGL */ - 0x23 2 0x0D 0x47 /* assign as CK4 */ - 0x23 2 0x0E 0x45 /* assign as CK2 */ - 0x23 2 0x0F 0x41 /* assign as STV1_EVEN */ - 0x23 2 0x10 0x1F /* assign as VGL */ - 0x23 2 0x11 0x1F /* assign as VGL */ - 0x23 2 0x12 0x1F /* assign as VGL */ - 0x23 2 0x13 0x55 /* assign as VGG */ - 0x23 2 0x14 0x1F /* assign as VGL */ - 0x23 2 0x15 0x1F /* assign as VGL */ - 0x23 2 0x16 0x52 /* GIP_R_Forward scan mapping, assign as RESET_ODD */ - 0x23 2 0x17 0x55 /* assign as VSSG_ODD */ - 0x23 2 0x18 0x55 /* assign as VSSA_ODD */ - 0x23 2 0x19 0x50 /* assign as STV2_ODD */ - 0x23 2 0x1A 0x77 /* assign as VDD2_ODD */ - 0x23 2 0x1B 0x57 /* assign as VDD1_ODD */ - 0x23 2 0x1C 0x1F /* assign as VGL */ - 0x23 2 0x1D 0x4E /* assign as CK11 */ - 0x23 2 0x1E 0x4C /* assign as CK9 */ - 0x23 2 0x1F 0x1F /* assign as VGL */ - 0x23 2 0x20 0x4A /* assign as CK7 */ - 0x23 2 0x21 0x48 /* assign as CK5 */ - 0x23 2 0x22 0x1F /* assign as VGL */ - 0x23 2 0x23 0x46 /* assign as CK3 */ - 0x23 2 0x24 0x44 /* assign as CK1 */ - 0x23 2 0x25 0x40 /* assign as STV1_ODD */ - 0x23 2 0x26 0x1F /* assign as VGL */ - 0x23 2 0x27 0x1F /* assign as VGL */ - 0x23 2 0x28 0x1F /* assign as VGL */ - 0x23 2 0x29 0x1F /* assign as VGL */ - 0x23 2 0x2A 0x1F /* assign as VGL */ - 0x23 2 0x2B 0x55 /* assign as VGG */ - 0x23 2 0x2C 0x12 /* GIP_L_Reverse Scan mapping, assign as RESET_EVEN */ - 0x23 2 0x2D 0x15 /* assign as VSSG_EVEN */ - 0x23 2 0x2E 0x15 /* assign as VSSA_EVEN */ - 0x23 2 0x2F 0x00 /* assign as STV2_EVEN */ - 0x23 2 0x30 0x17 /* assign as VDD2_EVEN */ - 0x23 2 0x31 0x17 /* assign as VDD1_EVEN */ - 0x23 2 0x32 0x1F /* assign as VGL */ - 0x23 2 0x33 0x08 /* assign as CK12 */ - 0x23 2 0x34 0x0A /* assign as CK10 */ - 0x23 2 0x35 0x1F /* assign as VGL */ - 0x23 2 0x36 0x0C /* assign as CK8 */ - 0x23 2 0x37 0x0E /* assign as CK6 */ - 0x23 2 0x38 0x1F /* assign as VGL */ - 0x23 2 0x39 0x04 /* assign as CK4 */ - 0x23 2 0x3A 0x06 /* assign as CK2 */ - 0x23 2 0x3B 0x10 /* assign as STV1_EVEN */ - 0x23 2 0x3C 0x1F /* assign as VGL */ - 0x23 2 0x3D 0x1F /* assign as VGL */ - 0x23 2 0x3E 0x1F /* assign as VGL */ - 0x23 2 0x3F 0x15 /* assign as VGG */ - 0x23 2 0x40 0x1F /* assign as VGL */ - 0x23 2 0x41 0x1F /* assign as VGL */ - 0x23 2 0x42 0x13 /* GIP_R_Reverse Scan mapping, assign as RESET_ODD */ - 0x23 2 0x43 0x15 /* assign as VSSG_ODD */ - 0x23 2 0x44 0x15 /* assign as VSSA_ODD */ - 0x23 2 0x45 0x01 /* assign as STV2_ODD */ - 0x23 2 0x46 0x17 /* assign as VDD2_ODD */ - 0x23 2 0x47 0x17 /* assign as VDD1_ODD */ - 0x23 2 0x48 0x1F /* assign as VGL */ - 0x23 2 0x49 0x09 /* assign as CK11 */ - 0x23 2 0x4A 0x0B /* assign as CK9 */ - 0x23 2 0x4B 0x1F /* assign as VGL */ - 0x23 2 0x4C 0x0D /* assign as CK7 */ - 0x23 2 0x4D 0x0F /* assign as CK5 */ - 0x23 2 0x4E 0x1F /* assign as VGL */ - 0x23 2 0x4F 0x05 /* assign as CK3 */ - 0x23 2 0x50 0x07 /* assign as CK1 */ - 0x23 2 0x51 0x11 /* assign as STV1_ODD */ - 0x23 2 0x52 0x1F /* assign as VGL */ - 0x23 2 0x53 0x1F /* assign as VGL */ - 0x23 2 0x54 0x1F /* assign as VGL */ - 0x23 2 0x55 0x1F /* assign as VGL */ - 0x23 2 0x56 0x1F /* assign as VGL */ - 0x23 2 0x57 0x15 /* assign as VGG */ - 0x23 2 0x58 0x40 /* GAS OPT=1, When abnormal power off, GIP will pull to VGH */ - 0x23 2 0x59 0x00 /* INIT_W=0, no INIT function in this panel */ - 0x23 2 0x5A 0x00 /* INIT[10:0], no INIT function in this panel */ - 0x23 2 0x5B 0x10 /* STV_NUM,STV_S0[10:8], 2 STV pulses */ - 0x23 2 0x5C 0x14 /* STV_S0[7:0], STV start from 21th hsync after vsync */ - 0x23 2 0x5D 0x40 /* STV_W=4, STV width is 4 Hline; STV1 delay 1 hline with STV0 */ - 0x23 2 0x5E 0x01 /* STV_S2, STV2 delay 2 hline with STV0 */ - 0x23 2 0x5F 0x02 /* STV_S3, STV3 delay 3 hline with STV0 */ - 0x23 2 0x60 0x40 /* ETV_W=4, ETV witdh is 4 hline; ETV1 delay 1 hilne from ETV0 */ - 0x23 2 0x61 0x03 /* ETV_S2, ETV2 delay 4 hline with ETV0 */ - 0x23 2 0x62 0x04 /* ETV_S3, ETV3 delay 5 hline with ETV0 */ - 0x23 2 0x63 0x7A /* SETV_ON for STV/ETV on time, rising at 12.2us after hsync */ - 0x23 2 0x64 0x7A /* SETV_OFF for STV/ETV off time , falling at 12.2us after hsync */ - 0x23 2 0x65 0x74 /* ETV_EN=1, enable ETV function; ETV_NUM=3, using 4 ETV pulse, */ - 0x23 2 0x66 0x16 /* ETV_S0=0x416, EVT start at 1046th hsync fater vaync */ - 0x23 2 0x67 0xB4 /* CKV_NUM=2'b1011, using 12 CKV pulse; CKV0_W=4. CKV width is 4 hline */ - 0x23 2 0x68 0x16 /* CKV0_S0 , CKV start from 23th hsync after vsync */ - 0x23 2 0x69 0x7A /* CKV0_on ,for CKV on time, rising at 12.2us after hsync */ - 0x23 2 0x6A 0x7A /* CKV0_off ,for CKV off time, falling at 12.2us after hsync */ - 0x23 2 0x6B 0x0C /* CKV0_DUM, total CKV pulse number=1024+12=1036 */ - 0x23 2 0x6C 0x00 /* GIP Line EQ option , disable GEQ_Line function */ - 0x23 2 0x6D 0x04 /* GIP rising EQ, period is 0.4us */ - 0x23 2 0x6E 0x04 /* GIP fallig EQ, period is 0.4us */ - 0x23 2 0x6F 0x88 /* GIP_DR; CKV0_CON, no continuous CKV0; CKV1_CON, no continuous CKV1 */ - 0x23 2 0x70 0x00 /* CKV1_NUM, CKV0_W , no CKV group 1 function in this panel, don't care */ - 0x23 2 0x71 0x00 /* CKV1_S0, no CKV group 1 function in this panel, don't care */ - 0x23 2 0x72 0x06 /* CKV1_on , no CKV group 1 function in this panel, don't care */ - 0x23 2 0x73 0x7B /* CKV1_off time, no CKV group 1 function in this panel, don't care */ - 0x23 2 0x74 0x00 /* CKV1_DUM, no CKV group 1 function in this panel, don't care */ - 0x23 2 0x75 0xBC /* FLM_EN, enable FLM function; FLM_W=0x3C, FLM toggle period is 60 frame */ - 0x23 2 0x76 0x00 /* FLM on time , FLM on(rising) at 1st hsync after vsync */ - 0x23 2 0x77 0x04 /* VEN_EN, VEN_W, no VEN function in this panel, don't care */ - 0x23 2 0x78 0x2C /* FLM_OFF, FLM off(falling) at 1068th hsync after vsync */ - 0x23 2 0x79 0x00 /* VEN_W , no VEN function in this panel, don't care */ - 0x23 2 0x7A 0x00 /* VEN_S0 , no VEN function in this panel, don't care */ - 0x23 2 0x7B 0x00 /* VEN_S1 , no VEN function in this panel, don't care */ - 0x23 2 0x7C 0x00 /* VEN_DUM , no VEN function in this panel, don't care */ - 0x23 2 0x7D 0x03 /* VEN on time , no VEN function in this panel, don't care */ - 0x23 2 0x7E 0x7B /* VEN off time , no VEN function in this panel, don't care */ - 0x23 2 0xE0 0x03 /* Register setting change to Page 3 */ - 0x23 2 0xAF 0x20 /* Set CABC, disable CABC TP detect, for CABC pattern change more smooth */ - 0x23 2 0xE0 0x04 /* Register setting change to Page 4 */ - 0x23 2 0x09 0x11 /* Source level at blanking period, sweeping V0 level */ - 0x23 2 0x0E 0x48 /* Source EQ option, EQ to PCAP,NCAP */ - 0x23 2 0x2B 0x2B /* ESD Protect, clock lane op behavior follow data lane, improve ESD performance */ - 0x23 2 0x2E 0x44 /* ESD protect, disable special packet */ - 0x23 2 0x41 0xFF /* Set CABC, for CABC pattern change more smooth */ - 0x23 2 0xE0 0x00 /* Register setting change to Page 0 */ - 0x23 2 0xE6 0x02 /* Enable Watch Dog */ - 0x23 2 0xE7 0x0C /* Watch Dog timer setting, WD alarm time is 12*512osc after hsync stop */ - 0x23 2 0x51 0xFF /* CABC Option, 0x80=50% duty, 0xFF=100% */ - 0x23 2 0x53 0x2C /* enable dimming, BCTRL, BL */ - 0x23 2 0x55 0x00 /* CABC mode, 0x00 is manual mode */ - 0x05 1 0x11 /* SLPOUT */ - 0xFF 125 /* Delay 125ms */ - 0x05 1 0x29 /* Display On */ - 0xFF 0xFF /* Ending */ - >; - init_off = < - 0xff 5 - 0x05 1 0x28 /* display off */ - 0xff 60 /* delay 60ms */ - 0x05 1 0x10 /* sleep in */ - 0xff 110 /* delay 110ms */ - 0xff 0xff>; /* ending */ - }; - }; - - backlight{ - compatible = "amlogic, backlight-g12a"; - status = "okay"; - key_valid = <0>; - pinctrl-names = "pwm_on","pwm_off"; - pinctrl-0 = <&pwm_f_pins2>; - pinctrl-1 = <&bl_pwm_off_pins>; - pinctrl_version = <2>; /* for uboot */ - bl_pwm_config = <&bl_pwm_conf>; - bl-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_HIGH - &gpio GPIOH_5 GPIO_ACTIVE_HIGH>; - bl_gpio_names = "GPIOH_4","GPIOH_5"; - - /* pwm port: PWM_A, PWM_B, PWM_C, PWM_D, PWM_E, PWM_F, PWM_VS*/ - /* power index:(point gpios_index, 0xff=invalid) - * power value:(0=output low, 1=output high, 2=input) - * power delay:(unit in ms) - */ - - backlight_0{ - index = <0>; - bl_name = "backlight_pwm"; - bl_level_default_uboot_kernel = <100 100>; - bl_level_attr = <255 10 /*max, min*/ - 128 128>; /*mid, mid_mapping*/ - bl_ctrl_method = <1>; /* 1=pwm, 2=pwm_combo, 4=extern */ - bl_power_attr = <0 /*en_gpio_index*/ - 1 0 /*on_value, off_value*/ - 200 200>; /*on_delay(ms), off_delay(ms)*/ - bl_pwm_port = "PWM_F"; - bl_pwm_attr = <0 /*pwm_method*/ - 180 /*pwm_freq(pwm:Hz, pwm_vs:multiple of vs)*/ - 100 25>; /*duty_max(%), duty_min(%)*/ - bl_pwm_power = <1 1 /*pwm_gpio_index, pwm_gpio_off*/ - 10 10>; /*pwm_on_delay(ms), pwm_off_delay(ms)*/ - bl_pwm_en_sequence_reverse = <0>; /* 1 for reverse */ - }; - backlight_1{ - index = <1>; - bl_name = "bl_extern"; - bl_level_default_uboot_kernel = <100 100>; - bl_level_attr = <255 10 /*max, min*/ - 128 128>; /*mid, mid_mapping*/ - bl_ctrl_method = <4>; /*1=pwm, 2=pwm_combo, 4=extern*/ - bl_power_attr = <1 /*en_gpio_index*/ - 1 0 /*on_value, off_value*/ - 200 200>; /*on_delay(ms), off_delay(ms)*/ - bl_extern_index = <0>; - }; - }; - bl_pwm_conf:bl_pwm_conf{ - pwm_channel_0 { - pwm_port_index = <5>; - pwms = <&pwm_ef MESON_PWM_1 30040 0>; - }; - }; - - bl_extern{ - compatible = "amlogic, bl_extern"; - status = "disabled"; - i2c_bus = "i2c_bus_3"; - - extern_0{ - index = <0>; - extern_name = "i2c_lp8556"; - type = <0>; /*0=i2c, 1=spi, 2=mipi*/ - i2c_address = <0x2c>; /*7bit i2c address*/ - dim_max_min = <255 10>; - }; - - extern_1{ - index = <1>; - extern_name = "mipi_lt070me05"; - type = <2>; /*0=i2c, 1=spi, 2=mipi*/ - dim_max_min = <255 10>; - }; - }; -};/* end of panel */
diff --git a/arch/arm/dts/meson-a-series.dtsi b/arch/arm/dts/meson-a-series.dtsi new file mode 100644 index 0000000..ccdac71 --- /dev/null +++ b/arch/arm/dts/meson-a-series.dtsi
@@ -0,0 +1,525 @@ +/* + * Copyright (c) 2016 Andreas Färber + * + * Copyright (c) 2016 BayLibre, SAS. + * Author: Neil Armstrong <narmstrong@baylibre.com> + * + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/pwm/pwm.h> +#include <dt-bindings/pwm/meson.h> +#include <dt-bindings/clock/a1-clkc.h> + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* 16 MiB reserved for Hardware ROM Firmware */ + hwrom_reserved: hwrom@0 { + reg = <0x0 0x0 0x0 0x1000000>; + no-map; + }; + + /* 2 MiB reserved for ARM Trusted Firmware (BL31) */ + secmon_reserved: secmon@10000000 { + reg = <0x0 0x10000000 0x0 0x200000>; + no-map; + }; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0xbc00000>; + alignment = <0x0 0x400000>; + linux,cma-default; + }; + }; + + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&l2>; + clocks = <&scpi_dvfs 0>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + next-level-cache = <&l2>; + clocks = <&scpi_dvfs 0>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x2>; + enable-method = "psci"; + next-level-cache = <&l2>; + clocks = <&scpi_dvfs 0>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x3>; + enable-method = "psci"; + next-level-cache = <&l2>; + clocks = <&scpi_dvfs 0>; + }; + + l2: l2-cache0 { + compatible = "cache"; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; + }; + + xtal: xtal-clk { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xtal"; + #clock-cells = <0>; + }; + + firmware { + sm: secure-monitor { + compatible = "amlogic,meson-gx-sm", "amlogic,meson-gxbb-sm"; + }; + }; + + efuse: efuse { + compatible = "amlogic,meson-gx-efuse", "amlogic,meson-gxbb-efuse"; + #address-cells = <1>; + #size-cells = <1>; + + sn: sn@14 { + reg = <0x14 0x10>; + }; + + eth_mac: eth_mac@34 { + reg = <0x34 0x10>; + }; + + bid: bid@46 { + reg = <0x46 0x30>; + }; + }; + + scpi { + compatible = "amlogic,meson-gxbb-scpi", "arm,scpi-pre-1.0"; + mboxes = <&mailbox 1 &mailbox 2>; + shmem = <&cpu_scp_lpri &cpu_scp_hpri>; + + scpi_clocks: clocks { + compatible = "arm,scpi-clocks"; + + scpi_dvfs: scpi_clocks@0 { + compatible = "arm,scpi-dvfs-clocks"; + #clock-cells = <1>; + clock-indices = <0>; + clock-output-names = "vcpu"; + }; + }; + + scpi_sensors: sensors { + compatible = "amlogic,meson-gxbb-scpi-sensors", "arm,scpi-sensors"; + #thermal-sensor-cells = <1>; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic: interrupt-controller@2c001000 { + compatible = "arm,gic-400"; + reg = <0x0 0xffc01000 0 0x1000>, + <0x0 0xffc02000 0 0x2000>, + <0x0 0xffc04000 0 0x2000>, + <0x0 0xffc06000 0 0x2000>; + interrupt-controller; + interrupts = <GIC_PPI 9 + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; + #interrupt-cells = <3>; + #address-cells = <0>; + }; + + sram: sram@fffa0000 { + compatible = "amlogic,meson-gx-sram", "amlogic,meson-gxbb-sram", "mmio-sram"; + reg = <0x0 0xfffa0000 0x0 0x48000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0xfffa0000 0x48000>; + + cpu_scp_lpri: scp-shmem@0 { + compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem"; + reg = <0x47000 0x400>; + }; + + cpu_scp_hpri: scp-shmem@200 { + compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem"; + reg = <0x47400 0x400>; + }; + }; + + cbus: cbus@fe000000 { + compatible = "simple-bus"; + reg = <0x0 0xfe000000 0x0 0x8000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x8000>; + + uart_a: serial@1c00 { + compatible = "amlogic,meson-uart"; + reg = <0x0 0x1c00 0x0 0x14>; + clocks = <&xtal>; + status = "disabled"; + }; + + uart_b: serial@2000 { + compatible = "amlogic,meson-uart"; + reg = <0x0 0x2000 0x0 0x14>; + clocks = <&xtal>; + status = "disabled"; + }; + + pwm_ab: pwm@2400 { + compatible = "amlogic,meson-v2-pwm"; + reg = <0x0 0x2400 0x0 0x20>, + <0x0 0x08c4 0x0 0x04>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm_cd: pwm@2800 { + compatible = "amlogic,meson-v2-pwm"; + reg = <0x0 0x2800 0x0 0x20>, + <0x0 0x08c8 0x0 0x04>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm_ef: pwm@5400 { + compatible = "amlogic,meson-v2-pwm"; + reg = <0x0 0x5400 0x0 0x20>, + <0x0 0x08cc 0x0 0x04>; + #pwm-cells = <3>; + status = "disabled"; + }; + + ir: ir@8040 { + compatible = "amlogic,meson-gx-ir", "amlogic,meson-gxbb-ir"; + reg = <0x0 0x8040 0x0 0x40>; + interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + }; + + reset: reset-controller@1000 { + compatible = "amlogic,meson-gx-reset", "amlogic,meson-gxbb-reset"; + reg = <0x0 0x01000 0x0 0x1000>; + #reset-cells = <1>; + }; + + uart_c: serial@22000 { + compatible = "amlogic,meson-uart"; + reg = <0x0 0x22000 0x0 0x18>; + interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>; + clocks = <&xtal>; + status = "disabled"; + }; + + spicc0: spi@3800 { + compatible = "amlogic,meson-g12a-spicc"; + reg = <0x0 0x3800 0x0 0x44>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spifc: spi@14000 { + compatible = "amlogic,spifc"; + reg = <0x0 0x14000 0x0 0x80>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + spi-flash@0 { + reg = <0>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + compatible = "spi-flash"; + status = "okay"; + }; + spi-nand@1 { + reg = <1>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + compatible = "spi-nand"; + status = "okay"; + }; + }; + + watchdog@0f0d0 { + compatible = "amlogic,meson-a1-wdt"; + reg = <0x0 0x0f0d0 0x0 0x10>; + clocks = <&xtal>; + clock-names = "wdt-clk"; + }; + + jtag { + compatible = "amlogic, jtag"; + status = "okay"; + select = "disable"; /* disable/jtag-a/swd-a */ + pinctrl-names="jtag_a_pins", "swd_a_pins"; + pinctrl-0=<&jtag_a_pins>; + pinctrl-1=<&swd_a_pins>; + }; + }; + + periphs: periphs@ff634000 { + compatible = "simple-bus"; + reg = <0x0 0xff634000 0x0 0x2000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>; + + hwrng: rng { + compatible = "amlogic,meson-rng"; + reg = <0x0 0x0 0x0 0x4>; + }; + }; + + hiubus: hiubus@ff63c000 { + compatible = "simple-bus"; + reg = <0x0 0xff63c000 0x0 0x2000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x2000>; + + mailbox: mailbox@404 { + compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu"; + reg = <0 0x404 0 0x4c>; + interrupts = <0 208 IRQ_TYPE_EDGE_RISING>, + <0 209 IRQ_TYPE_EDGE_RISING>, + <0 210 IRQ_TYPE_EDGE_RISING>; + #mbox-cells = <1>; + }; + }; + + clkc: clock-controller@0 { + compatible = "amlogic,a1-clkc"; + #clock-cells = <1>; + reg = <0x0 0xfe000800 0x0 0xe4>; + clocks = <&xtal>; + clock-names = "xtal"; + }; + + i2c0: i2c@fe001400 { + compatible = "amlogic,meson-a1-i2c"; + reg = <0x0 0xfe001400 0x0 0x24>; + #address-cells = <2>; + #size-cells = <0>; + clocks = <&clkc CLKID_I2C_M_A>; + clock-names = "clk_i2c"; + status = "disabled"; + }; + + i2c1: i2c@fe005c00 { + compatible = "amlogic,meson-a1-i2c"; + reg = <0x0 0xfe005c00 0x0 0x24>; + #address-cells = <2>; + #size-cells = <0>; + clocks = <&clkc CLKID_I2C_M_B>; + clock-names = "clk_i2c"; + status = "disabled"; + }; + + i2c2: i2c@fe006800 { + compatible = "amlogic,meson-a1-i2c"; + reg = <0x0 0xfe006800 0x0 0x24>; + #address-cells = <2>; + #size-cells = <0>; + clocks = <&clkc CLKID_I2C_M_C>; + clock-names = "clk_i2c"; + status = "disabled"; + }; + + i2c3: i2c@fe006c00 { + compatible = "amlogic,meson-a1-i2c"; + reg = <0x0 0xfe006c00 0x0 0x24>; + #address-cells = <2>; + #size-cells = <0>; + clocks = <&clkc CLKID_I2C_M_D>; + clock-names = "clk_i2c"; + status = "disabled"; + }; + + ethmac: ethernet@ff3f0000 { + compatible = "amlogic,g12a-eth-dwmac"; + phy_cntl1 = <0x41054147>; + pll_val = <0x9c0040a 0x927e0000 0xac5f49e5>; + analog_val = <0x20200000 0x0000c000 0x00000023>; + status = "disabled"; + }; + + saradc: adc@ff809000 { + compatible = "amlogic,meson-saradc"; + reg = <0x0 0xfe002c00 0x0 0x48>; + status = "disabled"; + }; + + nand: nfc@ffe07800 { + compatible = "amlogic,meson-nfc"; + reg = <0x0 0xFFE07800 0x0 0x200>; + interrupts = <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + clk_reg = <0 0xFFE07000>; + }; + + apb: apb@ffe01000 { + compatible = "simple-bus"; + reg = <0x0 0xffe01000 0x0 0x7f000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xffe01000 0x0 0x7f000>; + + sd_emmc_a: mmc@2000 { + compatible = ""; + reg = <0x0 0x2000 0x0 0x800>; + interrupts = <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + }; + + sd_emmc_b: mmc@4000 { + compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; + reg = <0x0 0x4000 0x0 0x800>; + interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + }; + + sd_emmc_c: mmc@6000 { + compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; + reg = <0x0 0x6000 0x0 0x800>; + interrupts = <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + }; + }; + + dwc3: dwc3@ff400000 { + compatible = "snps,dwc3","synopsys,xhci-dwc3"; + status = "disable"; + reg = <0x0 0xff400000 0x0 0x100000>; + phys = <&usb2_phy_v2>, <&usb3_phy_v2>; + phy-names = "usb2-phy", "usb3-phy"; + }; + + usb2_phy_v2: usb2phy@fe004420 { + compatible = "amlogic, amlogic-new-usb2-v2"; + status = "disable"; + #address-cells = <2>; + #size-cells = <2>; + phy-version = <2>; + reg = <0x0 0xfe004420 0x0 0x60 + 0x0 0xfe000004 0x0 0x100 + 0x0 0xfe004000 0x0 0x2000 + 0x0 0xfe0008dc 0x0 0x4>; + dwc2_a_reg = <0xff500000>; + #phy-cells = <0>; + }; + + usb3_phy_v2: usb3phy@fe004480 { + compatible = "amlogic, amlogic-new-usb3-v2"; + status = "disable"; + #address-cells = <2>; + #size-cells = <2>; + phy-version = <3>; + reg = <0x0 0xfe004480 0x0 0x20>; + #phy-cells = <0>; + }; + + }; +};
diff --git a/arch/arm/dts/meson-a1-a113l-ad401.dts b/arch/arm/dts/meson-a1-a113l-ad401.dts new file mode 100644 index 0000000..54d5bc6 --- /dev/null +++ b/arch/arm/dts/meson-a1-a113l-ad401.dts
@@ -0,0 +1,83 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "meson-a1-a113l-ad401.dtsi" +#include "meson-a1_skt-panel.dtsi" + +/ { + compatible = "amlogic,ad401", "amlogic,a113l", "amlogic,meson-a1"; + model = "Amlogic Meson A1 AD401 Development Board"; +}; + +/* This UART is brought out to the DB9 connector */ +&uart_a { + status = "okay"; +}; + +&uart_b { + status = "okay"; +}; + +&saradc { + status = "okay"; +}; + +/* demo for i2c user */ +&i2c3 { + status= "disabled"; + clock-frequency = <100000>; + /* pinctrl-names = "default";*/ + /* pinctrl-0 = <&i2c3_master_pins2>;*/ +}; + +&pinctrl_periphs { + bl_pwm_off_pins:bl_pwm_off_pin { + mux { + groups = "GPIOH_5"; + function = "gpio_periphs"; + output-high; + }; + }; +}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-a1-a113l-ad401.dtsi b/arch/arm/dts/meson-a1-a113l-ad401.dtsi new file mode 100644 index 0000000..bb9ff07 --- /dev/null +++ b/arch/arm/dts/meson-a1-a113l-ad401.dtsi
@@ -0,0 +1,311 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>. + * Based on meson-gx-p23x-q20x.dtsi: + * - Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * - Copyright (c) 2016 BayLibre, SAS. + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +/* Common DTSI for devices which are based on the P212 reference board. */ + +#include "meson-a1-a113l.dtsi" + +/ { + aliases { + serial0 = &uart_b; + serial1 = &uart_a; + spi0 = &spifc; + spi1 = &spicc0; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + vddio_boot: regulator-vddio_boot { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vddio_ao18: regulator-vddio_ao18 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + /*reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;*/ + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; + + leds { + compatible = "pwm-leds"; + status = "okay"; + + red { + label = "led_red"; + pwms = <&pwm_cd MESON_PWM_0 10000000 0>; + max-brightness=<255>; + default-brightness=<255>; + }; + + green { + label = "led_green"; + pwms = <&pwm_ab MESON_PWM_1 10000000 0>; + max-brightness=<255>; + default-brightness=<255>; + }; + + blue { + label = "led_blue"; + pwms = <&pwm_ab MESON_PWM_0 10000000 0>; + max-brightness=<255>; + default-brightness=<255>; + }; + }; +}; + +ðmac { + status = "okay"; + internal_phy = <1>; + mc_val = <0x4be04>; + /*mc_val = <0x1621>;*/ +}; + +&ir { + status = "disabled"; + /* pinctrl-0 = <&remote_input_ao_pins>; */ + /* pinctrl-names = "default"; */ +}; + +&saradc { + status = "okay"; + vref-supply = <&vddio_ao18>; +}; + +/* Wireless SDIO Module */ +&sd_emmc_a { + status = "disabled"; + /* pinctrl-0 = <&sdio_pins>; */ + /* pinctrl-names = "default"; */ + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + + non-removable; + disable-wp; + card_type = <3>; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* SD card */ +&sd_emmc_b { + status = "disabled"; + /*pinctrl-0 = <&sd_all_pins>;*/ + /*pinctrl-names = "default";*/ + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + card_type = <5>; + + /* cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>; */ + /* cd-inverted; */ + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "disabled"; + /* pinctrl-0 = <&emmc_conf_pull_up &emmc_conf_pull_done>; */ + /* pinctrl-names = "default"; */ + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <200000000>; + non-removable; + disable-wp; + /* mmc-ddr-1_8v; */ + /* mmc-hs200-1_8v; */ + card_type = <1>; + + core-phase0 = <3>; + tx-phase0 = <0>; + + core-phase1 = <3>; + tx-phase1 = <0>; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* nand */ +&nand { + status = "okay"; + /* pinctrl-names = "default", "nand_all_pins", "nand_cs_only"; */ + /* pinctrl-0 = <&all_nand_pins>; */ + /* pinctrl-1 = <&all_nand_pins>; */ + /* pinctrl-2 = <&nand_cs_pins>; */ + + /* + #address-cells = <1>; + #size-cells = <0>; + + nand@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + nand-on-flash-bbt; + nand-ecc-mode = "hw"; + nand-ecc-strength = <8>; + nand-ecc-step-size = <1024>; + + meson-nand-user-mode = <2>; + meson-nand-ran-mode = <1>; + + partition@0 { + label = "boot"; + reg = <0x00000000 0x00200000>; + read-only; + }; + partition@200000 { + label = "env"; + reg = <0x00200000 0x00400000>; + }; + partition@600000 { + label = "system"; + reg = <0x00600000 0x00a00000>; + }; + partition@1000000 { + label = "rootfs"; + reg = <0x01000000 0x03000000>; + }; + partition@4000000 { + label = "media"; + reg = <0x04000000 0x8000000>; + }; + };*/ + +}; + +&dwc3 { + status = "okay"; + dr_mode = "host"; +}; + +&usb2_phy_v2 { + status = "okay"; + portnum = <1>; +}; + +&usb3_phy_v2 { + status = "okay"; + portnum = <0>; + gpio-vbus-power = "GPIOH_6"; + /*gpios = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>;*/ +}; + +&pwm_ef { + status = "okay"; + /* pinctrl-0 = <&pwm_e_pins>; */ + /* pinctrl-names = "default"; */ +}; + +/* This is connected to the Bluetooth module: */ +&uart_a { + status = "okay"; + /* pinctrl-0 = <&a_uart_pins>; */ + /* pinctrl-names = "default"; */ + uart-has-rtscts; +}; + +&spifc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spifc_pins>; + max-frequency = <24000000>; + max-cs = <2>; + /* 512M */ + clocks = <&clkc CLKID_FCLK_DIV3>, + <&clkc CLKID_SPIFC_MUX>, + <&clkc CLKID_SPIFC_DIV>, + <&clkc CLKID_SPIFC_GATE>, + <&clkc CLKID_SPIFC_XTAL_GATE>; + clock-names = "fclk_source", "spifc_mux", "spifc_div", "spifc_gate", "spifc_xtal_gate"; +}; + +&spicc0 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc0_pins_a>; + cs-gpios = <&gpio GPIOA_8 0>; +}; + +&pwm_ab { + status = "okay"; + /* set mux pwm_a_pins4 pwm_b_pins2 for led */ + pinctrl-names="default"; + pinctrl-0=<&pwm_a_pins4 &pwm_b_pins2>; +}; + +&pwm_cd { + status = "okay"; + /* set mux pwm_c_pins3 for led */ + pinctrl-names="default"; + pinctrl-0=<&pwm_c_pins3>; +};
diff --git a/arch/arm/dts/meson-a1-a113l-ad402.dts b/arch/arm/dts/meson-a1-a113l-ad402.dts new file mode 100644 index 0000000..4b6aaab --- /dev/null +++ b/arch/arm/dts/meson-a1-a113l-ad402.dts
@@ -0,0 +1,83 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "meson-a1-a113l-ad402.dtsi" +#include "meson-a1_skt-panel.dtsi" + +/ { + compatible = "amlogic,ad402", "amlogic,a113l", "amlogic,meson-a1"; + model = "Amlogic Meson A1 AD401 Development Board"; +}; + +/* This UART is brought out to the DB9 connector */ +&uart_a { + status = "okay"; +}; + +&uart_b { + status = "okay"; +}; + +&saradc { + status = "okay"; +}; + +/* demo for i2c user */ +&i2c3 { + status= "disabled"; + clock-frequency = <100000>; + /* pinctrl-names = "default";*/ + /* pinctrl-0 = <&i2c3_master_pins2>;*/ +}; + +&pinctrl_periphs { + bl_pwm_off_pins:bl_pwm_off_pin { + mux { + groups = "GPIOH_5"; + function = "gpio_periphs"; + output-high; + }; + }; +}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-a1-a113l-ad402.dtsi b/arch/arm/dts/meson-a1-a113l-ad402.dtsi new file mode 100644 index 0000000..bb9ff07 --- /dev/null +++ b/arch/arm/dts/meson-a1-a113l-ad402.dtsi
@@ -0,0 +1,311 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>. + * Based on meson-gx-p23x-q20x.dtsi: + * - Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * - Copyright (c) 2016 BayLibre, SAS. + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +/* Common DTSI for devices which are based on the P212 reference board. */ + +#include "meson-a1-a113l.dtsi" + +/ { + aliases { + serial0 = &uart_b; + serial1 = &uart_a; + spi0 = &spifc; + spi1 = &spicc0; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + vddio_boot: regulator-vddio_boot { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vddio_ao18: regulator-vddio_ao18 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + /*reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;*/ + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; + + leds { + compatible = "pwm-leds"; + status = "okay"; + + red { + label = "led_red"; + pwms = <&pwm_cd MESON_PWM_0 10000000 0>; + max-brightness=<255>; + default-brightness=<255>; + }; + + green { + label = "led_green"; + pwms = <&pwm_ab MESON_PWM_1 10000000 0>; + max-brightness=<255>; + default-brightness=<255>; + }; + + blue { + label = "led_blue"; + pwms = <&pwm_ab MESON_PWM_0 10000000 0>; + max-brightness=<255>; + default-brightness=<255>; + }; + }; +}; + +ðmac { + status = "okay"; + internal_phy = <1>; + mc_val = <0x4be04>; + /*mc_val = <0x1621>;*/ +}; + +&ir { + status = "disabled"; + /* pinctrl-0 = <&remote_input_ao_pins>; */ + /* pinctrl-names = "default"; */ +}; + +&saradc { + status = "okay"; + vref-supply = <&vddio_ao18>; +}; + +/* Wireless SDIO Module */ +&sd_emmc_a { + status = "disabled"; + /* pinctrl-0 = <&sdio_pins>; */ + /* pinctrl-names = "default"; */ + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + + non-removable; + disable-wp; + card_type = <3>; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* SD card */ +&sd_emmc_b { + status = "disabled"; + /*pinctrl-0 = <&sd_all_pins>;*/ + /*pinctrl-names = "default";*/ + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + card_type = <5>; + + /* cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>; */ + /* cd-inverted; */ + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "disabled"; + /* pinctrl-0 = <&emmc_conf_pull_up &emmc_conf_pull_done>; */ + /* pinctrl-names = "default"; */ + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <200000000>; + non-removable; + disable-wp; + /* mmc-ddr-1_8v; */ + /* mmc-hs200-1_8v; */ + card_type = <1>; + + core-phase0 = <3>; + tx-phase0 = <0>; + + core-phase1 = <3>; + tx-phase1 = <0>; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* nand */ +&nand { + status = "okay"; + /* pinctrl-names = "default", "nand_all_pins", "nand_cs_only"; */ + /* pinctrl-0 = <&all_nand_pins>; */ + /* pinctrl-1 = <&all_nand_pins>; */ + /* pinctrl-2 = <&nand_cs_pins>; */ + + /* + #address-cells = <1>; + #size-cells = <0>; + + nand@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + nand-on-flash-bbt; + nand-ecc-mode = "hw"; + nand-ecc-strength = <8>; + nand-ecc-step-size = <1024>; + + meson-nand-user-mode = <2>; + meson-nand-ran-mode = <1>; + + partition@0 { + label = "boot"; + reg = <0x00000000 0x00200000>; + read-only; + }; + partition@200000 { + label = "env"; + reg = <0x00200000 0x00400000>; + }; + partition@600000 { + label = "system"; + reg = <0x00600000 0x00a00000>; + }; + partition@1000000 { + label = "rootfs"; + reg = <0x01000000 0x03000000>; + }; + partition@4000000 { + label = "media"; + reg = <0x04000000 0x8000000>; + }; + };*/ + +}; + +&dwc3 { + status = "okay"; + dr_mode = "host"; +}; + +&usb2_phy_v2 { + status = "okay"; + portnum = <1>; +}; + +&usb3_phy_v2 { + status = "okay"; + portnum = <0>; + gpio-vbus-power = "GPIOH_6"; + /*gpios = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>;*/ +}; + +&pwm_ef { + status = "okay"; + /* pinctrl-0 = <&pwm_e_pins>; */ + /* pinctrl-names = "default"; */ +}; + +/* This is connected to the Bluetooth module: */ +&uart_a { + status = "okay"; + /* pinctrl-0 = <&a_uart_pins>; */ + /* pinctrl-names = "default"; */ + uart-has-rtscts; +}; + +&spifc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spifc_pins>; + max-frequency = <24000000>; + max-cs = <2>; + /* 512M */ + clocks = <&clkc CLKID_FCLK_DIV3>, + <&clkc CLKID_SPIFC_MUX>, + <&clkc CLKID_SPIFC_DIV>, + <&clkc CLKID_SPIFC_GATE>, + <&clkc CLKID_SPIFC_XTAL_GATE>; + clock-names = "fclk_source", "spifc_mux", "spifc_div", "spifc_gate", "spifc_xtal_gate"; +}; + +&spicc0 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc0_pins_a>; + cs-gpios = <&gpio GPIOA_8 0>; +}; + +&pwm_ab { + status = "okay"; + /* set mux pwm_a_pins4 pwm_b_pins2 for led */ + pinctrl-names="default"; + pinctrl-0=<&pwm_a_pins4 &pwm_b_pins2>; +}; + +&pwm_cd { + status = "okay"; + /* set mux pwm_c_pins3 for led */ + pinctrl-names="default"; + pinctrl-0=<&pwm_c_pins3>; +};
diff --git a/arch/arm/dts/meson-a1-a113l-ad409.dts b/arch/arm/dts/meson-a1-a113l-ad409.dts new file mode 100644 index 0000000..4e2afc5 --- /dev/null +++ b/arch/arm/dts/meson-a1-a113l-ad409.dts
@@ -0,0 +1,83 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "meson-a1-a113l-ad409.dtsi" +#include "meson-a1_skt-panel.dtsi" + +/ { + compatible = "amlogic,ad409", "amlogic,a113l", "amlogic,meson-a1"; + model = "Amlogic Meson A1 AD409 Development Board"; +}; + +/* This UART is brought out to the DB9 connector */ +&uart_a { + status = "okay"; +}; + +&uart_b { + status = "okay"; +}; + +&saradc { + status = "okay"; +}; + +/* demo for i2c user */ +&i2c3 { + status= "disabled"; + clock-frequency = <100000>; + /* pinctrl-names = "default";*/ + /* pinctrl-0 = <&i2c3_master_pins2>;*/ +}; + +&pinctrl_periphs { + bl_pwm_off_pins:bl_pwm_off_pin { + mux { + groups = "GPIOH_5"; + function = "gpio_periphs"; + output-high; + }; + }; +}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-a1-a113l-ad409.dtsi b/arch/arm/dts/meson-a1-a113l-ad409.dtsi new file mode 100644 index 0000000..338a247 --- /dev/null +++ b/arch/arm/dts/meson-a1-a113l-ad409.dtsi
@@ -0,0 +1,271 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>. + * Based on meson-gx-p23x-q20x.dtsi: + * - Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * - Copyright (c) 2016 BayLibre, SAS. + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +/* Common DTSI for devices which are based on the P212 reference board. */ + +#include "meson-a1-a113l.dtsi" + +/ { + aliases { + serial0 = &uart_b; + serial1 = &uart_a; + spi0 = &spifc; + spi1 = &spicc0; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + vddio_boot: regulator-vddio_boot { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vddio_ao18: regulator-vddio_ao18 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + /*reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;*/ + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; +}; + +ðmac { + status = "okay"; + internal_phy = <1>; + mc_val = <0x4be04>; + /*mc_val = <0x1621>;*/ +}; + +&ir { + status = "disabled"; + /* pinctrl-0 = <&remote_input_ao_pins>; */ + /* pinctrl-names = "default"; */ +}; + +&saradc { + status = "okay"; + vref-supply = <&vddio_ao18>; +}; + +/* Wireless SDIO Module */ +&sd_emmc_a { + status = "disabled"; + /* pinctrl-0 = <&sdio_pins>; */ + /* pinctrl-names = "default"; */ + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + + non-removable; + disable-wp; + card_type = <3>; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* SD card */ +&sd_emmc_b { + status = "disabled"; + /*pinctrl-0 = <&sd_all_pins>;*/ + /*pinctrl-names = "default";*/ + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + card_type = <5>; + + /* cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>; */ + /* cd-inverted; */ + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "disabled"; + /* pinctrl-0 = <&emmc_conf_pull_up &emmc_conf_pull_done>; */ + /* pinctrl-names = "default"; */ + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <200000000>; + non-removable; + disable-wp; + /* mmc-ddr-1_8v; */ + /* mmc-hs200-1_8v; */ + card_type = <1>; + + core-phase0 = <3>; + tx-phase0 = <0>; + + core-phase1 = <3>; + tx-phase1 = <0>; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* nand */ +&nand { + status = "okay"; + /* pinctrl-names = "default", "nand_all_pins", "nand_cs_only"; */ + /* pinctrl-0 = <&all_nand_pins>; */ + /* pinctrl-1 = <&all_nand_pins>; */ + /* pinctrl-2 = <&nand_cs_pins>; */ + + /* + #address-cells = <1>; + #size-cells = <0>; + + nand@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + nand-on-flash-bbt; + nand-ecc-mode = "hw"; + nand-ecc-strength = <8>; + nand-ecc-step-size = <1024>; + + meson-nand-user-mode = <2>; + meson-nand-ran-mode = <1>; + + partition@0 { + label = "boot"; + reg = <0x00000000 0x00200000>; + read-only; + }; + partition@200000 { + label = "env"; + reg = <0x00200000 0x00400000>; + }; + partition@600000 { + label = "system"; + reg = <0x00600000 0x00a00000>; + }; + partition@1000000 { + label = "rootfs"; + reg = <0x01000000 0x03000000>; + }; + partition@4000000 { + label = "media"; + reg = <0x04000000 0x8000000>; + }; + };*/ + +}; + +&dwc3 { + status = "okay"; + dr_mode = "host"; +}; + +&usb2_phy_v2 { + status = "okay"; + portnum = <1>; +}; + +&usb3_phy_v2 { + status = "okay"; + portnum = <0>; + gpio-vbus-power = "GPIOH_6"; + /*gpios = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>;*/ +}; + +&pwm_ef { + status = "okay"; + /* pinctrl-0 = <&pwm_e_pins>; */ + /* pinctrl-names = "default"; */ +}; + +/* This is connected to the Bluetooth module: */ +&uart_a { + status = "okay"; + /* pinctrl-0 = <&a_uart_pins>; */ + /* pinctrl-names = "default"; */ + uart-has-rtscts; +}; + +&spifc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spifc_pins>; + max-frequency = <24000000>; + max-cs = <2>; + /* 512M */ + clocks = <&clkc CLKID_FCLK_DIV3>, + <&clkc CLKID_SPIFC_MUX>, + <&clkc CLKID_SPIFC_DIV>, + <&clkc CLKID_SPIFC_GATE>, + <&clkc CLKID_SPIFC_XTAL_GATE>; + clock-names = "fclk_source", "spifc_mux", "spifc_div", "spifc_gate", "spifc_xtal_gate"; +}; + +&spicc0 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc0_pins_a>; + cs-gpios = <&gpio GPIOA_8 0>; +};
diff --git a/arch/arm/dts/meson-a1-a113l.dtsi b/arch/arm/dts/meson-a1-a113l.dtsi new file mode 100644 index 0000000..ff78691 --- /dev/null +++ b/arch/arm/dts/meson-a1-a113l.dtsi
@@ -0,0 +1,54 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "meson-a1.dtsi" +#include "meson-a1-mali.dtsi" + +/ { + compatible = "amlogic,s905N", "amlogic,meson-a1"; +}; + +ðmac { + phy-mode = "rmii"; + phy-handle = <&internal_phy>; +};
diff --git a/arch/arm/dts/meson-a1-mali.dtsi b/arch/arm/dts/meson-a1-mali.dtsi new file mode 100644 index 0000000..2655b42 --- /dev/null +++ b/arch/arm/dts/meson-a1-mali.dtsi
@@ -0,0 +1,43 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 BayLibre SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +&apb { + mali: gpu@40000 { + compatible = "amlogic,meson-gxbb-mali", "arm,mali-450"; + reg = <0x0 0x40000 0x0 0x40000>; + interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "gp", "gpmmu", "pp", "pmu", + "pp0", "ppmmu0", "pp1", "ppmmu1", + "pp2", "ppmmu2"; + /*clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;*/ + clock-names = "bus", "core"; + + /* + * Mali clocking is provided by two identical clock paths + * MALI_0 and MALI_1 muxed to a single clock by a glitch + * free mux to safely change frequency while running. + */ + /* + assigned-clocks = <&clkc CLKID_MALI_0_SEL>, + <&clkc CLKID_MALI_0>, + <&clkc CLKID_MALI>; *//* Glitch free mux */ + /*assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, + <0>, *//* Do Nothing */ + //<&clkc CLKID_MALI_0>; + /*assigned-clock-rates = <0>,*/ /* Do Nothing */ + /* <666666666>, + <0>;*/ /* Do Nothing */ + }; +};
diff --git a/arch/arm/dts/meson-a1.dtsi b/arch/arm/dts/meson-a1.dtsi new file mode 100644 index 0000000..36d58cd --- /dev/null +++ b/arch/arm/dts/meson-a1.dtsi
@@ -0,0 +1,533 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "meson-a-series.dtsi" +#include <dt-bindings/gpio/meson-a1-gpio.h> +#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h> + +/ { + compatible = "amlogic,meson-a1"; + + vpu { + compatible = "amlogic, vpu-g12a"; + status = "okay"; + /*clocks = <&clkc CLKID_VAPB_MUX>, + * <&clkc CLKID_VPU_INTR>, + * <&clkc CLKID_VPU_P0_COMP>, + * <&clkc CLKID_VPU_P1_COMP>, + * <&clkc CLKID_VPU_MUX>; + *clock-names = "vapb_clk", + * "vpu_intr_gate", + * "vpu_clk0", + * "vpu_clk1", + * "vpu_clk"; + */ + clk_level = <7>; + /* 0: 100.0M 1: 166.7M 2: 200.0M 3: 250.0M */ + /* 4: 333.3M 5: 400.0M 6: 500.0M 7: 666.7M */ + }; + + meson-fb { + status = "okay"; + logo_addr = "0x7f800000"; + }; +}; + +ðmac { + reg = <0x0 0xff3f0000 0x0 0x10000 + 0x0 0xff634540 0x0 0x8>; + +// clocks = <&clkc CLKID_ETH_CORE>, +// <&clkc CLKID_FCLK_DIV2>, +// <&clkc CLKID_MPLL2>; +// clock-names = "stmmaceth", "clkin0", "clkin1"; + + mdio0: mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + }; +}; + +&cbus { + pinctrl_periphs: pinctrl@0400 { + compatible = "amlogic,meson-a1-periphs-pinctrl"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio: bank@0400 { + reg = <0x0 0x0400 0x0 0x003c>, + <0x0 0x0480 0x0 0x0118>; + reg-names = "mux", + "gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_periphs 0 0 63>; + }; + }; +}; + +&periphs { + + eth-phy-mux { + compatible = "mdio-mux-mmioreg", "mdio-mux"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x15c 0x0 0x4>; + mux-mask = <0xffffffff>; + mdio-parent-bus = <&mdio0>; + + internal_mdio: mdio@e40908ff { + reg = <0xe40908ff>; + #address-cells = <1>; + #size-cells = <0>; + + internal_phy: ethernet-phy@8 { + compatible = "ethernet-phy-id0181.4400", "ethernet-phy-ieee802.3-c22"; + reg = <8>; + max-speed = <100>; + }; + }; + + external_mdio: mdio@2009087f { + reg = <0x2009087f>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&saradc { + compatible = "amlogic,meson-g12a-saradc", "amlogic,meson-saradc"; + clocks = <&xtal>, + <&clkc CLKID_SARADC_MUX>, + <&clkc CLKID_SARADC_DIV>, + <&clkc CLKID_SAR_ADC_GATE>; + clock-names = "xtal", "adc_mux", "adc_div", "adc_gate"; +}; + +&sd_emmc_a { + /* + clocks = <&clkc CLKID_SD_EMMC_A>, + <&xtal>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + */ +}; + +&sd_emmc_b { + /* + clocks = <&clkc CLKID_FCLK_DIV2>, + <&xtal>, + <&clkc CLKID_SD_EMMC_B_P0_MUX>, + <&clkc CLKID_SD_EMMC_B_P0_DIV>, + <&clkc CLKID_SD_EMMC_B_P0_GATE>, + <&clkc CLKID_SD_EMMC_B>; + clock-names = "clkin", "clkin1", "clkin2", "clkin3", "clkin4", "core"; + */ +}; + +&sd_emmc_c { + /* + clocks = <&clkc CLKID_FCLK_DIV2>, + <&xtal>, + <&clkc CLKID_SD_EMMC_C_P0_MUX>, + <&clkc CLKID_SD_EMMC_C_P0_DIV>, + <&clkc CLKID_SD_EMMC_C_P0_GATE>, + <&clkc CLKID_SD_EMMC_C>; + clock-names = "clkin", "clkin1", "clkin2", "clkin3", "clkin4", "core"; + */ +}; + +&nand { + /* + clocks = <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_SD_EMMC_C_P0_MUX>, + <&clkc CLKID_SD_EMMC_C_P0_DIV>, + <&clkc CLKID_SD_EMMC_C_P0_GATE>; + clock-names = "clkin", "clkin1", "clkin2", "clkin3";*/ + /*amlogic,mmc-syscon = <&sd_emmc_c>;*/ +}; + +&spicc0 { + clocks = <&clkc CLKID_SPICC_A_DIV>, <&clkc CLKID_SPICC_A_GATE>; + clock-names = "async", "async-gate"; + assigned-clocks = <&clkc CLKID_SPICC_A_MUX>, <&clkc CLKID_SPICC_A_DIV>; + assigned-clock-parents = <&clkc CLKID_FCLK_DIV2>; + assigned-clock-rates = <0>, <200000000>; + /* =PM_SPICC, no set for power on already */ + /* pm-id = <22>; */ +}; + +&pinctrl_periphs { + jtag_a_pins:jtag_a_pin { + mux { + groups = "jtag_a_clk", + "jtag_a_tms", + "jtag_a_tdi", + "jtag_a_tdo"; + function = "jtag_a"; + }; + }; + + swd_a_pins:swd_a_pin { + mux { + groups = "swclk", + "swdio"; + function = "sw"; + }; + }; + + i2c0_master_pins1:i2c0_pins1 { + mux { + groups = "i2c_a_scl_f11", + "i2c_a_sda_f12"; + function = "i2c_a"; + bias-pull-up; + drive-strength = <3>; + }; + }; + + i2c0_master_pins2:i2c0_pins2 { + mux { + groups = "i2c_a_scl_f9", + "i2c_a_sda_f10"; + function = "i2c_a"; + bias-pull-up; + drive-strength = <3>; + }; + }; + + i2c1_master_pins1:i2c1_pins1 { + mux { + groups = "i2c_b_sda_x", + "i2c_b_scl_x"; + function = "i2c_b"; + bias-pull-up; + drive-strength = <3>; + }; + }; + + i2c1_master_pins2:i2c1_pins2 { + mux { + groups = "i2c_b_sda_a", + "i2c_b_scl_a"; + function = "i2c_b"; + bias-pull-up; + drive-strength = <3>; + }; + }; + + i2c2_master_pins1:i2c2_pins1 { + mux { + groups = "i2c_c_scl_x0", + "i2c_c_sda_x1"; + function = "i2c_c"; + bias-pull-up; + drive-strength = <3>; + }; + }; + + i2c2_master_pins2:i2c2_pins2 { + mux { + groups = "i2c_c_scl_x15", + "i2c_c_sda_x16"; + function = "i2c_c"; + bias-pull-up; + drive-strength = <3>; + }; + }; + + i2c2_master_pins3:i2c2_pins3 { + mux { + groups = "i2c_c_scl_a4", + "i2c_c_sda_a5"; + function = "i2c_c"; + bias-pull-up; + drive-strength = <3>; + }; + }; + + i2c2_master_pins4:i2c2_pins4 { + mux { + groups = "i2c_c_scl_a8", + "i2c_c_sda_a9"; + function = "i2c_c"; + bias-pull-up; + drive-strength = <3>; + }; + }; + + i2c3_master_pins1:i2c3_pins1 { + mux { + groups = "i2c_d_scl_x", + "i2c_d_sda_x"; + function = "i2c_d"; + bias-pull-up; + drive-strength = <3>; + }; + }; + + i2c3_master_pins2:i2c3_pins2 { + mux { + groups = "i2c_d_scl_f", + "i2c_d_sda_f"; + function = "i2c_d"; + bias-pull-up; + drive-strength = <3>; + }; + }; + + spifc_pins: spifc_pins { + mux { + groups = "spif_mo", + "spif_mi", + "spif_clk", + "spif_cs", + "spif_hold_n", + "spif_wp_n"; + function = "spif"; + drive-strength = <3>; + }; + }; + + spicc0_pins_a: spicc0_pins_a { + mux { + groups = "spi_a_mosi_a", + "spi_a_miso_a", + "spi_a_sclk_a"; + function = "spi_a"; + drive-strength = <2>; + }; + }; + + pwm_a_pins1: pwm_a_pins1 { + mux { + groups = "pwm_a_x6"; + function = "pwm_a"; + }; + }; + + pwm_a_pins2: pwm_a_pins2 { + mux { + groups = "pwm_a_x7"; + function = "pwm_a"; + }; + }; + + pwm_a_pins3: pwm_a_pins3 { + mux { + groups = "pwm_a_f10"; + function = "pwm_a"; + }; + }; + + pwm_a_pins4: pwm_a_pins4 { + mux { + groups = "pwm_a_f6"; + function = "pwm_a"; + }; + }; + + pwm_a_pins5: pwm_a_pins5 { + mux { + groups = "pwm_a_a"; + function = "pwm_a"; + }; + }; + + pwm_b_pins1: pwm_b_pins1 { + mux { + groups = "pwm_b_x"; + function = "pwm_b"; + }; + }; + + pwm_b_pins2: pwm_b_pins2 { + mux { + groups = "pwm_b_f"; + function = "pwm_b"; + }; + }; + + pwm_b_pins3: pwm_b_pins3 { + mux { + groups = "pwm_b_a"; + function = "pwm_b"; + }; + }; + + pwm_c_pins1: pwm_c_pins1 { + mux { + groups = "pwm_c_x"; + function = "pwm_c"; + }; + }; + + pwm_c_pins2: pwm_c_pins2 { + mux { + groups = "pwm_c_f3"; + function = "pwm_c"; + }; + }; + + pwm_c_pins3: pwm_c_pins3 { + mux { + groups = "pwm_c_f8"; + function = "pwm_c"; + }; + }; + + pwm_c_pins3: pwm_c_pins3 { + mux { + groups = "pwm_c_f8"; + function = "pwm_c"; + }; + }; + + pwm_c_pins4: pwm_c_pins4 { + mux { + groups = "pwm_c_a"; + function = "pwm_c"; + }; + }; + + pwm_d_pins1: pwm_d_pins1 { + mux { + groups = "pwm_d_x15"; + function = "pwm_d"; + }; + }; + + pwm_d_pins2: pwm_d_pins2 { + mux { + groups = "pwm_d_x13"; + function = "pwm_d"; + }; + }; + + pwm_d_pins3: pwm_d_pins3 { + mux { + groups = "pwm_d_x10"; + function = "pwm_d"; + }; + }; + + pwm_d_pins4: pwm_d_pins4 { + mux { + groups = "pwm_d_f"; + function = "pwm_d"; + }; + }; + + pwm_e_pins1: pwm_e_pins1 { + mux { + groups = "pwm_e_p"; + function = "pwm_e"; + }; + }; + + pwm_e_pins2: pwm_e_pins2 { + mux { + groups = "pwm_e_x16"; + function = "pwm_e"; + }; + }; + + pwm_e_pins3: pwm_e_pins3 { + mux { + groups = "pwm_e_x14"; + function = "pwm_e"; + }; + }; + + pwm_e_pins4: pwm_e_pins4 { + mux { + groups = "pwm_e_x2"; + function = "pwm_e"; + }; + }; + + pwm_e_pins5: pwm_e_pins5 { + mux { + groups = "pwm_e_f"; + function = "pwm_e"; + }; + }; + + pwm_e_pins6: pwm_e_pins6 { + mux { + groups = "pwm_e_a"; + function = "pwm_e"; + }; + }; + + pwm_f_pins1: pwm_f_pins1 { + mux { + groups = "pwm_f_b"; + function = "pwm_f"; + }; + }; + + pwm_f_pins2: pwm_f_pins2 { + mux { + groups = "pwm_f_x"; + function = "pwm_f"; + }; + }; + + pwm_f_pins3: pwm_f_pins3 { + mux { + groups = "pwm_f_f4"; + function = "pwm_f"; + }; + }; + + pwm_f_pins4: pwm_f_pins4 { + mux { + groups = "pwm_f_f12"; + function = "pwm_f"; + }; + }; +};
diff --git a/arch/arm/dts/meson-a1_skt-panel.dtsi b/arch/arm/dts/meson-a1_skt-panel.dtsi new file mode 100644 index 0000000..fbb676c --- /dev/null +++ b/arch/arm/dts/meson-a1_skt-panel.dtsi
@@ -0,0 +1,742 @@ +/* + * arch/arm64/boot/dts/amlogic/mesong12a_skt-panel.dtsi + * + * Copyright (C) 2016 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/ { + lcd{ + compatible = "amlogic, lcd-g12a"; + mode = "tablet"; + status = "okay"; + key_valid = <0>; + /* + clocks = <&clkc CLKID_MIPI_DSI_HOST + &clkc CLKID_MIPI_DSI_PHY + &clkc CLKID_DSI_MEAS_COMP + &clkc CLKID_VCLK2_ENCL + &clkc CLKID_VCLK2_VENCL + &clkc CLKID_GP0_PLL>; + clock-names = "dsi_host_gate", + "dsi_phy_gate", + "dsi_meas", + "encl_top_gate", + "encl_int_gate", + "gp0_pll"; + */ + reg = <0x0 0xffd07000 0x0 0x400 /* dsi_host */ + 0x0 0xff644000 0x0 0x200>; /* dsi_phy */ + interrupts = <0 3 1 + 0 56 1>; + interrupt-names = "vsync","vsync2"; + pinctrl_version = <2>; /* for uboot */ + + /* power type: + * (0=cpu_gpio, 1=pmu_gpio, 2=signal,3=extern, 0xff=ending) + * power index: + * (point gpios_index, or extern_index,0xff=invalid) + * power value:(0=output low, 1=output high, 2=input) + * power delay:(unit in ms) + */ + + /*lcd_cpu-gpios = <&gpio GPIOZ_9 GPIO_ACTIVE_HIGH + &gpio GPIOZ_8 GPIO_ACTIVE_HIGH>; + */ + lcd_cpu_gpio_names = "GPIOZ_9","GPIOZ_8"; + + lcd_0{ + model_name = "B080XAN01"; + interface = "mipi"; + basic_setting = <768 1024 /*h_active, v_active*/ + 948 1140 /*h_period, v_period*/ + 8 /*lcd_bits*/ + 119 159>; /*screen_widht, screen_height*/ + lcd_timing = <64 56 0 /*hs_width, hs_bp, hs_pol*/ + 50 30 0>; /*vs_width, vs_bp, vs_pol*/ + clk_attr = <0 /*fr_adj_type(0=clk, 1=htotal, 2=vtotal)*/ + 0 /*clk_ss_level */ + 1 /*clk_auto_generate*/ + 64843200>; /*pixel_clk(unit in Hz)*/ + mipi_attr = <4 /*lane_num*/ + 550 /*bit_rate_max(MHz)*/ + 0 /*factor(*100, default 0 for auto)*/ + 1 /*operation_mode_init(0=video, 1=command)*/ + 0 /*operation_mode_display(0=video, 1=command)*/ + 2 /* + *video_mode_type + *(0=sync_pulse,1=sync_event,2=burst) + */ + 1 /*clk_always_hs(0=disable,1=enable)*/ + 0>; /*phy_switch(0=auto,1=standard,2=slow)*/ + + /* dsi_init: data_type, num, data... */ + dsi_init_on = <0x05 1 0x11 + 0xfd 1 20 /*delay(ms)*/ + 0x05 1 0x29 + 0xfd 1 20 /*delay(ms)*/ + 0xff 0>; /*ending*/ + dsi_init_off = <0x05 1 0x28 + 0xfd 1 10 /*delay(ms)*/ + 0x05 1 0x10 + 0xfd 1 10 /*delay(ms)*/ + 0xff 0>; /*ending*/ + extern_init = <0xff>; /*0xff for invalid*/ + + /* power step: type, index, value, delay(ms) */ + power_on_step = < + 0 1 0 100 + 0 0 0 10 + 0 0 1 20 + 2 0 0 0 + 0xff 0 0 0>; /*ending*/ + power_off_step = < + 2 0 0 50 + 0 0 0 10 + 0 1 1 100 + 0xff 0 0 0>; /*ending*/ + backlight_index = <0>; + }; + + lcd_1{ + model_name = "P070ACB_FT"; + interface = "mipi"; + basic_setting = <600 1024 /*h_active, v_active*/ + 770 1070 /*h_period, v_period*/ + 8 /*lcd_bits*/ + 3 5>; /*screen_widht, screen_height*/ + lcd_timing = <10 80 0 /*hs_width,hs_bp,hs_pol*/ + 6 20 0>; /*vs_width,vs_bp,vs_pol*/ + clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/ + 0 /*clk_ss_level*/ + 1 /*clk_auto_generate*/ + 49434000>; /*pixel_clk(unit in Hz)*/ + mipi_attr = <4 /*lane_num*/ + 400 /*bit_rate_max(MHz)*/ + 0 /*factor(*100, default 0 for auto)*/ + 1 /*operation_mode_init(0=video, 1=command)*/ + 0 /*operation_mode_display(0=video, 1=command)*/ + 2 /* + *video_mode_type + *(0=sync_pulse,1=sync_event,2=burst) + */ + 0 /*clk_always_hs(0=disable,1=enable)*/ + 0>; /*phy_switch(0=auto,1=standard,2=slow)*/ + /* dsi_init: data_type, num, data... */ + dsi_init_on = < + 0xff 10 + 0xf0 3 0 1 30 /* reset high, delay 30ms */ + 0xf0 3 0 0 10 /* reset low, delay 10ms */ + 0xf0 3 0 1 30 /* reset high, delay 30ms */ + 0xfc 2 0x04 3 /* check_reg, check_cnt */ + 0xff 0>; /* ending flag */ + dsi_init_off = <0xff 0>; /* ending flag */ + /* extern_init: 0xff for invalid */ + extern_init = <2>; + /* power step: type,index,value,delay(ms) */ + power_on_step = < + 0 1 0 200 /* panel power on */ + 2 0 0 0 + 0xff 0 0 0>; + power_off_step = < + 2 0 0 0 + 0 0 0 20 /* reset low */ + 0 1 1 100 /* panel power off */ + 0xff 0 0 0>; + backlight_index = <0>; + }; + + lcd_3{ + model_name = "TL050FHV02CT"; + interface = "mipi"; + basic_setting = <1080 1920 /*h_active, v_active*/ + 1125 2100 /*h_period, v_period*/ + 8 /*lcd_bits*/ + 65 119>; /*screen_widht, screen_height*/ + lcd_timing = <5 30 0 /*hs_width,hs_bp,hs_pol*/ + 44 108 0>; /*vs_width,vs_bp,vs_pol*/ + clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/ + 0 /*clk_ss_level*/ + 1 /*clk_auto_generate*/ + 118125000>; /*pixel_clk(unit in Hz)*/ + mipi_attr = <4 /*lane_num*/ + 960 /*bit_rate_max(MHz)*/ + 0 /*factor(*100, default 0 for auto)*/ + 1 /*operation_mode_init(0=video, 1=command)*/ + 0 /*operation_mode_display(0=video, 1=command)*/ + 2 /* + *video_mode_type + *(0=sync_pulse,1=sync_event,2=burst) + */ + 1 /*clk_always_hs(0=disable,1=enable)*/ + 0>; /*phy_switch(0=auto,1=standard,2=slow)*/ + /* dsi_init: data_type, num, data... */ + dsi_init_on = <0xff 0>; /* ending flag */ + dsi_init_off = <0xff 0>; /* ending flag */ + /* extern_init: 0xff for invalid */ + extern_init = <3>; + /* power step: type,index,value,delay(ms) */ + power_on_step = < + 0 1 0 200 + 0 0 1 20 + 0 0 0 10 + 0 0 1 20 + 2 0 0 0 + 0xff 0 0 0>; + power_off_step = < + 2 0 0 0 + 0 0 0 20 + 0 1 1 100 + 0xff 0 0 0>; + backlight_index = <0>; + }; + + lcd_4{ + model_name = "TL070WSH27"; + interface = "mipi"; + basic_setting = <1024 600 /*h_active, v_active*/ + 1250 630 /*h_period, v_period*/ + 8 /*lcd_bits*/ + 154 86>; /*screen_widht, screen_height*/ + lcd_timing = <80 100 0 /*hs_width, hs_bp, hs_pol*/ + 5 20 0>; /*vs_width, vs_bp, vs_pol*/ + clk_attr = <0 /*fr_adj_type(0=clk, 1=htotal, 2=vtotal)*/ + 0 /*clk_ss_level */ + 1 /*clk_auto_generate*/ + 47250000>; /*pixel_clk(unit in Hz)*/ + mipi_attr = <4 /*lane_num*/ + 300 /*bit_rate_max(MHz)*/ + 0 /*factor(*100, default 0 for auto)*/ + 1 /*operation_mode_init(0=video, 1=command)*/ + 0 /*operation_mode_display(0=video, 1=command)*/ + 2 /* + *video_mode_type + *(0=sync_pulse,1=sync_event,2=burst) + */ + 1 /*clk_always_hs(0=disable,1=enable)*/ + 0>; /*phy_switch(0=auto,1=standard,2=slow)*/ + + /* dsi_init: data_type, num, data... */ + dsi_init_on = <0x05 1 0x11 + 0xfd 1 20 /*delay(ms)*/ + 0x05 1 0x29 + 0xfd 1 20 /*delay(ms)*/ + 0xff 0>; /*ending*/ + dsi_init_off = <0x05 1 0x28 + 0xfd 1 10 /*delay(ms)*/ + 0x05 1 0x10 + 0xfd 1 10 /*delay(ms)*/ + 0xff 0>; /*ending*/ + extern_init = <0xff>; /*0xff for invalid*/ + + /* power step: type, index, value, delay(ms) */ + power_on_step = < + 0 1 0 100 + 0 0 0 10 + 0 0 1 20 + 2 0 0 0 + 0xff 0 0 0>; /*ending*/ + power_off_step = < + 2 0 0 50 + 0 0 0 10 + 0 1 1 100 + 0xff 0 0 0>; /*ending*/ + backlight_index = <0>; + }; + }; + + lcd_extern{ + compatible = "amlogic, lcd_extern"; + status = "okay"; + i2c_bus = "i2c_bus_0"; + key_valid = <0>; + + extern_0{ + index = <0>; + extern_name = "mipi_default";/*default*/ + status = "okay"; + type = <2>; /* 0=i2c, 1=spi, 2=mipi */ + cmd_size = <0xff>; + init_on = < + 0xfd 1 10 + 0x05 1 0x11 + 0xfd 1 120 /* delay 120ms */ + 0x05 1 0x29 + 0xff 0>; /*ending*/ + init_off = < + 0x05 1 0x28 /* display off */ + 0xfd 1 10 /* delay 10ms */ + 0x05 1 0x10 /* sleep in */ + 0xfd 1 150 /* delay 150ms */ + 0xff 0>; /*ending*/ + }; + + extern_2{ + index = <2>; + extern_name = "mipi_default";/*P070ACB_FT*/ + status = "okay"; + type = <2>; /* 0=i2c, 1=spi, 2=mipi */ + cmd_size = <0xff>; + init_on = < + 0x23 2 0xE0 0x00 /* Page 0 */ + 0x23 2 0xE1 0x93 /* PASSWORD */ + 0x23 2 0xE2 0x65 + 0x23 2 0xE3 0xF8 + 0x23 2 0x80 0x03 + 0x23 2 0xE0 0x01 /* Page 01 */ + 0x23 2 0x0C 0x74 /* Set PWRIC */ + 0x23 2 0x17 0x00 /* Set Gamma Power */ + 0x23 2 0x18 0xEF /* VGMP=5.1V */ + 0x23 2 0x19 0x00 + 0x23 2 0x1A 0x00 + 0x23 2 0x1B 0xEF /* VGMN=-5.1V */ + 0x23 2 0x1C 0x00 + 0x23 2 0x1F 0x70 /* Set Gate Power */ + 0x23 2 0x20 0x2D + 0x23 2 0x21 0x2D + 0x23 2 0x22 0x7E + 0x23 2 0x26 0xF3 /* VDDD from IOVCC */ + 0x23 2 0x37 0x09 /* SetPanel */ + 0x23 2 0x38 0x04 /* SET RGBCYC */ + 0x23 2 0x39 0x00 + 0x23 2 0x3A 0x01 + 0x23 2 0x3C 0x90 + 0x23 2 0x3D 0xFF + 0x23 2 0x3E 0xFF + 0x23 2 0x3F 0xFF + 0x23 2 0x40 0x02 /* Set TCON */ + 0x23 2 0x41 0x80 + 0x23 2 0x42 0x99 + 0x23 2 0x43 0x14 + 0x23 2 0x44 0x19 + 0x23 2 0x45 0x5A + 0x23 2 0x4B 0x04 + 0x23 2 0x55 0x02 /* power voltage */ + 0x23 2 0x56 0x01 + 0x23 2 0x57 0x69 + 0x23 2 0x58 0x0A + 0x23 2 0x59 0x0A + 0x23 2 0x5A 0x2E /* VGH = 16.2V */ + 0x23 2 0x5B 0x19 /* VGL = -12V */ + 0x23 2 0x5C 0x15 + 0x23 2 0x5D 0x77 /* Gamma */ + 0x23 2 0x5E 0x56 + 0x23 2 0x5F 0x45 + 0x23 2 0x60 0x38 + 0x23 2 0x61 0x35 + 0x23 2 0x62 0x27 + 0x23 2 0x63 0x2D + 0x23 2 0x64 0x18 + 0x23 2 0x65 0x33 + 0x23 2 0x66 0x34 + 0x23 2 0x67 0x35 + 0x23 2 0x68 0x56 + 0x23 2 0x69 0x45 + 0x23 2 0x6A 0x4F + 0x23 2 0x6B 0x42 + 0x23 2 0x6C 0x40 + 0x23 2 0x6D 0x34 + 0x23 2 0x6E 0x25 + 0x23 2 0x6F 0x02 + 0x23 2 0x70 0x77 + 0x23 2 0x71 0x56 + 0x23 2 0x72 0x45 + 0x23 2 0x73 0x38 + 0x23 2 0x74 0x35 + 0x23 2 0x75 0x27 + 0x23 2 0x76 0x2D + 0x23 2 0x77 0x18 + 0x23 2 0x78 0x33 + 0x23 2 0x79 0x34 + 0x23 2 0x7A 0x35 + 0x23 2 0x7B 0x56 + 0x23 2 0x7C 0x45 + 0x23 2 0x7D 0x4F + 0x23 2 0x7E 0x42 + 0x23 2 0x7F 0x40 + 0x23 2 0x80 0x34 + 0x23 2 0x81 0x25 + 0x23 2 0x82 0x02 + 0x23 2 0xE0 0x02 /* Page2 */ + 0x23 2 0x00 0x53 + /* GIP_L Pin mapping RESET_EVEN */ + 0x23 2 0x01 0x55 /* VSSG_EVEN */ + 0x23 2 0x02 0x55 /* VSSA_EVEN */ + 0x23 2 0x03 0x51 /* STV2_EVEN */ + 0x23 2 0x04 0x77 /* VDD2_EVEN */ + 0x23 2 0x05 0x57 /* VDD1_EVEN */ + 0x23 2 0x06 0x1F + 0x23 2 0x07 0x4F /* CK12 */ + 0x23 2 0x08 0x4D /* CK10 */ + 0x23 2 0x09 0x1F + 0x23 2 0x0A 0x4B /* CK8 */ + 0x23 2 0x0B 0x49 /* CK6 */ + 0x23 2 0x0C 0x1F + 0x23 2 0x0D 0x47 /* CK4 */ + 0x23 2 0x0E 0x45 /* CK2 */ + 0x23 2 0x0F 0x41 /* STV1_EVEN */ + 0x23 2 0x10 0x1F + 0x23 2 0x11 0x1F + 0x23 2 0x12 0x1F + 0x23 2 0x13 0x55 /* VGG */ + 0x23 2 0x14 0x1F + 0x23 2 0x15 0x1F + 0x23 2 0x16 0x52 + /* GIP_R Pin mapping RESET_ODD */ + 0x23 2 0x17 0x55 /* VSSG_ODD */ + 0x23 2 0x18 0x55 /* VSSA_ODD */ + 0x23 2 0x19 0x50 /* STV2_ODD */ + 0x23 2 0x1A 0x77 /* VDD2_ODD */ + 0x23 2 0x1B 0x57 /* VDD1_ODD */ + 0x23 2 0x1C 0x1F + 0x23 2 0x1D 0x4E /* CK11 */ + 0x23 2 0x1E 0x4C /* CK9 */ + 0x23 2 0x1F 0x1F + 0x23 2 0x20 0x4A /* CK7 */ + 0x23 2 0x21 0x48 /* CK5 */ + 0x23 2 0x22 0x1F + 0x23 2 0x23 0x46 /* CK3 */ + 0x23 2 0x24 0x44 /* CK1 */ + 0x23 2 0x25 0x40 /* STV1_ODD */ + 0x23 2 0x26 0x1F + 0x23 2 0x27 0x1F + 0x23 2 0x28 0x1F + 0x23 2 0x29 0x1F + 0x23 2 0x2A 0x1F + 0x23 2 0x2B 0x55 /* VGG */ + 0x23 2 0x2C 0x12 /* GIP_L_GS Pin mapping */ + 0x23 2 0x2D 0x15 + 0x23 2 0x2E 0x15 + 0x23 2 0x2F 0x00 + 0x23 2 0x30 0x37 + 0x23 2 0x31 0x17 + 0x23 2 0x32 0x1F + 0x23 2 0x33 0x08 + 0x23 2 0x34 0x0A + 0x23 2 0x35 0x1F + 0x23 2 0x36 0x0C + 0x23 2 0x37 0x0E + 0x23 2 0x38 0x1F + 0x23 2 0x39 0x04 + 0x23 2 0x3A 0x06 + 0x23 2 0x3B 0x10 + 0x23 2 0x3C 0x1F + 0x23 2 0x3D 0x1F + 0x23 2 0x3E 0x1F + 0x23 2 0x3F 0x15 + 0x23 2 0x40 0x1F + 0x23 2 0x41 0x1F + 0x23 2 0x42 0x13 /* GIP_R_GS Pin mapping */ + 0x23 2 0x43 0x15 + 0x23 2 0x44 0x15 + 0x23 2 0x45 0x01 + 0x23 2 0x46 0x37 + 0x23 2 0x47 0x17 + 0x23 2 0x48 0x1F + 0x23 2 0x49 0x09 + 0x23 2 0x4A 0x0B + 0x23 2 0x4B 0x1F + 0x23 2 0x4C 0x0D + 0x23 2 0x4D 0x0F + 0x23 2 0x4E 0x1F + 0x23 2 0x4F 0x05 + 0x23 2 0x50 0x07 + 0x23 2 0x51 0x11 + 0x23 2 0x52 0x1F + 0x23 2 0x53 0x1F + 0x23 2 0x54 0x1F + 0x23 2 0x55 0x1F + 0x23 2 0x56 0x1F + 0x23 2 0x57 0x15 + 0x23 2 0x58 0x40 /* GIP Timing */ + 0x23 2 0x59 0x00 + 0x23 2 0x5A 0x00 + 0x23 2 0x5B 0x10 + 0x23 2 0x5C 0x14 + 0x23 2 0x5D 0x40 + 0x23 2 0x5E 0x01 + 0x23 2 0x5F 0x02 + 0x23 2 0x60 0x40 + 0x23 2 0x61 0x03 + 0x23 2 0x62 0x04 + 0x23 2 0x63 0x7A + 0x23 2 0x64 0x7A + 0x23 2 0x65 0x74 + 0x23 2 0x66 0x16 + 0x23 2 0x67 0xB4 + 0x23 2 0x68 0x16 + 0x23 2 0x69 0x7A + 0x23 2 0x6A 0x7A + 0x23 2 0x6B 0x0C + 0x23 2 0x6C 0x00 + 0x23 2 0x6D 0x04 + 0x23 2 0x6E 0x04 + 0x23 2 0x6F 0x88 + 0x23 2 0x70 0x00 + 0x23 2 0x71 0x00 + 0x23 2 0x72 0x06 + 0x23 2 0x73 0x7B + 0x23 2 0x74 0x00 + 0x23 2 0x75 0xBC + 0x23 2 0x76 0x00 + 0x23 2 0x77 0x04 + 0x23 2 0x78 0x2C + 0x23 2 0x79 0x00 + 0x23 2 0x7A 0x00 + 0x23 2 0x7B 0x00 + 0x23 2 0x7C 0x00 + 0x23 2 0x7D 0x03 + 0x23 2 0x7E 0x7B + 0x23 2 0xE0 0x04 /* Page4 */ + 0x23 2 0x09 0x11 /* Set RGBCYC2 */ + 0x23 2 0x0E 0x48 + 0x23 2 0x2B 0x2B /* ESD Protect */ + 0x23 2 0x2E 0x44 + 0x23 2 0xE0 0x00 /* Page0 */ + 0x23 2 0xE6 0x02 /* Watch dog */ + 0x23 2 0xE7 0x0C + 0x05 1 0x11 /* sleep out */ + 0xfd 1 120 + 0x05 1 0x29 /* display on */ + 0x05 1 0x35 + 0xfd 1 20 /* delay(ms) */ + 0xFF 0>; /*ending*/ + init_off = < + 0x05 1 0x28 /* display off */ + 0xfd 1 10 /* delay 10ms */ + 0x05 1 0x10 /* sleep in */ + 0xfd 1 150 /* delay 150ms */ + 0xff 0>; /*ending*/ + }; + + extern_3{ + index = <3>; + extern_name = "mipi_default";/*TL050FHV02CT*/ + status = "okay"; + type = <2>; /* 0=i2c, 1=spi, 2=mipi */ + cmd_size = <0xff>; + init_on = < + 0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x03 + 0x29 10 0x90 0x03 0x14 0x09 0x00 0x00 + 0x00 0x38 0x00 0x00 + 0x29 10 0x91 0x00 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 + 0x29 12 0x92 0x40 0x0B 0x0C 0x0D 0x0E + 0x00 0x38 0x00 0x10 0x03 0x04 + 0x29 9 0x94 0x00 0x08 0x0B 0x03 0xD2 + 0x03 0xD3 0x0C + 0x29 17 0x95 0x00 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 + 0x29 3 0x99 0x00 0x00 + 0x29 12 0x9A 0x00 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 0x00 0x00 + 0x29 7 0x9B 0x01 0x38 0x00 0x00 0x00 0x00 + 0x29 3 0x9C 0x00 0x00 + 0x29 9 0x9D 0x10 0x10 0x10 0x10 0x10 + 0x10 0x00 0x00 + 0x29 3 0x9E 0x00 0x00 + 0x29 11 0xA0 0x9F 0x1F 0x08 0x1F 0x0A + 0x1F 0x00 0x1F 0x14 0x1F + 0x29 11 0xA1 0x15 0x1F 0x1F 0x1F 0x1F + 0x1F 0x1F 0x1F 0x1F 0x1F + 0x29 11 0xA2 0x1F 0x1F 0x1F 0x1F 0x1F + 0x1F 0x1F 0x1F 0x1F 0x1F + 0x29 11 0xA4 0x1F 0x1F 0x1F 0x1F 0x1F + 0x1F 0x1F 0x1F 0x1F 0x1F + 0x29 11 0xA5 0x1F 0x1F 0x1F 0x1F 0x1F + 0x1F 0x1F 0x1F 0x1F 0x15 + 0x29 11 0xA6 0x1F 0x14 0x1F 0x01 0x1F + 0x0B 0x1F 0x09 0x1F 0x1F + 0x29 11 0xA7 0x1F 0x1F 0x0B 0x1F 0x09 + 0x1F 0x01 0x1F 0x15 0x1F + 0x29 11 0xA8 0x14 0x1F 0x1F 0x1F 0x1F + 0x1F 0x1F 0x1F 0x1F 0x1F + 0x29 11 0xA9 0x1F 0x1F 0x1F 0x1F 0x1F + 0x1F 0x1F 0x1F 0x1F 0x1F + 0x29 11 0xAB 0x1F 0x1F 0x1F 0x1F 0x1F + 0x1F 0x1F 0x1F 0x1F 0x1F + 0x29 11 0xAC 0x1F 0x1F 0x1F 0x1F 0x1F + 0x1F 0x1F 0x1F 0x1F 0x14 + 0x29 11 0xAD 0x1F 0x15 0x1F 0x00 0x1F + 0x08 0x1F 0x0A 0x1F 0x1F + 0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x00 + 0x29 4 0xBC 0x00 0x00 0x00 + 0x29 5 0xB8 0x01 0xAF 0x8F 0x8F + 0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x01 + 0x29 17 0xD1 0x00 0x00 0x00 0x09 0x00 + 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D + 0x00 0x79 0x00 0xA7 + 0x29 17 0xD2 0x00 0xCF 0x01 0x12 0x01 + 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED + 0x02 0x2F 0x02 0x74 + 0x29 17 0xD3 0x02 0x9F 0x02 0xD5 0x02 + 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73 + 0x03 0x8C 0x03 0xA5 + 0x29 5 0xD4 0x03 0xC5 0x03 0xFF + 0x29 17 0xD5 0x00 0x00 0x00 0x09 0x00 + 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D + 0x00 0x79 0x00 0xA7 + 0x29 17 0xD6 0x00 0xCF 0x01 0x12 0x01 + 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED + 0x02 0x2F 0x02 0x74 + 0x29 17 0xD7 0x02 0x9F 0x02 0xD5 0x02 + 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73 + 0x03 0x8C 0x03 0xA5 + 0x29 5 0xD8 0x03 0xC5 0x03 0xFF + 0x29 17 0xD9 0x00 0x00 0x00 0x09 0x00 + 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D + 0x00 0x79 0x00 0xA7 + 0x29 17 0xDD 0x00 0xCF 0x01 0x12 0x01 + 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED + 0x02 0x2F 0x02 0x74 + 0x29 17 0xDE 0x02 0x9F 0x02 0xD5 0x02 + 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73 + 0x03 0x8C 0x03 0xA5 + 0x29 5 0xDF 0x03 0xC5 0x03 0xFF + 0x29 17 0xE0 0x00 0x00 0x00 0x09 0x00 + 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D + 0x00 0x79 0x00 0xA7 + 0x29 17 0xE1 0x00 0xCF 0x01 0x12 0x01 + 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED + 0x02 0x2F 0x02 0x74 + 0x29 17 0xE2 0x02 0x9F 0x02 0xD5 0x02 + 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73 + 0x03 0x8C 0x03 0xA5 + 0x29 5 0xE3 0x03 0xC5 0x03 0xFF + 0x29 17 0xE4 0x00 0x00 0x00 0x09 0x00 + 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D + 0x00 0x79 0x00 0xA7 + 0x29 17 0xE5 0x00 0xCF 0x01 0x12 0x01 + 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED + 0x02 0x2F 0x02 0x74 + 0x29 17 0xE6 0x02 0x9F 0x02 0xD5 0x02 + 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73 + 0x03 0x8C 0x03 0xA5 + 0x29 5 0xE7 0x03 0xC5 0x03 0xFF + 0x29 17 0xE8 0x00 0x00 0x00 0x09 0x00 + 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D + 0x00 0x79 0x00 0xA7 + 0x29 17 0xE9 0x00 0xCF 0x01 0x12 0x01 + 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED + 0x02 0x2F 0x02 0x74 + 0x29 17 0xEA 0x02 0x9F 0x02 0xD5 0x02 + 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73 + 0x03 0x8C 0x03 0xA5 + 0x29 5 0xEB 0x03 0xC5 0x03 0xFF + 0x29 4 0xB0 0x05 0x05 0x05 + 0x29 4 0xB1 0x05 0x05 0x05 + 0x29 4 0xB3 0x10 0x10 0x10 + 0x29 4 0xB4 0x06 0x06 0x06 + 0x29 4 0xB6 0x44 0x44 0x44 + 0x29 4 0xB7 0x34 0x34 0x34 + 0x29 4 0xB8 0x34 0x34 0x34 + 0x29 4 0xB9 0x24 0x24 0x24 + 0x29 4 0xBA 0x24 0x24 0x24 + 0x29 4 0xBC 0x00 0x70 0x00 + 0x29 4 0xBD 0x00 0x70 0x00 + 0x23 2 0xBE 0x50 + 0x23 2 0x35 0x00 + 0x13 1 0x11 + 0xfd 1 200 + 0x13 1 0x29 + 0xfd 1 200 + 0xFF 0>; /*ending*/ + init_off = < + 0x05 1 0x28 /* display off */ + 0xfd 1 10 /* delay 10ms */ + 0x05 1 0x10 /* sleep in */ + 0xfd 1 150 /* delay 150ms */ + 0xff 0>; /*ending*/ + }; + }; + + backlight{ + compatible = "amlogic, backlight-g12a"; + status = "okay"; + key_valid = <0>; + pinctrl-names = "pwm_on","pwm_off"; + /* pinctrl-0 = <&pwm_f_pins2>; */ + /* pinctrl-1 = <&bl_pwm_off_pins>; */ + pinctrl_version = <2>; /* for uboot */ + bl_pwm_config = <&bl_pwm_conf>; + /*bl-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_HIGH + &gpio GPIOH_5 GPIO_ACTIVE_HIGH>;*/ + bl_gpio_names = "GPIOH_4","GPIOH_5"; + + /* pwm port: PWM_A, PWM_B, PWM_C, PWM_D, PWM_E, PWM_F, PWM_VS*/ + /* power index:(point gpios_index, 0xff=invalid) + * power value:(0=output low, 1=output high, 2=input) + * power delay:(unit in ms) + */ + + backlight_0{ + index = <0>; + bl_name = "backlight_pwm"; + bl_level_default_uboot_kernel = <100 100>; + bl_level_attr = <255 10 /*max, min*/ + 128 128>; /*mid, mid_mapping*/ + bl_ctrl_method = <1>; /* 1=pwm, 2=pwm_combo, 4=extern */ + bl_power_attr = <0 /*en_gpio_index*/ + 1 0 /*on_value, off_value*/ + 200 200>; /*on_delay(ms), off_delay(ms)*/ + bl_pwm_port = "PWM_F"; + bl_pwm_attr = <0 /*pwm_method*/ + 180 /*pwm_freq(pwm:Hz, pwm_vs:multiple of vs)*/ + 100 25>; /*duty_max(%), duty_min(%)*/ + bl_pwm_power = <1 1 /*pwm_gpio_index, pwm_gpio_off*/ + 10 10>; /*pwm_on_delay(ms), pwm_off_delay(ms)*/ + bl_pwm_en_sequence_reverse = <0>; /* 1 for reverse */ + }; + backlight_1{ + index = <1>; + bl_name = "bl_extern"; + bl_level_default_uboot_kernel = <100 100>; + bl_level_attr = <255 10 /*max, min*/ + 128 128>; /*mid, mid_mapping*/ + bl_ctrl_method = <4>; /*1=pwm, 2=pwm_combo, 4=extern*/ + bl_power_attr = <1 /*en_gpio_index*/ + 1 0 /*on_value, off_value*/ + 200 200>; /*on_delay(ms), off_delay(ms)*/ + bl_extern_index = <0>; + }; + }; + bl_pwm_conf:bl_pwm_conf{ + pwm_channel_0 { + pwm_port_index = <5>; + pwms = <&pwm_ef MESON_PWM_1 30040 0>; + }; + }; + + bl_extern{ + compatible = "amlogic, bl_extern"; + status = "disabled"; + i2c_bus = "i2c_bus_3"; + + extern_0{ + index = <0>; + extern_name = "i2c_lp8556"; + type = <0>; /*0=i2c, 1=spi, 2=mipi*/ + i2c_address = <0x2c>; /*7bit i2c address*/ + dim_max_min = <255 10>; + }; + + extern_1{ + index = <1>; + extern_name = "mipi_lt070me05"; + type = <2>; /*0=i2c, 1=spi, 2=mipi*/ + dim_max_min = <255 10>; + }; + }; +};/* end of panel */ +
diff --git a/arch/arm/dts/meson-c-series.dtsi b/arch/arm/dts/meson-c-series.dtsi new file mode 100644 index 0000000..89b755d --- /dev/null +++ b/arch/arm/dts/meson-c-series.dtsi
@@ -0,0 +1,554 @@ +/* + * Copyright (c) 2016 Andreas Färber + * + * Copyright (c) 2016 BayLibre, SAS. + * Author: Neil Armstrong <narmstrong@baylibre.com> + * + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/pwm/pwm.h> +#include <dt-bindings/pwm/meson.h> +#include <dt-bindings/clock/c1-clkc.h> + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* 16 MiB reserved for Hardware ROM Firmware */ + hwrom_reserved: hwrom@0 { + reg = <0x0 0x0 0x0 0x1000000>; + no-map; + }; + + /* 2 MiB reserved for ARM Trusted Firmware (BL31) */ + secmon_reserved: secmon@10000000 { + reg = <0x0 0x10000000 0x0 0x200000>; + no-map; + }; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0xbc00000>; + alignment = <0x0 0x400000>; + linux,cma-default; + }; + }; + + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&l2>; + clocks = <&scpi_dvfs 0>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + next-level-cache = <&l2>; + clocks = <&scpi_dvfs 0>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x2>; + enable-method = "psci"; + next-level-cache = <&l2>; + clocks = <&scpi_dvfs 0>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x3>; + enable-method = "psci"; + next-level-cache = <&l2>; + clocks = <&scpi_dvfs 0>; + }; + + l2: l2-cache0 { + compatible = "cache"; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; + }; + + xtal: xtal-clk { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xtal"; + #clock-cells = <0>; + }; + + firmware { + sm: secure-monitor { + compatible = "amlogic,meson-gx-sm", "amlogic,meson-gxbb-sm"; + }; + }; + + efuse: efuse { + compatible = "amlogic,meson-gx-efuse", "amlogic,meson-gxbb-efuse"; + #address-cells = <1>; + #size-cells = <1>; + + sn: sn@14 { + reg = <0x14 0x10>; + }; + + eth_mac: eth_mac@34 { + reg = <0x34 0x10>; + }; + + bid: bid@46 { + reg = <0x46 0x30>; + }; + }; + + scpi { + compatible = "amlogic,meson-gxbb-scpi", "arm,scpi-pre-1.0"; + mboxes = <&mailbox 1 &mailbox 2>; + shmem = <&cpu_scp_lpri &cpu_scp_hpri>; + + scpi_clocks: clocks { + compatible = "arm,scpi-clocks"; + + scpi_dvfs: scpi_clocks@0 { + compatible = "arm,scpi-dvfs-clocks"; + #clock-cells = <1>; + clock-indices = <0>; + clock-output-names = "vcpu"; + }; + }; + + scpi_sensors: sensors { + compatible = "amlogic,meson-gxbb-scpi-sensors", "arm,scpi-sensors"; + #thermal-sensor-cells = <1>; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic: interrupt-controller@2c001000 { + compatible = "arm,gic-400"; + reg = <0x0 0xffc01000 0 0x1000>, + <0x0 0xffc02000 0 0x2000>, + <0x0 0xffc04000 0 0x2000>, + <0x0 0xffc06000 0 0x2000>; + interrupt-controller; + interrupts = <GIC_PPI 9 + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; + #interrupt-cells = <3>; + #address-cells = <0>; + }; + + sram: sram@fffa0000 { + compatible = "amlogic,meson-gx-sram", "amlogic,meson-gxbb-sram", "mmio-sram"; + reg = <0x0 0xfffa0000 0x0 0x48000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0xfffa0000 0x48000>; + + cpu_scp_lpri: scp-shmem@0 { + compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem"; + reg = <0x47000 0x400>; + }; + + cpu_scp_hpri: scp-shmem@200 { + compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem"; + reg = <0x47400 0x400>; + }; + }; + + cbus: cbus@fe000000 { + compatible = "simple-bus"; + reg = <0x0 0xfe000000 0x0 0x8000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x8000>; + + uart_a: serial@1c00 { + compatible = "amlogic,meson-uart"; + reg = <0x0 0x1c00 0x0 0x14>; + clocks = <&xtal>; + status = "disabled"; + }; + + uart_b: serial@2000 { + compatible = "amlogic,meson-uart"; + reg = <0x0 0x2000 0x0 0x14>; + clocks = <&xtal>; + status = "disabled"; + }; + + pwm_ab: pwm@2400 { + compatible = "amlogic,meson-v2-pwm"; + reg = <0x0 0x2400 0x0 0x20>, + <0x0 0x08c4 0x0 0x04>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm_cd: pwm@2800 { + compatible = "amlogic,meson-v2-pwm"; + reg = <0x0 0x2800 0x0 0x20>, + <0x0 0x08c8 0x0 0x04>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm_ef: pwm@5400 { + compatible = "amlogic,meson-v2-pwm"; + reg = <0x0 0x5400 0x0 0x20>, + <0x0 0x08cc 0x0 0x04>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm_gh: pwm@a400 { + compatible = "amlogic,meson-v2-pwm"; + reg = <0x0 0xa400 0x0 0x20>, + <0x0 0x0928 0x0 0x04>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm_ij: pwm@a800 { + compatible = "amlogic,meson-v2-pwm"; + reg = <0x0 0xa800 0x0 0x20>, + <0x0 0x092c 0x0 0x04>; + #pwm-cells = <3>; + status = "disabled"; + }; + + ir: ir@8040 { + compatible = "amlogic,meson-gx-ir", "amlogic,meson-gxbb-ir"; + reg = <0x0 0x8040 0x0 0x40>; + interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + }; + + reset: reset-controller@1000 { + compatible = "amlogic,meson-gx-reset", "amlogic,meson-gxbb-reset"; + reg = <0x0 0x01000 0x0 0x1000>; + #reset-cells = <1>; + }; + + uart_c: serial@22000 { + compatible = "amlogic,meson-uart"; + reg = <0x0 0x22000 0x0 0x18>; + interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>; + clocks = <&xtal>; + status = "disabled"; + }; + + spicc0: spi@3800 { + compatible = "amlogic,meson-g12a-spicc"; + reg = <0x0 0x3800 0x0 0x44>; + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spifc: spi@14000 { + compatible = "amlogic,spifc"; + reg = <0x0 0x14000 0x0 0x80>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + spi-flash@0 { + reg = <0>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + compatible = "spi-flash"; + status = "okay"; + }; + spi-nand@1 { + reg = <1>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + compatible = "spi-nand"; + status = "okay"; + }; + }; + + spicc1: spi@3c00 { + compatible = "amlogic,meson-g12a-spicc"; + reg = <0x0 0x3c00 0x0 0x44>; + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + watchdog@0f0d0 { + compatible = "amlogic,meson-a1-wdt"; + reg = <0x0 0x0f0d0 0x0 0x10>; + clocks = <&xtal>; + clock-names = "wdt-clk"; + }; + + jtag { + compatible = "amlogic, jtag"; + status = "okay"; + select = "disable"; /* disable/jtag-a/jtag-b/swd-a */ + pinctrl-names="jtag_a_pins", "jtag_b_pins", "swd_a_pins"; + pinctrl-0=<&jtag_a_pins>; + pinctrl-1=<&jtag_b_pins>; + pinctrl-2=<&swd_a_pins>; + }; + }; + + periphs: periphs@ff634000 { + compatible = "simple-bus"; + reg = <0x0 0xff634000 0x0 0x2000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>; + + hwrng: rng { + compatible = "amlogic,meson-rng"; + reg = <0x0 0x0 0x0 0x4>; + }; + }; + + hiubus: hiubus@ff63c000 { + compatible = "simple-bus"; + reg = <0x0 0xff63c000 0x0 0x2000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x2000>; + + mailbox: mailbox@404 { + compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu"; + reg = <0 0x404 0 0x4c>; + interrupts = <0 208 IRQ_TYPE_EDGE_RISING>, + <0 209 IRQ_TYPE_EDGE_RISING>, + <0 210 IRQ_TYPE_EDGE_RISING>; + #mbox-cells = <1>; + }; + }; + + clkc: clock-controller@0 { + compatible = "amlogic,c1-clkc"; + #clock-cells = <1>; + reg = <0x0 0xfe000800 0x0 0xe4>; + clocks = <&xtal>; + clock-names = "xtal"; + }; + + i2c0: i2c@fe001400 { + compatible = "amlogic,meson-i2c"; + reg = <0x0 0xfe001400 0x0 0x24>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@fe005c00 { + compatible = "amlogic,meson-i2c"; + reg = <0x0 0xfe005c00 0x0 0x3c>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@fe006800 { + compatible = "amlogic,meson-i2c"; + reg = <0x0 0xfe006800 0x0 0x3c>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@fe006c00 { + compatible = "amlogic,meson-i2c"; + reg = <0x0 0xfe006c00 0x0 0x3c>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@fe00b000 { + compatible = "amlogic,meson-i2c"; + reg = <0x0 0xfe00b000 0x0 0x3c>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + ethmac: ethernet@ff3f0000 { + compatible = "amlogic,g12a-eth-dwmac"; + phy_cntl1 = <0x41054147>; + pll_val = <0x9c0040a 0x927e0000 0xac5f49e5>; + analog_val = <0x20200000 0x0000c000 0x00000023>; + status = "disabled"; + }; + + saradc: adc@ff809000 { + compatible = "amlogic,meson-saradc"; + reg = <0x0 0xfe002c00 0x0 0x48>; + status = "disabled"; + }; + + nand: nfc@fe012800 { + compatible = "amlogic,meson-nfc"; + reg = <0x0 0xfe012800 0x0 0x200>; + interrupts = <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + clk_reg = <0 0xfe012000>; + }; + + apb: apb@fe000000 { + compatible = "simple-bus"; + reg = <0x0 0xfe000000 0x0 0x1000000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x1000000>; + + sd_emmc_a: sdio { + compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; + reg = <0x0 0x10000 0x0 0x800>; + interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + pinname = "sdio"; + }; + + sd_emmc_b: sd { + compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; + reg = <0x0 0x11000 0x0 0x800>; + interrupts = <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + pinname = "sd"; + }; + + sd_emmc_c: emmc { + compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; + reg = <0x0 0x12000 0x0 0x800>; + interrupts = <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + pinname = "emmc"; + }; + }; + + dwc3: dwc3@ff400000 { + compatible = "snps,dwc3","synopsys,xhci-dwc3"; + status = "disable"; + reg = <0x0 0xff400000 0x0 0x100000>; + phys = <&usb2_phy_v2>, <&usb3_phy_v2>; + phy-names = "usb2-phy", "usb3-phy"; + }; + + usb2_phy_v2: usb2phy@fe004420 { + compatible = "amlogic, amlogic-new-usb2-v2"; + status = "disable"; + #address-cells = <2>; + #size-cells = <2>; + phy-version = <2>; + reg = <0x0 0xfe004420 0x0 0x60 + 0x0 0xfe000004 0x0 0x100 + 0x0 0xfe004000 0x0 0x2000 + 0x0 0xfe0008dc 0x0 0x4>; + dwc2_a_reg = <0xff500000>; + #phy-cells = <0>; + }; + + usb3_phy_v2: usb3phy@fe004480 { + compatible = "amlogic, amlogic-new-usb3-v2"; + status = "disable"; + #address-cells = <2>; + #size-cells = <2>; + phy-version = <3>; + reg = <0x0 0xfe004480 0x0 0x20>; + #phy-cells = <0>; + }; + + }; +};
diff --git a/arch/arm/dts/meson-c1-c308x-ae400.dts b/arch/arm/dts/meson-c1-c308x-ae400.dts new file mode 100644 index 0000000..ca74dfc --- /dev/null +++ b/arch/arm/dts/meson-c1-c308x-ae400.dts
@@ -0,0 +1,83 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "meson-c1-c308x-ae400.dtsi" +#include "meson-c1_skt-panel.dtsi" + +/ { + compatible = "amlogic,ae400", "amlogic,c308x", "amlogic,meson-c1"; + model = "Amlogic Meson C1 AE400 Reference Board"; +}; + +/* This UART is brought out to the DB9 connector */ +&uart_a { + status = "okay"; +}; + +&uart_b { + status = "okay"; +}; + +&saradc { + status = "okay"; +}; + +/* demo for i2c user */ +&i2c3 { + status= "disabled"; + clock-frequency = <100000>; + /* pinctrl-names = "default";*/ + /* pinctrl-0 = <&i2c3_master_pins2>;*/ +}; + +&pinctrl_periphs { + bl_pwm_off_pins:bl_pwm_off_pin { + mux { + groups = "GPIOH_5"; + function = "gpio_periphs"; + output-high; + }; + }; +}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-c1-c308x-ae400.dtsi b/arch/arm/dts/meson-c1-c308x-ae400.dtsi new file mode 100644 index 0000000..a88346f --- /dev/null +++ b/arch/arm/dts/meson-c1-c308x-ae400.dtsi
@@ -0,0 +1,251 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>. + * Based on meson-gx-p23x-q20x.dtsi: + * - Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * - Copyright (c) 2016 BayLibre, SAS. + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +/* Common DTSI for devices which are based on the P212 reference board. */ + +#include "meson-c1-c308x.dtsi" + +/ { + aliases { + serial0 = &uart_b; + serial1 = &uart_a; + spi0 = &spifc; + spi1 = &spicc0; + spi2 = &spicc1; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + vddio_boot: regulator-vddio_boot { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vddio_ao18: regulator-vddio_ao18 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + /*reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;*/ + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; +}; + +ðmac { + status = "okay"; + internal_phy = <1>; + mc_val = <0x4be04>; + /*mc_val = <0x1621>;*/ +}; + +&ir { + status = "disabled"; + /* pinctrl-0 = <&remote_input_ao_pins>; */ + /* pinctrl-names = "default"; */ +}; + +&saradc { + status = "okay"; + vref-supply = <&vddio_ao18>; +}; + +/* Wireless SDIO Module */ +&sd_emmc_a { + status = "disabled"; + /*pinctrl-0 = <&sdio_pins>;*/ + /*pinctrl-names = "default";*/ + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + + non-removable; + disable-wp; + card_type = <3>; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_pins>; + pinctrl-1 = <&sdcard_pins &to_sduart_pins>; + pinctrl-names = "sd_all_pins", "sd_uart"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>; + cd-inverted; + + card_type = <5>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + hs_co_phase = <2>; + hs_tx_phase = <0>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-hs200-1_8v; + max-frequency = <200000000>; + non-removable; + disable-wp; + /* mmc-ddr-1_8v; */ + card_type = <1>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + hs_co_phase = <2>; + hs_tx_phase = <0>; + + hs2_co_phase = <2>; + hs2_tx_phase = <0>; + + hw_reset = <&gpio GPIOB_9 GPIO_ACTIVE_HIGH>; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* nand */ +&nand { + status = "okay"; + pinctrl-names = "default", "nand_cs_only"; + pinctrl-0 = <&all_nand_pins>; + pinctrl-1 = <&nand_cs_pins>; +}; + +&dwc3 { + status = "okay"; + dr_mode = "host"; +}; + +&usb2_phy_v2 { + status = "okay"; + portnum = <1>; +}; + +&usb3_phy_v2 { + status = "okay"; + portnum = <0>; + gpio-vbus-power = "GPIOD_9"; + gpios = <&gpio GPIOD_9 GPIO_ACTIVE_HIGH>; +}; + +&pwm_ef { + status = "okay"; + /* pinctrl-0 = <&pwm_e_pins>; */ + /* pinctrl-names = "default"; */ +}; + +/* This is connected to the Bluetooth module: */ +&uart_a { + status = "okay"; + /* pinctrl-0 = <&a_uart_pins>; */ + /* pinctrl-names = "default"; */ + uart-has-rtscts; +}; + +&spifc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spifc_pins>; + max-frequency = <24000000>; + max-cs = <2>; + /* 512M */ + clocks = <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_SPIFC_MUX>, + <&clkc CLKID_SPIFC_DIV>, + <&clkc CLKID_SPIFC_GATE>, + <&clkc CLKID_SPIFC_XTAL_GATE>; + clock-names = "fclk_source", "spifc_mux", "spifc_div", "spifc_gate", "spifc_xtal_gate"; +}; + +&spicc0 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc0_pins1>; + cs-gpios = <&gpio GPIOA_8 0>; +}; + +&spicc1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc1_pins1>; + cs-gpios = <&gpio GPIOA_14 0>; +};
diff --git a/arch/arm/dts/meson-c1-c308x-ae401.dts b/arch/arm/dts/meson-c1-c308x-ae401.dts new file mode 100644 index 0000000..6c5e195 --- /dev/null +++ b/arch/arm/dts/meson-c1-c308x-ae401.dts
@@ -0,0 +1,83 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "meson-c1-c308x-ae401.dtsi" +#include "meson-c1_skt-panel.dtsi" + +/ { + compatible = "amlogic,ae401", "amlogic,c308x", "amlogic,meson-c1"; + model = "Amlogic Meson C1 AE401 Reference Board"; +}; + +/* This UART is brought out to the DB9 connector */ +&uart_a { + status = "okay"; +}; + +&uart_b { + status = "okay"; +}; + +&saradc { + status = "okay"; +}; + +/* demo for i2c user */ +&i2c3 { + status= "disabled"; + clock-frequency = <100000>; + /* pinctrl-names = "default";*/ + /* pinctrl-0 = <&i2c3_master_pins2>;*/ +}; + +&pinctrl_periphs { + bl_pwm_off_pins:bl_pwm_off_pin { + mux { + groups = "GPIOH_5"; + function = "gpio_periphs"; + output-high; + }; + }; +}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-c1-c308x-ae401.dtsi b/arch/arm/dts/meson-c1-c308x-ae401.dtsi new file mode 100644 index 0000000..d742529 --- /dev/null +++ b/arch/arm/dts/meson-c1-c308x-ae401.dtsi
@@ -0,0 +1,292 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>. + * Based on meson-gx-p23x-q20x.dtsi: + * - Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * - Copyright (c) 2016 BayLibre, SAS. + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +/* Common DTSI for devices which are based on the P212 reference board. */ + +#include "meson-c1-c308x.dtsi" + +/ { + aliases { + serial0 = &uart_b; + serial1 = &uart_a; + spi0 = &spifc; + spi1 = &spicc0; + spi2 = &spicc1; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + vddio_boot: regulator-vddio_boot { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vddio_ao18: regulator-vddio_ao18 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + /*reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;*/ + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; +}; + +ðmac { + status = "okay"; + internal_phy = <1>; + mc_val = <0x4be04>; + /*mc_val = <0x1621>;*/ +}; + +&ir { + status = "disabled"; + /* pinctrl-0 = <&remote_input_ao_pins>; */ + /* pinctrl-names = "default"; */ +}; + +&saradc { + status = "okay"; + vref-supply = <&vddio_ao18>; +}; + +/* Wireless SDIO Module */ +&sd_emmc_a { + status = "disabled"; + /*pinctrl-0 = <&sdio_pins>;*/ + /*pinctrl-names = "default";*/ + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + + non-removable; + disable-wp; + card_type = <3>; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_pins>; + pinctrl-1 = <&sdcard_pins &to_sduart_pins>; + pinctrl-names = "sd_all_pins", "sd_uart"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>; + cd-inverted; + + card_type = <5>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + hs_co_phase = <2>; + hs_tx_phase = <0>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + //mmc-hs200-1_8v; + max-frequency = <50000000>; + non-removable; + disable-wp; + /* mmc-ddr-1_8v; */ + card_type = <1>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + hs_co_phase = <2>; + hs_tx_phase = <0>; + + hs2_co_phase = <2>; + hs2_tx_phase = <0>; + + hw_reset = <&gpio GPIOB_9 GPIO_ACTIVE_HIGH>; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* nand */ +&nand { + status = "okay"; + pinctrl-names = "default", "nand_cs_only"; + pinctrl-0 = <&all_nand_pins>; + pinctrl-1 = <&nand_cs_pins>; + + /* + #address-cells = <1>; + #size-cells = <0>; + + nand@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + nand-on-flash-bbt; + nand-ecc-mode = "hw"; + nand-ecc-strength = <8>; + nand-ecc-step-size = <1024>; + + meson-nand-user-mode = <2>; + meson-nand-ran-mode = <1>; + + partition@0 { + label = "boot"; + reg = <0x00000000 0x00200000>; + read-only; + }; + partition@200000 { + label = "env"; + reg = <0x00200000 0x00400000>; + }; + partition@600000 { + label = "system"; + reg = <0x00600000 0x00a00000>; + }; + partition@1000000 { + label = "rootfs"; + reg = <0x01000000 0x03000000>; + }; + partition@4000000 { + label = "media"; + reg = <0x04000000 0x8000000>; + }; + };*/ + +}; + +&dwc3 { + status = "okay"; + dr_mode = "host"; +}; + +&usb2_phy_v2 { + status = "okay"; + portnum = <1>; +}; + +&usb3_phy_v2 { + status = "okay"; + portnum = <0>; + gpio-vbus-power = "GPIOD_9"; + gpios = <&gpio GPIOD_9 GPIO_ACTIVE_HIGH>; +}; + +&pwm_ef { + status = "okay"; + /* pinctrl-0 = <&pwm_e_pins>; */ + /* pinctrl-names = "default"; */ +}; + +/* This is connected to the Bluetooth module: */ +&uart_a { + status = "okay"; + /* pinctrl-0 = <&a_uart_pins>; */ + /* pinctrl-names = "default"; */ + uart-has-rtscts; +}; + +&spifc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spifc_pins>; + max-frequency = <24000000>; + max-cs = <2>; + /* 512M */ + clocks = <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_SPIFC_MUX>, + <&clkc CLKID_SPIFC_DIV>, + <&clkc CLKID_SPIFC_GATE>, + <&clkc CLKID_SPIFC_XTAL_GATE>; + clock-names = "fclk_source", "spifc_mux", "spifc_div", "spifc_gate", "spifc_xtal_gate"; +}; + +&spicc0 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc0_pins1>; + cs-gpios = <&gpio GPIOA_8 0>; +}; + +&spicc1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc1_pins1>; + cs-gpios = <&gpio GPIOA_14 0>; +};
diff --git a/arch/arm/dts/meson-c1-c308x-ae402.dts b/arch/arm/dts/meson-c1-c308x-ae402.dts new file mode 100644 index 0000000..2fb0f98 --- /dev/null +++ b/arch/arm/dts/meson-c1-c308x-ae402.dts
@@ -0,0 +1,83 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "meson-c1-c308x-ae402.dtsi" +#include "meson-c1_skt-panel.dtsi" + +/ { + compatible = "amlogic,ae402", "amlogic,c308x", "amlogic,meson-c1"; + model = "Amlogic Meson C1 AE402 Reference Board"; +}; + +/* This UART is brought out to the DB9 connector */ +&uart_a { + status = "okay"; +}; + +&uart_b { + status = "okay"; +}; + +&saradc { + status = "okay"; +}; + +/* demo for i2c user */ +&i2c3 { + status= "disabled"; + clock-frequency = <100000>; + /* pinctrl-names = "default";*/ + /* pinctrl-0 = <&i2c3_master_pins2>;*/ +}; + +&pinctrl_periphs { + bl_pwm_off_pins:bl_pwm_off_pin { + mux { + groups = "GPIOH_5"; + function = "gpio_periphs"; + output-high; + }; + }; +}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-c1-c308x-ae402.dtsi b/arch/arm/dts/meson-c1-c308x-ae402.dtsi new file mode 100644 index 0000000..43c7b60 --- /dev/null +++ b/arch/arm/dts/meson-c1-c308x-ae402.dtsi
@@ -0,0 +1,292 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>. + * Based on meson-gx-p23x-q20x.dtsi: + * - Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * - Copyright (c) 2016 BayLibre, SAS. + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +/* Common DTSI for devices which are based on the P212 reference board. */ + +#include "meson-c1-c308x.dtsi" + +/ { + aliases { + serial0 = &uart_b; + serial1 = &uart_a; + spi0 = &spifc; + spi1 = &spicc0; + spi2 = &spicc1; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x20000000>; + }; + + vddio_boot: regulator-vddio_boot { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vddio_ao18: regulator-vddio_ao18 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + /*reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;*/ + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; +}; + +ðmac { + status = "okay"; + internal_phy = <1>; + mc_val = <0x4be04>; + /*mc_val = <0x1621>;*/ +}; + +&ir { + status = "disabled"; + /* pinctrl-0 = <&remote_input_ao_pins>; */ + /* pinctrl-names = "default"; */ +}; + +&saradc { + status = "okay"; + vref-supply = <&vddio_ao18>; +}; + +/* Wireless SDIO Module */ +&sd_emmc_a { + status = "disabled"; + /*pinctrl-0 = <&sdio_pins>;*/ + /*pinctrl-names = "default";*/ + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + + non-removable; + disable-wp; + card_type = <3>; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_pins>; + pinctrl-1 = <&sdcard_pins &to_sduart_pins>; + pinctrl-names = "sd_all_pins", "sd_uart"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>; + cd-inverted; + + card_type = <5>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + hs_co_phase = <2>; + hs_tx_phase = <0>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + //mmc-hs200-1_8v; + max-frequency = <50000000>; + non-removable; + disable-wp; + /* mmc-ddr-1_8v; */ + card_type = <1>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + hs_co_phase = <2>; + hs_tx_phase = <0>; + + hs2_co_phase = <2>; + hs2_tx_phase = <0>; + + hw_reset = <&gpio GPIOB_9 GPIO_ACTIVE_HIGH>; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* nand */ +&nand { + status = "okay"; + pinctrl-names = "default", "nand_cs_only"; + pinctrl-0 = <&all_nand_pins>; + pinctrl-1 = <&nand_cs_pins>; + + /* + #address-cells = <1>; + #size-cells = <0>; + + nand@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + nand-on-flash-bbt; + nand-ecc-mode = "hw"; + nand-ecc-strength = <8>; + nand-ecc-step-size = <1024>; + + meson-nand-user-mode = <2>; + meson-nand-ran-mode = <1>; + + partition@0 { + label = "boot"; + reg = <0x00000000 0x00200000>; + read-only; + }; + partition@200000 { + label = "env"; + reg = <0x00200000 0x00400000>; + }; + partition@600000 { + label = "system"; + reg = <0x00600000 0x00a00000>; + }; + partition@1000000 { + label = "rootfs"; + reg = <0x01000000 0x03000000>; + }; + partition@4000000 { + label = "media"; + reg = <0x04000000 0x8000000>; + }; + };*/ + +}; + +&dwc3 { + status = "okay"; + dr_mode = "host"; +}; + +&usb2_phy_v2 { + status = "okay"; + portnum = <1>; +}; + +&usb3_phy_v2 { + status = "okay"; + portnum = <0>; + gpio-vbus-power = "GPIOD_9"; + gpios = <&gpio GPIOD_9 GPIO_ACTIVE_HIGH>; +}; + +&pwm_ef { + status = "okay"; + /* pinctrl-0 = <&pwm_e_pins>; */ + /* pinctrl-names = "default"; */ +}; + +/* This is connected to the Bluetooth module: */ +&uart_a { + status = "okay"; + /* pinctrl-0 = <&a_uart_pins>; */ + /* pinctrl-names = "default"; */ + uart-has-rtscts; +}; + +&spifc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spifc_pins>; + max-frequency = <24000000>; + max-cs = <2>; + /* 512M */ + clocks = <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_SPIFC_MUX>, + <&clkc CLKID_SPIFC_DIV>, + <&clkc CLKID_SPIFC_GATE>, + <&clkc CLKID_SPIFC_XTAL_GATE>; + clock-names = "fclk_source", "spifc_mux", "spifc_div", "spifc_gate", "spifc_xtal_gate"; +}; + +&spicc0 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc0_pins1>; + cs-gpios = <&gpio GPIOA_8 0>; +}; + +&spicc1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc1_pins1>; + cs-gpios = <&gpio GPIOA_14 0>; +};
diff --git a/arch/arm/dts/meson-c1-c308x-ae409.dts b/arch/arm/dts/meson-c1-c308x-ae409.dts new file mode 100644 index 0000000..ef6479b --- /dev/null +++ b/arch/arm/dts/meson-c1-c308x-ae409.dts
@@ -0,0 +1,83 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "meson-c1-c308x-ae409.dtsi" +#include "meson-c1_skt-panel.dtsi" + +/ { + compatible = "amlogic,ae409", "amlogic,c308x", "amlogic,meson-c1"; + model = "Amlogic Meson C1 AE409 Socket Board"; +}; + +/* This UART is brought out to the DB9 connector */ +&uart_a { + status = "okay"; +}; + +&uart_b { + status = "okay"; +}; + +&saradc { + status = "okay"; +}; + +/* demo for i2c user */ +&i2c3 { + status= "disabled"; + clock-frequency = <100000>; + /* pinctrl-names = "default";*/ + /* pinctrl-0 = <&i2c3_master_pins2>;*/ +}; + +&pinctrl_periphs { + bl_pwm_off_pins:bl_pwm_off_pin { + mux { + groups = "GPIOH_5"; + function = "gpio_periphs"; + output-high; + }; + }; +}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-c1-c308x-ae409.dtsi b/arch/arm/dts/meson-c1-c308x-ae409.dtsi new file mode 100644 index 0000000..18554d9 --- /dev/null +++ b/arch/arm/dts/meson-c1-c308x-ae409.dtsi
@@ -0,0 +1,251 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>. + * Based on meson-gx-p23x-q20x.dtsi: + * - Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * - Copyright (c) 2016 BayLibre, SAS. + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +/* Common DTSI for devices which are based on the P212 reference board. */ + +#include "meson-c1-c308x.dtsi" + +/ { + aliases { + serial0 = &uart_b; + serial1 = &uart_a; + spi0 = &spifc; + spi1 = &spicc0; + spi2 = &spicc1; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + vddio_boot: regulator-vddio_boot { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vddio_ao18: regulator-vddio_ao18 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + /*reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;*/ + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; +}; + +ðmac { + status = "okay"; + internal_phy = <1>; + mc_val = <0x4be04>; + /*mc_val = <0x1621>;*/ +}; + +&ir { + status = "disabled"; + /* pinctrl-0 = <&remote_input_ao_pins>; */ + /* pinctrl-names = "default"; */ +}; + +&saradc { + status = "okay"; + vref-supply = <&vddio_ao18>; +}; + +/* Wireless SDIO Module */ +&sd_emmc_a { + status = "disabled"; + /*pinctrl-0 = <&sdio_pins>;*/ + /*pinctrl-names = "default";*/ + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + + non-removable; + disable-wp; + card_type = <3>; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_pins>; + pinctrl-1 = <&sdcard_pins &to_sduart_pins>; + pinctrl-names = "sd_all_pins", "sd_uart"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>; + cd-inverted; + + card_type = <5>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + hs_co_phase = <2>; + hs_to_phase = <0>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-hs200-1_8v; + max-frequency = <200000000>; + non-removable; + disable-wp; + /* mmc-ddr-1_8v; */ + card_type = <1>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + hs_co_phase = <2>; + hs_to_phase = <0>; + + hs2_co_phase = <2>; + hs2_to_phase = <0>; + + hw_reset = <&gpio GPIOB_9 GPIO_ACTIVE_HIGH>; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* nand */ +&nand { + status = "okay"; + pinctrl-names = "default", "nand_cs_only"; + pinctrl-0 = <&all_nand_pins>; + pinctrl-1 = <&nand_cs_pins>; +}; + +&dwc3 { + status = "okay"; + dr_mode = "host"; +}; + +&usb2_phy_v2 { + status = "okay"; + portnum = <1>; +}; + +&usb3_phy_v2 { + status = "okay"; + portnum = <0>; + gpio-vbus-power = "GPIOD_9"; + gpios = <&gpio GPIOD_9 GPIO_ACTIVE_HIGH>; +}; + +&pwm_ef { + status = "okay"; + /* pinctrl-0 = <&pwm_e_pins>; */ + /* pinctrl-names = "default"; */ +}; + +/* This is connected to the Bluetooth module: */ +&uart_a { + status = "okay"; + /* pinctrl-0 = <&a_uart_pins>; */ + /* pinctrl-names = "default"; */ + uart-has-rtscts; +}; + +&spifc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spifc_pins>; + max-frequency = <24000000>; + max-cs = <2>; + /* 512M */ + clocks = <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_SPIFC_MUX>, + <&clkc CLKID_SPIFC_DIV>, + <&clkc CLKID_SPIFC_GATE>, + <&clkc CLKID_SPIFC_XTAL_GATE>; + clock-names = "fclk_source", "spifc_mux", "spifc_div", "spifc_gate", "spifc_xtal_gate"; +}; + +&spicc0 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc0_pins1>; + cs-gpios = <&gpio GPIOA_8 0>; +}; + +&spicc1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc1_pins1>; + cs-gpios = <&gpio GPIOA_14 0>; +};
diff --git a/arch/arm/dts/meson-c1-c308x.dtsi b/arch/arm/dts/meson-c1-c308x.dtsi new file mode 100644 index 0000000..644bb4b --- /dev/null +++ b/arch/arm/dts/meson-c1-c308x.dtsi
@@ -0,0 +1,54 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "meson-c1.dtsi" +#include "meson-c1-mali.dtsi" + +/ { + compatible = "amlogic,c308x", "amlogic,meson-c1"; +}; + +ðmac { + phy-mode = "rmii"; + phy-handle = <&internal_phy>; +};
diff --git a/arch/arm/dts/meson-c1-mali.dtsi b/arch/arm/dts/meson-c1-mali.dtsi new file mode 100644 index 0000000..2655b42 --- /dev/null +++ b/arch/arm/dts/meson-c1-mali.dtsi
@@ -0,0 +1,43 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 BayLibre SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +&apb { + mali: gpu@40000 { + compatible = "amlogic,meson-gxbb-mali", "arm,mali-450"; + reg = <0x0 0x40000 0x0 0x40000>; + interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "gp", "gpmmu", "pp", "pmu", + "pp0", "ppmmu0", "pp1", "ppmmu1", + "pp2", "ppmmu2"; + /*clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;*/ + clock-names = "bus", "core"; + + /* + * Mali clocking is provided by two identical clock paths + * MALI_0 and MALI_1 muxed to a single clock by a glitch + * free mux to safely change frequency while running. + */ + /* + assigned-clocks = <&clkc CLKID_MALI_0_SEL>, + <&clkc CLKID_MALI_0>, + <&clkc CLKID_MALI>; *//* Glitch free mux */ + /*assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, + <0>, *//* Do Nothing */ + //<&clkc CLKID_MALI_0>; + /*assigned-clock-rates = <0>,*/ /* Do Nothing */ + /* <666666666>, + <0>;*/ /* Do Nothing */ + }; +};
diff --git a/arch/arm/dts/meson-c1.dtsi b/arch/arm/dts/meson-c1.dtsi new file mode 100644 index 0000000..cc3138c --- /dev/null +++ b/arch/arm/dts/meson-c1.dtsi
@@ -0,0 +1,711 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "meson-c-series.dtsi" +#include <dt-bindings/gpio/meson-c1-gpio.h> +#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h> + +/ { + compatible = "amlogic,meson-c1"; + + vpu { + compatible = "amlogic, vpu-g12a"; + status = "okay"; + /*clocks = <&clkc CLKID_VAPB_MUX>, + * <&clkc CLKID_VPU_INTR>, + * <&clkc CLKID_VPU_P0_COMP>, + * <&clkc CLKID_VPU_P1_COMP>, + * <&clkc CLKID_VPU_MUX>; + *clock-names = "vapb_clk", + * "vpu_intr_gate", + * "vpu_clk0", + * "vpu_clk1", + * "vpu_clk"; + */ + clk_level = <7>; + /* 0: 100.0M 1: 166.7M 2: 200.0M 3: 250.0M */ + /* 4: 333.3M 5: 400.0M 6: 500.0M 7: 666.7M */ + }; + + meson-fb { + status = "okay"; + logo_addr = "0x7f800000"; + }; +}; + +ðmac { + compatible = "amlogic,g12a-eth-dwmac"; + reg = <0x0 0xff080000 0x0 0x10000 + 0x0 0xFE009000 0x0 0x8 + 0x0 0xFE009400 0x0 0xa0>; + reg-names = "eth_base", "eth_top", "eth_cfg"; + phy_cntl1 = <0x41054147>; + internal_phy = <1>; + mc_val = <0x4be04>; + pll_val = <0x9c0040a 0x927e0000 0xac5f49e5>; + analog_val = <0x20200000 0x0000c000 0x00000023>; + tx_amp_src = <0xfe005b30>; +// clocks = <&clkc CLKID_ETH_CORE>, +// <&clkc CLKID_FCLK_DIV2>, +// <&clkc CLKID_MPLL2>; +// clock-names = "stmmaceth", "clkin0", "clkin1"; + + mdio0: mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + }; +}; + +&cbus { + pinctrl_periphs: pinctrl@0400 { + compatible = "amlogic,meson-c1-periphs-pinctrl"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio: bank@0400 { + reg = <0x0 0x0400 0x0 0x0040>, + <0x0 0x0480 0x0 0x01d8>; + reg-names = "mux", + "gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_periphs 0 0 90>; + }; + }; +}; + +&periphs { + + eth-phy-mux { + compatible = "mdio-mux-mmioreg", "mdio-mux"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x15c 0x0 0x4>; + mux-mask = <0xffffffff>; + mdio-parent-bus = <&mdio0>; + + internal_mdio: mdio@e40908ff { + reg = <0xe40908ff>; + #address-cells = <1>; + #size-cells = <0>; + + internal_phy: ethernet-phy@8 { + compatible = "ethernet-phy-id0181.4400", "ethernet-phy-ieee802.3-c22"; + reg = <8>; + max-speed = <100>; + }; + }; + + external_mdio: mdio@2009087f { + reg = <0x2009087f>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&saradc { + compatible = "amlogic,meson-g12a-saradc", "amlogic,meson-saradc"; + clocks = <&xtal>, + <&clkc CLKID_SARADC_MUX>, + <&clkc CLKID_SARADC_DIV>, + <&clkc CLKID_SAR_ADC_GATE>; + clock-names = "xtal", "adc_mux", "adc_div", "adc_gate"; +}; + +&sd_emmc_a { + clocks = <&clkc CLKID_SD_EMMC_A_MUX>, + <&clkc CLKID_SD_EMMC_A_DIV>, + <&clkc CLKID_SD_EMMC_A_GATE>, + <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_SD_EMMC_A_XTAL_GATE>; + clock-names = "mux", "div", "gate", "clkin", "xtal"; +}; + +&sd_emmc_b { + clocks = <&clkc CLKID_SD_EMMC_B_MUX>, + <&clkc CLKID_SD_EMMC_B_DIV>, + <&clkc CLKID_SD_EMMC_B_GATE>, + <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_SD_EMMC_B_XTAL_GATE>; + clock-names = "mux", "div", "gate", "clkin", "xtal"; +}; + +&sd_emmc_c { + clocks = <&clkc CLKID_SD_EMMC_C_MUX>, + <&clkc CLKID_SD_EMMC_C_DIV>, + <&clkc CLKID_SD_EMMC_C_GATE>, + <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_SD_EMMC_C_XTAL_GATE>; + clock-names = "mux", "div", "gate", "clkin", "xtal"; +}; + +&nand { + clocks = <&clkc CLKID_SD_EMMC_C_MUX>, + <&clkc CLKID_SD_EMMC_C_DIV>, + <&clkc CLKID_SD_EMMC_C_GATE>, + <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_SD_EMMC_C_XTAL_GATE>; + clock-names = "mux", "div", "gate", "fdiv2", "xtal"; +}; + +&spicc0 { + clocks = <&clkc CLKID_SPICC_A_DIV>, <&clkc CLKID_SPICC_A_GATE>; + clock-names = "async", "async-gate"; + assigned-clocks = <&clkc CLKID_SPICC_A_MUX>, <&clkc CLKID_SPICC_A_DIV>; + assigned-clock-parents = <&clkc CLKID_FCLK_DIV2>; + assigned-clock-rates = <0>, <200000000>; + /* =PM_SPICC, no set for power on already */ + /* pm-id = <22>; */ +}; + +&spicc1 { + clocks = <&clkc CLKID_SPICC_B_DIV>, <&clkc CLKID_SPICC_B_GATE>; + clock-names = "async", "async-gate"; + assigned-clocks = <&clkc CLKID_SPICC_B_MUX>, <&clkc CLKID_SPICC_B_DIV>; + assigned-clock-parents = <&clkc CLKID_FCLK_DIV2>; + assigned-clock-rates = <0>, <200000000>; + /* =PM_SPICC_B, must set to power on */ + pm-id = <39>; +}; + +&pinctrl_periphs { + jtag_a_pins:jtag_a_pin { + mux { + groups = "jtag_a_clk", + "jtag_a_tms", + "jtag_a_tdi", + "jtag_a_tdo"; + function = "jtag_a"; + }; + }; + + jtag_b_pins:jtag_b_pin { + mux { + groups = "jtag_b_clk", + "jtag_b_tms", + "jtag_b_tdi", + "jtag_b_tdo"; + function = "jtag_b"; + }; + }; + + swd_a_pins:swd_a_pin { + mux { + groups = "swclk", + "swdio"; + function = "sw"; + }; + }; + + /*i2c0 pinmux*/ + i2c0_master_pins1:i2c0_pins1 { + mux { + groups = "i2c_a_scl_d", + "i2c_a_sda_d"; + function = "i2c_a"; + bias-pull-up; + drive-strength = <3>; + }; + }; + + i2c0_master_pins2:i2c0_pins2 { + mux { + groups = "i2c_a_scl_e", + "i2c_a_sda_e"; + function = "i2c_a"; + bias-pull-up; + drive-strength = <3>; + }; + }; + + /* i2c1 pinmux */ + i2c1_master_pins1:i2c1_pins1 { + mux { + groups = "i2c_b_scl_x", + "i2c_b_sda_x"; + function = "i2c_b"; + bias-pull-up; + drive-strength = <3>; + }; + }; + + i2c1_master_pins2:i2c1_pins2 { + mux { + groups = "i2c_b_scl_a", + "i2c_b_sda_a"; + function = "i2c_b"; + bias-pull-up; + drive-strength = <3>; + }; + }; + + i2c1_master_pins3:i2c1_pins3 { + mux { + groups = "i2c_b_scl_m", + "i2c_b_sda_m"; + function = "i2c_b"; + bias-pull-up; + drive-strength = <3>; + }; + }; + + /* i2c2 pinmux */ + i2c2_master_pins1:i2c2_pins1 { + mux { + groups = "i2c_c_scl_x", + "i2c_c_sda_x"; + function = "i2c_c"; + bias-pull-up; + drive-strength = <3>; + }; + }; + + i2c2_master_pins2:i2c2_pins2 { + mux { + groups = "i2c_c_scl_m", + "i2c_c_sda_m"; + function = "i2c_c"; + bias-pull-up; + drive-strength = <3>; + }; + }; + + i2c2_master_pins3:i2c2_pins3 { + mux { + groups = "i2c_c_scl_a", + "i2c_c_sda_a"; + function = "i2c_c"; + bias-pull-up; + drive-strength = <3>; + }; + }; + + /* i2c3 pinmux */ + i2c3_master_pins1:i2c3_pins1 { + mux { + groups = "i2c_d_scl_x", + "i2c_d_sda_x"; + function = "i2c_d"; + bias-pull-up; + drive-strength = <3>; + }; + }; + + i2c3_master_pins2:i2c3_pins2 { + mux { + groups = "i2c_d_scl_a", + "i2c_d_sda_a"; + function = "i2c_d"; + bias-pull-up; + drive-strength = <3>; + }; + }; + + i2c3_master_pins3:i2c3_pins3 { + mux { + groups = "i2c_d_scl_m", + "i2c_d_sda_m"; + function = "i2c_d"; + bias-pull-up; + drive-strength = <3>; + }; + }; + + /* i2c4 pinmux */ + i2c4_master_pins1:i2c4_pins1 { + mux { + groups = "i2c_e_scl_c", + "i2c_e_sda_c"; + function = "i2c_e"; + bias-pull-up; + drive-strength = <3>; + }; + }; + + i2c4_master_pins2:i2c4_pins2 { + mux { + groups = "i2c_e_scl_m", + "i2c_e_sda_m"; + function = "i2c_e"; + bias-pull-up; + drive-strength = <3>; + }; + }; + + i2c4_master_pins3:i2c4_pins3 { + mux { + groups = "i2c_e_scl_a", + "i2c_e_sda_a"; + function = "i2c_e"; + bias-pull-up; + drive-strength = <3>; + }; + }; + + pwm_a_pins1: pwm_a_pins1 { + mux { + groups = "pwm_a"; + function = "pwm_a"; + }; + }; + + pwm_b_pins1: pwm_b_pins1 { + mux { + groups = "pwm_b"; + function = "pwm_b"; + }; + }; + + pwm_c_pins1: pwm_c_pins1 { + mux { + groups = "pwm_c"; + function = "pwm_c"; + }; + }; + + pwm_d_pins1: pwm_d_pins1 { + mux { + groups = "pwm_d"; + function = "pwm_d"; + }; + }; + + pwm_e_pins1: pwm_e_pins1 { + mux { + groups = "pwm_e"; + function = "pwm_e"; + }; + }; + + pwm_f_pins1: pwm_f_pins1 { + mux { + groups = "pwm_f_d"; + function = "pwm_f"; + }; + }; + + pwm_f_pins2: pwm_f_pins2 { + mux { + groups = "pwm_f_m"; + function = "pwm_f"; + }; + }; + + pwm_f_pins3: pwm_f_pins3 { + mux { + groups = "pwm_f_x"; + function = "pwm_f"; + }; + }; + + pwm_g_pins1: pwm_g_pins1 { + mux { + groups = "pwm_g_d"; + function = "pwm_g"; + }; + }; + + pwm_g_pins2: pwm_g_pins2 { + mux { + groups = "pwm_g_x"; + function = "pwm_g"; + }; + }; + + pwm_g_pins3: pwm_g_pins3 { + mux { + groups = "pwm_g_m"; + function = "pwm_g"; + }; + }; + + pwm_g_pins4: pwm_g_pins4 { + mux { + groups = "pwm_g_a7"; + function = "pwm_g"; + }; + }; + + pwm_g_pins5: pwm_g_pins5 { + mux { + groups = "pwm_g_a1"; + function = "pwm_g"; + }; + }; + + pwm_h_pins1: pwm_h_pins1 { + mux { + groups = "pwm_h_x"; + function = "pwm_h"; + }; + }; + + pwm_h_pins2: pwm_h_pins2 { + mux { + groups = "pwm_h_m"; + function = "pwm_h"; + }; + }; + + pwm_h_pins3: pwm_h_pins3 { + mux { + groups = "pwm_h_a8"; + function = "pwm_h"; + }; + }; + + pwm_h_pins4: pwm_h_pins4 { + mux { + groups = "pwm_h_a2"; + function = "pwm_h"; + }; + }; + + pwm_i_pins1: pwm_i_pins1 { + mux { + groups = "pwm_i_x"; + function = "pwm_i"; + }; + }; + + pwm_i_pins2: pwm_i_pins2 { + mux { + groups = "pwm_i_m"; + function = "pwm_i"; + }; + }; + + pwm_i_pins3: pwm_i_pins3 { + mux { + groups = "pwm_i_a9"; + function = "pwm_i"; + }; + }; + + pwm_i_pins4: pwm_i_pins4 { + mux { + groups = "pwm_i_a3"; + function = "pwm_i"; + }; + }; + + pwm_j_pins1: pwm_j_pins1 { + mux { + groups = "pwm_j_x"; + function = "pwm_j"; + }; + }; + + pwm_j_pins2: pwm_j_pins2 { + mux { + groups = "pwm_j_m"; + function = "pwm_j"; + }; + }; + + pwm_j_pins3: pwm_j_pins3 { + mux { + groups = "pwm_j_a10"; + function = "pwm_j"; + }; + }; + + pwm_j_pins4: pwm_j_pins4 { + mux { + groups = "pwm_j_a4"; + function = "pwm_j"; + }; + }; + + emmc_pins: emmc { + mux { + groups = "emmc_nand_d0", + "emmc_nand_d1", + "emmc_nand_d2", + "emmc_nand_d3", + "emmc_nand_d4", + "emmc_nand_d5", + "emmc_nand_d6", + "emmc_nand_d7", + "emmc_clk", + "emmc_cmd"; + function = "emmc"; + bias-pull-up; + input-enable; + }; + mux1 { + groups = "emmc_nand_ds"; + function = "emmc"; + input-enable; + bias-pull-down; + }; + }; + + emmc_clk_gate_pins: emmc_clk_gate { + mux { + groups = "emmc_clk"; + function = "emmc"; + bias-pull-down; + }; + }; + + all_nand_pins: all_nand_pins { + mux { + groups = "emmc_nand_d0", + "emmc_nand_d1", + "emmc_nand_d2", + "emmc_nand_d3", + "emmc_nand_d4", + "emmc_nand_d5", + "emmc_nand_d6", + "emmc_nand_d7", + "nand_ce0", + "nand_ale", + "nand_cle", + "nand_wen_clk", + "nand_ren_wr"; + function = "nand"; + input-enable; + }; + }; + + nand_cs_pins: nand_cs { + mux { + groups = "nand_ce0"; + function = "nand"; + }; + }; + + sdcard_pins: sdcard { + mux { + groups = "sdcard_d0", + "sdcard_d1", + "sdcard_d2", + "sdcard_d3", + "sdcard_cmd"; + function = "sdcard"; + bias-pull-up; + input-enable; + drive-strength = <4>; + }; + mux1 { + groups ="sdcard_clk"; + function = "sdcard"; + bias-pull-up; + output-high; + drive-strength = <4>; + }; + }; + + sdcard_clk_gate_pins: sdcard_clk_gate { + mux { + groups = "sdcard_clk"; + function = "sdcard"; + bias-pull-down; + }; + }; + + to_sduart_pins: to_sduart_pins{ + mux { + groups = "uart_b_rx_c", "uart_b_tx_c"; + function = "uart_b"; + bias-pull-up; + input-enable; + }; + }; + + sd_to_uart_pins: sd_to_uart_pins{ + mux { + groups = "uart_b_rx_d", "uart_b_tx_d"; + function = "uart_b"; + bias-pull-up; + input-enable; + }; + }; + + spicc0_pins1: spicc0_pins1 { + mux { + groups = "spi_a_mosi_a", + "spi_a_miso_a", + "spi_a_sclk_a"; + function = "spi_a"; + drive-strength = <2>; + }; + }; + + spicc0_pins2: spicc0_pins2 { + mux { + groups = "spi_a_mosi_c", + "spi_a_miso_c", + "spi_a_sclk_c"; + function = "spi_a"; + drive-strength = <2>; + }; + }; + + spicc1_pins1: spicc1_pins1 { + mux { + groups = "spi_b_mosi_a", + "spi_b_miso_a", + "spi_b_sclk_a"; + function = "spi_b"; + drive-strength = <2>; + }; + }; + + spifc_pins: spifc_pins { + mux { + groups = "spif_mo", + "spif_mi", + "spif_clk", + "spif_cs", + "spif_hold", + "spif_wp_n"; + function = "spif"; + drive-strength = <3>; + }; + }; +};
diff --git a/arch/arm/dts/meson-c1_skt-panel.dtsi b/arch/arm/dts/meson-c1_skt-panel.dtsi new file mode 100644 index 0000000..fbb676c --- /dev/null +++ b/arch/arm/dts/meson-c1_skt-panel.dtsi
@@ -0,0 +1,742 @@ +/* + * arch/arm64/boot/dts/amlogic/mesong12a_skt-panel.dtsi + * + * Copyright (C) 2016 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/ { + lcd{ + compatible = "amlogic, lcd-g12a"; + mode = "tablet"; + status = "okay"; + key_valid = <0>; + /* + clocks = <&clkc CLKID_MIPI_DSI_HOST + &clkc CLKID_MIPI_DSI_PHY + &clkc CLKID_DSI_MEAS_COMP + &clkc CLKID_VCLK2_ENCL + &clkc CLKID_VCLK2_VENCL + &clkc CLKID_GP0_PLL>; + clock-names = "dsi_host_gate", + "dsi_phy_gate", + "dsi_meas", + "encl_top_gate", + "encl_int_gate", + "gp0_pll"; + */ + reg = <0x0 0xffd07000 0x0 0x400 /* dsi_host */ + 0x0 0xff644000 0x0 0x200>; /* dsi_phy */ + interrupts = <0 3 1 + 0 56 1>; + interrupt-names = "vsync","vsync2"; + pinctrl_version = <2>; /* for uboot */ + + /* power type: + * (0=cpu_gpio, 1=pmu_gpio, 2=signal,3=extern, 0xff=ending) + * power index: + * (point gpios_index, or extern_index,0xff=invalid) + * power value:(0=output low, 1=output high, 2=input) + * power delay:(unit in ms) + */ + + /*lcd_cpu-gpios = <&gpio GPIOZ_9 GPIO_ACTIVE_HIGH + &gpio GPIOZ_8 GPIO_ACTIVE_HIGH>; + */ + lcd_cpu_gpio_names = "GPIOZ_9","GPIOZ_8"; + + lcd_0{ + model_name = "B080XAN01"; + interface = "mipi"; + basic_setting = <768 1024 /*h_active, v_active*/ + 948 1140 /*h_period, v_period*/ + 8 /*lcd_bits*/ + 119 159>; /*screen_widht, screen_height*/ + lcd_timing = <64 56 0 /*hs_width, hs_bp, hs_pol*/ + 50 30 0>; /*vs_width, vs_bp, vs_pol*/ + clk_attr = <0 /*fr_adj_type(0=clk, 1=htotal, 2=vtotal)*/ + 0 /*clk_ss_level */ + 1 /*clk_auto_generate*/ + 64843200>; /*pixel_clk(unit in Hz)*/ + mipi_attr = <4 /*lane_num*/ + 550 /*bit_rate_max(MHz)*/ + 0 /*factor(*100, default 0 for auto)*/ + 1 /*operation_mode_init(0=video, 1=command)*/ + 0 /*operation_mode_display(0=video, 1=command)*/ + 2 /* + *video_mode_type + *(0=sync_pulse,1=sync_event,2=burst) + */ + 1 /*clk_always_hs(0=disable,1=enable)*/ + 0>; /*phy_switch(0=auto,1=standard,2=slow)*/ + + /* dsi_init: data_type, num, data... */ + dsi_init_on = <0x05 1 0x11 + 0xfd 1 20 /*delay(ms)*/ + 0x05 1 0x29 + 0xfd 1 20 /*delay(ms)*/ + 0xff 0>; /*ending*/ + dsi_init_off = <0x05 1 0x28 + 0xfd 1 10 /*delay(ms)*/ + 0x05 1 0x10 + 0xfd 1 10 /*delay(ms)*/ + 0xff 0>; /*ending*/ + extern_init = <0xff>; /*0xff for invalid*/ + + /* power step: type, index, value, delay(ms) */ + power_on_step = < + 0 1 0 100 + 0 0 0 10 + 0 0 1 20 + 2 0 0 0 + 0xff 0 0 0>; /*ending*/ + power_off_step = < + 2 0 0 50 + 0 0 0 10 + 0 1 1 100 + 0xff 0 0 0>; /*ending*/ + backlight_index = <0>; + }; + + lcd_1{ + model_name = "P070ACB_FT"; + interface = "mipi"; + basic_setting = <600 1024 /*h_active, v_active*/ + 770 1070 /*h_period, v_period*/ + 8 /*lcd_bits*/ + 3 5>; /*screen_widht, screen_height*/ + lcd_timing = <10 80 0 /*hs_width,hs_bp,hs_pol*/ + 6 20 0>; /*vs_width,vs_bp,vs_pol*/ + clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/ + 0 /*clk_ss_level*/ + 1 /*clk_auto_generate*/ + 49434000>; /*pixel_clk(unit in Hz)*/ + mipi_attr = <4 /*lane_num*/ + 400 /*bit_rate_max(MHz)*/ + 0 /*factor(*100, default 0 for auto)*/ + 1 /*operation_mode_init(0=video, 1=command)*/ + 0 /*operation_mode_display(0=video, 1=command)*/ + 2 /* + *video_mode_type + *(0=sync_pulse,1=sync_event,2=burst) + */ + 0 /*clk_always_hs(0=disable,1=enable)*/ + 0>; /*phy_switch(0=auto,1=standard,2=slow)*/ + /* dsi_init: data_type, num, data... */ + dsi_init_on = < + 0xff 10 + 0xf0 3 0 1 30 /* reset high, delay 30ms */ + 0xf0 3 0 0 10 /* reset low, delay 10ms */ + 0xf0 3 0 1 30 /* reset high, delay 30ms */ + 0xfc 2 0x04 3 /* check_reg, check_cnt */ + 0xff 0>; /* ending flag */ + dsi_init_off = <0xff 0>; /* ending flag */ + /* extern_init: 0xff for invalid */ + extern_init = <2>; + /* power step: type,index,value,delay(ms) */ + power_on_step = < + 0 1 0 200 /* panel power on */ + 2 0 0 0 + 0xff 0 0 0>; + power_off_step = < + 2 0 0 0 + 0 0 0 20 /* reset low */ + 0 1 1 100 /* panel power off */ + 0xff 0 0 0>; + backlight_index = <0>; + }; + + lcd_3{ + model_name = "TL050FHV02CT"; + interface = "mipi"; + basic_setting = <1080 1920 /*h_active, v_active*/ + 1125 2100 /*h_period, v_period*/ + 8 /*lcd_bits*/ + 65 119>; /*screen_widht, screen_height*/ + lcd_timing = <5 30 0 /*hs_width,hs_bp,hs_pol*/ + 44 108 0>; /*vs_width,vs_bp,vs_pol*/ + clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/ + 0 /*clk_ss_level*/ + 1 /*clk_auto_generate*/ + 118125000>; /*pixel_clk(unit in Hz)*/ + mipi_attr = <4 /*lane_num*/ + 960 /*bit_rate_max(MHz)*/ + 0 /*factor(*100, default 0 for auto)*/ + 1 /*operation_mode_init(0=video, 1=command)*/ + 0 /*operation_mode_display(0=video, 1=command)*/ + 2 /* + *video_mode_type + *(0=sync_pulse,1=sync_event,2=burst) + */ + 1 /*clk_always_hs(0=disable,1=enable)*/ + 0>; /*phy_switch(0=auto,1=standard,2=slow)*/ + /* dsi_init: data_type, num, data... */ + dsi_init_on = <0xff 0>; /* ending flag */ + dsi_init_off = <0xff 0>; /* ending flag */ + /* extern_init: 0xff for invalid */ + extern_init = <3>; + /* power step: type,index,value,delay(ms) */ + power_on_step = < + 0 1 0 200 + 0 0 1 20 + 0 0 0 10 + 0 0 1 20 + 2 0 0 0 + 0xff 0 0 0>; + power_off_step = < + 2 0 0 0 + 0 0 0 20 + 0 1 1 100 + 0xff 0 0 0>; + backlight_index = <0>; + }; + + lcd_4{ + model_name = "TL070WSH27"; + interface = "mipi"; + basic_setting = <1024 600 /*h_active, v_active*/ + 1250 630 /*h_period, v_period*/ + 8 /*lcd_bits*/ + 154 86>; /*screen_widht, screen_height*/ + lcd_timing = <80 100 0 /*hs_width, hs_bp, hs_pol*/ + 5 20 0>; /*vs_width, vs_bp, vs_pol*/ + clk_attr = <0 /*fr_adj_type(0=clk, 1=htotal, 2=vtotal)*/ + 0 /*clk_ss_level */ + 1 /*clk_auto_generate*/ + 47250000>; /*pixel_clk(unit in Hz)*/ + mipi_attr = <4 /*lane_num*/ + 300 /*bit_rate_max(MHz)*/ + 0 /*factor(*100, default 0 for auto)*/ + 1 /*operation_mode_init(0=video, 1=command)*/ + 0 /*operation_mode_display(0=video, 1=command)*/ + 2 /* + *video_mode_type + *(0=sync_pulse,1=sync_event,2=burst) + */ + 1 /*clk_always_hs(0=disable,1=enable)*/ + 0>; /*phy_switch(0=auto,1=standard,2=slow)*/ + + /* dsi_init: data_type, num, data... */ + dsi_init_on = <0x05 1 0x11 + 0xfd 1 20 /*delay(ms)*/ + 0x05 1 0x29 + 0xfd 1 20 /*delay(ms)*/ + 0xff 0>; /*ending*/ + dsi_init_off = <0x05 1 0x28 + 0xfd 1 10 /*delay(ms)*/ + 0x05 1 0x10 + 0xfd 1 10 /*delay(ms)*/ + 0xff 0>; /*ending*/ + extern_init = <0xff>; /*0xff for invalid*/ + + /* power step: type, index, value, delay(ms) */ + power_on_step = < + 0 1 0 100 + 0 0 0 10 + 0 0 1 20 + 2 0 0 0 + 0xff 0 0 0>; /*ending*/ + power_off_step = < + 2 0 0 50 + 0 0 0 10 + 0 1 1 100 + 0xff 0 0 0>; /*ending*/ + backlight_index = <0>; + }; + }; + + lcd_extern{ + compatible = "amlogic, lcd_extern"; + status = "okay"; + i2c_bus = "i2c_bus_0"; + key_valid = <0>; + + extern_0{ + index = <0>; + extern_name = "mipi_default";/*default*/ + status = "okay"; + type = <2>; /* 0=i2c, 1=spi, 2=mipi */ + cmd_size = <0xff>; + init_on = < + 0xfd 1 10 + 0x05 1 0x11 + 0xfd 1 120 /* delay 120ms */ + 0x05 1 0x29 + 0xff 0>; /*ending*/ + init_off = < + 0x05 1 0x28 /* display off */ + 0xfd 1 10 /* delay 10ms */ + 0x05 1 0x10 /* sleep in */ + 0xfd 1 150 /* delay 150ms */ + 0xff 0>; /*ending*/ + }; + + extern_2{ + index = <2>; + extern_name = "mipi_default";/*P070ACB_FT*/ + status = "okay"; + type = <2>; /* 0=i2c, 1=spi, 2=mipi */ + cmd_size = <0xff>; + init_on = < + 0x23 2 0xE0 0x00 /* Page 0 */ + 0x23 2 0xE1 0x93 /* PASSWORD */ + 0x23 2 0xE2 0x65 + 0x23 2 0xE3 0xF8 + 0x23 2 0x80 0x03 + 0x23 2 0xE0 0x01 /* Page 01 */ + 0x23 2 0x0C 0x74 /* Set PWRIC */ + 0x23 2 0x17 0x00 /* Set Gamma Power */ + 0x23 2 0x18 0xEF /* VGMP=5.1V */ + 0x23 2 0x19 0x00 + 0x23 2 0x1A 0x00 + 0x23 2 0x1B 0xEF /* VGMN=-5.1V */ + 0x23 2 0x1C 0x00 + 0x23 2 0x1F 0x70 /* Set Gate Power */ + 0x23 2 0x20 0x2D + 0x23 2 0x21 0x2D + 0x23 2 0x22 0x7E + 0x23 2 0x26 0xF3 /* VDDD from IOVCC */ + 0x23 2 0x37 0x09 /* SetPanel */ + 0x23 2 0x38 0x04 /* SET RGBCYC */ + 0x23 2 0x39 0x00 + 0x23 2 0x3A 0x01 + 0x23 2 0x3C 0x90 + 0x23 2 0x3D 0xFF + 0x23 2 0x3E 0xFF + 0x23 2 0x3F 0xFF + 0x23 2 0x40 0x02 /* Set TCON */ + 0x23 2 0x41 0x80 + 0x23 2 0x42 0x99 + 0x23 2 0x43 0x14 + 0x23 2 0x44 0x19 + 0x23 2 0x45 0x5A + 0x23 2 0x4B 0x04 + 0x23 2 0x55 0x02 /* power voltage */ + 0x23 2 0x56 0x01 + 0x23 2 0x57 0x69 + 0x23 2 0x58 0x0A + 0x23 2 0x59 0x0A + 0x23 2 0x5A 0x2E /* VGH = 16.2V */ + 0x23 2 0x5B 0x19 /* VGL = -12V */ + 0x23 2 0x5C 0x15 + 0x23 2 0x5D 0x77 /* Gamma */ + 0x23 2 0x5E 0x56 + 0x23 2 0x5F 0x45 + 0x23 2 0x60 0x38 + 0x23 2 0x61 0x35 + 0x23 2 0x62 0x27 + 0x23 2 0x63 0x2D + 0x23 2 0x64 0x18 + 0x23 2 0x65 0x33 + 0x23 2 0x66 0x34 + 0x23 2 0x67 0x35 + 0x23 2 0x68 0x56 + 0x23 2 0x69 0x45 + 0x23 2 0x6A 0x4F + 0x23 2 0x6B 0x42 + 0x23 2 0x6C 0x40 + 0x23 2 0x6D 0x34 + 0x23 2 0x6E 0x25 + 0x23 2 0x6F 0x02 + 0x23 2 0x70 0x77 + 0x23 2 0x71 0x56 + 0x23 2 0x72 0x45 + 0x23 2 0x73 0x38 + 0x23 2 0x74 0x35 + 0x23 2 0x75 0x27 + 0x23 2 0x76 0x2D + 0x23 2 0x77 0x18 + 0x23 2 0x78 0x33 + 0x23 2 0x79 0x34 + 0x23 2 0x7A 0x35 + 0x23 2 0x7B 0x56 + 0x23 2 0x7C 0x45 + 0x23 2 0x7D 0x4F + 0x23 2 0x7E 0x42 + 0x23 2 0x7F 0x40 + 0x23 2 0x80 0x34 + 0x23 2 0x81 0x25 + 0x23 2 0x82 0x02 + 0x23 2 0xE0 0x02 /* Page2 */ + 0x23 2 0x00 0x53 + /* GIP_L Pin mapping RESET_EVEN */ + 0x23 2 0x01 0x55 /* VSSG_EVEN */ + 0x23 2 0x02 0x55 /* VSSA_EVEN */ + 0x23 2 0x03 0x51 /* STV2_EVEN */ + 0x23 2 0x04 0x77 /* VDD2_EVEN */ + 0x23 2 0x05 0x57 /* VDD1_EVEN */ + 0x23 2 0x06 0x1F + 0x23 2 0x07 0x4F /* CK12 */ + 0x23 2 0x08 0x4D /* CK10 */ + 0x23 2 0x09 0x1F + 0x23 2 0x0A 0x4B /* CK8 */ + 0x23 2 0x0B 0x49 /* CK6 */ + 0x23 2 0x0C 0x1F + 0x23 2 0x0D 0x47 /* CK4 */ + 0x23 2 0x0E 0x45 /* CK2 */ + 0x23 2 0x0F 0x41 /* STV1_EVEN */ + 0x23 2 0x10 0x1F + 0x23 2 0x11 0x1F + 0x23 2 0x12 0x1F + 0x23 2 0x13 0x55 /* VGG */ + 0x23 2 0x14 0x1F + 0x23 2 0x15 0x1F + 0x23 2 0x16 0x52 + /* GIP_R Pin mapping RESET_ODD */ + 0x23 2 0x17 0x55 /* VSSG_ODD */ + 0x23 2 0x18 0x55 /* VSSA_ODD */ + 0x23 2 0x19 0x50 /* STV2_ODD */ + 0x23 2 0x1A 0x77 /* VDD2_ODD */ + 0x23 2 0x1B 0x57 /* VDD1_ODD */ + 0x23 2 0x1C 0x1F + 0x23 2 0x1D 0x4E /* CK11 */ + 0x23 2 0x1E 0x4C /* CK9 */ + 0x23 2 0x1F 0x1F + 0x23 2 0x20 0x4A /* CK7 */ + 0x23 2 0x21 0x48 /* CK5 */ + 0x23 2 0x22 0x1F + 0x23 2 0x23 0x46 /* CK3 */ + 0x23 2 0x24 0x44 /* CK1 */ + 0x23 2 0x25 0x40 /* STV1_ODD */ + 0x23 2 0x26 0x1F + 0x23 2 0x27 0x1F + 0x23 2 0x28 0x1F + 0x23 2 0x29 0x1F + 0x23 2 0x2A 0x1F + 0x23 2 0x2B 0x55 /* VGG */ + 0x23 2 0x2C 0x12 /* GIP_L_GS Pin mapping */ + 0x23 2 0x2D 0x15 + 0x23 2 0x2E 0x15 + 0x23 2 0x2F 0x00 + 0x23 2 0x30 0x37 + 0x23 2 0x31 0x17 + 0x23 2 0x32 0x1F + 0x23 2 0x33 0x08 + 0x23 2 0x34 0x0A + 0x23 2 0x35 0x1F + 0x23 2 0x36 0x0C + 0x23 2 0x37 0x0E + 0x23 2 0x38 0x1F + 0x23 2 0x39 0x04 + 0x23 2 0x3A 0x06 + 0x23 2 0x3B 0x10 + 0x23 2 0x3C 0x1F + 0x23 2 0x3D 0x1F + 0x23 2 0x3E 0x1F + 0x23 2 0x3F 0x15 + 0x23 2 0x40 0x1F + 0x23 2 0x41 0x1F + 0x23 2 0x42 0x13 /* GIP_R_GS Pin mapping */ + 0x23 2 0x43 0x15 + 0x23 2 0x44 0x15 + 0x23 2 0x45 0x01 + 0x23 2 0x46 0x37 + 0x23 2 0x47 0x17 + 0x23 2 0x48 0x1F + 0x23 2 0x49 0x09 + 0x23 2 0x4A 0x0B + 0x23 2 0x4B 0x1F + 0x23 2 0x4C 0x0D + 0x23 2 0x4D 0x0F + 0x23 2 0x4E 0x1F + 0x23 2 0x4F 0x05 + 0x23 2 0x50 0x07 + 0x23 2 0x51 0x11 + 0x23 2 0x52 0x1F + 0x23 2 0x53 0x1F + 0x23 2 0x54 0x1F + 0x23 2 0x55 0x1F + 0x23 2 0x56 0x1F + 0x23 2 0x57 0x15 + 0x23 2 0x58 0x40 /* GIP Timing */ + 0x23 2 0x59 0x00 + 0x23 2 0x5A 0x00 + 0x23 2 0x5B 0x10 + 0x23 2 0x5C 0x14 + 0x23 2 0x5D 0x40 + 0x23 2 0x5E 0x01 + 0x23 2 0x5F 0x02 + 0x23 2 0x60 0x40 + 0x23 2 0x61 0x03 + 0x23 2 0x62 0x04 + 0x23 2 0x63 0x7A + 0x23 2 0x64 0x7A + 0x23 2 0x65 0x74 + 0x23 2 0x66 0x16 + 0x23 2 0x67 0xB4 + 0x23 2 0x68 0x16 + 0x23 2 0x69 0x7A + 0x23 2 0x6A 0x7A + 0x23 2 0x6B 0x0C + 0x23 2 0x6C 0x00 + 0x23 2 0x6D 0x04 + 0x23 2 0x6E 0x04 + 0x23 2 0x6F 0x88 + 0x23 2 0x70 0x00 + 0x23 2 0x71 0x00 + 0x23 2 0x72 0x06 + 0x23 2 0x73 0x7B + 0x23 2 0x74 0x00 + 0x23 2 0x75 0xBC + 0x23 2 0x76 0x00 + 0x23 2 0x77 0x04 + 0x23 2 0x78 0x2C + 0x23 2 0x79 0x00 + 0x23 2 0x7A 0x00 + 0x23 2 0x7B 0x00 + 0x23 2 0x7C 0x00 + 0x23 2 0x7D 0x03 + 0x23 2 0x7E 0x7B + 0x23 2 0xE0 0x04 /* Page4 */ + 0x23 2 0x09 0x11 /* Set RGBCYC2 */ + 0x23 2 0x0E 0x48 + 0x23 2 0x2B 0x2B /* ESD Protect */ + 0x23 2 0x2E 0x44 + 0x23 2 0xE0 0x00 /* Page0 */ + 0x23 2 0xE6 0x02 /* Watch dog */ + 0x23 2 0xE7 0x0C + 0x05 1 0x11 /* sleep out */ + 0xfd 1 120 + 0x05 1 0x29 /* display on */ + 0x05 1 0x35 + 0xfd 1 20 /* delay(ms) */ + 0xFF 0>; /*ending*/ + init_off = < + 0x05 1 0x28 /* display off */ + 0xfd 1 10 /* delay 10ms */ + 0x05 1 0x10 /* sleep in */ + 0xfd 1 150 /* delay 150ms */ + 0xff 0>; /*ending*/ + }; + + extern_3{ + index = <3>; + extern_name = "mipi_default";/*TL050FHV02CT*/ + status = "okay"; + type = <2>; /* 0=i2c, 1=spi, 2=mipi */ + cmd_size = <0xff>; + init_on = < + 0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x03 + 0x29 10 0x90 0x03 0x14 0x09 0x00 0x00 + 0x00 0x38 0x00 0x00 + 0x29 10 0x91 0x00 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 + 0x29 12 0x92 0x40 0x0B 0x0C 0x0D 0x0E + 0x00 0x38 0x00 0x10 0x03 0x04 + 0x29 9 0x94 0x00 0x08 0x0B 0x03 0xD2 + 0x03 0xD3 0x0C + 0x29 17 0x95 0x00 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 + 0x29 3 0x99 0x00 0x00 + 0x29 12 0x9A 0x00 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 0x00 0x00 + 0x29 7 0x9B 0x01 0x38 0x00 0x00 0x00 0x00 + 0x29 3 0x9C 0x00 0x00 + 0x29 9 0x9D 0x10 0x10 0x10 0x10 0x10 + 0x10 0x00 0x00 + 0x29 3 0x9E 0x00 0x00 + 0x29 11 0xA0 0x9F 0x1F 0x08 0x1F 0x0A + 0x1F 0x00 0x1F 0x14 0x1F + 0x29 11 0xA1 0x15 0x1F 0x1F 0x1F 0x1F + 0x1F 0x1F 0x1F 0x1F 0x1F + 0x29 11 0xA2 0x1F 0x1F 0x1F 0x1F 0x1F + 0x1F 0x1F 0x1F 0x1F 0x1F + 0x29 11 0xA4 0x1F 0x1F 0x1F 0x1F 0x1F + 0x1F 0x1F 0x1F 0x1F 0x1F + 0x29 11 0xA5 0x1F 0x1F 0x1F 0x1F 0x1F + 0x1F 0x1F 0x1F 0x1F 0x15 + 0x29 11 0xA6 0x1F 0x14 0x1F 0x01 0x1F + 0x0B 0x1F 0x09 0x1F 0x1F + 0x29 11 0xA7 0x1F 0x1F 0x0B 0x1F 0x09 + 0x1F 0x01 0x1F 0x15 0x1F + 0x29 11 0xA8 0x14 0x1F 0x1F 0x1F 0x1F + 0x1F 0x1F 0x1F 0x1F 0x1F + 0x29 11 0xA9 0x1F 0x1F 0x1F 0x1F 0x1F + 0x1F 0x1F 0x1F 0x1F 0x1F + 0x29 11 0xAB 0x1F 0x1F 0x1F 0x1F 0x1F + 0x1F 0x1F 0x1F 0x1F 0x1F + 0x29 11 0xAC 0x1F 0x1F 0x1F 0x1F 0x1F + 0x1F 0x1F 0x1F 0x1F 0x14 + 0x29 11 0xAD 0x1F 0x15 0x1F 0x00 0x1F + 0x08 0x1F 0x0A 0x1F 0x1F + 0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x00 + 0x29 4 0xBC 0x00 0x00 0x00 + 0x29 5 0xB8 0x01 0xAF 0x8F 0x8F + 0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x01 + 0x29 17 0xD1 0x00 0x00 0x00 0x09 0x00 + 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D + 0x00 0x79 0x00 0xA7 + 0x29 17 0xD2 0x00 0xCF 0x01 0x12 0x01 + 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED + 0x02 0x2F 0x02 0x74 + 0x29 17 0xD3 0x02 0x9F 0x02 0xD5 0x02 + 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73 + 0x03 0x8C 0x03 0xA5 + 0x29 5 0xD4 0x03 0xC5 0x03 0xFF + 0x29 17 0xD5 0x00 0x00 0x00 0x09 0x00 + 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D + 0x00 0x79 0x00 0xA7 + 0x29 17 0xD6 0x00 0xCF 0x01 0x12 0x01 + 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED + 0x02 0x2F 0x02 0x74 + 0x29 17 0xD7 0x02 0x9F 0x02 0xD5 0x02 + 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73 + 0x03 0x8C 0x03 0xA5 + 0x29 5 0xD8 0x03 0xC5 0x03 0xFF + 0x29 17 0xD9 0x00 0x00 0x00 0x09 0x00 + 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D + 0x00 0x79 0x00 0xA7 + 0x29 17 0xDD 0x00 0xCF 0x01 0x12 0x01 + 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED + 0x02 0x2F 0x02 0x74 + 0x29 17 0xDE 0x02 0x9F 0x02 0xD5 0x02 + 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73 + 0x03 0x8C 0x03 0xA5 + 0x29 5 0xDF 0x03 0xC5 0x03 0xFF + 0x29 17 0xE0 0x00 0x00 0x00 0x09 0x00 + 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D + 0x00 0x79 0x00 0xA7 + 0x29 17 0xE1 0x00 0xCF 0x01 0x12 0x01 + 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED + 0x02 0x2F 0x02 0x74 + 0x29 17 0xE2 0x02 0x9F 0x02 0xD5 0x02 + 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73 + 0x03 0x8C 0x03 0xA5 + 0x29 5 0xE3 0x03 0xC5 0x03 0xFF + 0x29 17 0xE4 0x00 0x00 0x00 0x09 0x00 + 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D + 0x00 0x79 0x00 0xA7 + 0x29 17 0xE5 0x00 0xCF 0x01 0x12 0x01 + 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED + 0x02 0x2F 0x02 0x74 + 0x29 17 0xE6 0x02 0x9F 0x02 0xD5 0x02 + 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73 + 0x03 0x8C 0x03 0xA5 + 0x29 5 0xE7 0x03 0xC5 0x03 0xFF + 0x29 17 0xE8 0x00 0x00 0x00 0x09 0x00 + 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D + 0x00 0x79 0x00 0xA7 + 0x29 17 0xE9 0x00 0xCF 0x01 0x12 0x01 + 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED + 0x02 0x2F 0x02 0x74 + 0x29 17 0xEA 0x02 0x9F 0x02 0xD5 0x02 + 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73 + 0x03 0x8C 0x03 0xA5 + 0x29 5 0xEB 0x03 0xC5 0x03 0xFF + 0x29 4 0xB0 0x05 0x05 0x05 + 0x29 4 0xB1 0x05 0x05 0x05 + 0x29 4 0xB3 0x10 0x10 0x10 + 0x29 4 0xB4 0x06 0x06 0x06 + 0x29 4 0xB6 0x44 0x44 0x44 + 0x29 4 0xB7 0x34 0x34 0x34 + 0x29 4 0xB8 0x34 0x34 0x34 + 0x29 4 0xB9 0x24 0x24 0x24 + 0x29 4 0xBA 0x24 0x24 0x24 + 0x29 4 0xBC 0x00 0x70 0x00 + 0x29 4 0xBD 0x00 0x70 0x00 + 0x23 2 0xBE 0x50 + 0x23 2 0x35 0x00 + 0x13 1 0x11 + 0xfd 1 200 + 0x13 1 0x29 + 0xfd 1 200 + 0xFF 0>; /*ending*/ + init_off = < + 0x05 1 0x28 /* display off */ + 0xfd 1 10 /* delay 10ms */ + 0x05 1 0x10 /* sleep in */ + 0xfd 1 150 /* delay 150ms */ + 0xff 0>; /*ending*/ + }; + }; + + backlight{ + compatible = "amlogic, backlight-g12a"; + status = "okay"; + key_valid = <0>; + pinctrl-names = "pwm_on","pwm_off"; + /* pinctrl-0 = <&pwm_f_pins2>; */ + /* pinctrl-1 = <&bl_pwm_off_pins>; */ + pinctrl_version = <2>; /* for uboot */ + bl_pwm_config = <&bl_pwm_conf>; + /*bl-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_HIGH + &gpio GPIOH_5 GPIO_ACTIVE_HIGH>;*/ + bl_gpio_names = "GPIOH_4","GPIOH_5"; + + /* pwm port: PWM_A, PWM_B, PWM_C, PWM_D, PWM_E, PWM_F, PWM_VS*/ + /* power index:(point gpios_index, 0xff=invalid) + * power value:(0=output low, 1=output high, 2=input) + * power delay:(unit in ms) + */ + + backlight_0{ + index = <0>; + bl_name = "backlight_pwm"; + bl_level_default_uboot_kernel = <100 100>; + bl_level_attr = <255 10 /*max, min*/ + 128 128>; /*mid, mid_mapping*/ + bl_ctrl_method = <1>; /* 1=pwm, 2=pwm_combo, 4=extern */ + bl_power_attr = <0 /*en_gpio_index*/ + 1 0 /*on_value, off_value*/ + 200 200>; /*on_delay(ms), off_delay(ms)*/ + bl_pwm_port = "PWM_F"; + bl_pwm_attr = <0 /*pwm_method*/ + 180 /*pwm_freq(pwm:Hz, pwm_vs:multiple of vs)*/ + 100 25>; /*duty_max(%), duty_min(%)*/ + bl_pwm_power = <1 1 /*pwm_gpio_index, pwm_gpio_off*/ + 10 10>; /*pwm_on_delay(ms), pwm_off_delay(ms)*/ + bl_pwm_en_sequence_reverse = <0>; /* 1 for reverse */ + }; + backlight_1{ + index = <1>; + bl_name = "bl_extern"; + bl_level_default_uboot_kernel = <100 100>; + bl_level_attr = <255 10 /*max, min*/ + 128 128>; /*mid, mid_mapping*/ + bl_ctrl_method = <4>; /*1=pwm, 2=pwm_combo, 4=extern*/ + bl_power_attr = <1 /*en_gpio_index*/ + 1 0 /*on_value, off_value*/ + 200 200>; /*on_delay(ms), off_delay(ms)*/ + bl_extern_index = <0>; + }; + }; + bl_pwm_conf:bl_pwm_conf{ + pwm_channel_0 { + pwm_port_index = <5>; + pwms = <&pwm_ef MESON_PWM_1 30040 0>; + }; + }; + + bl_extern{ + compatible = "amlogic, bl_extern"; + status = "disabled"; + i2c_bus = "i2c_bus_3"; + + extern_0{ + index = <0>; + extern_name = "i2c_lp8556"; + type = <0>; /*0=i2c, 1=spi, 2=mipi*/ + i2c_address = <0x2c>; /*7bit i2c address*/ + dim_max_min = <255 10>; + }; + + extern_1{ + index = <1>; + extern_name = "mipi_lt070me05"; + type = <2>; /*0=i2c, 1=spi, 2=mipi*/ + dim_max_min = <255 10>; + }; + }; +};/* end of panel */ +
diff --git a/arch/arm/dts/meson-c2-c305x-af400.dts b/arch/arm/dts/meson-c2-c305x-af400.dts new file mode 100644 index 0000000..69dcdd9 --- /dev/null +++ b/arch/arm/dts/meson-c2-c305x-af400.dts
@@ -0,0 +1,90 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "meson-c2-c305x-af400.dtsi" +#include "meson-c2_skt-panel.dtsi" + +/ { + compatible = "amlogic,af400", "amlogic,c305x", "amlogic,meson-c2"; + model = "Amlogic Meson C2 AF400 Socket Board"; +}; + +/* This UART is brought out to the DB9 connector */ +&uart_a { + status = "okay"; +}; + +&uart_b { + status = "okay"; +}; + +&saradc { + status = "okay"; +}; + +/* demo for i2c user */ +&i2c3 { + status= "disabled"; + clock-frequency = <100000>; + /* pinctrl-names = "default";*/ + /* pinctrl-0 = <&i2c3_master_pins2>;*/ +}; + +ðmac { + status = "okay"; + internal_phy = <0>; + pinctrl-0 = <&external_eth_rmii_pins>; + pinctrl-names = "external_eth_rmii_pins"; + mc_val = <0x1624>; +}; +&pinctrl_periphs { + bl_pwm_off_pins:bl_pwm_off_pin { + mux { + groups = "GPIOH_5"; + function = "gpio_periphs"; + output-high; + }; + }; +}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-c2-c305x-af400.dtsi b/arch/arm/dts/meson-c2-c305x-af400.dtsi new file mode 100644 index 0000000..f313da1 --- /dev/null +++ b/arch/arm/dts/meson-c2-c305x-af400.dtsi
@@ -0,0 +1,252 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>. + * Based on meson-gx-p23x-q20x.dtsi: + * - Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * - Copyright (c) 2016 BayLibre, SAS. + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +/* Common DTSI for devices which are based on the P212 reference board. */ + +#include "meson-c2-c305x.dtsi" + +/ { + aliases { + serial0 = &uart_b; + serial1 = &uart_a; + spi0 = &spifc; + spi1 = &spicc0; + spi2 = &spicc1; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c_gpio_0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + vddio_boot: regulator-vddio_boot { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vddio_ao18: regulator-vddio_ao18 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + /*reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;*/ + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; +}; + +ðmac { + status = "okay"; + internal_phy = <1>; + mc_val = <0x4be04>; + /*mc_val = <0x1621>;*/ +}; + +&ir { + status = "disabled"; + /* pinctrl-0 = <&remote_input_ao_pins>; */ + /* pinctrl-names = "default"; */ +}; + +&saradc { + status = "okay"; + vref-supply = <&vddio_ao18>; +}; + +/* Wireless SDIO Module */ +&sd_emmc_a { + status = "disabled"; + /*pinctrl-0 = <&sdio_pins>;*/ + /*pinctrl-names = "default";*/ + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + + non-removable; + disable-wp; + card_type = <3>; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_pins>; + pinctrl-1 = <&sdcard_pins &to_sduart_pins>; + pinctrl-names = "sd_all_pins", "sd_uart"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>; + cd-inverted; + + card_type = <5>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + hs_co_phase = <2>; + hs_to_phase = <0>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-hs200-1_8v; + max-frequency = <200000000>; + non-removable; + disable-wp; + /* mmc-ddr-1_8v; */ + card_type = <1>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + hs_co_phase = <2>; + hs_to_phase = <0>; + + hs2_co_phase = <2>; + hs2_to_phase = <0>; + + hw_reset = <&gpio GPIOB_9 GPIO_ACTIVE_HIGH>; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* nand */ +&nand { + status = "okay"; + pinctrl-names = "default", "nand_cs_only"; + pinctrl-0 = <&all_nand_pins>; + pinctrl-1 = <&nand_cs_pins>; +}; + +&dwc3 { + status = "okay"; + dr_mode = "host"; +}; + +&usb2_phy_v2 { + status = "okay"; + portnum = <1>; +}; + +&usb3_phy_v2 { + status = "okay"; + portnum = <0>; + gpio-vbus-power = "GPIOD_9"; + gpios = <&gpio GPIOD_9 GPIO_ACTIVE_HIGH>; +}; + +&pwm_ef { + status = "okay"; + /* pinctrl-0 = <&pwm_e_pins>; */ + /* pinctrl-names = "default"; */ +}; + +/* This is connected to the Bluetooth module: */ +&uart_a { + status = "okay"; + /* pinctrl-0 = <&a_uart_pins>; */ + /* pinctrl-names = "default"; */ + uart-has-rtscts; +}; + +&spifc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spifc_pins>; + max-frequency = <24000000>; + max-cs = <2>; + /* 512M */ + clocks = <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_SPIFC_MUX>, + <&clkc CLKID_SPIFC_DIV>, + <&clkc CLKID_SPIFC_GATE>, + <&clkc CLKID_SPIFC_XTAL_GATE>; + clock-names = "fclk_source", "spifc_mux", "spifc_div", "spifc_gate", "spifc_xtal_gate"; +}; + +&spicc0 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc0_pins1>; + cs-gpios = <&gpio GPIOA_8 0>; +}; + +&spicc1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc1_pins1>; + cs-gpios = <&gpio GPIOA_14 0>; +};
diff --git a/arch/arm/dts/meson-c2-c305x-af401.dts b/arch/arm/dts/meson-c2-c305x-af401.dts new file mode 100644 index 0000000..707f9c2 --- /dev/null +++ b/arch/arm/dts/meson-c2-c305x-af401.dts
@@ -0,0 +1,90 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "meson-c2-c305x-af401.dtsi" +#include "meson-c2_skt-panel.dtsi" + +/ { + compatible = "amlogic,af401", "amlogic,c305x", "amlogic,meson-c2"; + model = "Amlogic Meson C2 AF401 Board"; +}; + +/* This UART is brought out to the DB9 connector */ +&uart_a { + status = "okay"; +}; + +&uart_b { + status = "okay"; +}; + +&saradc { + status = "okay"; +}; + +/* demo for i2c user */ +&i2c3 { + status= "disabled"; + clock-frequency = <100000>; + /* pinctrl-names = "default";*/ + /* pinctrl-0 = <&i2c3_master_pins2>;*/ +}; + +ðmac { + status = "okay"; + internal_phy = <0>; + pinctrl-0 = <&external_eth_rmii_pins>; + pinctrl-names = "external_eth_rmii_pins"; + mc_val = <0x1624>; +}; +&pinctrl_periphs { + bl_pwm_off_pins:bl_pwm_off_pin { + mux { + groups = "GPIOH_5"; + function = "gpio_periphs"; + output-high; + }; + }; +}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-c2-c305x-af401.dtsi b/arch/arm/dts/meson-c2-c305x-af401.dtsi new file mode 100644 index 0000000..2857303 --- /dev/null +++ b/arch/arm/dts/meson-c2-c305x-af401.dtsi
@@ -0,0 +1,251 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>. + * Based on meson-gx-p23x-q20x.dtsi: + * - Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * - Copyright (c) 2016 BayLibre, SAS. + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +/* Common DTSI for devices which are based on the P212 reference board. */ + +#include "meson-c2-c305x.dtsi" + +/ { + aliases { + serial0 = &uart_b; + serial1 = &uart_a; + spi0 = &spifc; + spi1 = &spicc0; + spi2 = &spicc1; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x20000000>; + }; + + vddio_boot: regulator-vddio_boot { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vddio_ao18: regulator-vddio_ao18 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + /*reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;*/ + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; +}; + +ðmac { + status = "okay"; + internal_phy = <1>; + mc_val = <0x4be04>; + /*mc_val = <0x1621>;*/ +}; + +&ir { + status = "disabled"; + /* pinctrl-0 = <&remote_input_ao_pins>; */ + /* pinctrl-names = "default"; */ +}; + +&saradc { + status = "okay"; + vref-supply = <&vddio_ao18>; +}; + +/* Wireless SDIO Module */ +&sd_emmc_a { + status = "disabled"; + /*pinctrl-0 = <&sdio_pins>;*/ + /*pinctrl-names = "default";*/ + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + + non-removable; + disable-wp; + card_type = <3>; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_pins>; + pinctrl-1 = <&sdcard_pins &to_sduart_pins>; + pinctrl-names = "sd_all_pins", "sd_uart"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>; + cd-inverted; + + card_type = <5>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + hs_co_phase = <2>; + hs_to_phase = <0>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-hs200-1_8v; + max-frequency = <200000000>; + non-removable; + disable-wp; + /* mmc-ddr-1_8v; */ + card_type = <1>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + hs_co_phase = <2>; + hs_to_phase = <0>; + + hs2_co_phase = <2>; + hs2_to_phase = <0>; + + hw_reset = <&gpio GPIOB_9 GPIO_ACTIVE_HIGH>; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* nand */ +&nand { + status = "okay"; + pinctrl-names = "default", "nand_cs_only"; + pinctrl-0 = <&all_nand_pins>; + pinctrl-1 = <&nand_cs_pins>; +}; + +&dwc3 { + status = "okay"; + dr_mode = "host"; +}; + +&usb2_phy_v2 { + status = "okay"; + portnum = <1>; +}; + +&usb3_phy_v2 { + status = "okay"; + portnum = <0>; + gpio-vbus-power = "GPIOD_9"; + gpios = <&gpio GPIOD_9 GPIO_ACTIVE_HIGH>; +}; + +&pwm_ef { + status = "okay"; + /* pinctrl-0 = <&pwm_e_pins>; */ + /* pinctrl-names = "default"; */ +}; + +/* This is connected to the Bluetooth module: */ +&uart_a { + status = "okay"; + /* pinctrl-0 = <&a_uart_pins>; */ + /* pinctrl-names = "default"; */ + uart-has-rtscts; +}; + +&spifc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spifc_pins>; + max-frequency = <24000000>; + max-cs = <2>; + /* 512M */ + clocks = <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_SPIFC_MUX>, + <&clkc CLKID_SPIFC_DIV>, + <&clkc CLKID_SPIFC_GATE>, + <&clkc CLKID_SPIFC_XTAL_GATE>; + clock-names = "fclk_source", "spifc_mux", "spifc_div", "spifc_gate", "spifc_xtal_gate"; +}; + +&spicc0 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc0_pins1>; + cs-gpios = <&gpio GPIOA_8 0>; +}; + +&spicc1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc1_pins1>; + cs-gpios = <&gpio GPIOA_14 0>; +};
diff --git a/arch/arm/dts/meson-c2-c305x-af402.dts b/arch/arm/dts/meson-c2-c305x-af402.dts new file mode 100644 index 0000000..d4b56d7 --- /dev/null +++ b/arch/arm/dts/meson-c2-c305x-af402.dts
@@ -0,0 +1,90 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "meson-c2-c305x-af402.dtsi" +#include "meson-c2_skt-panel.dtsi" + +/ { + compatible = "amlogic,af402", "amlogic,c305x", "amlogic,meson-c2"; + model = "Amlogic Meson C2 AF402 Socket Board"; +}; + +/* This UART is brought out to the DB9 connector */ +&uart_a { + status = "okay"; +}; + +&uart_b { + status = "okay"; +}; + +&saradc { + status = "okay"; +}; + +/* demo for i2c user */ +&i2c3 { + status= "disabled"; + clock-frequency = <100000>; + /* pinctrl-names = "default";*/ + /* pinctrl-0 = <&i2c3_master_pins2>;*/ +}; + +ðmac { + status = "okay"; + internal_phy = <0>; + pinctrl-0 = <&external_eth_rmii_pins>; + pinctrl-names = "external_eth_rmii_pins"; + mc_val = <0x1624>; +}; +&pinctrl_periphs { + bl_pwm_off_pins:bl_pwm_off_pin { + mux { + groups = "GPIOH_5"; + function = "gpio_periphs"; + output-high; + }; + }; +}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-c2-c305x-af402.dtsi b/arch/arm/dts/meson-c2-c305x-af402.dtsi new file mode 100644 index 0000000..ad57a2a --- /dev/null +++ b/arch/arm/dts/meson-c2-c305x-af402.dtsi
@@ -0,0 +1,252 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>. + * Based on meson-gx-p23x-q20x.dtsi: + * - Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * - Copyright (c) 2016 BayLibre, SAS. + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +/* Common DTSI for devices which are based on the P212 reference board. */ + +#include "meson-c2-c305x.dtsi" + +/ { + aliases { + serial0 = &uart_b; + serial1 = &uart_a; + spi0 = &spifc; + spi1 = &spicc0; + spi2 = &spicc1; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c_gpio_0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + vddio_boot: regulator-vddio_boot { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vddio_ao18: regulator-vddio_ao18 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + /*reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;*/ + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; +}; + +ðmac { + status = "okay"; + internal_phy = <1>; + mc_val = <0x4be04>; + /*mc_val = <0x1621>;*/ +}; + +&ir { + status = "disabled"; + /* pinctrl-0 = <&remote_input_ao_pins>; */ + /* pinctrl-names = "default"; */ +}; + +&saradc { + status = "okay"; + vref-supply = <&vddio_ao18>; +}; + +/* Wireless SDIO Module */ +&sd_emmc_a { + status = "disabled"; + /*pinctrl-0 = <&sdio_pins>;*/ + /*pinctrl-names = "default";*/ + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + + non-removable; + disable-wp; + card_type = <3>; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_pins>; + pinctrl-1 = <&sdcard_pins &to_sduart_pins>; + pinctrl-names = "sd_all_pins", "sd_uart"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>; + cd-inverted; + + card_type = <5>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + hs_co_phase = <2>; + hs_to_phase = <0>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-hs200-1_8v; + max-frequency = <200000000>; + non-removable; + disable-wp; + /* mmc-ddr-1_8v; */ + card_type = <1>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + hs_co_phase = <2>; + hs_to_phase = <0>; + + hs2_co_phase = <2>; + hs2_to_phase = <0>; + + hw_reset = <&gpio GPIOB_9 GPIO_ACTIVE_HIGH>; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* nand */ +&nand { + status = "okay"; + pinctrl-names = "default", "nand_cs_only"; + pinctrl-0 = <&all_nand_pins>; + pinctrl-1 = <&nand_cs_pins>; +}; + +&dwc3 { + status = "okay"; + dr_mode = "host"; +}; + +&usb2_phy_v2 { + status = "okay"; + portnum = <1>; +}; + +&usb3_phy_v2 { + status = "okay"; + portnum = <0>; + gpio-vbus-power = "GPIOD_9"; + gpios = <&gpio GPIOD_9 GPIO_ACTIVE_HIGH>; +}; + +&pwm_ef { + status = "okay"; + /* pinctrl-0 = <&pwm_e_pins>; */ + /* pinctrl-names = "default"; */ +}; + +/* This is connected to the Bluetooth module: */ +&uart_a { + status = "okay"; + /* pinctrl-0 = <&a_uart_pins>; */ + /* pinctrl-names = "default"; */ + uart-has-rtscts; +}; + +&spifc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spifc_pins>; + max-frequency = <96000000>; + max-cs = <2>; + /* 512M */ + clocks = <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_SPIFC_MUX>, + <&clkc CLKID_SPIFC_DIV>, + <&clkc CLKID_SPIFC_GATE>, + <&clkc CLKID_SPIFC_XTAL_GATE>; + clock-names = "fclk_source", "spifc_mux", "spifc_div", "spifc_gate", "spifc_xtal_gate"; +}; + +&spicc0 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc0_pins1>; + cs-gpios = <&gpio GPIOA_8 0>; +}; + +&spicc1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc1_pins1>; + cs-gpios = <&gpio GPIOA_14 0>; +};
diff --git a/arch/arm/dts/meson-c2-c305x-af409.dts b/arch/arm/dts/meson-c2-c305x-af409.dts new file mode 100644 index 0000000..b0d4fdc --- /dev/null +++ b/arch/arm/dts/meson-c2-c305x-af409.dts
@@ -0,0 +1,90 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "meson-c2-c305x-af409.dtsi" +#include "meson-c2_skt-panel.dtsi" + +/ { + compatible = "amlogic,af409", "amlogic,c305x", "amlogic,meson-c2"; + model = "Amlogic Meson C2 AF409 Socket Board"; +}; + +/* This UART is brought out to the DB9 connector */ +&uart_a { + status = "okay"; +}; + +&uart_b { + status = "okay"; +}; + +&saradc { + status = "okay"; +}; + +/* demo for i2c user */ +&i2c3 { + status= "disabled"; + clock-frequency = <100000>; + /* pinctrl-names = "default";*/ + /* pinctrl-0 = <&i2c3_master_pins2>;*/ +}; + +ðmac { + status = "okay"; + internal_phy = <0>; + pinctrl-0 = <&external_eth_rmii_pins>; + pinctrl-names = "external_eth_rmii_pins"; + mc_val = <0x1624>; +}; +&pinctrl_periphs { + bl_pwm_off_pins:bl_pwm_off_pin { + mux { + groups = "GPIOH_5"; + function = "gpio_periphs"; + output-high; + }; + }; +}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-c2-c305x-af409.dtsi b/arch/arm/dts/meson-c2-c305x-af409.dtsi new file mode 100644 index 0000000..f313da1 --- /dev/null +++ b/arch/arm/dts/meson-c2-c305x-af409.dtsi
@@ -0,0 +1,252 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>. + * Based on meson-gx-p23x-q20x.dtsi: + * - Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * - Copyright (c) 2016 BayLibre, SAS. + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +/* Common DTSI for devices which are based on the P212 reference board. */ + +#include "meson-c2-c305x.dtsi" + +/ { + aliases { + serial0 = &uart_b; + serial1 = &uart_a; + spi0 = &spifc; + spi1 = &spicc0; + spi2 = &spicc1; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c_gpio_0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + vddio_boot: regulator-vddio_boot { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vddio_ao18: regulator-vddio_ao18 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + /*reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;*/ + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; +}; + +ðmac { + status = "okay"; + internal_phy = <1>; + mc_val = <0x4be04>; + /*mc_val = <0x1621>;*/ +}; + +&ir { + status = "disabled"; + /* pinctrl-0 = <&remote_input_ao_pins>; */ + /* pinctrl-names = "default"; */ +}; + +&saradc { + status = "okay"; + vref-supply = <&vddio_ao18>; +}; + +/* Wireless SDIO Module */ +&sd_emmc_a { + status = "disabled"; + /*pinctrl-0 = <&sdio_pins>;*/ + /*pinctrl-names = "default";*/ + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + + non-removable; + disable-wp; + card_type = <3>; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_pins>; + pinctrl-1 = <&sdcard_pins &to_sduart_pins>; + pinctrl-names = "sd_all_pins", "sd_uart"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>; + cd-inverted; + + card_type = <5>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + hs_co_phase = <2>; + hs_to_phase = <0>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-hs200-1_8v; + max-frequency = <200000000>; + non-removable; + disable-wp; + /* mmc-ddr-1_8v; */ + card_type = <1>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + hs_co_phase = <2>; + hs_to_phase = <0>; + + hs2_co_phase = <2>; + hs2_to_phase = <0>; + + hw_reset = <&gpio GPIOB_9 GPIO_ACTIVE_HIGH>; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* nand */ +&nand { + status = "okay"; + pinctrl-names = "default", "nand_cs_only"; + pinctrl-0 = <&all_nand_pins>; + pinctrl-1 = <&nand_cs_pins>; +}; + +&dwc3 { + status = "okay"; + dr_mode = "host"; +}; + +&usb2_phy_v2 { + status = "okay"; + portnum = <1>; +}; + +&usb3_phy_v2 { + status = "okay"; + portnum = <0>; + gpio-vbus-power = "GPIOD_9"; + gpios = <&gpio GPIOD_9 GPIO_ACTIVE_HIGH>; +}; + +&pwm_ef { + status = "okay"; + /* pinctrl-0 = <&pwm_e_pins>; */ + /* pinctrl-names = "default"; */ +}; + +/* This is connected to the Bluetooth module: */ +&uart_a { + status = "okay"; + /* pinctrl-0 = <&a_uart_pins>; */ + /* pinctrl-names = "default"; */ + uart-has-rtscts; +}; + +&spifc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spifc_pins>; + max-frequency = <24000000>; + max-cs = <2>; + /* 512M */ + clocks = <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_SPIFC_MUX>, + <&clkc CLKID_SPIFC_DIV>, + <&clkc CLKID_SPIFC_GATE>, + <&clkc CLKID_SPIFC_XTAL_GATE>; + clock-names = "fclk_source", "spifc_mux", "spifc_div", "spifc_gate", "spifc_xtal_gate"; +}; + +&spicc0 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc0_pins1>; + cs-gpios = <&gpio GPIOA_8 0>; +}; + +&spicc1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc1_pins1>; + cs-gpios = <&gpio GPIOA_14 0>; +};
diff --git a/arch/arm/dts/meson-c2-c305x-af419.dts b/arch/arm/dts/meson-c2-c305x-af419.dts new file mode 100644 index 0000000..3799307 --- /dev/null +++ b/arch/arm/dts/meson-c2-c305x-af419.dts
@@ -0,0 +1,90 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "meson-c2-c305x-af419.dtsi" +#include "meson-c2_skt-panel.dtsi" + +/ { + compatible = "amlogic,af419", "amlogic,c305x", "amlogic,meson-c2"; + model = "Amlogic Meson C2 AF419 Socket Board"; +}; + +/* This UART is brought out to the DB9 connector */ +&uart_a { + status = "okay"; +}; + +&uart_b { + status = "okay"; +}; + +&saradc { + status = "okay"; +}; + +/* demo for i2c user */ +&i2c3 { + status= "disabled"; + clock-frequency = <100000>; + /* pinctrl-names = "default";*/ + /* pinctrl-0 = <&i2c3_master_pins2>;*/ +}; + +ðmac { + status = "okay"; + internal_phy = <0>; + pinctrl-0 = <&external_eth_rmii_pins>; + pinctrl-names = "external_eth_rmii_pins"; + mc_val = <0x1624>; +}; +&pinctrl_periphs { + bl_pwm_off_pins:bl_pwm_off_pin { + mux { + groups = "GPIOH_5"; + function = "gpio_periphs"; + output-high; + }; + }; +}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-c2-c305x-af419.dtsi b/arch/arm/dts/meson-c2-c305x-af419.dtsi new file mode 100644 index 0000000..f313da1 --- /dev/null +++ b/arch/arm/dts/meson-c2-c305x-af419.dtsi
@@ -0,0 +1,252 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>. + * Based on meson-gx-p23x-q20x.dtsi: + * - Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * - Copyright (c) 2016 BayLibre, SAS. + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +/* Common DTSI for devices which are based on the P212 reference board. */ + +#include "meson-c2-c305x.dtsi" + +/ { + aliases { + serial0 = &uart_b; + serial1 = &uart_a; + spi0 = &spifc; + spi1 = &spicc0; + spi2 = &spicc1; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c_gpio_0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + vddio_boot: regulator-vddio_boot { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vddio_ao18: regulator-vddio_ao18 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + /*reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;*/ + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; +}; + +ðmac { + status = "okay"; + internal_phy = <1>; + mc_val = <0x4be04>; + /*mc_val = <0x1621>;*/ +}; + +&ir { + status = "disabled"; + /* pinctrl-0 = <&remote_input_ao_pins>; */ + /* pinctrl-names = "default"; */ +}; + +&saradc { + status = "okay"; + vref-supply = <&vddio_ao18>; +}; + +/* Wireless SDIO Module */ +&sd_emmc_a { + status = "disabled"; + /*pinctrl-0 = <&sdio_pins>;*/ + /*pinctrl-names = "default";*/ + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + + non-removable; + disable-wp; + card_type = <3>; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_pins>; + pinctrl-1 = <&sdcard_pins &to_sduart_pins>; + pinctrl-names = "sd_all_pins", "sd_uart"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>; + cd-inverted; + + card_type = <5>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + hs_co_phase = <2>; + hs_to_phase = <0>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-hs200-1_8v; + max-frequency = <200000000>; + non-removable; + disable-wp; + /* mmc-ddr-1_8v; */ + card_type = <1>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + hs_co_phase = <2>; + hs_to_phase = <0>; + + hs2_co_phase = <2>; + hs2_to_phase = <0>; + + hw_reset = <&gpio GPIOB_9 GPIO_ACTIVE_HIGH>; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* nand */ +&nand { + status = "okay"; + pinctrl-names = "default", "nand_cs_only"; + pinctrl-0 = <&all_nand_pins>; + pinctrl-1 = <&nand_cs_pins>; +}; + +&dwc3 { + status = "okay"; + dr_mode = "host"; +}; + +&usb2_phy_v2 { + status = "okay"; + portnum = <1>; +}; + +&usb3_phy_v2 { + status = "okay"; + portnum = <0>; + gpio-vbus-power = "GPIOD_9"; + gpios = <&gpio GPIOD_9 GPIO_ACTIVE_HIGH>; +}; + +&pwm_ef { + status = "okay"; + /* pinctrl-0 = <&pwm_e_pins>; */ + /* pinctrl-names = "default"; */ +}; + +/* This is connected to the Bluetooth module: */ +&uart_a { + status = "okay"; + /* pinctrl-0 = <&a_uart_pins>; */ + /* pinctrl-names = "default"; */ + uart-has-rtscts; +}; + +&spifc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spifc_pins>; + max-frequency = <24000000>; + max-cs = <2>; + /* 512M */ + clocks = <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_SPIFC_MUX>, + <&clkc CLKID_SPIFC_DIV>, + <&clkc CLKID_SPIFC_GATE>, + <&clkc CLKID_SPIFC_XTAL_GATE>; + clock-names = "fclk_source", "spifc_mux", "spifc_div", "spifc_gate", "spifc_xtal_gate"; +}; + +&spicc0 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc0_pins1>; + cs-gpios = <&gpio GPIOA_8 0>; +}; + +&spicc1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc1_pins1>; + cs-gpios = <&gpio GPIOA_14 0>; +};
diff --git a/arch/arm/dts/meson-c2-c305x.dtsi b/arch/arm/dts/meson-c2-c305x.dtsi new file mode 100644 index 0000000..9668492 --- /dev/null +++ b/arch/arm/dts/meson-c2-c305x.dtsi
@@ -0,0 +1,54 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "meson-c2.dtsi" +#include "meson-c2-mali.dtsi" + +/ { + compatible = "amlogic,c305x", "amlogic,meson-c2"; +}; + +ðmac { + phy-mode = "rmii"; + phy-handle = <&internal_phy>; +};
diff --git a/arch/arm/dts/meson-c2-mali.dtsi b/arch/arm/dts/meson-c2-mali.dtsi new file mode 100644 index 0000000..2655b42 --- /dev/null +++ b/arch/arm/dts/meson-c2-mali.dtsi
@@ -0,0 +1,43 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 BayLibre SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +&apb { + mali: gpu@40000 { + compatible = "amlogic,meson-gxbb-mali", "arm,mali-450"; + reg = <0x0 0x40000 0x0 0x40000>; + interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "gp", "gpmmu", "pp", "pmu", + "pp0", "ppmmu0", "pp1", "ppmmu1", + "pp2", "ppmmu2"; + /*clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;*/ + clock-names = "bus", "core"; + + /* + * Mali clocking is provided by two identical clock paths + * MALI_0 and MALI_1 muxed to a single clock by a glitch + * free mux to safely change frequency while running. + */ + /* + assigned-clocks = <&clkc CLKID_MALI_0_SEL>, + <&clkc CLKID_MALI_0>, + <&clkc CLKID_MALI>; *//* Glitch free mux */ + /*assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, + <0>, *//* Do Nothing */ + //<&clkc CLKID_MALI_0>; + /*assigned-clock-rates = <0>,*/ /* Do Nothing */ + /* <666666666>, + <0>;*/ /* Do Nothing */ + }; +};
diff --git a/arch/arm/dts/meson-c2-pxp.dts b/arch/arm/dts/meson-c2-pxp.dts new file mode 100644 index 0000000..02c94a0 --- /dev/null +++ b/arch/arm/dts/meson-c2-pxp.dts
@@ -0,0 +1,83 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "meson-c2-c305x-af409.dtsi" +#include "meson-c2_skt-panel.dtsi" + +/ { + compatible = "amlogic,af409", "amlogic,c305x", "amlogic,meson-c2"; + model = "Amlogic Meson C2 AF409 Socket Board"; +}; + +/* This UART is brought out to the DB9 connector */ +&uart_a { + status = "okay"; +}; + +&uart_b { + status = "okay"; +}; + +&saradc { + status = "okay"; +}; + +/* demo for i2c user */ +&i2c3 { + status= "disabled"; + clock-frequency = <100000>; + /* pinctrl-names = "default";*/ + /* pinctrl-0 = <&i2c3_master_pins2>;*/ +}; + +&pinctrl_periphs { + bl_pwm_off_pins:bl_pwm_off_pin { + mux { + groups = "GPIOH_5"; + function = "gpio_periphs"; + output-high; + }; + }; +}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-c2.dtsi b/arch/arm/dts/meson-c2.dtsi new file mode 100644 index 0000000..ea5b4bb --- /dev/null +++ b/arch/arm/dts/meson-c2.dtsi
@@ -0,0 +1,776 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "meson-c-series.dtsi" +#include <dt-bindings/gpio/meson-c2-gpio.h> +#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h> + +/ { + compatible = "amlogic,meson-c2"; + + vpu { + compatible = "amlogic, vpu-g12a"; + status = "okay"; + /*clocks = <&clkc CLKID_VAPB_MUX>, + * <&clkc CLKID_VPU_INTR>, + * <&clkc CLKID_VPU_P0_COMP>, + * <&clkc CLKID_VPU_P1_COMP>, + * <&clkc CLKID_VPU_MUX>; + *clock-names = "vapb_clk", + * "vpu_intr_gate", + * "vpu_clk0", + * "vpu_clk1", + * "vpu_clk"; + */ + clk_level = <7>; + /* 0: 100.0M 1: 166.7M 2: 200.0M 3: 250.0M */ + /* 4: 333.3M 5: 400.0M 6: 500.0M 7: 666.7M */ + }; + + meson-fb { + status = "okay"; + logo_addr = "0x7f800000"; + }; +}; + +ðmac { + compatible = "amlogic,g12a-eth-dwmac"; + reg = <0x0 0xff080000 0x0 0x10000 + 0x0 0xFE009000 0x0 0x8 + 0x0 0xFE009400 0x0 0xa0>; + reg-names = "eth_base", "eth_top", "eth_cfg"; + phy_cntl1 = <0x41054147>; + internal_phy = <1>; + mc_val = <0x4be04>; + reset-gpios = <&gpio GPIOX_20 GPIO_ACTIVE_HIGH>; + analog_ver = <2>; /*1:c1; 2:c2*/ + pll_val = <0x9c0040a 0x927e0000 0xac5f49e5>; + analog_val = <0x20200000 0x0000c000 0x00000023>; + tx_amp_src = <0xfe005b30>; +// clocks = <&clkc CLKID_ETH_CORE>, +// <&clkc CLKID_FCLK_DIV2>, +// <&clkc CLKID_MPLL2>; +// clock-names = "stmmaceth", "clkin0", "clkin1"; + + mdio0: mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + }; +}; + +&cbus { + pinctrl_periphs: pinctrl@0400 { + compatible = "amlogic,meson-c2-periphs-pinctrl"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio: bank@0400 { + reg = <0x0 0x0400 0x0 0x0040>, + <0x0 0x0480 0x0 0x01d8>; + reg-names = "mux", + "gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_periphs 0 0 90>; + }; + }; + + i2c_gpio_0: i2c-gpio-0 { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "i2c-gpio"; + status = "okay"; + gpios = <&gpio GPIOM_12 GPIO_ACTIVE_HIGH>, /* SDA */ + <&gpio GPIOM_13 GPIO_ACTIVE_HIGH>; /* CLK */ + + i2c-gpio,delay-us = <5>; + }; +}; + +&periphs { + + eth-phy-mux { + compatible = "mdio-mux-mmioreg", "mdio-mux"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x15c 0x0 0x4>; + mux-mask = <0xffffffff>; + mdio-parent-bus = <&mdio0>; + + internal_mdio: mdio@e40908ff { + reg = <0xe40908ff>; + #address-cells = <1>; + #size-cells = <0>; + + internal_phy: ethernet-phy@8 { + compatible = "ethernet-phy-id0181.4400", "ethernet-phy-ieee802.3-c22"; + reg = <8>; + max-speed = <100>; + }; + }; + + external_mdio: mdio@2009087f { + reg = <0x2009087f>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&saradc { + compatible = "amlogic,meson-c2-saradc", "amlogic,meson-saradc"; + clocks = <&xtal>, + <&clkc CLKID_SARADC_MUX>, + <&clkc CLKID_SARADC_DIV>, + <&clkc CLKID_SAR_ADC_GATE>; + clock-names = "xtal", "adc_mux", "adc_div", "adc_gate"; +}; + +&sd_emmc_a { + clocks = <&clkc CLKID_SD_EMMC_A_MUX>, + <&clkc CLKID_SD_EMMC_A_DIV>, + <&clkc CLKID_SD_EMMC_A_GATE>, + <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_SD_EMMC_A_XTAL_GATE>; + clock-names = "mux", "div", "gate", "clkin", "xtal"; +}; + +&sd_emmc_b { + clocks = <&clkc CLKID_SD_EMMC_B_MUX>, + <&clkc CLKID_SD_EMMC_B_DIV>, + <&clkc CLKID_SD_EMMC_B_GATE>, + <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_SD_EMMC_B_XTAL_GATE>; + clock-names = "mux", "div", "gate", "clkin", "xtal"; +}; + +&sd_emmc_c { + clocks = <&clkc CLKID_SD_EMMC_C_MUX>, + <&clkc CLKID_SD_EMMC_C_DIV>, + <&clkc CLKID_SD_EMMC_C_GATE>, + <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_SD_EMMC_C_XTAL_GATE>; + clock-names = "mux", "div", "gate", "clkin", "xtal"; +}; + +&nand { + clocks = <&clkc CLKID_SD_EMMC_C_MUX>, + <&clkc CLKID_SD_EMMC_C_DIV>, + <&clkc CLKID_SD_EMMC_C_GATE>, + <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_SD_EMMC_C_XTAL_GATE>; + clock-names = "mux", "div", "gate", "fdiv2", "xtal"; +}; + +&spicc0 { + clocks = <&clkc CLKID_SPICC_A_DIV>, <&clkc CLKID_SPICC_A_GATE>; + clock-names = "async", "async-gate"; + assigned-clocks = <&clkc CLKID_SPICC_A_MUX>, <&clkc CLKID_SPICC_A_DIV>; + assigned-clock-parents = <&clkc CLKID_FCLK_DIV2>; + assigned-clock-rates = <0>, <200000000>; + /* =PM_SPICC, no set for power on already */ + /* pm-id = <22>; */ +}; + +&spicc1 { + clocks = <&clkc CLKID_SPICC_B_DIV>, <&clkc CLKID_SPICC_B_GATE>; + clock-names = "async", "async-gate"; + assigned-clocks = <&clkc CLKID_SPICC_B_MUX>, <&clkc CLKID_SPICC_B_DIV>; + assigned-clock-parents = <&clkc CLKID_FCLK_DIV2>; + assigned-clock-rates = <0>, <200000000>; + /* =PM_SPICC_B, must set to power on */ + pm-id = <39>; +}; + +&pinctrl_periphs { + jtag_a_pins:jtag_a_pin { + mux { + groups = "jtag_a_clk", + "jtag_a_tms", + "jtag_a_tdi", + "jtag_a_tdo"; + function = "jtag_a"; + }; + }; + + jtag_b_pins:jtag_b_pin { + mux { + groups = "jtag_b_clk", + "jtag_b_tms", + "jtag_b_tdi", + "jtag_b_tdo"; + function = "jtag_b"; + }; + }; + + swd_a_pins:swd_a_pin { + mux { + groups = "swclk", + "swdio"; + function = "sw"; + }; + }; + + /*i2c0 pinmux*/ + i2c0_master_pins1:i2c0_pins1 { + mux { + groups = "i2c_a_scl_d", + "i2c_a_sda_d"; + function = "i2c_a"; + bias-disable; + drive-strength = <3>; + }; + }; + + i2c0_master_pins2:i2c0_pins2 { + mux { + groups = "i2c_a_scl_e", + "i2c_a_sda_e"; + function = "i2c_a"; + bias-disable; + drive-strength = <3>; + }; + }; + + /* i2c1 pinmux */ + i2c1_master_pins2:i2c1_pins2 { + mux { + groups = "i2c_b_scl_a", + "i2c_b_sda_a"; + function = "i2c_b"; + bias-disable; + drive-strength = <3>; + }; + }; + + i2c1_master_pins3:i2c1_pins3 { + mux { + groups = "i2c_b_scl_m", + "i2c_b_sda_m"; + function = "i2c_b"; + bias-disable; + drive-strength = <3>; + }; + }; + + /* i2c2 pinmux */ + i2c2_master_pins1:i2c2_pins1 { + mux { + groups = "i2c_c_scl_x", + "i2c_c_sda_x"; + function = "i2c_c"; + bias-disable; + drive-strength = <3>; + }; + }; + + i2c2_master_pins2:i2c2_pins2 { + mux { + groups = "i2c_c_scl_m", + "i2c_c_sda_m"; + function = "i2c_c"; + bias-disable; + drive-strength = <3>; + }; + }; + + i2c2_master_pins3:i2c2_pins3 { + mux { + groups = "i2c_c_scl_a", + "i2c_c_sda_a"; + function = "i2c_c"; + bias-disable; + drive-strength = <3>; + }; + }; + + /* i2c3 pinmux */ + i2c3_master_pins1:i2c3_pins1 { + mux { + groups = "i2c_d_scl_x", + "i2c_d_sda_x"; + function = "i2c_d"; + bias-disable; + drive-strength = <3>; + }; + }; + + i2c3_master_pins2:i2c3_pins2 { + mux { + groups = "i2c_d_scl_a", + "i2c_d_sda_a"; + function = "i2c_d"; + bias-disable; + drive-strength = <3>; + }; + }; + + i2c3_master_pins3:i2c3_pins3 { + mux { + groups = "i2c_d_scl_m", + "i2c_d_sda_m"; + function = "i2c_d"; + bias-disable; + drive-strength = <3>; + }; + }; + + /* i2c4 pinmux */ + i2c4_master_pins1:i2c4_pins1 { + mux { + groups = "i2c_e_scl_c", + "i2c_e_sda_c"; + function = "i2c_e"; + bias-disable; + drive-strength = <3>; + }; + }; + + i2c4_master_pins2:i2c4_pins2 { + mux { + groups = "i2c_e_scl_m", + "i2c_e_sda_m"; + function = "i2c_e"; + bias-disable; + drive-strength = <3>; + }; + }; + + i2c4_master_pins3:i2c4_pins3 { + mux { + groups = "i2c_e_scl_a", + "i2c_e_sda_a"; + function = "i2c_e"; + bias-disable; + drive-strength = <3>; + }; + }; + + pwm_a_pins1: pwm_a_pins1 { + mux { + groups = "pwm_a"; + function = "pwm_a"; + }; + }; + + pwm_b_pins1: pwm_b_pins1 { + mux { + groups = "pwm_b"; + function = "pwm_b"; + }; + }; + + pwm_c_pins1: pwm_c_pins1 { + mux { + groups = "pwm_c"; + function = "pwm_c"; + }; + }; + + pwm_d_pins1: pwm_d_pins1 { + mux { + groups = "pwm_d"; + function = "pwm_d"; + }; + }; + + pwm_e_pins1: pwm_e_pins1 { + mux { + groups = "pwm_e"; + function = "pwm_e"; + }; + }; + + pwm_f_pins1: pwm_f_pins1 { + mux { + groups = "pwm_f_d"; + function = "pwm_f"; + }; + }; + + pwm_f_pins2: pwm_f_pins2 { + mux { + groups = "pwm_f_m"; + function = "pwm_f"; + }; + }; + + pwm_f_pins3: pwm_f_pins3 { + mux { + groups = "pwm_f_x"; + function = "pwm_f"; + }; + }; + + pwm_g_pins1: pwm_g_pins1 { + mux { + groups = "pwm_g_d10"; + function = "pwm_g"; + }; + }; + + pwm_g_pins2: pwm_g_pins2 { + mux { + groups = "pwm_g_x"; + function = "pwm_g"; + }; + }; + + pwm_g_pins3: pwm_g_pins3 { + mux { + groups = "pwm_g_m"; + function = "pwm_g"; + }; + }; + + pwm_g_pins4: pwm_g_pins4 { + mux { + groups = "pwm_g_a7"; + function = "pwm_g"; + }; + }; + + pwm_g_pins5: pwm_g_pins5 { + mux { + groups = "pwm_g_a1"; + function = "pwm_g"; + }; + }; + + pwm_g_pins6: pwm_g_pins6 { + mux { + groups = "pwm_g_d12"; + function = "pwm_g"; + }; + }; + + pwm_g_pins7: pwm_g_pins7 { + mux { + groups = "pwm_g_d13"; + function = "pwm_g"; + }; + }; + + pwm_h_pins1: pwm_h_pins1 { + mux { + groups = "pwm_h_x"; + function = "pwm_h"; + }; + }; + + pwm_h_pins2: pwm_h_pins2 { + mux { + groups = "pwm_h_m"; + function = "pwm_h"; + }; + }; + + pwm_h_pins3: pwm_h_pins3 { + mux { + groups = "pwm_h_a8"; + function = "pwm_h"; + }; + }; + + pwm_h_pins4: pwm_h_pins4 { + mux { + groups = "pwm_h_a2"; + function = "pwm_h"; + }; + }; + + pwm_h_pins5: pwm_h_pins5 { + mux { + groups = "pwm_h_d"; + function = "pwm_h"; + }; + }; + + pwm_i_pins1: pwm_i_pins1 { + mux { + groups = "pwm_i_m"; + function = "pwm_i"; + }; + }; + + pwm_i_pins2: pwm_i_pins2 { + mux { + groups = "pwm_i_a9"; + function = "pwm_i"; + }; + }; + + pwm_i_pins3: pwm_i_pins3 { + mux { + groups = "pwm_i_a3"; + function = "pwm_i"; + }; + }; + + pwm_i_pins4: pwm_i_pins4 { + mux { + groups = "pwm_i_d"; + function = "pwm_i"; + }; + }; + + pwm_j_pins1: pwm_j_pins1 { + mux { + groups = "pwm_j_x"; + function = "pwm_j"; + }; + }; + + pwm_j_pins2: pwm_j_pins2 { + mux { + groups = "pwm_j_m"; + function = "pwm_j"; + }; + }; + + pwm_j_pins3: pwm_j_pins3 { + mux { + groups = "pwm_j_a10"; + function = "pwm_j"; + }; + }; + + pwm_j_pins4: pwm_j_pins4 { + mux { + groups = "pwm_j_a4"; + function = "pwm_j"; + }; + }; + + emmc_pins: emmc { + mux { + groups = "emmc_nand_d0", + "emmc_nand_d1", + "emmc_nand_d2", + "emmc_nand_d3", + "emmc_nand_d4", + "emmc_nand_d5", + "emmc_nand_d6", + "emmc_nand_d7", + "emmc_clk", + "emmc_cmd"; + function = "emmc"; + bias-pull-up; + input-enable; + drive-strength = <3>; + }; + mux1 { + groups = "emmc_nand_ds"; + function = "emmc"; + input-enable; + bias-pull-down; + drive-strength = <3>; + }; + }; + + emmc_clk_gate_pins: emmc_clk_gate { + mux { + groups = "emmc_clk"; + function = "emmc"; + bias-pull-down; + drive-strength = <3>; + }; + }; + + all_nand_pins: all_nand_pins { + mux { + groups = "emmc_nand_d0", + "emmc_nand_d1", + "emmc_nand_d2", + "emmc_nand_d3", + "emmc_nand_d4", + "emmc_nand_d5", + "emmc_nand_d6", + "emmc_nand_d7", + "nand_ce0", + "nand_ale", + "nand_cle", + "nand_wen_clk", + "nand_ren_wr"; + function = "nand"; + input-enable; + drive-strength = <4>; + }; + }; + + nand_cs_pins: nand_cs { + mux { + groups = "nand_ce0"; + function = "nand"; + }; + }; + + sdcard_pins: sdcard { + mux { + groups = "sdcard_d0", + "sdcard_d1", + "sdcard_d2", + "sdcard_d3", + "sdcard_cmd"; + function = "sdcard"; + bias-pull-up; + input-enable; + drive-strength = <4>; + }; + mux1 { + groups ="sdcard_clk"; + function = "sdcard"; + bias-pull-up; + output-high; + drive-strength = <4>; + }; + }; + + sdcard_clk_gate_pins: sdcard_clk_gate { + mux { + groups = "sdcard_clk"; + function = "sdcard"; + bias-pull-down; + drive-strength = <4>; + }; + }; + + to_sduart_pins: to_sduart_pins{ + mux { + groups = "uart_b_rx_c", "uart_b_tx_c"; + function = "uart_b"; + bias-pull-up; + input-enable; + }; + }; + + sd_to_uart_pins: sd_to_uart_pins{ + mux { + groups = "uart_b_rx_d", "uart_b_tx_d"; + function = "uart_b"; + bias-pull-up; + input-enable; + }; + }; + + spicc0_pins1: spicc0_pins1 { + mux { + groups = "spi_a_mosi_a", + "spi_a_miso_a", + "spi_a_sclk_a"; + function = "spi_a"; + drive-strength = <2>; + }; + }; + + spicc0_pins2: spicc0_pins2 { + mux { + groups = "spi_a_mosi_c", + "spi_a_miso_c", + "spi_a_sclk_c"; + function = "spi_a"; + drive-strength = <2>; + }; + }; + + spicc1_pins1: spicc1_pins1 { + mux { + groups = "spi_b_mosi_a", + "spi_b_miso_a", + "spi_b_sclk_a"; + function = "spi_b"; + drive-strength = <2>; + }; + }; + + spifc_pins: spifc_pins { + mux { + groups = "spif_mo", + "spif_mi", + "spif_clk", + "spif_cs", + "spif_hold", + "spif_wp_n"; + function = "spif"; + drive-strength = <4>; + }; + }; + external_eth_rmii_pins: external_eth_rmii_pins { + mux { + groups = "eth_mdio", + "eth_mdc", + "eth_rx_clk", + "eth_rx_dv", + "eth_rxd0", + "eth_rxd1", + "eth_txen", + "eth_txd0", + "eth_txd1"; + function = "eth"; + drive-strength = <3>; + }; + }; + external_eth_rgmii_pins: external_eth_rgmii_pins { + mux { + groups = "eth_mdio", + "eth_mdc", + "eth_rx_clk", + "eth_rx_dv", + "eth_rxd0", + "eth_rxd1", + "eth_rxd2_rgmii", + "eth_rxd3_rgmii", + "eth_tx_clk", + "eth_txen", + "eth_txd0", + "eth_txd1", + "eth_txd2_rgmii", + "eth_txd3_rgmii"; + function = "eth"; + drive-strength = <3>; + }; + }; +};
diff --git a/arch/arm/dts/meson-c2_skt-panel.dtsi b/arch/arm/dts/meson-c2_skt-panel.dtsi new file mode 100644 index 0000000..c3ac22e --- /dev/null +++ b/arch/arm/dts/meson-c2_skt-panel.dtsi
@@ -0,0 +1,742 @@ +/* + * arch/arm64/boot/dts/amlogic/meson-c2__skt-panel.dtsi + * + * Copyright (C) 2016 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/ { + lcd{ + compatible = "amlogic, lcd-g12a"; + mode = "tablet"; + status = "okay"; + key_valid = <0>; + /* + clocks = <&clkc CLKID_MIPI_DSI_HOST + &clkc CLKID_MIPI_DSI_PHY + &clkc CLKID_DSI_MEAS_COMP + &clkc CLKID_VCLK2_ENCL + &clkc CLKID_VCLK2_VENCL + &clkc CLKID_GP0_PLL>; + clock-names = "dsi_host_gate", + "dsi_phy_gate", + "dsi_meas", + "encl_top_gate", + "encl_int_gate", + "gp0_pll"; + */ + reg = <0x0 0xffd07000 0x0 0x400 /* dsi_host */ + 0x0 0xff644000 0x0 0x200>; /* dsi_phy */ + interrupts = <0 3 1 + 0 56 1>; + interrupt-names = "vsync","vsync2"; + pinctrl_version = <2>; /* for uboot */ + + /* power type: + * (0=cpu_gpio, 1=pmu_gpio, 2=signal,3=extern, 0xff=ending) + * power index: + * (point gpios_index, or extern_index,0xff=invalid) + * power value:(0=output low, 1=output high, 2=input) + * power delay:(unit in ms) + */ + + /*lcd_cpu-gpios = <&gpio GPIOZ_9 GPIO_ACTIVE_HIGH + &gpio GPIOZ_8 GPIO_ACTIVE_HIGH>; + */ + lcd_cpu_gpio_names = "GPIOZ_9","GPIOZ_8"; + + lcd_0{ + model_name = "B080XAN01"; + interface = "mipi"; + basic_setting = <768 1024 /*h_active, v_active*/ + 948 1140 /*h_period, v_period*/ + 8 /*lcd_bits*/ + 119 159>; /*screen_widht, screen_height*/ + lcd_timing = <64 56 0 /*hs_width, hs_bp, hs_pol*/ + 50 30 0>; /*vs_width, vs_bp, vs_pol*/ + clk_attr = <0 /*fr_adj_type(0=clk, 1=htotal, 2=vtotal)*/ + 0 /*clk_ss_level */ + 1 /*clk_auto_generate*/ + 64843200>; /*pixel_clk(unit in Hz)*/ + mipi_attr = <4 /*lane_num*/ + 550 /*bit_rate_max(MHz)*/ + 0 /*factor(*100, default 0 for auto)*/ + 1 /*operation_mode_init(0=video, 1=command)*/ + 0 /*operation_mode_display(0=video, 1=command)*/ + 2 /* + *video_mode_type + *(0=sync_pulse,1=sync_event,2=burst) + */ + 1 /*clk_always_hs(0=disable,1=enable)*/ + 0>; /*phy_switch(0=auto,1=standard,2=slow)*/ + + /* dsi_init: data_type, num, data... */ + dsi_init_on = <0x05 1 0x11 + 0xfd 1 20 /*delay(ms)*/ + 0x05 1 0x29 + 0xfd 1 20 /*delay(ms)*/ + 0xff 0>; /*ending*/ + dsi_init_off = <0x05 1 0x28 + 0xfd 1 10 /*delay(ms)*/ + 0x05 1 0x10 + 0xfd 1 10 /*delay(ms)*/ + 0xff 0>; /*ending*/ + extern_init = <0xff>; /*0xff for invalid*/ + + /* power step: type, index, value, delay(ms) */ + power_on_step = < + 0 1 0 100 + 0 0 0 10 + 0 0 1 20 + 2 0 0 0 + 0xff 0 0 0>; /*ending*/ + power_off_step = < + 2 0 0 50 + 0 0 0 10 + 0 1 1 100 + 0xff 0 0 0>; /*ending*/ + backlight_index = <0>; + }; + + lcd_1{ + model_name = "P070ACB_FT"; + interface = "mipi"; + basic_setting = <600 1024 /*h_active, v_active*/ + 770 1070 /*h_period, v_period*/ + 8 /*lcd_bits*/ + 3 5>; /*screen_widht, screen_height*/ + lcd_timing = <10 80 0 /*hs_width,hs_bp,hs_pol*/ + 6 20 0>; /*vs_width,vs_bp,vs_pol*/ + clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/ + 0 /*clk_ss_level*/ + 1 /*clk_auto_generate*/ + 49434000>; /*pixel_clk(unit in Hz)*/ + mipi_attr = <4 /*lane_num*/ + 400 /*bit_rate_max(MHz)*/ + 0 /*factor(*100, default 0 for auto)*/ + 1 /*operation_mode_init(0=video, 1=command)*/ + 0 /*operation_mode_display(0=video, 1=command)*/ + 2 /* + *video_mode_type + *(0=sync_pulse,1=sync_event,2=burst) + */ + 0 /*clk_always_hs(0=disable,1=enable)*/ + 0>; /*phy_switch(0=auto,1=standard,2=slow)*/ + /* dsi_init: data_type, num, data... */ + dsi_init_on = < + 0xff 10 + 0xf0 3 0 1 30 /* reset high, delay 30ms */ + 0xf0 3 0 0 10 /* reset low, delay 10ms */ + 0xf0 3 0 1 30 /* reset high, delay 30ms */ + 0xfc 2 0x04 3 /* check_reg, check_cnt */ + 0xff 0>; /* ending flag */ + dsi_init_off = <0xff 0>; /* ending flag */ + /* extern_init: 0xff for invalid */ + extern_init = <2>; + /* power step: type,index,value,delay(ms) */ + power_on_step = < + 0 1 0 200 /* panel power on */ + 2 0 0 0 + 0xff 0 0 0>; + power_off_step = < + 2 0 0 0 + 0 0 0 20 /* reset low */ + 0 1 1 100 /* panel power off */ + 0xff 0 0 0>; + backlight_index = <0>; + }; + + lcd_3{ + model_name = "TL050FHV02CT"; + interface = "mipi"; + basic_setting = <1080 1920 /*h_active, v_active*/ + 1125 2100 /*h_period, v_period*/ + 8 /*lcd_bits*/ + 65 119>; /*screen_widht, screen_height*/ + lcd_timing = <5 30 0 /*hs_width,hs_bp,hs_pol*/ + 44 108 0>; /*vs_width,vs_bp,vs_pol*/ + clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/ + 0 /*clk_ss_level*/ + 1 /*clk_auto_generate*/ + 118125000>; /*pixel_clk(unit in Hz)*/ + mipi_attr = <4 /*lane_num*/ + 960 /*bit_rate_max(MHz)*/ + 0 /*factor(*100, default 0 for auto)*/ + 1 /*operation_mode_init(0=video, 1=command)*/ + 0 /*operation_mode_display(0=video, 1=command)*/ + 2 /* + *video_mode_type + *(0=sync_pulse,1=sync_event,2=burst) + */ + 1 /*clk_always_hs(0=disable,1=enable)*/ + 0>; /*phy_switch(0=auto,1=standard,2=slow)*/ + /* dsi_init: data_type, num, data... */ + dsi_init_on = <0xff 0>; /* ending flag */ + dsi_init_off = <0xff 0>; /* ending flag */ + /* extern_init: 0xff for invalid */ + extern_init = <3>; + /* power step: type,index,value,delay(ms) */ + power_on_step = < + 0 1 0 200 + 0 0 1 20 + 0 0 0 10 + 0 0 1 20 + 2 0 0 0 + 0xff 0 0 0>; + power_off_step = < + 2 0 0 0 + 0 0 0 20 + 0 1 1 100 + 0xff 0 0 0>; + backlight_index = <0>; + }; + + lcd_4{ + model_name = "TL070WSH27"; + interface = "mipi"; + basic_setting = <1024 600 /*h_active, v_active*/ + 1250 630 /*h_period, v_period*/ + 8 /*lcd_bits*/ + 154 86>; /*screen_widht, screen_height*/ + lcd_timing = <80 100 0 /*hs_width, hs_bp, hs_pol*/ + 5 20 0>; /*vs_width, vs_bp, vs_pol*/ + clk_attr = <0 /*fr_adj_type(0=clk, 1=htotal, 2=vtotal)*/ + 0 /*clk_ss_level */ + 1 /*clk_auto_generate*/ + 47250000>; /*pixel_clk(unit in Hz)*/ + mipi_attr = <4 /*lane_num*/ + 300 /*bit_rate_max(MHz)*/ + 0 /*factor(*100, default 0 for auto)*/ + 1 /*operation_mode_init(0=video, 1=command)*/ + 0 /*operation_mode_display(0=video, 1=command)*/ + 2 /* + *video_mode_type + *(0=sync_pulse,1=sync_event,2=burst) + */ + 1 /*clk_always_hs(0=disable,1=enable)*/ + 0>; /*phy_switch(0=auto,1=standard,2=slow)*/ + + /* dsi_init: data_type, num, data... */ + dsi_init_on = <0x05 1 0x11 + 0xfd 1 20 /*delay(ms)*/ + 0x05 1 0x29 + 0xfd 1 20 /*delay(ms)*/ + 0xff 0>; /*ending*/ + dsi_init_off = <0x05 1 0x28 + 0xfd 1 10 /*delay(ms)*/ + 0x05 1 0x10 + 0xfd 1 10 /*delay(ms)*/ + 0xff 0>; /*ending*/ + extern_init = <0xff>; /*0xff for invalid*/ + + /* power step: type, index, value, delay(ms) */ + power_on_step = < + 0 1 0 100 + 0 0 0 10 + 0 0 1 20 + 2 0 0 0 + 0xff 0 0 0>; /*ending*/ + power_off_step = < + 2 0 0 50 + 0 0 0 10 + 0 1 1 100 + 0xff 0 0 0>; /*ending*/ + backlight_index = <0>; + }; + }; + + lcd_extern{ + compatible = "amlogic, lcd_extern"; + status = "okay"; + i2c_bus = "i2c_bus_0"; + key_valid = <0>; + + extern_0{ + index = <0>; + extern_name = "mipi_default";/*default*/ + status = "okay"; + type = <2>; /* 0=i2c, 1=spi, 2=mipi */ + cmd_size = <0xff>; + init_on = < + 0xfd 1 10 + 0x05 1 0x11 + 0xfd 1 120 /* delay 120ms */ + 0x05 1 0x29 + 0xff 0>; /*ending*/ + init_off = < + 0x05 1 0x28 /* display off */ + 0xfd 1 10 /* delay 10ms */ + 0x05 1 0x10 /* sleep in */ + 0xfd 1 150 /* delay 150ms */ + 0xff 0>; /*ending*/ + }; + + extern_2{ + index = <2>; + extern_name = "mipi_default";/*P070ACB_FT*/ + status = "okay"; + type = <2>; /* 0=i2c, 1=spi, 2=mipi */ + cmd_size = <0xff>; + init_on = < + 0x23 2 0xE0 0x00 /* Page 0 */ + 0x23 2 0xE1 0x93 /* PASSWORD */ + 0x23 2 0xE2 0x65 + 0x23 2 0xE3 0xF8 + 0x23 2 0x80 0x03 + 0x23 2 0xE0 0x01 /* Page 01 */ + 0x23 2 0x0C 0x74 /* Set PWRIC */ + 0x23 2 0x17 0x00 /* Set Gamma Power */ + 0x23 2 0x18 0xEF /* VGMP=5.1V */ + 0x23 2 0x19 0x00 + 0x23 2 0x1A 0x00 + 0x23 2 0x1B 0xEF /* VGMN=-5.1V */ + 0x23 2 0x1C 0x00 + 0x23 2 0x1F 0x70 /* Set Gate Power */ + 0x23 2 0x20 0x2D + 0x23 2 0x21 0x2D + 0x23 2 0x22 0x7E + 0x23 2 0x26 0xF3 /* VDDD from IOVCC */ + 0x23 2 0x37 0x09 /* SetPanel */ + 0x23 2 0x38 0x04 /* SET RGBCYC */ + 0x23 2 0x39 0x00 + 0x23 2 0x3A 0x01 + 0x23 2 0x3C 0x90 + 0x23 2 0x3D 0xFF + 0x23 2 0x3E 0xFF + 0x23 2 0x3F 0xFF + 0x23 2 0x40 0x02 /* Set TCON */ + 0x23 2 0x41 0x80 + 0x23 2 0x42 0x99 + 0x23 2 0x43 0x14 + 0x23 2 0x44 0x19 + 0x23 2 0x45 0x5A + 0x23 2 0x4B 0x04 + 0x23 2 0x55 0x02 /* power voltage */ + 0x23 2 0x56 0x01 + 0x23 2 0x57 0x69 + 0x23 2 0x58 0x0A + 0x23 2 0x59 0x0A + 0x23 2 0x5A 0x2E /* VGH = 16.2V */ + 0x23 2 0x5B 0x19 /* VGL = -12V */ + 0x23 2 0x5C 0x15 + 0x23 2 0x5D 0x77 /* Gamma */ + 0x23 2 0x5E 0x56 + 0x23 2 0x5F 0x45 + 0x23 2 0x60 0x38 + 0x23 2 0x61 0x35 + 0x23 2 0x62 0x27 + 0x23 2 0x63 0x2D + 0x23 2 0x64 0x18 + 0x23 2 0x65 0x33 + 0x23 2 0x66 0x34 + 0x23 2 0x67 0x35 + 0x23 2 0x68 0x56 + 0x23 2 0x69 0x45 + 0x23 2 0x6A 0x4F + 0x23 2 0x6B 0x42 + 0x23 2 0x6C 0x40 + 0x23 2 0x6D 0x34 + 0x23 2 0x6E 0x25 + 0x23 2 0x6F 0x02 + 0x23 2 0x70 0x77 + 0x23 2 0x71 0x56 + 0x23 2 0x72 0x45 + 0x23 2 0x73 0x38 + 0x23 2 0x74 0x35 + 0x23 2 0x75 0x27 + 0x23 2 0x76 0x2D + 0x23 2 0x77 0x18 + 0x23 2 0x78 0x33 + 0x23 2 0x79 0x34 + 0x23 2 0x7A 0x35 + 0x23 2 0x7B 0x56 + 0x23 2 0x7C 0x45 + 0x23 2 0x7D 0x4F + 0x23 2 0x7E 0x42 + 0x23 2 0x7F 0x40 + 0x23 2 0x80 0x34 + 0x23 2 0x81 0x25 + 0x23 2 0x82 0x02 + 0x23 2 0xE0 0x02 /* Page2 */ + 0x23 2 0x00 0x53 + /* GIP_L Pin mapping RESET_EVEN */ + 0x23 2 0x01 0x55 /* VSSG_EVEN */ + 0x23 2 0x02 0x55 /* VSSA_EVEN */ + 0x23 2 0x03 0x51 /* STV2_EVEN */ + 0x23 2 0x04 0x77 /* VDD2_EVEN */ + 0x23 2 0x05 0x57 /* VDD1_EVEN */ + 0x23 2 0x06 0x1F + 0x23 2 0x07 0x4F /* CK12 */ + 0x23 2 0x08 0x4D /* CK10 */ + 0x23 2 0x09 0x1F + 0x23 2 0x0A 0x4B /* CK8 */ + 0x23 2 0x0B 0x49 /* CK6 */ + 0x23 2 0x0C 0x1F + 0x23 2 0x0D 0x47 /* CK4 */ + 0x23 2 0x0E 0x45 /* CK2 */ + 0x23 2 0x0F 0x41 /* STV1_EVEN */ + 0x23 2 0x10 0x1F + 0x23 2 0x11 0x1F + 0x23 2 0x12 0x1F + 0x23 2 0x13 0x55 /* VGG */ + 0x23 2 0x14 0x1F + 0x23 2 0x15 0x1F + 0x23 2 0x16 0x52 + /* GIP_R Pin mapping RESET_ODD */ + 0x23 2 0x17 0x55 /* VSSG_ODD */ + 0x23 2 0x18 0x55 /* VSSA_ODD */ + 0x23 2 0x19 0x50 /* STV2_ODD */ + 0x23 2 0x1A 0x77 /* VDD2_ODD */ + 0x23 2 0x1B 0x57 /* VDD1_ODD */ + 0x23 2 0x1C 0x1F + 0x23 2 0x1D 0x4E /* CK11 */ + 0x23 2 0x1E 0x4C /* CK9 */ + 0x23 2 0x1F 0x1F + 0x23 2 0x20 0x4A /* CK7 */ + 0x23 2 0x21 0x48 /* CK5 */ + 0x23 2 0x22 0x1F + 0x23 2 0x23 0x46 /* CK3 */ + 0x23 2 0x24 0x44 /* CK1 */ + 0x23 2 0x25 0x40 /* STV1_ODD */ + 0x23 2 0x26 0x1F + 0x23 2 0x27 0x1F + 0x23 2 0x28 0x1F + 0x23 2 0x29 0x1F + 0x23 2 0x2A 0x1F + 0x23 2 0x2B 0x55 /* VGG */ + 0x23 2 0x2C 0x12 /* GIP_L_GS Pin mapping */ + 0x23 2 0x2D 0x15 + 0x23 2 0x2E 0x15 + 0x23 2 0x2F 0x00 + 0x23 2 0x30 0x37 + 0x23 2 0x31 0x17 + 0x23 2 0x32 0x1F + 0x23 2 0x33 0x08 + 0x23 2 0x34 0x0A + 0x23 2 0x35 0x1F + 0x23 2 0x36 0x0C + 0x23 2 0x37 0x0E + 0x23 2 0x38 0x1F + 0x23 2 0x39 0x04 + 0x23 2 0x3A 0x06 + 0x23 2 0x3B 0x10 + 0x23 2 0x3C 0x1F + 0x23 2 0x3D 0x1F + 0x23 2 0x3E 0x1F + 0x23 2 0x3F 0x15 + 0x23 2 0x40 0x1F + 0x23 2 0x41 0x1F + 0x23 2 0x42 0x13 /* GIP_R_GS Pin mapping */ + 0x23 2 0x43 0x15 + 0x23 2 0x44 0x15 + 0x23 2 0x45 0x01 + 0x23 2 0x46 0x37 + 0x23 2 0x47 0x17 + 0x23 2 0x48 0x1F + 0x23 2 0x49 0x09 + 0x23 2 0x4A 0x0B + 0x23 2 0x4B 0x1F + 0x23 2 0x4C 0x0D + 0x23 2 0x4D 0x0F + 0x23 2 0x4E 0x1F + 0x23 2 0x4F 0x05 + 0x23 2 0x50 0x07 + 0x23 2 0x51 0x11 + 0x23 2 0x52 0x1F + 0x23 2 0x53 0x1F + 0x23 2 0x54 0x1F + 0x23 2 0x55 0x1F + 0x23 2 0x56 0x1F + 0x23 2 0x57 0x15 + 0x23 2 0x58 0x40 /* GIP Timing */ + 0x23 2 0x59 0x00 + 0x23 2 0x5A 0x00 + 0x23 2 0x5B 0x10 + 0x23 2 0x5C 0x14 + 0x23 2 0x5D 0x40 + 0x23 2 0x5E 0x01 + 0x23 2 0x5F 0x02 + 0x23 2 0x60 0x40 + 0x23 2 0x61 0x03 + 0x23 2 0x62 0x04 + 0x23 2 0x63 0x7A + 0x23 2 0x64 0x7A + 0x23 2 0x65 0x74 + 0x23 2 0x66 0x16 + 0x23 2 0x67 0xB4 + 0x23 2 0x68 0x16 + 0x23 2 0x69 0x7A + 0x23 2 0x6A 0x7A + 0x23 2 0x6B 0x0C + 0x23 2 0x6C 0x00 + 0x23 2 0x6D 0x04 + 0x23 2 0x6E 0x04 + 0x23 2 0x6F 0x88 + 0x23 2 0x70 0x00 + 0x23 2 0x71 0x00 + 0x23 2 0x72 0x06 + 0x23 2 0x73 0x7B + 0x23 2 0x74 0x00 + 0x23 2 0x75 0xBC + 0x23 2 0x76 0x00 + 0x23 2 0x77 0x04 + 0x23 2 0x78 0x2C + 0x23 2 0x79 0x00 + 0x23 2 0x7A 0x00 + 0x23 2 0x7B 0x00 + 0x23 2 0x7C 0x00 + 0x23 2 0x7D 0x03 + 0x23 2 0x7E 0x7B + 0x23 2 0xE0 0x04 /* Page4 */ + 0x23 2 0x09 0x11 /* Set RGBCYC2 */ + 0x23 2 0x0E 0x48 + 0x23 2 0x2B 0x2B /* ESD Protect */ + 0x23 2 0x2E 0x44 + 0x23 2 0xE0 0x00 /* Page0 */ + 0x23 2 0xE6 0x02 /* Watch dog */ + 0x23 2 0xE7 0x0C + 0x05 1 0x11 /* sleep out */ + 0xfd 1 120 + 0x05 1 0x29 /* display on */ + 0x05 1 0x35 + 0xfd 1 20 /* delay(ms) */ + 0xFF 0>; /*ending*/ + init_off = < + 0x05 1 0x28 /* display off */ + 0xfd 1 10 /* delay 10ms */ + 0x05 1 0x10 /* sleep in */ + 0xfd 1 150 /* delay 150ms */ + 0xff 0>; /*ending*/ + }; + + extern_3{ + index = <3>; + extern_name = "mipi_default";/*TL050FHV02CT*/ + status = "okay"; + type = <2>; /* 0=i2c, 1=spi, 2=mipi */ + cmd_size = <0xff>; + init_on = < + 0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x03 + 0x29 10 0x90 0x03 0x14 0x09 0x00 0x00 + 0x00 0x38 0x00 0x00 + 0x29 10 0x91 0x00 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 + 0x29 12 0x92 0x40 0x0B 0x0C 0x0D 0x0E + 0x00 0x38 0x00 0x10 0x03 0x04 + 0x29 9 0x94 0x00 0x08 0x0B 0x03 0xD2 + 0x03 0xD3 0x0C + 0x29 17 0x95 0x00 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 + 0x29 3 0x99 0x00 0x00 + 0x29 12 0x9A 0x00 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 0x00 0x00 + 0x29 7 0x9B 0x01 0x38 0x00 0x00 0x00 0x00 + 0x29 3 0x9C 0x00 0x00 + 0x29 9 0x9D 0x10 0x10 0x10 0x10 0x10 + 0x10 0x00 0x00 + 0x29 3 0x9E 0x00 0x00 + 0x29 11 0xA0 0x9F 0x1F 0x08 0x1F 0x0A + 0x1F 0x00 0x1F 0x14 0x1F + 0x29 11 0xA1 0x15 0x1F 0x1F 0x1F 0x1F + 0x1F 0x1F 0x1F 0x1F 0x1F + 0x29 11 0xA2 0x1F 0x1F 0x1F 0x1F 0x1F + 0x1F 0x1F 0x1F 0x1F 0x1F + 0x29 11 0xA4 0x1F 0x1F 0x1F 0x1F 0x1F + 0x1F 0x1F 0x1F 0x1F 0x1F + 0x29 11 0xA5 0x1F 0x1F 0x1F 0x1F 0x1F + 0x1F 0x1F 0x1F 0x1F 0x15 + 0x29 11 0xA6 0x1F 0x14 0x1F 0x01 0x1F + 0x0B 0x1F 0x09 0x1F 0x1F + 0x29 11 0xA7 0x1F 0x1F 0x0B 0x1F 0x09 + 0x1F 0x01 0x1F 0x15 0x1F + 0x29 11 0xA8 0x14 0x1F 0x1F 0x1F 0x1F + 0x1F 0x1F 0x1F 0x1F 0x1F + 0x29 11 0xA9 0x1F 0x1F 0x1F 0x1F 0x1F + 0x1F 0x1F 0x1F 0x1F 0x1F + 0x29 11 0xAB 0x1F 0x1F 0x1F 0x1F 0x1F + 0x1F 0x1F 0x1F 0x1F 0x1F + 0x29 11 0xAC 0x1F 0x1F 0x1F 0x1F 0x1F + 0x1F 0x1F 0x1F 0x1F 0x14 + 0x29 11 0xAD 0x1F 0x15 0x1F 0x00 0x1F + 0x08 0x1F 0x0A 0x1F 0x1F + 0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x00 + 0x29 4 0xBC 0x00 0x00 0x00 + 0x29 5 0xB8 0x01 0xAF 0x8F 0x8F + 0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x01 + 0x29 17 0xD1 0x00 0x00 0x00 0x09 0x00 + 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D + 0x00 0x79 0x00 0xA7 + 0x29 17 0xD2 0x00 0xCF 0x01 0x12 0x01 + 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED + 0x02 0x2F 0x02 0x74 + 0x29 17 0xD3 0x02 0x9F 0x02 0xD5 0x02 + 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73 + 0x03 0x8C 0x03 0xA5 + 0x29 5 0xD4 0x03 0xC5 0x03 0xFF + 0x29 17 0xD5 0x00 0x00 0x00 0x09 0x00 + 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D + 0x00 0x79 0x00 0xA7 + 0x29 17 0xD6 0x00 0xCF 0x01 0x12 0x01 + 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED + 0x02 0x2F 0x02 0x74 + 0x29 17 0xD7 0x02 0x9F 0x02 0xD5 0x02 + 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73 + 0x03 0x8C 0x03 0xA5 + 0x29 5 0xD8 0x03 0xC5 0x03 0xFF + 0x29 17 0xD9 0x00 0x00 0x00 0x09 0x00 + 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D + 0x00 0x79 0x00 0xA7 + 0x29 17 0xDD 0x00 0xCF 0x01 0x12 0x01 + 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED + 0x02 0x2F 0x02 0x74 + 0x29 17 0xDE 0x02 0x9F 0x02 0xD5 0x02 + 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73 + 0x03 0x8C 0x03 0xA5 + 0x29 5 0xDF 0x03 0xC5 0x03 0xFF + 0x29 17 0xE0 0x00 0x00 0x00 0x09 0x00 + 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D + 0x00 0x79 0x00 0xA7 + 0x29 17 0xE1 0x00 0xCF 0x01 0x12 0x01 + 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED + 0x02 0x2F 0x02 0x74 + 0x29 17 0xE2 0x02 0x9F 0x02 0xD5 0x02 + 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73 + 0x03 0x8C 0x03 0xA5 + 0x29 5 0xE3 0x03 0xC5 0x03 0xFF + 0x29 17 0xE4 0x00 0x00 0x00 0x09 0x00 + 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D + 0x00 0x79 0x00 0xA7 + 0x29 17 0xE5 0x00 0xCF 0x01 0x12 0x01 + 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED + 0x02 0x2F 0x02 0x74 + 0x29 17 0xE6 0x02 0x9F 0x02 0xD5 0x02 + 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73 + 0x03 0x8C 0x03 0xA5 + 0x29 5 0xE7 0x03 0xC5 0x03 0xFF + 0x29 17 0xE8 0x00 0x00 0x00 0x09 0x00 + 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D + 0x00 0x79 0x00 0xA7 + 0x29 17 0xE9 0x00 0xCF 0x01 0x12 0x01 + 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED + 0x02 0x2F 0x02 0x74 + 0x29 17 0xEA 0x02 0x9F 0x02 0xD5 0x02 + 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73 + 0x03 0x8C 0x03 0xA5 + 0x29 5 0xEB 0x03 0xC5 0x03 0xFF + 0x29 4 0xB0 0x05 0x05 0x05 + 0x29 4 0xB1 0x05 0x05 0x05 + 0x29 4 0xB3 0x10 0x10 0x10 + 0x29 4 0xB4 0x06 0x06 0x06 + 0x29 4 0xB6 0x44 0x44 0x44 + 0x29 4 0xB7 0x34 0x34 0x34 + 0x29 4 0xB8 0x34 0x34 0x34 + 0x29 4 0xB9 0x24 0x24 0x24 + 0x29 4 0xBA 0x24 0x24 0x24 + 0x29 4 0xBC 0x00 0x70 0x00 + 0x29 4 0xBD 0x00 0x70 0x00 + 0x23 2 0xBE 0x50 + 0x23 2 0x35 0x00 + 0x13 1 0x11 + 0xfd 1 200 + 0x13 1 0x29 + 0xfd 1 200 + 0xFF 0>; /*ending*/ + init_off = < + 0x05 1 0x28 /* display off */ + 0xfd 1 10 /* delay 10ms */ + 0x05 1 0x10 /* sleep in */ + 0xfd 1 150 /* delay 150ms */ + 0xff 0>; /*ending*/ + }; + }; + + backlight{ + compatible = "amlogic, backlight-g12a"; + status = "okay"; + key_valid = <0>; + pinctrl-names = "pwm_on","pwm_off"; + /* pinctrl-0 = <&pwm_f_pins2>; */ + /* pinctrl-1 = <&bl_pwm_off_pins>; */ + pinctrl_version = <2>; /* for uboot */ + bl_pwm_config = <&bl_pwm_conf>; + /*bl-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_HIGH + &gpio GPIOH_5 GPIO_ACTIVE_HIGH>;*/ + bl_gpio_names = "GPIOH_4","GPIOH_5"; + + /* pwm port: PWM_A, PWM_B, PWM_C, PWM_D, PWM_E, PWM_F, PWM_VS*/ + /* power index:(point gpios_index, 0xff=invalid) + * power value:(0=output low, 1=output high, 2=input) + * power delay:(unit in ms) + */ + + backlight_0{ + index = <0>; + bl_name = "backlight_pwm"; + bl_level_default_uboot_kernel = <100 100>; + bl_level_attr = <255 10 /*max, min*/ + 128 128>; /*mid, mid_mapping*/ + bl_ctrl_method = <1>; /* 1=pwm, 2=pwm_combo, 4=extern */ + bl_power_attr = <0 /*en_gpio_index*/ + 1 0 /*on_value, off_value*/ + 200 200>; /*on_delay(ms), off_delay(ms)*/ + bl_pwm_port = "PWM_F"; + bl_pwm_attr = <0 /*pwm_method*/ + 180 /*pwm_freq(pwm:Hz, pwm_vs:multiple of vs)*/ + 100 25>; /*duty_max(%), duty_min(%)*/ + bl_pwm_power = <1 1 /*pwm_gpio_index, pwm_gpio_off*/ + 10 10>; /*pwm_on_delay(ms), pwm_off_delay(ms)*/ + bl_pwm_en_sequence_reverse = <0>; /* 1 for reverse */ + }; + backlight_1{ + index = <1>; + bl_name = "bl_extern"; + bl_level_default_uboot_kernel = <100 100>; + bl_level_attr = <255 10 /*max, min*/ + 128 128>; /*mid, mid_mapping*/ + bl_ctrl_method = <4>; /*1=pwm, 2=pwm_combo, 4=extern*/ + bl_power_attr = <1 /*en_gpio_index*/ + 1 0 /*on_value, off_value*/ + 200 200>; /*on_delay(ms), off_delay(ms)*/ + bl_extern_index = <0>; + }; + }; + bl_pwm_conf:bl_pwm_conf{ + pwm_channel_0 { + pwm_port_index = <5>; + pwms = <&pwm_ef MESON_PWM_1 30040 0>; + }; + }; + + bl_extern{ + compatible = "amlogic, bl_extern"; + status = "disabled"; + i2c_bus = "i2c_bus_3"; + + extern_0{ + index = <0>; + extern_name = "i2c_lp8556"; + type = <0>; /*0=i2c, 1=spi, 2=mipi*/ + i2c_address = <0x2c>; /*7bit i2c address*/ + dim_max_min = <255 10>; + }; + + extern_1{ + index = <1>; + extern_name = "mipi_lt070me05"; + type = <2>; /*0=i2c, 1=spi, 2=mipi*/ + dim_max_min = <255 10>; + }; + }; +};/* end of panel */ +
diff --git a/arch/arm/dts/meson-g12.dtsi b/arch/arm/dts/meson-g12.dtsi index 52ecf7c..45bb2e9 100644 --- a/arch/arm/dts/meson-g12.dtsi +++ b/arch/arm/dts/meson-g12.dtsi
@@ -330,14 +330,10 @@ status = "disabled"; spi-flash@0 { compatible = "spi-flash"; - #address-cells = <1>; - #size-cells = <0>; status = "disabled"; }; spi-nand@1 { compatible = "spi-nand"; - #address-cells = <1>; - #size-cells = <0>; status = "disabled"; }; }; @@ -391,12 +387,12 @@ }; }; - aobus: aobus@ff800000 { + aobus: aobus@fe000000 { compatible = "simple-bus"; - reg = <0x0 0xff800000 0x0 0x100000>; + reg = <0x0 0xfe000000 0x0 0x100000>; #address-cells = <2>; #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; + ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x100000>; clkc_AO: clock-controller@0 { compatible = "amlogic,g12a-aoclkc"; @@ -404,9 +400,9 @@ #clock-cells = <1>; }; - uart_AO: serial@3000 { + uart_AO: serial@1c00 { compatible = "amlogic,meson-uart"; - reg = <0x0 0x3000 0x0 0x14>; + reg = <0x0 0x1c00 0x0 0x14>; interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; clocks = <&xtal>; status = "disabled"; @@ -507,7 +503,7 @@ }; nand: nfc@ffe07800 { - compatible = "amlogic,meson-g12a-nfc"; + compatible = "amlogic,meson-nfc"; reg = <0x0 0xFFE07800 0x0 0x200>; interrupts = <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>; status = "disabled"; @@ -521,21 +517,21 @@ #size-cells = <2>; ranges = <0x0 0x0 0x0 0xffe01000 0x0 0x7f000>; - sd_emmc_a: mmc@2000 { + sd_emmc_a: sdio { compatible = ""; reg = <0x0 0x2000 0x0 0x800>; interrupts = <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>; status = "disabled"; }; - sd_emmc_b: mmc@4000 { + sd_emmc_b: sd { compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; reg = <0x0 0x4000 0x0 0x800>; interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>; status = "disabled"; }; - sd_emmc_c: mmc@6000 { + sd_emmc_c: emmc { compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; reg = <0x0 0x6000 0x0 0x800>; interrupts = <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>;
diff --git a/arch/arm/dts/meson-g12a-s905d2-u200.dtsi b/arch/arm/dts/meson-g12a-s905d2-u200.dtsi old mode 100644 new mode 100755 index 60b5e01..839642b --- a/arch/arm/dts/meson-g12a-s905d2-u200.dtsi +++ b/arch/arm/dts/meson-g12a-s905d2-u200.dtsi
@@ -117,6 +117,7 @@ disable-wp; pinname = "sdio"; + card_type = <3>; mmc-pwrseq = <&sdio_pwrseq>; vmmc-supply = <&vddao_3v3>; @@ -135,6 +136,7 @@ disable-wp; pinname = "sd"; + card_type = <5>; init_co_phase = <3>; init_tx_phase = <0>; sd_hs_co_phase = <2>; @@ -142,7 +144,7 @@ sdr104_co_phase = <2>; sdr104_hs_tx_phase = <0>; - cd-detect = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>; + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>; /* cd-inverted; */ vmmc-supply = <&vddao_3v3>; @@ -165,7 +167,7 @@ mmc-hs200-1_8v; pinname = "emmc"; - + card_type = <1>; init_co_phase = <3>; init_tx_phase = <0>; hs_co_phase = <3>; @@ -239,11 +241,14 @@ &usb2_phy_v2 { status = "okay"; portnum = <2>; + dwc2_a_reg = <0xff400000>; }; &usb3_phy_v2 { status = "okay"; portnum = <0>; + gpio-vbus-power = "GPIOH_6"; + gpios = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>; }; &pwm_ef {
diff --git a/arch/arm/dts/meson-g12a-s905d3-elaine-b1.dts b/arch/arm/dts/meson-g12a-s905d3-elaine-b1.dts deleted file mode 100644 index d178c2f..0000000 --- a/arch/arm/dts/meson-g12a-s905d3-elaine-b1.dts +++ /dev/null
@@ -1,93 +0,0 @@ -/* - * Copyright (c) 2016 Endless Computers, Inc. - * Author: Carlo Caione <carlo@endlessm.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "meson-g12a-s905d2-u200.dtsi" -#include "elaine-b1-panel.dtsi" - -/ { - compatible = "amlogic,u200", "amlogic,s905d2", "amlogic,meson-g12a"; - model = "Amlogic Meson G12A (S905D2) U200 Development Board"; -}; - -/* This UART is brought out to the DB9 connector */ -&uart_AO { - status = "okay"; -}; - -&saradc { - status = "okay"; -}; - -/* demo for i2c user */ -&i2c2 { - status= "okay"; - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_master_pins2>; -}; - -&i2c3 { - status= "okay"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_master_pins2>; -}; - -&i2c_AO { - status= "okay"; - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&ao_i2c_master_pins1>; -}; - -&pinctrl_periphs { - bl_pwm_off_pins:bl_pwm_off_pin { - mux { - groups = "GPIOH_5"; - function = "gpio_periphs"; - output-high; - }; - }; -}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-g12a-s905d3-elaine-bx.dts b/arch/arm/dts/meson-g12a-s905d3-elaine-bx.dts deleted file mode 100644 index e292ea7..0000000 --- a/arch/arm/dts/meson-g12a-s905d3-elaine-bx.dts +++ /dev/null
@@ -1,93 +0,0 @@ -/* - * Copyright (c) 2016 Endless Computers, Inc. - * Author: Carlo Caione <carlo@endlessm.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "meson-g12a-s905d2-u200.dtsi" -#include "elaine-bx-panel.dtsi" - -/ { - compatible = "amlogic,u200", "amlogic,s905d2", "amlogic,meson-g12a"; - model = "Amlogic Meson G12A (S905D2) U200 Development Board"; -}; - -/* This UART is brought out to the DB9 connector */ -&uart_AO { - status = "okay"; -}; - -&saradc { - status = "okay"; -}; - -/* demo for i2c user */ -&i2c2 { - status= "okay"; - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_master_pins2>; -}; - -&i2c3 { - status= "okay"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_master_pins2>; -}; - -&i2c_AO { - status= "okay"; - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&ao_i2c_master_pins1>; -}; - -&pinctrl_periphs { - bl_pwm_off_pins:bl_pwm_off_pin { - mux { - groups = "GPIOH_5"; - function = "gpio_periphs"; - output-high; - }; - }; -}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-g12a-s905d3-elaine-p0.dts b/arch/arm/dts/meson-g12a-s905d3-elaine-p0.dts deleted file mode 100644 index ab7ec65..0000000 --- a/arch/arm/dts/meson-g12a-s905d3-elaine-p0.dts +++ /dev/null
@@ -1,93 +0,0 @@ -/* - * Copyright (c) 2016 Endless Computers, Inc. - * Author: Carlo Caione <carlo@endlessm.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "meson-g12a-s905d2-u200.dtsi" -#include "elaine-p0-panel.dtsi" - -/ { - compatible = "amlogic,u200", "amlogic,s905d2", "amlogic,meson-g12a"; - model = "Amlogic Meson G12A (S905D2) U200 Development Board"; -}; - -/* This UART is brought out to the DB9 connector */ -&uart_AO { - status = "okay"; -}; - -&saradc { - status = "okay"; -}; - -/* demo for i2c user */ -&i2c2 { - status= "okay"; - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_master_pins2>; -}; - -&i2c3 { - status= "okay"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_master_pins2>; -}; - -&i2c_AO { - status= "okay"; - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&ao_i2c_master_pins1>; -}; - -&pinctrl_periphs { - bl_pwm_off_pins:bl_pwm_off_pin { - mux { - groups = "GPIOH_5"; - function = "gpio_periphs"; - output-high; - }; - }; -}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-g12a-s905d3-elaine-p1.dts b/arch/arm/dts/meson-g12a-s905d3-elaine-p1.dts deleted file mode 100644 index f13a466..0000000 --- a/arch/arm/dts/meson-g12a-s905d3-elaine-p1.dts +++ /dev/null
@@ -1,93 +0,0 @@ -/* - * Copyright (c) 2016 Endless Computers, Inc. - * Author: Carlo Caione <carlo@endlessm.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "meson-g12a-s905d2-u200.dtsi" -#include "elaine-p1-panel.dtsi" - -/ { - compatible = "amlogic,u200", "amlogic,s905d2", "amlogic,meson-g12a"; - model = "Amlogic Meson G12A (S905D2) U200 Development Board"; -}; - -/* This UART is brought out to the DB9 connector */ -&uart_AO { - status = "okay"; -}; - -&saradc { - status = "okay"; -}; - -/* demo for i2c user */ -&i2c2 { - status= "okay"; - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_master_pins2>; -}; - -&i2c3 { - status= "okay"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_master_pins2>; -}; - -&i2c_AO { - status= "okay"; - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&ao_i2c_master_pins1>; -}; - -&pinctrl_periphs { - bl_pwm_off_pins:bl_pwm_off_pin { - mux { - groups = "GPIOH_5"; - function = "gpio_periphs"; - output-high; - }; - }; -}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-g12a-s905d3-elaine-p2.dts b/arch/arm/dts/meson-g12a-s905d3-elaine-p2.dts deleted file mode 100644 index 128e48e..0000000 --- a/arch/arm/dts/meson-g12a-s905d3-elaine-p2.dts +++ /dev/null
@@ -1,93 +0,0 @@ -/* - * Copyright (c) 2016 Endless Computers, Inc. - * Author: Carlo Caione <carlo@endlessm.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "meson-g12a-s905d2-u200.dtsi" -#include "elaine-p2-panel.dtsi" - -/ { - compatible = "amlogic,u200", "amlogic,s905d2", "amlogic,meson-g12a"; - model = "Amlogic Meson G12A (S905D2) U200 Development Board"; -}; - -/* This UART is brought out to the DB9 connector */ -&uart_AO { - status = "okay"; -}; - -&saradc { - status = "okay"; -}; - -/* demo for i2c user */ -&i2c2 { - status= "okay"; - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_master_pins2>; -}; - -&i2c3 { - status= "okay"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_master_pins2>; -}; - -&i2c_AO { - status= "okay"; - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&ao_i2c_master_pins1>; -}; - -&pinctrl_periphs { - bl_pwm_off_pins:bl_pwm_off_pin { - mux { - groups = "GPIOH_5"; - function = "gpio_periphs"; - output-high; - }; - }; -}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-g12a.dtsi b/arch/arm/dts/meson-g12a.dtsi index 4280551..5f1902b 100644 --- a/arch/arm/dts/meson-g12a.dtsi +++ b/arch/arm/dts/meson-g12a.dtsi
@@ -69,7 +69,7 @@ meson-fb { status = "okay"; - logo_addr = "0x5f800000"; + logo_addr = "0x7f800000"; }; }; @@ -145,7 +145,7 @@ groups = "i2c_ao_sck", "i2c_ao_sda"; function = "i2c_ao"; - drive-strength = <2>; + drive-strength = <3>; }; }; @@ -154,7 +154,7 @@ groups = "i2c_ao_sck_e", "i2c_ao_sda_e"; function = "i2c_ao"; - drive-strength = <2>; + drive-strength = <3>; }; }; @@ -323,14 +323,14 @@ function = "sdcard"; input-enable; bias-pull-up; - drive-strength = <3>; + drive-strength = <4>; }; mux1 { groups = "sdcard_clk_c"; function = "sdcard"; bias-pull-up; output-high; - drive-strength = <3>; + drive-strength = <4>; }; }; @@ -344,14 +344,14 @@ function = "sdcard"; input-enable; bias-pull-up; - drive-strength = <3>; + drive-strength = <4>; }; mux1 { groups = "sdcard_clk_c"; function = "sdcard"; bias-pull-up; output-high; - drive-strength = <3>; + drive-strength = <4>; }; }; @@ -362,14 +362,14 @@ function = "sdcard"; input-enable; bias-pull-up; - drive-strength = <3>; + drive-strength = <4>; }; mux1 { groups = "sdcard_clk_c"; function = "sdcard"; bias-pull-up; output-high; - drive-strength = <3>; + drive-strength = <4>; }; }; @@ -419,7 +419,7 @@ function = "sdio"; input-enable; bias-pull-up; - drive-strength = <3>; + drive-strength = <4>; }; }; @@ -434,7 +434,7 @@ function = "sdio"; input-enable; bias-pull-up; - drive-strength = <3>; + drive-strength = <4>; }; }; @@ -444,14 +444,14 @@ function = "gpio_periphs"; input-enable; bias-pull-up; - drive-strength = <3>; + drive-strength = <4>; }; mux1 { groups = "GPIOX_4"; function = "gpio_periphs"; bias-pull-up; output-high; - drive-strength = <3>; + drive-strength = <4>; }; }; @@ -465,14 +465,14 @@ function = "gpio_periphs"; input-enable; bias-pull-up; - drive-strength = <3>; + drive-strength = <4>; }; mux1 { groups = "GPIOX_4"; function = "gpio_periphs"; bias-pull-up; output-high; - drive-strength = <3>; + drive-strength = <4>; }; }; @@ -532,7 +532,7 @@ groups = "i2c0_sda_c", "i2c0_sck_c"; function = "i2c0"; - drive-strength = <2>; + drive-strength = <3>; }; }; @@ -541,7 +541,7 @@ groups = "i2c0_sda_z0", "i2c0_sck_z1"; function = "i2c0"; - drive-strength = <2>; + drive-strength = <3>; }; }; @@ -550,7 +550,7 @@ groups = "i2c0_sda_z7", "i2c0_sck_z8"; function = "i2c0"; - drive-strength = <2>; + drive-strength = <3>; }; }; @@ -559,7 +559,7 @@ groups = "i2c1_sda_x", "i2c1_sck_x"; function = "i2c1"; - drive-strength = <2>; + drive-strength = <3>; }; }; @@ -568,7 +568,7 @@ groups = "i2c1_sda_h2", "i2c1_sck_h3"; function = "i2c1"; - drive-strength = <2>; + drive-strength = <3>; }; }; @@ -577,7 +577,7 @@ groups = "i2c1_sda_h6", "i2c1_sck_h7"; function = "i2c1"; - drive-strength = <2>; + drive-strength = <3>; }; }; @@ -586,7 +586,7 @@ groups = "i2c2_sda_x", "i2c2_sck_x"; function = "i2c2"; - drive-strength = <2>; + drive-strength = <3>; }; }; @@ -595,7 +595,7 @@ groups = "i2c2_sda_z", "i2c2_sck_z"; function = "i2c2"; - drive-strength = <2>; + drive-strength = <3>; }; }; @@ -604,7 +604,7 @@ groups = "i2c3_sda_h", "i2c3_sck_h"; function = "i2c3"; - drive-strength = <2>; + drive-strength = <3>; }; }; @@ -613,7 +613,7 @@ groups = "i2c3_sda_a", "i2c3_sck_a"; function = "i2c3"; - drive-strength = <2>; + drive-strength = <3>; }; }; @@ -700,7 +700,7 @@ "spi0_miso_x", "spi0_clk_x"; function = "spi0"; - drive-strength = <1>; + drive-strength = <2>; }; }; @@ -710,7 +710,7 @@ "spi0_miso_c", "spi0_clk_c"; function = "spi0"; - drive-strength = <1>; + drive-strength = <2>; }; }; @@ -720,7 +720,7 @@ "spi1_miso", "spi1_clk"; function = "spi1"; - drive-strength = <1>; + drive-strength = <2>; }; }; @@ -732,7 +732,7 @@ "nor_hold", "nor_wp"; function = "nor"; - drive-strength = <3>; + drive-strength = <4>; }; }; @@ -784,7 +784,7 @@ "hdmitx_sck"; function = "hdmitx"; bias-disable; - drive-strength = <3>; + drive-strength = <4>; }; }; @@ -837,7 +837,7 @@ "eth_txd2_rgmii", "eth_txd3_rgmii"; function = "eth"; - drive-strength = <3>; + drive-strength = <4>; }; }; }; @@ -916,30 +916,22 @@ <&clkc CLKID_SD_EMMC_C_P0_DIV>, <&clkc CLKID_SD_EMMC_C_P0_GATE>; clock-names = "clkin", "clkin1", "clkin2", "clkin3"; - /*amlogic,mmc-syscon = <&sd_emmc_c>;*/ }; -/* &spicc0 { - clocks = <&clkc CLKID_SPICC0>, - <&clkc CLKID_SPICC0_COMP>; - clock-names = "core", "comp"; + clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_SPICC0>, + <&clkc CLKID_SPICC0_DIV>, <&clkc CLKID_SPICC0_GATE>; + clock-names = "core", "core-gate", "async", "async-gate"; + assigned-clocks = <&clkc CLKID_SPICC0_MUX>, <&clkc CLKID_SPICC0_DIV>; + assigned-clock-parents = <&clkc CLKID_FCLK_DIV2>; + assigned-clock-rates = <0>, <200000000>; }; &spicc1 { - clocks = <&clkc CLKID_SPICC1>, - <&clkc CLKID_SPICC1_COMP>; - clock-names = "core", "comp"; - }; -*/ - -&usb2_phy_v2 { - pll-setting-1 = <0x09400414>; - pll-setting-2 = <0x927E0000>; - pll-setting-3 = <0xac5f49e5>; - pll-setting-4 = <0xfe18>; - pll-setting-5 = <0x8000fff>; - pll-setting-6 = <0x78000>; - pll-setting-7 = <0xe0004>; - pll-setting-8 = <0xe000c>; + clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_SPICC1>, + <&clkc CLKID_SPICC1_DIV>, <&clkc CLKID_SPICC1_GATE>; + clock-names = "core", "core-gate", "async", "async-gate"; + assigned-clocks = <&clkc CLKID_SPICC1_MUX>, <&clkc CLKID_SPICC1_DIV>; + assigned-clock-parents = <&clkc CLKID_FCLK_DIV2>; + assigned-clock-rates = <0>, <200000000>; };
diff --git a/arch/arm/dts/meson-g12b-a311d-w400.dtsi b/arch/arm/dts/meson-g12b-a311d-w400.dtsi old mode 100644 new mode 100755 index 28fa8aa..a19771a --- a/arch/arm/dts/meson-g12b-a311d-w400.dtsi +++ b/arch/arm/dts/meson-g12b-a311d-w400.dtsi
@@ -117,6 +117,7 @@ disable-wp; pinname = "sdio"; + card_type = <3>; mmc-pwrseq = <&sdio_pwrseq>; vmmc-supply = <&vddao_3v3>; @@ -135,6 +136,7 @@ disable-wp; pinname = "sd"; + card_type = <5>; init_co_phase = <2>; init_tx_phase = <0>; sd_hs_co_phase = <2>; @@ -142,7 +144,7 @@ sdr104_co_phase = <2>; sdr104_hs_tx_phase = <0>; - cd-detect = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>; + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>; /* cd-inverted; */ vmmc-supply = <&vddao_3v3>; @@ -165,6 +167,7 @@ mmc-hs200-1_8v; pinname = "emmc"; + card_type = <1>; init_co_phase = <2>; init_tx_phase = <0>; hs_co_phase = <1>; @@ -188,6 +191,7 @@ &usb2_phy_v2 { status = "okay"; portnum = <2>; + dwc2_a_reg = <0xff400000>; }; &usb3_phy_v2 {
diff --git a/arch/arm/dts/meson-g12b-t931-newman.dts b/arch/arm/dts/meson-g12b-t931-newman.dts deleted file mode 100644 index 4a07011..0000000 --- a/arch/arm/dts/meson-g12b-t931-newman.dts +++ /dev/null
@@ -1,93 +0,0 @@ -/* - * Copyright (c) 2016 Endless Computers, Inc. - * Author: Carlo Caione <carlo@endlessm.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "meson-g12b-t931.dtsi" -#include "newman-panel.dtsi" - -/ { - compatible = "amlogic,newman", "amlogic,t931", "amlogic,meson-g12b"; - model = "Amlogic Meson G12B (T931) Newman Development Board"; -}; - -/* This UART is brought out to the DB9 connector */ -&uart_AO { - status = "okay"; -}; - -&saradc { - status = "okay"; -}; - -/* demo for i2c user */ -&i2c2 { - status= "okay"; - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_master_pins2>; -}; - -&i2c3 { - status= "okay"; - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_master_pins2>; -}; - -&i2c_AO { - status= "okay"; - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&ao_i2c_master_pins1>; -}; - -&pinctrl_periphs { - bl_pwm_off_pins:bl_pwm_off_pin { - mux { - groups = "GPIOH_5"; - function = "gpio_periphs"; - output-high; - }; - }; -}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-g12b-t931-puddy.dts b/arch/arm/dts/meson-g12b-t931-puddy.dts deleted file mode 100644 index 37db120..0000000 --- a/arch/arm/dts/meson-g12b-t931-puddy.dts +++ /dev/null
@@ -1,93 +0,0 @@ -/* - * Copyright (c) 2016 Endless Computers, Inc. - * Author: Carlo Caione <carlo@endlessm.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "meson-g12b-t931.dtsi" -#include "puddy-panel.dtsi" - -/ { - compatible = "amlogic,newman", "amlogic,t931", "amlogic,meson-g12b"; - model = "Amlogic Meson G12B (T931) Newman Development Board"; -}; - -/* This UART is brought out to the DB9 connector */ -&uart_AO { - status = "okay"; -}; - -&saradc { - status = "okay"; -}; - -/* demo for i2c user */ -&i2c2 { - status= "okay"; - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_master_pins2>; -}; - -&i2c3 { - status= "okay"; - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_master_pins2>; -}; - -&i2c_AO { - status= "okay"; - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&ao_i2c_master_pins1>; -}; - -&pinctrl_periphs { - bl_pwm_off_pins:bl_pwm_off_pin { - mux { - groups = "GPIOH_5"; - function = "gpio_periphs"; - output-high; - }; - }; -}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-g12b-t931.dtsi b/arch/arm/dts/meson-g12b-t931.dtsi deleted file mode 100644 index 16b6166..0000000 --- a/arch/arm/dts/meson-g12b-t931.dtsi +++ /dev/null
@@ -1,242 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>. - * Based on meson-gx-p23x-q20x.dtsi: - * - Copyright (c) 2016 Endless Computers, Inc. - * Author: Carlo Caione <carlo@endlessm.com> - * - Copyright (c) 2016 BayLibre, SAS. - * Author: Neil Armstrong <narmstrong@baylibre.com> - */ - -/* Common DTSI for devices which are based on the P212 reference board. */ - -#include "meson-g12b.dtsi" -#include "meson-g12b-mali.dtsi" - -/ { - compatible = "amlogic,t931", "amlogic,meson-g12b"; -}; - -/ { - aliases { - serial0 = &uart_AO; - serial1 = &uart_A; - spi0 = &spifc; - spi1 = &spicc0; - spi2 = &spicc1; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c_AO; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - vddio_boot: regulator-vddio_boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vddao_3v3: regulator-vddao_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vddio_ao18: regulator-vddio_ao18 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; - }; - - wifi32k: wifi32k { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; - clocks = <&wifi32k>; - clock-names = "ext_clock"; - }; -}; - -ðmac { - status = "okay"; - internal_phy = <1>; - mc_val = <0x4be04>; - /*mc_val = <0x1621>;*/ -}; - -&ir { - status = "disabled"; - //pinctrl-0 = <&remote_input_ao_pins>; - //pinctrl-names = "default"; -}; - -&saradc { - status = "okay"; - vref-supply = <&vddio_ao18>; -}; - -/* Wireless SDIO Module */ -&sd_emmc_a { - status = "disabled"; - //pinctrl-0 = <&sdio_pins>; - //pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <100000000>; - - non-removable; - disable-wp; - - pinname = "sdio"; - mmc-pwrseq = <&sdio_pwrseq>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sd_all_pins>; - pinctrl-names = "default"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <100000000>; - disable-wp; - - pinname = "sd"; - init_co_phase = <2>; - init_tx_phase = <0>; - sd_hs_co_phase = <2>; - sd_hs_tx_phase = <0>; - sdr104_co_phase = <2>; - sdr104_hs_tx_phase = <0>; - - cd-detect = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>; - /* cd-inverted; */ - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_conf_pull_up &emmc_conf_pull_done>; - pinctrl-names = "default"; - - bus-width = <8>; - cap-sd-highspeed; - cap-mmc-highspeed; - max-frequency = <200000000>; - non-removable; - disable-wp; -// mmc-ddr-1_8v; -// mmc-hs200-1_8v; - - pinname = "emmc"; - init_co_phase = <2>; - init_tx_phase = <0>; - hs_co_phase = <1>; - hs_tx_phase = <0>; - ddr_co_phase = <2>; - ddr_tx_phase = <0>; - hs2_co_phase = <2>; - hs2_tx_phase = <0>; - - hw_reset = <&gpio BOOT_12 GPIO_ACTIVE_HIGH>; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -&dwc3 { - status = "okay"; - dr_mode = "host"; -}; - -&usb2_phy_v2 { - status = "okay"; - portnum = <2>; -}; - -&usb3_phy_v2 { - status = "okay"; - portnum = <0>; - gpio-vbus-power = "GPIOH_6"; - gpios = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>; -}; - -&pwm_ef { - status = "okay"; - //pinctrl-0 = <&pwm_e_pins>; - pinctrl-names = "default"; -}; - -/* This is connected to the Bluetooth module: */ -&uart_A { - status = "okay"; - pinctrl-0 = <&a_uart_pins>; - pinctrl-names = "default"; - uart-has-rtscts; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&ao_uart_pins>; - pinctrl-names = "default"; -}; - -&spifc { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spifc_all_pins>; - max-frequency = <80000000>; - max-io = <4>; - cs-gpios = <&gpio BOOT_14 GPIO_ACTIVE_HIGH>; - clocks = <&clkc CLKID_CLK81>; - clock-names = "core"; -}; - -&spicc1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spicc1_pins>; - cs-gpios = <&gpio GPIOH_6 0>; -};
diff --git a/arch/arm/dts/meson-g12b.dtsi b/arch/arm/dts/meson-g12b.dtsi index 92aad7e..f3131ce 100644 --- a/arch/arm/dts/meson-g12b.dtsi +++ b/arch/arm/dts/meson-g12b.dtsi
@@ -69,7 +69,7 @@ meson-fb { status = "okay"; - logo_addr = "0x76800000"; + logo_addr = "0x7f800000"; }; }; @@ -145,7 +145,7 @@ groups = "i2c_ao_sck", "i2c_ao_sda"; function = "i2c_ao"; - drive-strength = <2>; + drive-strength = <3>; }; }; @@ -154,7 +154,7 @@ groups = "i2c_ao_sck_e", "i2c_ao_sda_e"; function = "i2c_ao"; - drive-strength = <2>; + drive-strength = <3>; }; }; @@ -323,19 +323,18 @@ function = "sdcard"; input-enable; bias-pull-up; - drive-strength = <3>; + drive-strength = <4>; }; mux1 { groups = "sdcard_clk_c"; function = "sdcard"; bias-pull-up; output-high; - drive-strength = <3>; + drive-strength = <4>; }; }; sd_all_pins:sd_all_pins { - /* mux { groups = "sdcard_d0_c", "sdcard_d1_c", @@ -345,16 +344,15 @@ function = "sdcard"; input-enable; bias-pull-up; - drive-strength = <3>; + drive-strength = <4>; }; mux1 { groups = "sdcard_clk_c"; function = "sdcard"; bias-pull-up; output-high; - drive-strength = <3>; + drive-strength = <4>; }; - */ }; sd_1bit_pins:sd_1bit_pins { @@ -364,14 +362,14 @@ function = "sdcard"; input-enable; bias-pull-up; - drive-strength = <3>; + drive-strength = <4>; }; mux1 { groups = "sdcard_clk_c"; function = "sdcard"; bias-pull-up; output-high; - drive-strength = <3>; + drive-strength = <4>; }; }; @@ -421,7 +419,7 @@ function = "sdio"; input-enable; bias-pull-up; - drive-strength = <3>; + drive-strength = <4>; }; }; @@ -436,7 +434,7 @@ function = "sdio"; input-enable; bias-pull-up; - drive-strength = <3>; + drive-strength = <4>; }; }; @@ -446,14 +444,14 @@ function = "gpio_periphs"; input-enable; bias-pull-up; - drive-strength = <3>; + drive-strength = <4>; }; mux1 { groups = "GPIOX_4"; function = "gpio_periphs"; bias-pull-up; output-high; - drive-strength = <3>; + drive-strength = <4>; }; }; @@ -467,14 +465,14 @@ function = "gpio_periphs"; input-enable; bias-pull-up; - drive-strength = <3>; + drive-strength = <4>; }; mux1 { groups = "GPIOX_4"; function = "gpio_periphs"; bias-pull-up; output-high; - drive-strength = <3>; + drive-strength = <4>; }; }; @@ -534,7 +532,7 @@ groups = "i2c0_sda_c", "i2c0_sck_c"; function = "i2c0"; - drive-strength = <2>; + drive-strength = <3>; }; }; @@ -543,7 +541,7 @@ groups = "i2c0_sda_z0", "i2c0_sck_z1"; function = "i2c0"; - drive-strength = <2>; + drive-strength = <3>; }; }; @@ -552,7 +550,7 @@ groups = "i2c0_sda_z7", "i2c0_sck_z8"; function = "i2c0"; - drive-strength = <2>; + drive-strength = <3>; }; }; @@ -561,7 +559,7 @@ groups = "i2c1_sda_x", "i2c1_sck_x"; function = "i2c1"; - drive-strength = <2>; + drive-strength = <3>; }; }; @@ -570,7 +568,7 @@ groups = "i2c1_sda_h2", "i2c1_sck_h3"; function = "i2c1"; - drive-strength = <2>; + drive-strength = <3>; }; }; @@ -579,7 +577,7 @@ groups = "i2c1_sda_h6", "i2c1_sck_h7"; function = "i2c1"; - drive-strength = <2>; + drive-strength = <3>; }; }; @@ -588,7 +586,7 @@ groups = "i2c2_sda_x", "i2c2_sck_x"; function = "i2c2"; - drive-strength = <2>; + drive-strength = <3>; }; }; @@ -597,7 +595,7 @@ groups = "i2c2_sda_z", "i2c2_sck_z"; function = "i2c2"; - drive-strength = <2>; + drive-strength = <3>; }; }; @@ -606,7 +604,7 @@ groups = "i2c3_sda_h", "i2c3_sck_h"; function = "i2c3"; - drive-strength = <2>; + drive-strength = <3>; }; }; @@ -615,7 +613,7 @@ groups = "i2c3_sda_a", "i2c3_sck_a"; function = "i2c3"; - drive-strength = <2>; + drive-strength = <3>; }; }; @@ -712,7 +710,7 @@ "spi0_miso_c", "spi0_clk_c"; function = "spi0"; - drive-strength = <1>; + drive-strength = <2>; }; }; @@ -722,7 +720,7 @@ "spi1_miso", "spi1_clk"; function = "spi1"; - drive-strength = <1>; + drive-strength = <2>; }; }; @@ -734,7 +732,7 @@ "nor_hold", "nor_wp"; function = "nor"; - drive-strength = <1>; + drive-strength = <2>; }; }; @@ -786,7 +784,7 @@ "hdmitx_sck"; function = "hdmitx"; bias-disable; - drive-strength = <3>; + drive-strength = <4>; }; }; @@ -839,7 +837,7 @@ "eth_txd2_rgmii", "eth_txd3_rgmii"; function = "eth"; - drive-strength = <3>; + drive-strength = <4>; }; }; }; @@ -912,34 +910,27 @@ }; -/* &spicc0 { - clocks = <&clkc CLKID_SPICC0>, - <&clkc CLKID_SPICC0_COMP>; - clock-names = "core", "comp"; + clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_SPICC0>, + <&clkc CLKID_SPICC0_DIV>, <&clkc CLKID_SPICC0_GATE>; + clock-names = "core", "core-gate", "async", "async-gate"; + assigned-clocks = <&clkc CLKID_SPICC0_MUX>, <&clkc CLKID_SPICC0_DIV>; + assigned-clock-parents = <&clkc CLKID_FCLK_DIV2>; + assigned-clock-rates = <0>, <200000000>; }; &spicc1 { - clocks = <&clkc CLKID_SPICC1>, - <&clkc CLKID_SPICC1_COMP>; - clock-names = "core", "comp"; - }; -*/ + clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_SPICC1>, + <&clkc CLKID_SPICC1_DIV>, <&clkc CLKID_SPICC1_GATE>; + clock-names = "core", "core-gate", "async", "async-gate"; + assigned-clocks = <&clkc CLKID_SPICC1_MUX>, <&clkc CLKID_SPICC1_DIV>; + assigned-clock-parents = <&clkc CLKID_FCLK_DIV2>; + assigned-clock-rates = <0>, <200000000>; +}; + /* &spifc { clocks = <&clkc CLKID_CLK81>; clock-names = "core"; }; */ -&usb2_phy_v2 { - pll-setting-1 = <0x09400414>; - pll-setting-2 = <0x927E0000>; - pll-setting-3 = <0xac5f69e5>; - pll-setting-4 = <0xfe18>; - pll-setting-5 = <0xfff>; - pll-setting-6 = <0x78000>; - pll-setting-7 = <0xe0004>; - pll-setting-8 = <0xe000c>; - disconnect-threshold = <0x3c>; -}; -
diff --git a/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts b/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts index d32cf38..5f27542 100644 --- a/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts +++ b/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts
@@ -33,8 +33,6 @@ gpio-keys-polled { compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; poll-interval = <100>; button@0 {
diff --git a/arch/arm/dts/meson-gxm-khadas-vim2.dts b/arch/arm/dts/meson-gxm-khadas-vim2.dts index 313f88f..560fe53 100644 --- a/arch/arm/dts/meson-gxm-khadas-vim2.dts +++ b/arch/arm/dts/meson-gxm-khadas-vim2.dts
@@ -63,8 +63,6 @@ gpio-keys-polled { compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; poll-interval = <100>; button@0 {
diff --git a/arch/arm/dts/meson-s4-ap201.dts b/arch/arm/dts/meson-s4-ap201.dts new file mode 100644 index 0000000..553410b --- /dev/null +++ b/arch/arm/dts/meson-s4-ap201.dts
@@ -0,0 +1,83 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "meson-s4-ap201.dtsi" +#include "meson-s4_skt-panel.dtsi" + +/ { + compatible = "amlogic,s4-ap201", "amlogic,s4-txxx", "amlogic,meson-s4"; + model = "Amlogic Meson S4 AP201 Board"; +}; + +/* This UART is brought out to the DB9 connector */ +&uart_a { + status = "okay"; +}; + +&uart_b { + status = "disabled"; +}; + +&saradc { + status = "okay"; +}; + +/* demo for i2c user */ +&i2c3 { + status= "disabled"; + clock-frequency = <100000>; + /* pinctrl-names = "default";*/ + /* pinctrl-0 = <&i2c3_master_pins2>;*/ +}; + +&pinctrl_periphs { + bl_pwm_off_pins:bl_pwm_off_pin { + mux { + groups = "GPIOH_5"; + function = "gpio_periphs"; + output-high; + }; + }; +}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-s4-ap201.dtsi b/arch/arm/dts/meson-s4-ap201.dtsi new file mode 100644 index 0000000..280a62b --- /dev/null +++ b/arch/arm/dts/meson-s4-ap201.dtsi
@@ -0,0 +1,253 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>. + * Based on meson-gx-p23x-q20x.dtsi: + * - Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * - Copyright (c) 2016 BayLibre, SAS. + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +/* Common DTSI for devices which are based on the P212 reference board. */ + +#include "meson-s4-txxx.dtsi" + +/ { + aliases { + serial0 = &uart_a; + serial1 = &uart_b; + spi0 = &spifc; + spi1 = &spicc0; + spi2 = &spicc1; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + }; + + chosen { + stdout-path = "serial1:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + vddio_boot: regulator-vddio_boot { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vddio_ao18: regulator-vddio_ao18 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + /*reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;*/ + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; + + tee: tee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; +}; + +&vpu { + clk_level = <7>; +}; + +ðmac { + status = "okay"; + internal_phy = <1>; + mc_val = <0x4be04>; + /*mc_val = <0x1621>;*/ +}; + +&ir { + status = "disabled"; + /* pinctrl-0 = <&remote_input_ao_pins>; */ + /* pinctrl-names = "default"; */ +}; + +&saradc { + status = "disabled"; + vref-supply = <&vddio_ao18>; +}; + +/* Wireless SDIO Module */ +&sd_emmc_a { + status = "disabled"; + /*pinctrl-0 = <&sdio_pins>;*/ + /*pinctrl-names = "default";*/ + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + + non-removable; + disable-wp; + card_type = <3>; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_pins>; + pinctrl-1 = <&sdcard_pins &to_sduart_pins>; + pinctrl-names = "sd_all_pins", "sd_uart"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>; + cd-inverted; + + card_type = <5>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + sd_hs_co_phase = <2>; + sd_hs_to_phase = <0>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + max-frequency = <200000000>; + non-removable; + disable-wp; + /* mmc-ddr-1_8v; */ + card_type = <1>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + hs_co_phase = <2>; + hs_to_phase = <0>; + + hs2_co_phase = <2>; + hs2_to_phase = <0>; + + hw_reset = <&gpio GPIOB_9 GPIO_ACTIVE_HIGH>; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* nand */ +&nand { + status = "okay"; + pinctrl-names = "default", "nand_cs_only"; + pinctrl-0 = <&all_nand_pins>; + pinctrl-1 = <&nand_cs_pins>; +}; + +&crg { + status = "okay"; + dr_mode = "host"; +}; + +&usb2_phy_v2 { + status = "okay"; + portnum = <2>; +}; + +&usb3_phy_v2 { + status = "okay"; + portnum = <0>; + gpio-vbus-power = "GPIOH_6"; + gpios = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>; +}; + +&pwm_ef { + status = "okay"; + /* pinctrl-0 = <&pwm_e_pins>; */ + /* pinctrl-names = "default"; */ +}; + +/* This is connected to the Bluetooth module: */ +&uart_b { + status = "okay"; + /* pinctrl-0 = <&a_uart_pins>; */ + /* pinctrl-names = "default"; */ + uart-has-rtscts; +}; + +&spifc { + status = "okay"; + cs-gpios = <&gpio GPIOB_13 GPIO_ACTIVE_HIGH>; + spi-flash@0 { + status = "okay"; + }; +}; + +&spicc0 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc0_pins1>; + //cs-gpios = <&gpio GPIOA_8 0>, + // <&gpio GPIOA_9 0>; +}; + +&spicc1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc1_pins1>; + //cs-gpios = <&gpio GPIOA_14 0>; +};
diff --git a/arch/arm/dts/meson-s4-ap222.dts b/arch/arm/dts/meson-s4-ap222.dts new file mode 100644 index 0000000..aa22711 --- /dev/null +++ b/arch/arm/dts/meson-s4-ap222.dts
@@ -0,0 +1,83 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "meson-s4-ap222.dtsi" +#include "meson-s4_skt-panel.dtsi" + +/ { + compatible = "amlogic,s4-ap222", "amlogic,s4-txxx", "amlogic,meson-s4"; + model = "Amlogic Meson S4 AP222 Board"; +}; + +/* This UART is brought out to the DB9 connector */ +&uart_a { + status = "okay"; +}; + +&uart_b { + status = "disabled"; +}; + +&saradc { + status = "okay"; +}; + +/* demo for i2c user */ +&i2c3 { + status= "disabled"; + clock-frequency = <100000>; + /* pinctrl-names = "default";*/ + /* pinctrl-0 = <&i2c3_master_pins2>;*/ +}; + +&pinctrl_periphs { + bl_pwm_off_pins:bl_pwm_off_pin { + mux { + groups = "GPIOH_5"; + function = "gpio_periphs"; + output-high; + }; + }; +}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-s4-ap222.dtsi b/arch/arm/dts/meson-s4-ap222.dtsi new file mode 100644 index 0000000..280a62b --- /dev/null +++ b/arch/arm/dts/meson-s4-ap222.dtsi
@@ -0,0 +1,253 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>. + * Based on meson-gx-p23x-q20x.dtsi: + * - Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * - Copyright (c) 2016 BayLibre, SAS. + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +/* Common DTSI for devices which are based on the P212 reference board. */ + +#include "meson-s4-txxx.dtsi" + +/ { + aliases { + serial0 = &uart_a; + serial1 = &uart_b; + spi0 = &spifc; + spi1 = &spicc0; + spi2 = &spicc1; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + }; + + chosen { + stdout-path = "serial1:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + vddio_boot: regulator-vddio_boot { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vddio_ao18: regulator-vddio_ao18 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + /*reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;*/ + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; + + tee: tee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; +}; + +&vpu { + clk_level = <7>; +}; + +ðmac { + status = "okay"; + internal_phy = <1>; + mc_val = <0x4be04>; + /*mc_val = <0x1621>;*/ +}; + +&ir { + status = "disabled"; + /* pinctrl-0 = <&remote_input_ao_pins>; */ + /* pinctrl-names = "default"; */ +}; + +&saradc { + status = "disabled"; + vref-supply = <&vddio_ao18>; +}; + +/* Wireless SDIO Module */ +&sd_emmc_a { + status = "disabled"; + /*pinctrl-0 = <&sdio_pins>;*/ + /*pinctrl-names = "default";*/ + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + + non-removable; + disable-wp; + card_type = <3>; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_pins>; + pinctrl-1 = <&sdcard_pins &to_sduart_pins>; + pinctrl-names = "sd_all_pins", "sd_uart"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>; + cd-inverted; + + card_type = <5>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + sd_hs_co_phase = <2>; + sd_hs_to_phase = <0>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + max-frequency = <200000000>; + non-removable; + disable-wp; + /* mmc-ddr-1_8v; */ + card_type = <1>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + hs_co_phase = <2>; + hs_to_phase = <0>; + + hs2_co_phase = <2>; + hs2_to_phase = <0>; + + hw_reset = <&gpio GPIOB_9 GPIO_ACTIVE_HIGH>; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* nand */ +&nand { + status = "okay"; + pinctrl-names = "default", "nand_cs_only"; + pinctrl-0 = <&all_nand_pins>; + pinctrl-1 = <&nand_cs_pins>; +}; + +&crg { + status = "okay"; + dr_mode = "host"; +}; + +&usb2_phy_v2 { + status = "okay"; + portnum = <2>; +}; + +&usb3_phy_v2 { + status = "okay"; + portnum = <0>; + gpio-vbus-power = "GPIOH_6"; + gpios = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>; +}; + +&pwm_ef { + status = "okay"; + /* pinctrl-0 = <&pwm_e_pins>; */ + /* pinctrl-names = "default"; */ +}; + +/* This is connected to the Bluetooth module: */ +&uart_b { + status = "okay"; + /* pinctrl-0 = <&a_uart_pins>; */ + /* pinctrl-names = "default"; */ + uart-has-rtscts; +}; + +&spifc { + status = "okay"; + cs-gpios = <&gpio GPIOB_13 GPIO_ACTIVE_HIGH>; + spi-flash@0 { + status = "okay"; + }; +}; + +&spicc0 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc0_pins1>; + //cs-gpios = <&gpio GPIOA_8 0>, + // <&gpio GPIOA_9 0>; +}; + +&spicc1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc1_pins1>; + //cs-gpios = <&gpio GPIOA_14 0>; +};
diff --git a/arch/arm/dts/meson-s4-ap229.dts b/arch/arm/dts/meson-s4-ap229.dts new file mode 100644 index 0000000..8a44c45 --- /dev/null +++ b/arch/arm/dts/meson-s4-ap229.dts
@@ -0,0 +1,83 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "meson-s4-ap229.dtsi" +#include "meson-s4_skt-panel.dtsi" + +/ { + compatible = "amlogic,s4-ap229", "amlogic,s4-txxx", "amlogic,meson-s4"; + model = "Amlogic Meson S4 AP229 Board"; +}; + +/* This UART is brought out to the DB9 connector */ +&uart_a { + status = "okay"; +}; + +&uart_b { + status = "disabled"; +}; + +&saradc { + status = "okay"; +}; + +/* demo for i2c user */ +&i2c3 { + status= "disabled"; + clock-frequency = <100000>; + /* pinctrl-names = "default";*/ + /* pinctrl-0 = <&i2c3_master_pins2>;*/ +}; + +&pinctrl_periphs { + bl_pwm_off_pins:bl_pwm_off_pin { + mux { + groups = "GPIOH_5"; + function = "gpio_periphs"; + output-high; + }; + }; +}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-s4-ap229.dtsi b/arch/arm/dts/meson-s4-ap229.dtsi new file mode 100644 index 0000000..280a62b --- /dev/null +++ b/arch/arm/dts/meson-s4-ap229.dtsi
@@ -0,0 +1,253 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>. + * Based on meson-gx-p23x-q20x.dtsi: + * - Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * - Copyright (c) 2016 BayLibre, SAS. + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +/* Common DTSI for devices which are based on the P212 reference board. */ + +#include "meson-s4-txxx.dtsi" + +/ { + aliases { + serial0 = &uart_a; + serial1 = &uart_b; + spi0 = &spifc; + spi1 = &spicc0; + spi2 = &spicc1; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + }; + + chosen { + stdout-path = "serial1:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + vddio_boot: regulator-vddio_boot { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vddio_ao18: regulator-vddio_ao18 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + /*reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;*/ + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; + + tee: tee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; +}; + +&vpu { + clk_level = <7>; +}; + +ðmac { + status = "okay"; + internal_phy = <1>; + mc_val = <0x4be04>; + /*mc_val = <0x1621>;*/ +}; + +&ir { + status = "disabled"; + /* pinctrl-0 = <&remote_input_ao_pins>; */ + /* pinctrl-names = "default"; */ +}; + +&saradc { + status = "disabled"; + vref-supply = <&vddio_ao18>; +}; + +/* Wireless SDIO Module */ +&sd_emmc_a { + status = "disabled"; + /*pinctrl-0 = <&sdio_pins>;*/ + /*pinctrl-names = "default";*/ + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + + non-removable; + disable-wp; + card_type = <3>; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_pins>; + pinctrl-1 = <&sdcard_pins &to_sduart_pins>; + pinctrl-names = "sd_all_pins", "sd_uart"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>; + cd-inverted; + + card_type = <5>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + sd_hs_co_phase = <2>; + sd_hs_to_phase = <0>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + max-frequency = <200000000>; + non-removable; + disable-wp; + /* mmc-ddr-1_8v; */ + card_type = <1>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + hs_co_phase = <2>; + hs_to_phase = <0>; + + hs2_co_phase = <2>; + hs2_to_phase = <0>; + + hw_reset = <&gpio GPIOB_9 GPIO_ACTIVE_HIGH>; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* nand */ +&nand { + status = "okay"; + pinctrl-names = "default", "nand_cs_only"; + pinctrl-0 = <&all_nand_pins>; + pinctrl-1 = <&nand_cs_pins>; +}; + +&crg { + status = "okay"; + dr_mode = "host"; +}; + +&usb2_phy_v2 { + status = "okay"; + portnum = <2>; +}; + +&usb3_phy_v2 { + status = "okay"; + portnum = <0>; + gpio-vbus-power = "GPIOH_6"; + gpios = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>; +}; + +&pwm_ef { + status = "okay"; + /* pinctrl-0 = <&pwm_e_pins>; */ + /* pinctrl-names = "default"; */ +}; + +/* This is connected to the Bluetooth module: */ +&uart_b { + status = "okay"; + /* pinctrl-0 = <&a_uart_pins>; */ + /* pinctrl-names = "default"; */ + uart-has-rtscts; +}; + +&spifc { + status = "okay"; + cs-gpios = <&gpio GPIOB_13 GPIO_ACTIVE_HIGH>; + spi-flash@0 { + status = "okay"; + }; +}; + +&spicc0 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc0_pins1>; + //cs-gpios = <&gpio GPIOA_8 0>, + // <&gpio GPIOA_9 0>; +}; + +&spicc1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc1_pins1>; + //cs-gpios = <&gpio GPIOA_14 0>; +};
diff --git a/arch/arm/dts/meson-s4-aq222.dts b/arch/arm/dts/meson-s4-aq222.dts new file mode 100644 index 0000000..7bd7ac2 --- /dev/null +++ b/arch/arm/dts/meson-s4-aq222.dts
@@ -0,0 +1,83 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "meson-s4-aq222.dtsi" +#include "meson-s4_skt-panel.dtsi" + +/ { + compatible = "amlogic,s4-aq222", "amlogic,s4-txxx", "amlogic,meson-s4"; + model = "Amlogic Meson S4 AQ222 Board"; +}; + +/* This UART is brought out to the DB9 connector */ +&uart_a { + status = "okay"; +}; + +&uart_b { + status = "disabled"; +}; + +&saradc { + status = "okay"; +}; + +/* demo for i2c user */ +&i2c3 { + status= "disabled"; + clock-frequency = <100000>; + /* pinctrl-names = "default";*/ + /* pinctrl-0 = <&i2c3_master_pins2>;*/ +}; + +&pinctrl_periphs { + bl_pwm_off_pins:bl_pwm_off_pin { + mux { + groups = "GPIOH_5"; + function = "gpio_periphs"; + output-high; + }; + }; +}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-s4-aq222.dtsi b/arch/arm/dts/meson-s4-aq222.dtsi new file mode 100644 index 0000000..9f7437d --- /dev/null +++ b/arch/arm/dts/meson-s4-aq222.dtsi
@@ -0,0 +1,259 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>. + * Based on meson-gx-p23x-q20x.dtsi: + * - Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * - Copyright (c) 2016 BayLibre, SAS. + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +/* Common DTSI for devices which are based on the P212 reference board. */ + +#include "meson-s4-txxx.dtsi" + +/ { + aliases { + serial0 = &uart_a; + serial1 = &uart_b; + spi0 = &spifc; + spi1 = &spicc0; + spi2 = &spicc1; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + }; + + chosen { + stdout-path = "serial1:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + vddio_boot: regulator-vddio_boot { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vddio_ao18: regulator-vddio_ao18 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + /*reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;*/ + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; + + tee: tee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + + amhdmitx { + compatible = "amlogic, amhdmitx-s4"; + status = "okay"; + res_1080p = <1>; + }; +}; + +&vpu { + clk_level = <5>; +}; + +ðmac { + status = "okay"; + internal_phy = <1>; + mc_val = <0x4be04>; + /*mc_val = <0x1621>;*/ +}; + +&ir { + status = "disabled"; + /* pinctrl-0 = <&remote_input_ao_pins>; */ + /* pinctrl-names = "default"; */ +}; + +&saradc { + status = "disabled"; + vref-supply = <&vddio_ao18>; +}; + +/* Wireless SDIO Module */ +&sd_emmc_a { + status = "disabled"; + /*pinctrl-0 = <&sdio_pins>;*/ + /*pinctrl-names = "default";*/ + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + + non-removable; + disable-wp; + card_type = <3>; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_pins>; + pinctrl-1 = <&sdcard_pins &to_sduart_pins>; + pinctrl-names = "sd_all_pins", "sd_uart"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>; + cd-inverted; + + card_type = <5>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + sd_hs_co_phase = <2>; + sd_hs_to_phase = <0>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + max-frequency = <200000000>; + non-removable; + disable-wp; + /* mmc-ddr-1_8v; */ + card_type = <1>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + hs_co_phase = <2>; + hs_to_phase = <0>; + + hs2_co_phase = <2>; + hs2_to_phase = <0>; + + hw_reset = <&gpio GPIOB_9 GPIO_ACTIVE_HIGH>; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* nand */ +&nand { + status = "okay"; + pinctrl-names = "default", "nand_cs_only"; + pinctrl-0 = <&all_nand_pins>; + pinctrl-1 = <&nand_cs_pins>; +}; + +&crg { + status = "okay"; + dr_mode = "host"; +}; + +&usb2_phy_v2 { + status = "okay"; + portnum = <2>; +}; + +&usb3_phy_v2 { + status = "okay"; + portnum = <0>; + gpio-vbus-power = "GPIOH_6"; + gpios = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>; +}; + +&pwm_ef { + status = "okay"; + /* pinctrl-0 = <&pwm_e_pins>; */ + /* pinctrl-names = "default"; */ +}; + +/* This is connected to the Bluetooth module: */ +&uart_b { + status = "okay"; + /* pinctrl-0 = <&a_uart_pins>; */ + /* pinctrl-names = "default"; */ + uart-has-rtscts; +}; + +&spifc { + status = "okay"; + cs-gpios = <&gpio GPIOB_13 GPIO_ACTIVE_HIGH>; + spi-flash@0 { + status = "okay"; + }; +}; + +&spicc0 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc0_pins1>; + //cs-gpios = <&gpio GPIOA_8 0>, + // <&gpio GPIOA_9 0>; +}; + +&spicc1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc1_pins1>; + //cs-gpios = <&gpio GPIOA_14 0>; +};
diff --git a/arch/arm/dts/meson-s4-aq229.dts b/arch/arm/dts/meson-s4-aq229.dts new file mode 100644 index 0000000..9bf539f --- /dev/null +++ b/arch/arm/dts/meson-s4-aq229.dts
@@ -0,0 +1,83 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "meson-s4-aq229.dtsi" +#include "meson-s4_skt-panel.dtsi" + +/ { + compatible = "amlogic,s4-aq229", "amlogic,s4-txxx", "amlogic,meson-s4"; + model = "Amlogic Meson S4 AQ229 Board"; +}; + +/* This UART is brought out to the DB9 connector */ +&uart_a { + status = "okay"; +}; + +&uart_b { + status = "disabled"; +}; + +&saradc { + status = "okay"; +}; + +/* demo for i2c user */ +&i2c3 { + status= "disabled"; + clock-frequency = <100000>; + /* pinctrl-names = "default";*/ + /* pinctrl-0 = <&i2c3_master_pins2>;*/ +}; + +&pinctrl_periphs { + bl_pwm_off_pins:bl_pwm_off_pin { + mux { + groups = "GPIOH_5"; + function = "gpio_periphs"; + output-high; + }; + }; +}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-s4-aq229.dtsi b/arch/arm/dts/meson-s4-aq229.dtsi new file mode 100644 index 0000000..9f7437d --- /dev/null +++ b/arch/arm/dts/meson-s4-aq229.dtsi
@@ -0,0 +1,259 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>. + * Based on meson-gx-p23x-q20x.dtsi: + * - Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * - Copyright (c) 2016 BayLibre, SAS. + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +/* Common DTSI for devices which are based on the P212 reference board. */ + +#include "meson-s4-txxx.dtsi" + +/ { + aliases { + serial0 = &uart_a; + serial1 = &uart_b; + spi0 = &spifc; + spi1 = &spicc0; + spi2 = &spicc1; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + }; + + chosen { + stdout-path = "serial1:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + vddio_boot: regulator-vddio_boot { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vddio_ao18: regulator-vddio_ao18 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + /*reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;*/ + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; + + tee: tee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + + amhdmitx { + compatible = "amlogic, amhdmitx-s4"; + status = "okay"; + res_1080p = <1>; + }; +}; + +&vpu { + clk_level = <5>; +}; + +ðmac { + status = "okay"; + internal_phy = <1>; + mc_val = <0x4be04>; + /*mc_val = <0x1621>;*/ +}; + +&ir { + status = "disabled"; + /* pinctrl-0 = <&remote_input_ao_pins>; */ + /* pinctrl-names = "default"; */ +}; + +&saradc { + status = "disabled"; + vref-supply = <&vddio_ao18>; +}; + +/* Wireless SDIO Module */ +&sd_emmc_a { + status = "disabled"; + /*pinctrl-0 = <&sdio_pins>;*/ + /*pinctrl-names = "default";*/ + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + + non-removable; + disable-wp; + card_type = <3>; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_pins>; + pinctrl-1 = <&sdcard_pins &to_sduart_pins>; + pinctrl-names = "sd_all_pins", "sd_uart"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>; + cd-inverted; + + card_type = <5>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + sd_hs_co_phase = <2>; + sd_hs_to_phase = <0>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + max-frequency = <200000000>; + non-removable; + disable-wp; + /* mmc-ddr-1_8v; */ + card_type = <1>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + hs_co_phase = <2>; + hs_to_phase = <0>; + + hs2_co_phase = <2>; + hs2_to_phase = <0>; + + hw_reset = <&gpio GPIOB_9 GPIO_ACTIVE_HIGH>; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* nand */ +&nand { + status = "okay"; + pinctrl-names = "default", "nand_cs_only"; + pinctrl-0 = <&all_nand_pins>; + pinctrl-1 = <&nand_cs_pins>; +}; + +&crg { + status = "okay"; + dr_mode = "host"; +}; + +&usb2_phy_v2 { + status = "okay"; + portnum = <2>; +}; + +&usb3_phy_v2 { + status = "okay"; + portnum = <0>; + gpio-vbus-power = "GPIOH_6"; + gpios = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>; +}; + +&pwm_ef { + status = "okay"; + /* pinctrl-0 = <&pwm_e_pins>; */ + /* pinctrl-names = "default"; */ +}; + +/* This is connected to the Bluetooth module: */ +&uart_b { + status = "okay"; + /* pinctrl-0 = <&a_uart_pins>; */ + /* pinctrl-names = "default"; */ + uart-has-rtscts; +}; + +&spifc { + status = "okay"; + cs-gpios = <&gpio GPIOB_13 GPIO_ACTIVE_HIGH>; + spi-flash@0 { + status = "okay"; + }; +}; + +&spicc0 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc0_pins1>; + //cs-gpios = <&gpio GPIOA_8 0>, + // <&gpio GPIOA_9 0>; +}; + +&spicc1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc1_pins1>; + //cs-gpios = <&gpio GPIOA_14 0>; +};
diff --git a/arch/arm/dts/meson-s4-mali.dtsi b/arch/arm/dts/meson-s4-mali.dtsi new file mode 100644 index 0000000..2655b42 --- /dev/null +++ b/arch/arm/dts/meson-s4-mali.dtsi
@@ -0,0 +1,43 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 BayLibre SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +&apb { + mali: gpu@40000 { + compatible = "amlogic,meson-gxbb-mali", "arm,mali-450"; + reg = <0x0 0x40000 0x0 0x40000>; + interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "gp", "gpmmu", "pp", "pmu", + "pp0", "ppmmu0", "pp1", "ppmmu1", + "pp2", "ppmmu2"; + /*clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;*/ + clock-names = "bus", "core"; + + /* + * Mali clocking is provided by two identical clock paths + * MALI_0 and MALI_1 muxed to a single clock by a glitch + * free mux to safely change frequency while running. + */ + /* + assigned-clocks = <&clkc CLKID_MALI_0_SEL>, + <&clkc CLKID_MALI_0>, + <&clkc CLKID_MALI>; *//* Glitch free mux */ + /*assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, + <0>, *//* Do Nothing */ + //<&clkc CLKID_MALI_0>; + /*assigned-clock-rates = <0>,*/ /* Do Nothing */ + /* <666666666>, + <0>;*/ /* Do Nothing */ + }; +};
diff --git a/arch/arm/dts/meson-s4-pxp.dts b/arch/arm/dts/meson-s4-pxp.dts new file mode 100644 index 0000000..b2b90b4 --- /dev/null +++ b/arch/arm/dts/meson-s4-pxp.dts
@@ -0,0 +1,83 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "meson-s4-pxp.dtsi" +#include "meson-s4_skt-panel.dtsi" + +/ { + compatible = "amlogic,s4-pxp", "amlogic,s4-txxx", "amlogic,meson-s4"; + model = "Amlogic Meson S4 PXP Board"; +}; + +/* This UART is brought out to the DB9 connector */ +&uart_a { + status = "okay"; +}; + +&uart_b { + status = "disabled"; +}; + +&saradc { + status = "disabled"; +}; + +/* demo for i2c user */ +&i2c3 { + status= "disabled"; + clock-frequency = <100000>; + /* pinctrl-names = "default";*/ + /* pinctrl-0 = <&i2c3_master_pins2>;*/ +}; + +&pinctrl_periphs { + bl_pwm_off_pins:bl_pwm_off_pin { + mux { + groups = "GPIOH_5"; + function = "gpio_periphs"; + output-high; + }; + }; +}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-s4-pxp.dtsi b/arch/arm/dts/meson-s4-pxp.dtsi new file mode 100644 index 0000000..e087329 --- /dev/null +++ b/arch/arm/dts/meson-s4-pxp.dtsi
@@ -0,0 +1,244 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>. + * Based on meson-gx-p23x-q20x.dtsi: + * - Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * - Copyright (c) 2016 BayLibre, SAS. + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +/* Common DTSI for devices which are based on the P212 reference board. */ + +#include "meson-s4-txxx.dtsi" + +/ { + aliases { + serial0 = &uart_a; + serial1 = &uart_b; + spi0 = &spifc; + spi1 = &spicc0; + spi2 = &spicc1; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + }; + + chosen { + stdout-path = "serial1:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + vddio_boot: regulator-vddio_boot { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vddio_ao18: regulator-vddio_ao18 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + /*reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;*/ + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; +}; + +ðmac { + status = "okay"; + internal_phy = <1>; + mc_val = <0x4be04>; + /*mc_val = <0x1621>;*/ +}; + +&ir { + status = "disabled"; + /* pinctrl-0 = <&remote_input_ao_pins>; */ + /* pinctrl-names = "default"; */ +}; + +&saradc { + status = "disabled"; + vref-supply = <&vddio_ao18>; +}; + +/* Wireless SDIO Module */ +&sd_emmc_a { + status = "disabled"; + /*pinctrl-0 = <&sdio_pins>;*/ + /*pinctrl-names = "default";*/ + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + + non-removable; + disable-wp; + card_type = <3>; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_pins>; + pinctrl-1 = <&sdcard_pins &to_sduart_pins>; + pinctrl-names = "sd_all_pins", "sd_uart"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>; + cd-inverted; + + card_type = <5>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + sd_hs_co_phase = <2>; + sd_hs_to_phase = <0>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + cap-mmc-highspeed; +// mmc-hs200-1_8v; + max-frequency = <200000000>; + non-removable; + disable-wp; + /* mmc-ddr-1_8v; */ + card_type = <1>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + hs_co_phase = <2>; + hs_to_phase = <0>; + + hs2_co_phase = <2>; + hs2_to_phase = <0>; + + hw_reset = <&gpio GPIOB_9 GPIO_ACTIVE_HIGH>; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* nand */ +&nand { + status = "okay"; + pinctrl-names = "default", "nand_cs_only"; + pinctrl-0 = <&all_nand_pins>; + pinctrl-1 = <&nand_cs_pins>; +}; + +&crg { + status = "okay"; + dr_mode = "host"; +}; + +&usb2_phy_v2 { + status = "okay"; + portnum = <2>; +}; + +&usb3_phy_v2 { + status = "okay"; + portnum = <0>; + gpio-vbus-power = "GPIOH_6"; + gpios = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>; +}; + +&pwm_ef { + status = "okay"; + /* pinctrl-0 = <&pwm_e_pins>; */ + /* pinctrl-names = "default"; */ +}; + +/* This is connected to the Bluetooth module: */ +&uart_b { + status = "okay"; + /* pinctrl-0 = <&a_uart_pins>; */ + /* pinctrl-names = "default"; */ + uart-has-rtscts; +}; + +&spifc { + status = "disabled"; + //cs-gpios = <&gpio GPIOB_14 GPIO_ACTIVE_HIGH>; + spi-flash@0 { + status = "disabled"; + }; +}; + +&spicc0 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc0_pins1>; + //cs-gpios = <&gpio GPIOA_8 0>, + // <&gpio GPIOA_9 0>; +}; + +&spicc1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc1_pins1>; + //cs-gpios = <&gpio GPIOA_14 0>; +};
diff --git a/arch/arm/dts/meson-s4-series.dtsi b/arch/arm/dts/meson-s4-series.dtsi new file mode 100644 index 0000000..607e7b7 --- /dev/null +++ b/arch/arm/dts/meson-s4-series.dtsi
@@ -0,0 +1,511 @@ +/* + * Copyright (c) 2016 Andreas Färber + * + * Copyright (c) 2016 BayLibre, SAS. + * Author: Neil Armstrong <narmstrong@baylibre.com> + * + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/pwm/pwm.h> +#include <dt-bindings/pwm/meson.h> +#include <dt-bindings/clock/s4-clkc.h> + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* 16 MiB reserved for Hardware ROM Firmware */ + hwrom_reserved: hwrom@0 { + reg = <0x0 0x0 0x0 0x1000000>; + no-map; + }; + + /* 2 MiB reserved for ARM Trusted Firmware (BL31) */ + secmon_reserved: secmon@10000000 { + reg = <0x0 0x10000000 0x0 0x200000>; + no-map; + }; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0xbc00000>; + alignment = <0x0 0x400000>; + linux,cma-default; + }; + }; + + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&l2>; + clocks = <&scpi_dvfs 0>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + next-level-cache = <&l2>; + clocks = <&scpi_dvfs 0>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x2>; + enable-method = "psci"; + next-level-cache = <&l2>; + clocks = <&scpi_dvfs 0>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x3>; + enable-method = "psci"; + next-level-cache = <&l2>; + clocks = <&scpi_dvfs 0>; + }; + + l2: l2-cache0 { + compatible = "cache"; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; + }; + + xtal: xtal-clk { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xtal"; + #clock-cells = <0>; + }; + + firmware { + sm: secure-monitor { + compatible = "amlogic,meson-gx-sm", "amlogic,meson-gxbb-sm"; + }; + }; + + efuse: efuse { + compatible = "amlogic,meson-sc2-efuse", "amlogic,meson-sc2-efuse"; + #address-cells = <1>; + #size-cells = <1>; + + }; + + scpi { + compatible = "amlogic,meson-gxbb-scpi", "arm,scpi-pre-1.0"; + mboxes = <&mailbox 1 &mailbox 2>; + shmem = <&cpu_scp_lpri &cpu_scp_hpri>; + + scpi_clocks: clocks { + compatible = "arm,scpi-clocks"; + + scpi_dvfs: scpi_clocks@0 { + compatible = "arm,scpi-dvfs-clocks"; + #clock-cells = <1>; + clock-indices = <0>; + clock-output-names = "vcpu"; + }; + }; + + scpi_sensors: sensors { + compatible = "amlogic,meson-gxbb-scpi-sensors", "arm,scpi-sensors"; + #thermal-sensor-cells = <1>; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic: interrupt-controller@2c001000 { + compatible = "arm,gic-400"; + reg = <0x0 0xffc01000 0 0x1000>, + <0x0 0xffc02000 0 0x2000>, + <0x0 0xffc04000 0 0x2000>, + <0x0 0xffc06000 0 0x2000>; + interrupt-controller; + interrupts = <GIC_PPI 9 + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; + #interrupt-cells = <3>; + #address-cells = <0>; + }; + + sram: sram@f7000000 { + compatible = "amlogic,meson-sc2-sram", "amlogic,meson-sc2-sram", "mmio-sram"; + reg = <0x0 0xf7000000 0x0 0x48000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0xf7000000 0x48000>; + + cpu_scp_lpri: scp-shmem@0 { + compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem"; + reg = <0x47000 0x400>; + }; + + cpu_scp_hpri: scp-shmem@200 { + compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem"; + reg = <0x47400 0x400>; + }; + }; + + cbus: cbus@fe070000 { + compatible = "simple-bus"; + reg = <0x0 0xfe070000 0x0 0xF000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xfe070000 0x0 0xF000>; + + uart_a: serial@8000 { + compatible = "amlogic,meson-uart"; + reg = <0x0 0x8000 0x0 0x18>; + clocks = <&xtal>; + status = "disabled"; + }; + + uart_b: serial@a000 { + compatible = "amlogic,meson-uart"; + reg = <0x0 0xa000 0x0 0x18>; + clocks = <&xtal>; + status = "disabled"; + }; + + ir: ir@8040 { + compatible = "amlogic,meson-gx-ir", "amlogic,meson-gxbb-ir"; + reg = <0x0 0x8040 0x0 0x40>; + interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + }; + + reset: reset-controller@1000 { + compatible = "amlogic,meson-gx-reset", "amlogic,meson-gxbb-reset"; + reg = <0x0 0x01000 0x0 0x1000>; + #reset-cells = <1>; + }; + + uart_c: serial@22000 { + compatible = "amlogic,meson-uart"; + reg = <0x0 0x22000 0x0 0x18>; + interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>; + clocks = <&xtal>; + status = "disabled"; + }; + + spicc0: spi@3800 { + compatible = "amlogic,meson-g12a-spicc"; + reg = <0x0 0x3800 0x0 0x44>; + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spicc1: spi@3c00 { + compatible = "amlogic,meson-g12a-spicc"; + reg = <0x0 0x3c00 0x0 0x44>; + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + jtag { + compatible = "amlogic, jtag"; + status = "okay"; + select = "disable"; /* disable/jtag-a/jtag-b */ + pinctrl-names="jtag_a_pins", "jtag_b_pins"; + pinctrl-0=<&jtag_a_pins>; + pinctrl-1=<&jtag_b_pins>; + }; + }; + + periphs: periphs@ff634000 { + compatible = "simple-bus"; + reg = <0x0 0xff634000 0x0 0x2000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>; + + hwrng: rng { + compatible = "amlogic,meson-rng"; + reg = <0x0 0x0 0x0 0x4>; + }; + }; + + hiubus: hiubus@ff63c000 { + compatible = "simple-bus"; + reg = <0x0 0xff63c000 0x0 0x2000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x2000>; + + mailbox: mailbox@404 { + compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu"; + reg = <0 0x404 0 0x4c>; + interrupts = <0 208 IRQ_TYPE_EDGE_RISING>, + <0 209 IRQ_TYPE_EDGE_RISING>, + <0 210 IRQ_TYPE_EDGE_RISING>; + #mbox-cells = <1>; + }; + }; + + clkc: clock-controller@0 { + compatible = "amlogic,s4-clkc"; + #clock-cells = <1>; + reg = <0x0 0xfe000000 0x0 0x82e8>; + clocks = <&xtal>; + clock-names = "xtal"; + }; + + i2c0: i2c@fe066000 { + compatible = "amlogic,meson-i2c"; + reg = <0x0 0xfe066000 0x0 0x24>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@fe068000 { + compatible = "amlogic,meson-i2c"; + reg = <0x0 0xfe068000 0x0 0x24>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@fe06a000 { + compatible = "amlogic,meson-i2c"; + reg = <0x0 0xfe06a000 0x0 0x24>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@fe06c000 { + compatible = "amlogic,meson-i2c"; + reg = <0x0 0xfe06c000 0x0 0x24>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@fe06e000 { + compatible = "amlogic,meson-i2c"; + reg = <0x0 0xfe06e000 0x0 0x24>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spifc: spi@fe056000 { + compatible = "amlogic,spifc"; + status = "disabled"; + reg = <0x0 0xfe056000 0x0 0x80>; + /* clocks = <&clkc CLKID_CLK81>; */ + /* clock-names = "core"; */ + pinctrl-names = "default"; + pinctrl-0 = <&spifc_pins>; + #address-cells = <1>; + #size-cells = <0>; + spi-flash@0 { + compatible = "spi-flash"; + reg = <0>; + spi-max-frequency = <20000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + status = "disabled"; + }; + spi-nand@1 { + compatible = "spi-nand"; + reg = <1>; + spi-max-frequency = <20000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + status = "disabled"; + }; + }; + + ethmac: ethernet@ff3f0000 { + compatible = "amlogic,g12a-eth-dwmac"; + phy_cntl1 = <0x41054147>; + pll_val = <0x9c0040a 0x927e0000 0xac5f49e5>; + analog_val = <0x20200000 0x0000c000 0x00000023>; + status = "disabled"; + }; + + saradc: adc@fe026000 { + compatible = "amlogic,meson-saradc"; + reg = <0x0 0xfe026000 0x0 0x48>; + status = "disabled"; + }; + + nand: nfc@fe08c800 { + compatible = "amlogic,meson-nfc"; + reg = <0x0 0xfe08c800 0x0 0x200>; + interrupts = <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + clk_reg = <0 0xfe08c000>; + }; + + apb: apb@fe000000 { + compatible = "simple-bus"; + reg = <0x0 0xfe000000 0x0 0x1000000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x1000000>; + + watchdog@2100 { + compatible = "amlogic,meson-sc2-wdt"; + reg = <0x0 0x2100 0x0 0x10>; + clocks = <&xtal>; + clock-names = "wdt-clk"; + }; + + sd_emmc_a: sdio { + compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; + reg = <0x0 0x88000 0x0 0x800>; + interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + pinname = "sdio"; + }; + + sd_emmc_b: sd { + compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; + reg = <0x0 0x8a000 0x0 0x800>; + interrupts = <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + pinname = "sd"; + }; + + sd_emmc_c: emmc { + compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; + reg = <0x0 0x8c000 0x0 0x800>; + interrupts = <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + pinname = "emmc"; + }; + }; + + crg: crg@fde00000 { + compatible = "crg-xhci"; + status = "disable"; + reg = <0x0 0xfde00000 0x0 0x100000>; + phys = <&usb2_phy_v2>, <&usb3_phy_v2>; + phy-names = "usb2-phy", "usb3-phy"; + }; + + usb2_phy_v2: usb2phy@fe03a000 { + compatible = "amlogic, amlogic-new-usb2-v2"; + status = "disable"; + #address-cells = <2>; + #size-cells = <2>; + phy-version = <2>; + reg = <0x0 0xfe03a000 0x0 0x80 + 0x0 0xFE002000 0x0 0x100 + 0x0 0xfe03c000 0x0 0x2000 + 0x0 0xfe03e000 0x0 0x2000>; + dwc2_a_reg = <0xfdd00000>; + #phy-cells = <0>; + }; + + usb3_phy_v2: usb3phy@fe03a080 { + compatible = "amlogic, amlogic-new-usb3-v2"; + status = "disable"; + #address-cells = <2>; + #size-cells = <2>; + phy-version = <3>; + reg = <0x0 0xfe03a080 0x0 0x20>; + phy-reg = <0xfe03c000>; + phy-reg-size = <0x2000>; + usb2-phy-reg = <0xfe03a000>; + usb2-phy-reg-size = <0x80>; + #phy-cells = <0>; + }; + }; +};
diff --git a/arch/arm/dts/meson-s4-t211.dts b/arch/arm/dts/meson-s4-t211.dts new file mode 100644 index 0000000..9c8ec03 --- /dev/null +++ b/arch/arm/dts/meson-s4-t211.dts
@@ -0,0 +1,130 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include <dt-bindings/usb/pd.h> +#include "meson-s4-t211.dtsi" +#include "meson-s4_skt-panel.dtsi" + +/ { + compatible = "amlogic,s4-t211", "amlogic,s4-txxx", "amlogic,meson-s4"; + model = "Amlogic Meson S4 T211 Board"; +}; + +/* This UART is brought out to the DB9 connector */ +&uart_a { + status = "okay"; +}; + +&uart_b { + status = "disabled"; +}; + +&saradc { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + pinctrl-names="default"; + pinctrl-0=<&i2c0_pins1>; + clock-frequency = <100000>; +}; + +/* demo for i2c user */ +&i2c3 { + status= "disabled"; + clock-frequency = <100000>; + /* pinctrl-names = "default";*/ + /* pinctrl-0 = <&i2c3_master_pins2>;*/ +}; + +&i2c4 { + status = "okay"; + pinctrl-names="default"; + pinctrl-0=<&i2c4_pins2>; + clock-frequency = <100000>; + rt1711h@4e { + compatible = "richtek,rt1711h"; + reg = <0x4e>; + label = "rt1711h"; + gpios = <&gpio GPIOC_7 GPIO_ACTIVE_LOW>; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "sink"; + data-role = "dual"; + /* Only support one sink-pdo instead of many */ + sink-pdo = <PDO_FIXED(5000, 900, PDO_FIXED_USB_COMM)>; + op-sink-microwatt = <4500000>; + no-vconn; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + }; + }; + + }; + }; +}; + + +&pinctrl_periphs { + bl_pwm_off_pins:bl_pwm_off_pin { + mux { + groups = "GPIOH_5"; + function = "gpio_periphs"; + output-high; + }; + }; +}; /* end of pinctrl_periphs */ + +&fb { + logo_addr = "0x3f800000"; +};
diff --git a/arch/arm/dts/meson-s4-t211.dtsi b/arch/arm/dts/meson-s4-t211.dtsi new file mode 100644 index 0000000..1f45d80 --- /dev/null +++ b/arch/arm/dts/meson-s4-t211.dtsi
@@ -0,0 +1,255 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>. + * Based on meson-gx-p23x-q20x.dtsi: + * - Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * - Copyright (c) 2016 BayLibre, SAS. + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +/* Common DTSI for devices which are based on the P212 reference board. */ + +#include "meson-s4-txxx.dtsi" + +/ { + aliases { + serial0 = &uart_a; + serial1 = &uart_b; + spi0 = &spifc; + spi1 = &spicc0; + spi2 = &spicc1; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + }; + + chosen { + stdout-path = "serial1:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + vddio_boot: regulator-vddio_boot { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vddio_ao18: regulator-vddio_ao18 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + /*reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;*/ + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; + + tee: tee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + + amhdmitx { + compatible = "amlogic, amhdmitx-s4"; + status = "okay"; + res_1080p = <1>; + }; +}; + +ðmac { + status = "okay"; + internal_phy = <1>; + mc_val = <0x4be04>; + /*mc_val = <0x1621>;*/ +}; + +&ir { + status = "disabled"; + /* pinctrl-0 = <&remote_input_ao_pins>; */ + /* pinctrl-names = "default"; */ +}; + +&saradc { + status = "disabled"; + vref-supply = <&vddio_ao18>; +}; + +/* Wireless SDIO Module */ +&sd_emmc_a { + status = "disabled"; + /*pinctrl-0 = <&sdio_pins>;*/ + /*pinctrl-names = "default";*/ + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + + non-removable; + disable-wp; + card_type = <3>; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_pins>; + pinctrl-1 = <&sdcard_pins &to_sduart_pins>; + pinctrl-names = "sd_all_pins", "sd_uart"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>; + cd-inverted; + + card_type = <5>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + sd_hs_co_phase = <2>; + sd_hs_to_phase = <0>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + max-frequency = <200000000>; + non-removable; + disable-wp; + /* mmc-ddr-1_8v; */ + card_type = <1>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + hs_co_phase = <2>; + hs_to_phase = <0>; + + hs2_co_phase = <2>; + hs2_to_phase = <0>; + + hw_reset = <&gpio GPIOB_9 GPIO_ACTIVE_HIGH>; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* nand */ +&nand { + status = "okay"; + pinctrl-names = "default", "nand_cs_only"; + pinctrl-0 = <&all_nand_pins>; + pinctrl-1 = <&nand_cs_pins>; +}; + +&crg { + status = "okay"; + dr_mode = "host"; +}; + +&usb2_phy_v2 { + status = "okay"; + portnum = <2>; +}; + +&usb3_phy_v2 { + status = "okay"; + portnum = <0>; + gpio-vbus-power = "GPIOH_6"; + gpios = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>; +}; + +&pwm_ef { + status = "okay"; + /* pinctrl-0 = <&pwm_e_pins>; */ + /* pinctrl-names = "default"; */ +}; + +/* This is connected to the Bluetooth module: */ +&uart_b { + status = "okay"; + /* pinctrl-0 = <&a_uart_pins>; */ + /* pinctrl-names = "default"; */ + uart-has-rtscts; +}; + +&spifc { + status = "disabled"; + //cs-gpios = <&gpio GPIOB_14 GPIO_ACTIVE_HIGH>; + spi-flash@0 { + status = "disabled"; + }; +}; + +&spicc0 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc0_pins1>; + //cs-gpios = <&gpio GPIOA_8 0>, + // <&gpio GPIOA_9 0>; +}; + +&spicc1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc1_pins1>; + //cs-gpios = <&gpio GPIOA_14 0>; +};
diff --git a/arch/arm/dts/meson-s4-txxx.dtsi b/arch/arm/dts/meson-s4-txxx.dtsi new file mode 100644 index 0000000..81d562d --- /dev/null +++ b/arch/arm/dts/meson-s4-txxx.dtsi
@@ -0,0 +1,54 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "meson-s4.dtsi" +#include "meson-s4-mali.dtsi" + +/ { + compatible = "amlogic,txxx", "amlogic,meson-s4"; +}; + +ðmac { + phy-mode = "rmii"; + phy-handle = <&internal_phy>; +};
diff --git a/arch/arm/dts/meson-s4.dtsi b/arch/arm/dts/meson-s4.dtsi new file mode 100644 index 0000000..a7d1644 --- /dev/null +++ b/arch/arm/dts/meson-s4.dtsi
@@ -0,0 +1,715 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "meson-s4-series.dtsi" +#include <dt-bindings/gpio/meson-s4-gpio.h> +#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h> +#include <dt-bindings/pwm/pwm.h> +#include <dt-bindings/pwm/meson.h> + +/ { + compatible = "amlogic,meson-s4"; + + vpu: vpu { + compatible = "amlogic, vpu-s4"; + status = "okay"; + /*clocks = <&clkc CLKID_VAPB_MUX>, + * <&clkc CLKID_VPU_INTR>, + * <&clkc CLKID_VPU_P0_COMP>, + * <&clkc CLKID_VPU_P1_COMP>, + * <&clkc CLKID_VPU_MUX>; + *clock-names = "vapb_clk", + * "vpu_intr_gate", + * "vpu_clk0", + * "vpu_clk1", + * "vpu_clk"; + */ + clk_level = <7>; + /* 0: 100.0M 1: 166.7M 2: 200.0M 3: 250.0M */ + /* 4: 333.3M 5: 400.0M 6: 500.0M 7: 666.7M */ + }; + + fb: fb { + status = "okay"; + logo_addr = "0x5f800000"; + }; + + pinctrl_periphs: pinctrl@fe004000 { + compatible = "amlogic,meson-s4-periphs-pinctrl"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio: bank@fe004000 { + reg = <0x0 0xfe004000 0x0 0x0064>, + <0x0 0xfe0040c0 0x0 0x0220>; + reg-names = "mux", + "gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_periphs 0 0 82>; + }; + }; + + i2c_gpio_0: i2c-gpio-0 { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "i2c-gpio"; + status = "okay"; + gpios = <&gpio GPIOH_0 GPIO_ACTIVE_HIGH>, /* SDA */ + <&gpio GPIOH_1 GPIO_ACTIVE_HIGH>; /* CLK */ + + i2c-gpio,delay-us = <5>; + is_odpin = <1>; + }; + + pwm_ab: pwm@fe058000 { + compatible = "amlogic,meson-v2-pwm"; + reg = <0x0 0xfe058000 0x0 0x20>, + <0x0 0xfe000180 0x0 0x04>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm_cd: pwm@fe05a000 { + compatible = "amlogic,meson-v2-pwm"; + reg = <0x0 0xfe05a000 0x0 0x20>, + <0x0 0xfe000184 0x0 0x04>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm_ef: pwm@fe05c000 { + compatible = "amlogic,meson-v2-pwm"; + reg = <0x0 0xfe05c000 0x0 0x20>, + <0x0 0xfe000188 0x0 0x04>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm_gh: pwm@fe05e000 { + compatible = "amlogic,meson-v2-pwm"; + reg = <0x0 0xfe05e000 0x0 0x20>, + <0x0 0xfe00018c 0x0 0x04>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm_ij: pwm@fe060000 { + compatible = "amlogic,meson-v2-pwm"; + reg = <0x0 0xfe060000 0x0 0x20>, + <0x0 0xfe000190 0x0 0x04>; + #pwm-cells = <3>; + status = "disabled"; + }; +}; + +ðmac { + compatible = "amlogic,g12a-eth-dwmac"; + reg = <0x0 0xfdc00000 0x0 0x10000 + 0x0 0xFE024000 0x0 0x8 + 0x0 0xFE028000 0x0 0xa0>; + reg-names = "eth_base", "eth_top", "eth_cfg"; + phy_cntl1 = <0x41054147>; + internal_phy = <1>; + mc_val = <0x4be04>; + pll_val = <0x9c0040a 0x927e0000 0xac5f49e5>; + analog_val = <0x20200000 0x0000c000 0x00000023>; + chip_num = <3>; + //tx_amp_src = <0xfe005b30>; +// clocks = <&clkc CLKID_ETH_CORE>, +// <&clkc CLKID_FCLK_DIV2>, +// <&clkc CLKID_MPLL2>; +// clock-names = "stmmaceth", "clkin0", "clkin1"; + + mdio0: mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + }; +}; + +&periphs { + + eth-phy-mux { + compatible = "mdio-mux-mmioreg", "mdio-mux"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x15c 0x0 0x4>; + mux-mask = <0xffffffff>; + mdio-parent-bus = <&mdio0>; + + internal_mdio: mdio@e40908ff { + reg = <0xe40908ff>; + #address-cells = <1>; + #size-cells = <0>; + + internal_phy: ethernet-phy@8 { + compatible = "ethernet-phy-id0181.4400", "ethernet-phy-ieee802.3-c22"; + reg = <8>; + max-speed = <100>; + }; + }; + + external_mdio: mdio@2009087f { + reg = <0x2009087f>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&saradc { + compatible = "amlogic,meson-g12a-saradc", "amlogic,meson-saradc"; + clocks = <&xtal>, + <&clkc CLKID_SARADC_MUX>, + <&clkc CLKID_SARADC_DIV>, + <&clkc CLKID_SAR_ADC_GATE>; + clock-names = "xtal", "adc_mux", "adc_div", "adc_gate"; +}; + +&sd_emmc_a { + clocks = <&clkc CLKID_SD_EMMC_A_MUX>, + <&clkc CLKID_SD_EMMC_A_DIV>, + <&clkc CLKID_SD_EMMC_A_GATE>, + <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_XTAL>; + clock-names = "mux", "div", "gate", "clkin", "xtal"; +}; + +&sd_emmc_b { + clocks = <&clkc CLKID_SD_EMMC_B_MUX>, + <&clkc CLKID_SD_EMMC_B_DIV>, + <&clkc CLKID_SD_EMMC_B_GATE>, + <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_XTAL>; + clock-names = "mux", "div", "gate", "clkin", "xtal"; +}; + +&sd_emmc_c { + clocks = <&clkc CLKID_SD_EMMC_C_MUX>, + <&clkc CLKID_SD_EMMC_C_DIV>, + <&clkc CLKID_SD_EMMC_C_GATE>, + <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_XTAL>; + clock-names = "mux", "div", "gate", "clkin", "xtal"; +}; + +&nand { + clocks = <&clkc CLKID_SD_EMMC_C_MUX>, + <&clkc CLKID_SD_EMMC_C_DIV>, + <&clkc CLKID_SD_EMMC_C_GATE>, + <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_XTAL>; + clock-names = "mux", "div", "gate", "fdiv2", "xtal"; +}; + +/* +&spicc0 { + clocks = <&clkc CLKID_SPICC0>, + <&clkc CLKID_SPICC0_COMP>; + clock-names = "core", "comp"; +}; + +&spicc1 { + clocks = <&clkc CLKID_SPICC1>, + <&clkc CLKID_SPICC1_COMP>; + clock-names = "core", "comp"; + }; +*/ +&pinctrl_periphs { + i2c0_pins1:i2c0_pins1 { + mux { + groups = "i2c0_sda", + "i2c0_scl"; + function = "i2c0"; + drive-strength = <3>; + bias-disable; + }; + }; + + i2c1_pins1:i2c1_pins1 { + mux { + groups = "i2c1_sda_c", + "i2c1_scl_c"; + function = "i2c1"; + drive-strength = <3>; + bias-disable; + }; + }; + + i2c1_pins2:i2c1_pins2 { + mux { + groups = "i2c1_sda_d", + "i2c1_scl_d"; + function = "i2c1"; + drive-strength = <3>; + bias-disable; + }; + }; + + i2c1_pins3:i2c1_pins3 { + mux { + groups = "i2c1_sda_h", + "i2c1_scl_h"; + function = "i2c1"; + drive-strength = <3>; + bias-disable; + }; + }; + + i2c1_pins4:i2c1_pins4 { + mux { + groups = "i2c1_sda_x", + "i2c1_scl_x"; + function = "i2c1"; + drive-strength = <3>; + bias-disable; + }; + }; + + i2c2_pins1:i2c2_pins1 { + mux { + groups = "i2c2_sda_d", + "i2c2_scl_d"; + function = "i2c2"; + drive-strength = <3>; + bias-disable; + }; + }; + + i2c2_pins2:i2c2_pins2 { + mux { + groups = "i2c2_sda_h8", + "i2c2_scl_h9"; + function = "i2c2"; + drive-strength = <3>; + bias-disable; + }; + }; + + i2c2_pins3:i2c2_pins3 { + mux { + groups = "i2c2_sda_h0", + "i2c2_scl_h1"; + function = "i2c2"; + drive-strength = <3>; + bias-disable; + }; + }; + + i2c3_pins1:i2c3_pins1 { + mux { + groups = "i2c3_sda_x", + "i2c3_scl_x"; + function = "i2c3"; + drive-strength = <3>; + bias-disable; + }; + }; + + i2c3_pins2:i2c3_pins2 { + mux { + groups = "i2c3_sda_z", + "i2c3_scl_z"; + function = "i2c3"; + drive-strength = <3>; + bias-disable; + }; + }; + + i2c4_pins1:i2c4_pins1 { + mux { + groups = "i2c4_sda_c", + "i2c4_scl_c"; + function = "i2c4"; + drive-strength = <3>; + bias-disable; + }; + }; + + i2c4_pins2:i2c4_pins2 { + mux { + groups = "i2c4_sda_d", + "i2c4_scl_d"; + function = "i2c4"; + drive-strength = <3>; + bias-disable; + }; + }; + + i2c4_pins3:i2c4_pins3 { + mux { + groups = "i2c4_sda_z", + "i2c4_scl_z"; + function = "i2c4"; + drive-strength = <3>; + bias-disable; + }; + }; + + jtag_a_pins:jtag_a_pin { + mux { + groups = "jtag_1_clk", + "jtag_1_tms", + "jtag_1_tdi", + "jtag_1_tdo"; + function = "jtag_1"; + }; + }; + + jtag_b_pins:jtag_b_pin { + mux { + groups = "jtag_2_clk", + "jtag_2_tms", + "jtag_2_tdi", + "jtag_2_tdo"; + function = "jtag_2"; + }; + }; + + swd_a_pins:swd_a_pin { + mux { + groups = "swclk", + "swdio"; + function = "sw"; + }; + }; + + emmc_pins: emmc { + mux { + groups = "emmc_nand_d0", + "emmc_nand_d1", + "emmc_nand_d2", + "emmc_nand_d3", + "emmc_nand_d4", + "emmc_nand_d5", + "emmc_nand_d6", + "emmc_nand_d7", + "emmc_clk", + "emmc_cmd"; + function = "emmc"; + bias-pull-up; + input-enable; + }; + mux1 { + groups = "emmc_nand_ds"; + function = "emmc"; + input-enable; + bias-pull-down; + }; + }; + + emmc_clk_gate_pins: emmc_clk_gate { + mux { + groups = "emmc_clk"; + function = "emmc"; + bias-pull-down; + }; + }; + + all_nand_pins: all_nand_pins { + mux { + groups = "emmc_nand_d0", + "emmc_nand_d1", + "emmc_nand_d2", + "emmc_nand_d3", + "emmc_nand_d4", + "emmc_nand_d5", + "emmc_nand_d6", + "emmc_nand_d7", + "nand_ce0", + "nand_ale", + "nand_cle", + "nand_wen_clk", + "nand_ren_wr"; + function = "nand"; + input-enable; + }; + }; + + nand_cs_pins: nand_cs { + mux { + groups = "nand_ce0"; + function = "nand"; + }; + }; + + sdcard_pins: sdcard { + mux { + groups = "sdcard_d0_c", + "sdcard_d1_c", + "sdcard_d2_c", + "sdcard_d3_c", + "sdcard_cmd_c"; + function = "sdcard"; + bias-pull-up; + input-enable; + drive-strength = <4>; + }; + mux1 { + groups ="sdcard_clk_c"; + function = "sdcard"; + bias-pull-up; + output-high; + drive-strength = <4>; + }; + }; + + sdcard_clk_gate_pins: sdcard_clk_gate { + mux { + groups = "sdcard_clk_c"; + function = "sdcard"; + bias-pull-down; + }; + }; + + to_sduart_pins: to_sduart_pins{ + mux { + groups = "uart_b_rx_c", "uart_b_tx_c"; + function = "uart_b"; + bias-pull-up; + input-enable; + }; + }; + + sd_to_uart_pins: sd_to_uart_pins{ + mux { + groups = "uart_b_rx_d", "uart_b_tx_d"; + function = "uart_b"; + bias-pull-up; + input-enable; + }; + }; + + spicc0_pins1: spicc0_pins1 { + mux { + groups = "spi_a_mosi_a", + "spi_a_miso_a", + "spi_a_sclk_a"; + function = "spi_a"; + drive-strength = <2>; + }; + }; + + spicc0_pins2: spicc0_pins2 { + mux { + groups = "spi_a_mosi_c", + "spi_a_miso_c", + "spi_a_sclk_c"; + function = "spi_a"; + drive-strength = <2>; + }; + }; + + spicc1_pins1: spicc1_pins1 { + mux { + groups = "spi_b_mosi_a", + "spi_b_miso_a", + "spi_b_sclk_a"; + function = "spi_b"; + drive-strength = <2>; + }; + }; + + spifc_pins: spifc_pins { + mux { + groups = "spif_hold", + "spif_mo", + "spif_mi", + //"spif_cs", + "spif_clk", + "spif_wp"; + function = "spif"; + drive-strength = <3>; + }; + }; + + pwm_a_pins: pwm_a_pins { + mux { + groups = "pwm_a_d"; + function = "pwm_a"; + }; + }; + + pwm_b_pins1: pwm_b_pins1 { + mux { + groups = "pwm_b_d"; + function = "pwm_b"; + }; + }; + + pwm_b_pins2: pwm_b_pins2 { + mux { + groups = "pwm_b_x"; + function = "pwm_b"; + }; + }; + + pwm_c_pins1: pwm_c_pins1 { + mux { + groups = "pwm_c_d"; + function = "pwm_c"; + }; + }; + + pwm_c_pins2: pwm_c_pins2 { + mux { + groups = "pwm_c_x"; + function = "pwm_c"; + }; + }; + + pwm_d_pins1: pwm_d_pins1 { + mux { + groups = "pwm_d_d"; + function = "pwm_d"; + }; + }; + + pwm_d_pins2: pwm_d_pins2 { + mux { + groups = "pwm_d_h"; + function = "pwm_d"; + }; + }; + + pwm_e_pins1: pwm_e_pins1 { + mux { + groups = "pwm_e_x"; + function = "pwm_e"; + }; + }; + + pwm_e_pins2: pwm_e_pins2 { + mux { + groups = "pwm_e_z"; + function = "pwm_e"; + }; + }; + + pwm_f_pins1: pwm_f_pins1 { + mux { + groups = "pwm_f_x"; + function = "pwm_f"; + }; + }; + + pwm_f_pins2: pwm_f_pins2 { + mux { + groups = "pwm_f_z"; + function = "pwm_f"; + }; + }; + + pwm_g_pins1: pwm_g_pins1 { + mux { + groups = "pwm_g_d"; + function = "pwm_g"; + }; + }; + + pwm_g_pins2: pwm_g_pins2 { + mux { + groups = "pwm_g_z"; + function = "pwm_g"; + }; + }; + + pwm_h_pins: pwm_h_pins { + mux { + groups = "pwm_h"; + function = "pwm_h"; + }; + }; + + pwm_i_pins1: pwm_i_pins1 { + mux { + groups = "pwm_i_d"; + function = "pwm_i"; + }; + }; + + pwm_i_pins2: pwm_i_pins2 { + mux { + groups = "pwm_i_h"; + function = "pwm_i"; + }; + }; + + pwm_j_pins: pwm_j_pins { + mux { + groups = "pwm_j"; + function = "pwm_j"; + }; + }; + + pwm_a_hiz_pins: pwm_a_hiz_pins { + mux { + groups = "pwm_a_hiz"; + function = "pwm_a_hiz"; + }; + }; + + pwm_b_hiz_pins: pwm_b_hiz_pins { + mux { + groups = "pwm_b_hiz"; + function = "pwm_b_hiz"; + }; + }; + + pwm_c_hiz_pins: pwm_c_hiz_pins { + mux { + groups = "pwm_c_hiz"; + function = "pwm_b_hiz"; + }; + }; + + pwm_g_hiz_pins: pwm_g_hiz_pins { + mux { + groups = "pwm_g_hiz"; + function = "pwm_g_hiz"; + }; + }; +};
diff --git a/arch/arm/dts/meson-s4_skt-panel.dtsi b/arch/arm/dts/meson-s4_skt-panel.dtsi new file mode 100644 index 0000000..fbb676c --- /dev/null +++ b/arch/arm/dts/meson-s4_skt-panel.dtsi
@@ -0,0 +1,742 @@ +/* + * arch/arm64/boot/dts/amlogic/mesong12a_skt-panel.dtsi + * + * Copyright (C) 2016 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/ { + lcd{ + compatible = "amlogic, lcd-g12a"; + mode = "tablet"; + status = "okay"; + key_valid = <0>; + /* + clocks = <&clkc CLKID_MIPI_DSI_HOST + &clkc CLKID_MIPI_DSI_PHY + &clkc CLKID_DSI_MEAS_COMP + &clkc CLKID_VCLK2_ENCL + &clkc CLKID_VCLK2_VENCL + &clkc CLKID_GP0_PLL>; + clock-names = "dsi_host_gate", + "dsi_phy_gate", + "dsi_meas", + "encl_top_gate", + "encl_int_gate", + "gp0_pll"; + */ + reg = <0x0 0xffd07000 0x0 0x400 /* dsi_host */ + 0x0 0xff644000 0x0 0x200>; /* dsi_phy */ + interrupts = <0 3 1 + 0 56 1>; + interrupt-names = "vsync","vsync2"; + pinctrl_version = <2>; /* for uboot */ + + /* power type: + * (0=cpu_gpio, 1=pmu_gpio, 2=signal,3=extern, 0xff=ending) + * power index: + * (point gpios_index, or extern_index,0xff=invalid) + * power value:(0=output low, 1=output high, 2=input) + * power delay:(unit in ms) + */ + + /*lcd_cpu-gpios = <&gpio GPIOZ_9 GPIO_ACTIVE_HIGH + &gpio GPIOZ_8 GPIO_ACTIVE_HIGH>; + */ + lcd_cpu_gpio_names = "GPIOZ_9","GPIOZ_8"; + + lcd_0{ + model_name = "B080XAN01"; + interface = "mipi"; + basic_setting = <768 1024 /*h_active, v_active*/ + 948 1140 /*h_period, v_period*/ + 8 /*lcd_bits*/ + 119 159>; /*screen_widht, screen_height*/ + lcd_timing = <64 56 0 /*hs_width, hs_bp, hs_pol*/ + 50 30 0>; /*vs_width, vs_bp, vs_pol*/ + clk_attr = <0 /*fr_adj_type(0=clk, 1=htotal, 2=vtotal)*/ + 0 /*clk_ss_level */ + 1 /*clk_auto_generate*/ + 64843200>; /*pixel_clk(unit in Hz)*/ + mipi_attr = <4 /*lane_num*/ + 550 /*bit_rate_max(MHz)*/ + 0 /*factor(*100, default 0 for auto)*/ + 1 /*operation_mode_init(0=video, 1=command)*/ + 0 /*operation_mode_display(0=video, 1=command)*/ + 2 /* + *video_mode_type + *(0=sync_pulse,1=sync_event,2=burst) + */ + 1 /*clk_always_hs(0=disable,1=enable)*/ + 0>; /*phy_switch(0=auto,1=standard,2=slow)*/ + + /* dsi_init: data_type, num, data... */ + dsi_init_on = <0x05 1 0x11 + 0xfd 1 20 /*delay(ms)*/ + 0x05 1 0x29 + 0xfd 1 20 /*delay(ms)*/ + 0xff 0>; /*ending*/ + dsi_init_off = <0x05 1 0x28 + 0xfd 1 10 /*delay(ms)*/ + 0x05 1 0x10 + 0xfd 1 10 /*delay(ms)*/ + 0xff 0>; /*ending*/ + extern_init = <0xff>; /*0xff for invalid*/ + + /* power step: type, index, value, delay(ms) */ + power_on_step = < + 0 1 0 100 + 0 0 0 10 + 0 0 1 20 + 2 0 0 0 + 0xff 0 0 0>; /*ending*/ + power_off_step = < + 2 0 0 50 + 0 0 0 10 + 0 1 1 100 + 0xff 0 0 0>; /*ending*/ + backlight_index = <0>; + }; + + lcd_1{ + model_name = "P070ACB_FT"; + interface = "mipi"; + basic_setting = <600 1024 /*h_active, v_active*/ + 770 1070 /*h_period, v_period*/ + 8 /*lcd_bits*/ + 3 5>; /*screen_widht, screen_height*/ + lcd_timing = <10 80 0 /*hs_width,hs_bp,hs_pol*/ + 6 20 0>; /*vs_width,vs_bp,vs_pol*/ + clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/ + 0 /*clk_ss_level*/ + 1 /*clk_auto_generate*/ + 49434000>; /*pixel_clk(unit in Hz)*/ + mipi_attr = <4 /*lane_num*/ + 400 /*bit_rate_max(MHz)*/ + 0 /*factor(*100, default 0 for auto)*/ + 1 /*operation_mode_init(0=video, 1=command)*/ + 0 /*operation_mode_display(0=video, 1=command)*/ + 2 /* + *video_mode_type + *(0=sync_pulse,1=sync_event,2=burst) + */ + 0 /*clk_always_hs(0=disable,1=enable)*/ + 0>; /*phy_switch(0=auto,1=standard,2=slow)*/ + /* dsi_init: data_type, num, data... */ + dsi_init_on = < + 0xff 10 + 0xf0 3 0 1 30 /* reset high, delay 30ms */ + 0xf0 3 0 0 10 /* reset low, delay 10ms */ + 0xf0 3 0 1 30 /* reset high, delay 30ms */ + 0xfc 2 0x04 3 /* check_reg, check_cnt */ + 0xff 0>; /* ending flag */ + dsi_init_off = <0xff 0>; /* ending flag */ + /* extern_init: 0xff for invalid */ + extern_init = <2>; + /* power step: type,index,value,delay(ms) */ + power_on_step = < + 0 1 0 200 /* panel power on */ + 2 0 0 0 + 0xff 0 0 0>; + power_off_step = < + 2 0 0 0 + 0 0 0 20 /* reset low */ + 0 1 1 100 /* panel power off */ + 0xff 0 0 0>; + backlight_index = <0>; + }; + + lcd_3{ + model_name = "TL050FHV02CT"; + interface = "mipi"; + basic_setting = <1080 1920 /*h_active, v_active*/ + 1125 2100 /*h_period, v_period*/ + 8 /*lcd_bits*/ + 65 119>; /*screen_widht, screen_height*/ + lcd_timing = <5 30 0 /*hs_width,hs_bp,hs_pol*/ + 44 108 0>; /*vs_width,vs_bp,vs_pol*/ + clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/ + 0 /*clk_ss_level*/ + 1 /*clk_auto_generate*/ + 118125000>; /*pixel_clk(unit in Hz)*/ + mipi_attr = <4 /*lane_num*/ + 960 /*bit_rate_max(MHz)*/ + 0 /*factor(*100, default 0 for auto)*/ + 1 /*operation_mode_init(0=video, 1=command)*/ + 0 /*operation_mode_display(0=video, 1=command)*/ + 2 /* + *video_mode_type + *(0=sync_pulse,1=sync_event,2=burst) + */ + 1 /*clk_always_hs(0=disable,1=enable)*/ + 0>; /*phy_switch(0=auto,1=standard,2=slow)*/ + /* dsi_init: data_type, num, data... */ + dsi_init_on = <0xff 0>; /* ending flag */ + dsi_init_off = <0xff 0>; /* ending flag */ + /* extern_init: 0xff for invalid */ + extern_init = <3>; + /* power step: type,index,value,delay(ms) */ + power_on_step = < + 0 1 0 200 + 0 0 1 20 + 0 0 0 10 + 0 0 1 20 + 2 0 0 0 + 0xff 0 0 0>; + power_off_step = < + 2 0 0 0 + 0 0 0 20 + 0 1 1 100 + 0xff 0 0 0>; + backlight_index = <0>; + }; + + lcd_4{ + model_name = "TL070WSH27"; + interface = "mipi"; + basic_setting = <1024 600 /*h_active, v_active*/ + 1250 630 /*h_period, v_period*/ + 8 /*lcd_bits*/ + 154 86>; /*screen_widht, screen_height*/ + lcd_timing = <80 100 0 /*hs_width, hs_bp, hs_pol*/ + 5 20 0>; /*vs_width, vs_bp, vs_pol*/ + clk_attr = <0 /*fr_adj_type(0=clk, 1=htotal, 2=vtotal)*/ + 0 /*clk_ss_level */ + 1 /*clk_auto_generate*/ + 47250000>; /*pixel_clk(unit in Hz)*/ + mipi_attr = <4 /*lane_num*/ + 300 /*bit_rate_max(MHz)*/ + 0 /*factor(*100, default 0 for auto)*/ + 1 /*operation_mode_init(0=video, 1=command)*/ + 0 /*operation_mode_display(0=video, 1=command)*/ + 2 /* + *video_mode_type + *(0=sync_pulse,1=sync_event,2=burst) + */ + 1 /*clk_always_hs(0=disable,1=enable)*/ + 0>; /*phy_switch(0=auto,1=standard,2=slow)*/ + + /* dsi_init: data_type, num, data... */ + dsi_init_on = <0x05 1 0x11 + 0xfd 1 20 /*delay(ms)*/ + 0x05 1 0x29 + 0xfd 1 20 /*delay(ms)*/ + 0xff 0>; /*ending*/ + dsi_init_off = <0x05 1 0x28 + 0xfd 1 10 /*delay(ms)*/ + 0x05 1 0x10 + 0xfd 1 10 /*delay(ms)*/ + 0xff 0>; /*ending*/ + extern_init = <0xff>; /*0xff for invalid*/ + + /* power step: type, index, value, delay(ms) */ + power_on_step = < + 0 1 0 100 + 0 0 0 10 + 0 0 1 20 + 2 0 0 0 + 0xff 0 0 0>; /*ending*/ + power_off_step = < + 2 0 0 50 + 0 0 0 10 + 0 1 1 100 + 0xff 0 0 0>; /*ending*/ + backlight_index = <0>; + }; + }; + + lcd_extern{ + compatible = "amlogic, lcd_extern"; + status = "okay"; + i2c_bus = "i2c_bus_0"; + key_valid = <0>; + + extern_0{ + index = <0>; + extern_name = "mipi_default";/*default*/ + status = "okay"; + type = <2>; /* 0=i2c, 1=spi, 2=mipi */ + cmd_size = <0xff>; + init_on = < + 0xfd 1 10 + 0x05 1 0x11 + 0xfd 1 120 /* delay 120ms */ + 0x05 1 0x29 + 0xff 0>; /*ending*/ + init_off = < + 0x05 1 0x28 /* display off */ + 0xfd 1 10 /* delay 10ms */ + 0x05 1 0x10 /* sleep in */ + 0xfd 1 150 /* delay 150ms */ + 0xff 0>; /*ending*/ + }; + + extern_2{ + index = <2>; + extern_name = "mipi_default";/*P070ACB_FT*/ + status = "okay"; + type = <2>; /* 0=i2c, 1=spi, 2=mipi */ + cmd_size = <0xff>; + init_on = < + 0x23 2 0xE0 0x00 /* Page 0 */ + 0x23 2 0xE1 0x93 /* PASSWORD */ + 0x23 2 0xE2 0x65 + 0x23 2 0xE3 0xF8 + 0x23 2 0x80 0x03 + 0x23 2 0xE0 0x01 /* Page 01 */ + 0x23 2 0x0C 0x74 /* Set PWRIC */ + 0x23 2 0x17 0x00 /* Set Gamma Power */ + 0x23 2 0x18 0xEF /* VGMP=5.1V */ + 0x23 2 0x19 0x00 + 0x23 2 0x1A 0x00 + 0x23 2 0x1B 0xEF /* VGMN=-5.1V */ + 0x23 2 0x1C 0x00 + 0x23 2 0x1F 0x70 /* Set Gate Power */ + 0x23 2 0x20 0x2D + 0x23 2 0x21 0x2D + 0x23 2 0x22 0x7E + 0x23 2 0x26 0xF3 /* VDDD from IOVCC */ + 0x23 2 0x37 0x09 /* SetPanel */ + 0x23 2 0x38 0x04 /* SET RGBCYC */ + 0x23 2 0x39 0x00 + 0x23 2 0x3A 0x01 + 0x23 2 0x3C 0x90 + 0x23 2 0x3D 0xFF + 0x23 2 0x3E 0xFF + 0x23 2 0x3F 0xFF + 0x23 2 0x40 0x02 /* Set TCON */ + 0x23 2 0x41 0x80 + 0x23 2 0x42 0x99 + 0x23 2 0x43 0x14 + 0x23 2 0x44 0x19 + 0x23 2 0x45 0x5A + 0x23 2 0x4B 0x04 + 0x23 2 0x55 0x02 /* power voltage */ + 0x23 2 0x56 0x01 + 0x23 2 0x57 0x69 + 0x23 2 0x58 0x0A + 0x23 2 0x59 0x0A + 0x23 2 0x5A 0x2E /* VGH = 16.2V */ + 0x23 2 0x5B 0x19 /* VGL = -12V */ + 0x23 2 0x5C 0x15 + 0x23 2 0x5D 0x77 /* Gamma */ + 0x23 2 0x5E 0x56 + 0x23 2 0x5F 0x45 + 0x23 2 0x60 0x38 + 0x23 2 0x61 0x35 + 0x23 2 0x62 0x27 + 0x23 2 0x63 0x2D + 0x23 2 0x64 0x18 + 0x23 2 0x65 0x33 + 0x23 2 0x66 0x34 + 0x23 2 0x67 0x35 + 0x23 2 0x68 0x56 + 0x23 2 0x69 0x45 + 0x23 2 0x6A 0x4F + 0x23 2 0x6B 0x42 + 0x23 2 0x6C 0x40 + 0x23 2 0x6D 0x34 + 0x23 2 0x6E 0x25 + 0x23 2 0x6F 0x02 + 0x23 2 0x70 0x77 + 0x23 2 0x71 0x56 + 0x23 2 0x72 0x45 + 0x23 2 0x73 0x38 + 0x23 2 0x74 0x35 + 0x23 2 0x75 0x27 + 0x23 2 0x76 0x2D + 0x23 2 0x77 0x18 + 0x23 2 0x78 0x33 + 0x23 2 0x79 0x34 + 0x23 2 0x7A 0x35 + 0x23 2 0x7B 0x56 + 0x23 2 0x7C 0x45 + 0x23 2 0x7D 0x4F + 0x23 2 0x7E 0x42 + 0x23 2 0x7F 0x40 + 0x23 2 0x80 0x34 + 0x23 2 0x81 0x25 + 0x23 2 0x82 0x02 + 0x23 2 0xE0 0x02 /* Page2 */ + 0x23 2 0x00 0x53 + /* GIP_L Pin mapping RESET_EVEN */ + 0x23 2 0x01 0x55 /* VSSG_EVEN */ + 0x23 2 0x02 0x55 /* VSSA_EVEN */ + 0x23 2 0x03 0x51 /* STV2_EVEN */ + 0x23 2 0x04 0x77 /* VDD2_EVEN */ + 0x23 2 0x05 0x57 /* VDD1_EVEN */ + 0x23 2 0x06 0x1F + 0x23 2 0x07 0x4F /* CK12 */ + 0x23 2 0x08 0x4D /* CK10 */ + 0x23 2 0x09 0x1F + 0x23 2 0x0A 0x4B /* CK8 */ + 0x23 2 0x0B 0x49 /* CK6 */ + 0x23 2 0x0C 0x1F + 0x23 2 0x0D 0x47 /* CK4 */ + 0x23 2 0x0E 0x45 /* CK2 */ + 0x23 2 0x0F 0x41 /* STV1_EVEN */ + 0x23 2 0x10 0x1F + 0x23 2 0x11 0x1F + 0x23 2 0x12 0x1F + 0x23 2 0x13 0x55 /* VGG */ + 0x23 2 0x14 0x1F + 0x23 2 0x15 0x1F + 0x23 2 0x16 0x52 + /* GIP_R Pin mapping RESET_ODD */ + 0x23 2 0x17 0x55 /* VSSG_ODD */ + 0x23 2 0x18 0x55 /* VSSA_ODD */ + 0x23 2 0x19 0x50 /* STV2_ODD */ + 0x23 2 0x1A 0x77 /* VDD2_ODD */ + 0x23 2 0x1B 0x57 /* VDD1_ODD */ + 0x23 2 0x1C 0x1F + 0x23 2 0x1D 0x4E /* CK11 */ + 0x23 2 0x1E 0x4C /* CK9 */ + 0x23 2 0x1F 0x1F + 0x23 2 0x20 0x4A /* CK7 */ + 0x23 2 0x21 0x48 /* CK5 */ + 0x23 2 0x22 0x1F + 0x23 2 0x23 0x46 /* CK3 */ + 0x23 2 0x24 0x44 /* CK1 */ + 0x23 2 0x25 0x40 /* STV1_ODD */ + 0x23 2 0x26 0x1F + 0x23 2 0x27 0x1F + 0x23 2 0x28 0x1F + 0x23 2 0x29 0x1F + 0x23 2 0x2A 0x1F + 0x23 2 0x2B 0x55 /* VGG */ + 0x23 2 0x2C 0x12 /* GIP_L_GS Pin mapping */ + 0x23 2 0x2D 0x15 + 0x23 2 0x2E 0x15 + 0x23 2 0x2F 0x00 + 0x23 2 0x30 0x37 + 0x23 2 0x31 0x17 + 0x23 2 0x32 0x1F + 0x23 2 0x33 0x08 + 0x23 2 0x34 0x0A + 0x23 2 0x35 0x1F + 0x23 2 0x36 0x0C + 0x23 2 0x37 0x0E + 0x23 2 0x38 0x1F + 0x23 2 0x39 0x04 + 0x23 2 0x3A 0x06 + 0x23 2 0x3B 0x10 + 0x23 2 0x3C 0x1F + 0x23 2 0x3D 0x1F + 0x23 2 0x3E 0x1F + 0x23 2 0x3F 0x15 + 0x23 2 0x40 0x1F + 0x23 2 0x41 0x1F + 0x23 2 0x42 0x13 /* GIP_R_GS Pin mapping */ + 0x23 2 0x43 0x15 + 0x23 2 0x44 0x15 + 0x23 2 0x45 0x01 + 0x23 2 0x46 0x37 + 0x23 2 0x47 0x17 + 0x23 2 0x48 0x1F + 0x23 2 0x49 0x09 + 0x23 2 0x4A 0x0B + 0x23 2 0x4B 0x1F + 0x23 2 0x4C 0x0D + 0x23 2 0x4D 0x0F + 0x23 2 0x4E 0x1F + 0x23 2 0x4F 0x05 + 0x23 2 0x50 0x07 + 0x23 2 0x51 0x11 + 0x23 2 0x52 0x1F + 0x23 2 0x53 0x1F + 0x23 2 0x54 0x1F + 0x23 2 0x55 0x1F + 0x23 2 0x56 0x1F + 0x23 2 0x57 0x15 + 0x23 2 0x58 0x40 /* GIP Timing */ + 0x23 2 0x59 0x00 + 0x23 2 0x5A 0x00 + 0x23 2 0x5B 0x10 + 0x23 2 0x5C 0x14 + 0x23 2 0x5D 0x40 + 0x23 2 0x5E 0x01 + 0x23 2 0x5F 0x02 + 0x23 2 0x60 0x40 + 0x23 2 0x61 0x03 + 0x23 2 0x62 0x04 + 0x23 2 0x63 0x7A + 0x23 2 0x64 0x7A + 0x23 2 0x65 0x74 + 0x23 2 0x66 0x16 + 0x23 2 0x67 0xB4 + 0x23 2 0x68 0x16 + 0x23 2 0x69 0x7A + 0x23 2 0x6A 0x7A + 0x23 2 0x6B 0x0C + 0x23 2 0x6C 0x00 + 0x23 2 0x6D 0x04 + 0x23 2 0x6E 0x04 + 0x23 2 0x6F 0x88 + 0x23 2 0x70 0x00 + 0x23 2 0x71 0x00 + 0x23 2 0x72 0x06 + 0x23 2 0x73 0x7B + 0x23 2 0x74 0x00 + 0x23 2 0x75 0xBC + 0x23 2 0x76 0x00 + 0x23 2 0x77 0x04 + 0x23 2 0x78 0x2C + 0x23 2 0x79 0x00 + 0x23 2 0x7A 0x00 + 0x23 2 0x7B 0x00 + 0x23 2 0x7C 0x00 + 0x23 2 0x7D 0x03 + 0x23 2 0x7E 0x7B + 0x23 2 0xE0 0x04 /* Page4 */ + 0x23 2 0x09 0x11 /* Set RGBCYC2 */ + 0x23 2 0x0E 0x48 + 0x23 2 0x2B 0x2B /* ESD Protect */ + 0x23 2 0x2E 0x44 + 0x23 2 0xE0 0x00 /* Page0 */ + 0x23 2 0xE6 0x02 /* Watch dog */ + 0x23 2 0xE7 0x0C + 0x05 1 0x11 /* sleep out */ + 0xfd 1 120 + 0x05 1 0x29 /* display on */ + 0x05 1 0x35 + 0xfd 1 20 /* delay(ms) */ + 0xFF 0>; /*ending*/ + init_off = < + 0x05 1 0x28 /* display off */ + 0xfd 1 10 /* delay 10ms */ + 0x05 1 0x10 /* sleep in */ + 0xfd 1 150 /* delay 150ms */ + 0xff 0>; /*ending*/ + }; + + extern_3{ + index = <3>; + extern_name = "mipi_default";/*TL050FHV02CT*/ + status = "okay"; + type = <2>; /* 0=i2c, 1=spi, 2=mipi */ + cmd_size = <0xff>; + init_on = < + 0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x03 + 0x29 10 0x90 0x03 0x14 0x09 0x00 0x00 + 0x00 0x38 0x00 0x00 + 0x29 10 0x91 0x00 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 + 0x29 12 0x92 0x40 0x0B 0x0C 0x0D 0x0E + 0x00 0x38 0x00 0x10 0x03 0x04 + 0x29 9 0x94 0x00 0x08 0x0B 0x03 0xD2 + 0x03 0xD3 0x0C + 0x29 17 0x95 0x00 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 + 0x29 3 0x99 0x00 0x00 + 0x29 12 0x9A 0x00 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 0x00 0x00 + 0x29 7 0x9B 0x01 0x38 0x00 0x00 0x00 0x00 + 0x29 3 0x9C 0x00 0x00 + 0x29 9 0x9D 0x10 0x10 0x10 0x10 0x10 + 0x10 0x00 0x00 + 0x29 3 0x9E 0x00 0x00 + 0x29 11 0xA0 0x9F 0x1F 0x08 0x1F 0x0A + 0x1F 0x00 0x1F 0x14 0x1F + 0x29 11 0xA1 0x15 0x1F 0x1F 0x1F 0x1F + 0x1F 0x1F 0x1F 0x1F 0x1F + 0x29 11 0xA2 0x1F 0x1F 0x1F 0x1F 0x1F + 0x1F 0x1F 0x1F 0x1F 0x1F + 0x29 11 0xA4 0x1F 0x1F 0x1F 0x1F 0x1F + 0x1F 0x1F 0x1F 0x1F 0x1F + 0x29 11 0xA5 0x1F 0x1F 0x1F 0x1F 0x1F + 0x1F 0x1F 0x1F 0x1F 0x15 + 0x29 11 0xA6 0x1F 0x14 0x1F 0x01 0x1F + 0x0B 0x1F 0x09 0x1F 0x1F + 0x29 11 0xA7 0x1F 0x1F 0x0B 0x1F 0x09 + 0x1F 0x01 0x1F 0x15 0x1F + 0x29 11 0xA8 0x14 0x1F 0x1F 0x1F 0x1F + 0x1F 0x1F 0x1F 0x1F 0x1F + 0x29 11 0xA9 0x1F 0x1F 0x1F 0x1F 0x1F + 0x1F 0x1F 0x1F 0x1F 0x1F + 0x29 11 0xAB 0x1F 0x1F 0x1F 0x1F 0x1F + 0x1F 0x1F 0x1F 0x1F 0x1F + 0x29 11 0xAC 0x1F 0x1F 0x1F 0x1F 0x1F + 0x1F 0x1F 0x1F 0x1F 0x14 + 0x29 11 0xAD 0x1F 0x15 0x1F 0x00 0x1F + 0x08 0x1F 0x0A 0x1F 0x1F + 0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x00 + 0x29 4 0xBC 0x00 0x00 0x00 + 0x29 5 0xB8 0x01 0xAF 0x8F 0x8F + 0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x01 + 0x29 17 0xD1 0x00 0x00 0x00 0x09 0x00 + 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D + 0x00 0x79 0x00 0xA7 + 0x29 17 0xD2 0x00 0xCF 0x01 0x12 0x01 + 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED + 0x02 0x2F 0x02 0x74 + 0x29 17 0xD3 0x02 0x9F 0x02 0xD5 0x02 + 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73 + 0x03 0x8C 0x03 0xA5 + 0x29 5 0xD4 0x03 0xC5 0x03 0xFF + 0x29 17 0xD5 0x00 0x00 0x00 0x09 0x00 + 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D + 0x00 0x79 0x00 0xA7 + 0x29 17 0xD6 0x00 0xCF 0x01 0x12 0x01 + 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED + 0x02 0x2F 0x02 0x74 + 0x29 17 0xD7 0x02 0x9F 0x02 0xD5 0x02 + 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73 + 0x03 0x8C 0x03 0xA5 + 0x29 5 0xD8 0x03 0xC5 0x03 0xFF + 0x29 17 0xD9 0x00 0x00 0x00 0x09 0x00 + 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D + 0x00 0x79 0x00 0xA7 + 0x29 17 0xDD 0x00 0xCF 0x01 0x12 0x01 + 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED + 0x02 0x2F 0x02 0x74 + 0x29 17 0xDE 0x02 0x9F 0x02 0xD5 0x02 + 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73 + 0x03 0x8C 0x03 0xA5 + 0x29 5 0xDF 0x03 0xC5 0x03 0xFF + 0x29 17 0xE0 0x00 0x00 0x00 0x09 0x00 + 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D + 0x00 0x79 0x00 0xA7 + 0x29 17 0xE1 0x00 0xCF 0x01 0x12 0x01 + 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED + 0x02 0x2F 0x02 0x74 + 0x29 17 0xE2 0x02 0x9F 0x02 0xD5 0x02 + 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73 + 0x03 0x8C 0x03 0xA5 + 0x29 5 0xE3 0x03 0xC5 0x03 0xFF + 0x29 17 0xE4 0x00 0x00 0x00 0x09 0x00 + 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D + 0x00 0x79 0x00 0xA7 + 0x29 17 0xE5 0x00 0xCF 0x01 0x12 0x01 + 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED + 0x02 0x2F 0x02 0x74 + 0x29 17 0xE6 0x02 0x9F 0x02 0xD5 0x02 + 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73 + 0x03 0x8C 0x03 0xA5 + 0x29 5 0xE7 0x03 0xC5 0x03 0xFF + 0x29 17 0xE8 0x00 0x00 0x00 0x09 0x00 + 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D + 0x00 0x79 0x00 0xA7 + 0x29 17 0xE9 0x00 0xCF 0x01 0x12 0x01 + 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED + 0x02 0x2F 0x02 0x74 + 0x29 17 0xEA 0x02 0x9F 0x02 0xD5 0x02 + 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73 + 0x03 0x8C 0x03 0xA5 + 0x29 5 0xEB 0x03 0xC5 0x03 0xFF + 0x29 4 0xB0 0x05 0x05 0x05 + 0x29 4 0xB1 0x05 0x05 0x05 + 0x29 4 0xB3 0x10 0x10 0x10 + 0x29 4 0xB4 0x06 0x06 0x06 + 0x29 4 0xB6 0x44 0x44 0x44 + 0x29 4 0xB7 0x34 0x34 0x34 + 0x29 4 0xB8 0x34 0x34 0x34 + 0x29 4 0xB9 0x24 0x24 0x24 + 0x29 4 0xBA 0x24 0x24 0x24 + 0x29 4 0xBC 0x00 0x70 0x00 + 0x29 4 0xBD 0x00 0x70 0x00 + 0x23 2 0xBE 0x50 + 0x23 2 0x35 0x00 + 0x13 1 0x11 + 0xfd 1 200 + 0x13 1 0x29 + 0xfd 1 200 + 0xFF 0>; /*ending*/ + init_off = < + 0x05 1 0x28 /* display off */ + 0xfd 1 10 /* delay 10ms */ + 0x05 1 0x10 /* sleep in */ + 0xfd 1 150 /* delay 150ms */ + 0xff 0>; /*ending*/ + }; + }; + + backlight{ + compatible = "amlogic, backlight-g12a"; + status = "okay"; + key_valid = <0>; + pinctrl-names = "pwm_on","pwm_off"; + /* pinctrl-0 = <&pwm_f_pins2>; */ + /* pinctrl-1 = <&bl_pwm_off_pins>; */ + pinctrl_version = <2>; /* for uboot */ + bl_pwm_config = <&bl_pwm_conf>; + /*bl-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_HIGH + &gpio GPIOH_5 GPIO_ACTIVE_HIGH>;*/ + bl_gpio_names = "GPIOH_4","GPIOH_5"; + + /* pwm port: PWM_A, PWM_B, PWM_C, PWM_D, PWM_E, PWM_F, PWM_VS*/ + /* power index:(point gpios_index, 0xff=invalid) + * power value:(0=output low, 1=output high, 2=input) + * power delay:(unit in ms) + */ + + backlight_0{ + index = <0>; + bl_name = "backlight_pwm"; + bl_level_default_uboot_kernel = <100 100>; + bl_level_attr = <255 10 /*max, min*/ + 128 128>; /*mid, mid_mapping*/ + bl_ctrl_method = <1>; /* 1=pwm, 2=pwm_combo, 4=extern */ + bl_power_attr = <0 /*en_gpio_index*/ + 1 0 /*on_value, off_value*/ + 200 200>; /*on_delay(ms), off_delay(ms)*/ + bl_pwm_port = "PWM_F"; + bl_pwm_attr = <0 /*pwm_method*/ + 180 /*pwm_freq(pwm:Hz, pwm_vs:multiple of vs)*/ + 100 25>; /*duty_max(%), duty_min(%)*/ + bl_pwm_power = <1 1 /*pwm_gpio_index, pwm_gpio_off*/ + 10 10>; /*pwm_on_delay(ms), pwm_off_delay(ms)*/ + bl_pwm_en_sequence_reverse = <0>; /* 1 for reverse */ + }; + backlight_1{ + index = <1>; + bl_name = "bl_extern"; + bl_level_default_uboot_kernel = <100 100>; + bl_level_attr = <255 10 /*max, min*/ + 128 128>; /*mid, mid_mapping*/ + bl_ctrl_method = <4>; /*1=pwm, 2=pwm_combo, 4=extern*/ + bl_power_attr = <1 /*en_gpio_index*/ + 1 0 /*on_value, off_value*/ + 200 200>; /*on_delay(ms), off_delay(ms)*/ + bl_extern_index = <0>; + }; + }; + bl_pwm_conf:bl_pwm_conf{ + pwm_channel_0 { + pwm_port_index = <5>; + pwms = <&pwm_ef MESON_PWM_1 30040 0>; + }; + }; + + bl_extern{ + compatible = "amlogic, bl_extern"; + status = "disabled"; + i2c_bus = "i2c_bus_3"; + + extern_0{ + index = <0>; + extern_name = "i2c_lp8556"; + type = <0>; /*0=i2c, 1=spi, 2=mipi*/ + i2c_address = <0x2c>; /*7bit i2c address*/ + dim_max_min = <255 10>; + }; + + extern_1{ + index = <1>; + extern_name = "mipi_lt070me05"; + type = <2>; /*0=i2c, 1=spi, 2=mipi*/ + dim_max_min = <255 10>; + }; + }; +};/* end of panel */ +
diff --git a/arch/arm/dts/meson-sc2-mali.dtsi b/arch/arm/dts/meson-sc2-mali.dtsi new file mode 100644 index 0000000..2655b42 --- /dev/null +++ b/arch/arm/dts/meson-sc2-mali.dtsi
@@ -0,0 +1,43 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 BayLibre SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +&apb { + mali: gpu@40000 { + compatible = "amlogic,meson-gxbb-mali", "arm,mali-450"; + reg = <0x0 0x40000 0x0 0x40000>; + interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "gp", "gpmmu", "pp", "pmu", + "pp0", "ppmmu0", "pp1", "ppmmu1", + "pp2", "ppmmu2"; + /*clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;*/ + clock-names = "bus", "core"; + + /* + * Mali clocking is provided by two identical clock paths + * MALI_0 and MALI_1 muxed to a single clock by a glitch + * free mux to safely change frequency while running. + */ + /* + assigned-clocks = <&clkc CLKID_MALI_0_SEL>, + <&clkc CLKID_MALI_0>, + <&clkc CLKID_MALI>; *//* Glitch free mux */ + /*assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, + <0>, *//* Do Nothing */ + //<&clkc CLKID_MALI_0>; + /*assigned-clock-rates = <0>,*/ /* Do Nothing */ + /* <666666666>, + <0>;*/ /* Do Nothing */ + }; +};
diff --git a/arch/arm/dts/meson-sc2-pxp.dts b/arch/arm/dts/meson-sc2-pxp.dts new file mode 100644 index 0000000..657a17e --- /dev/null +++ b/arch/arm/dts/meson-sc2-pxp.dts
@@ -0,0 +1,83 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "meson-sc2-pxp.dtsi" +#include "meson-sc2_skt-panel.dtsi" + +/ { + compatible = "amlogic,sc2-pxp", "amlogic,s905c2", "amlogic,meson-sc2"; + model = "Amlogic Meson SC2 PXP Board"; +}; + +/* This UART is brought out to the DB9 connector */ +&uart_a { + status = "okay"; +}; + +&uart_b { + status = "okay"; +}; + +&saradc { + status = "okay"; +}; + +/* demo for i2c user */ +&i2c3 { + status= "disabled"; + clock-frequency = <100000>; + /* pinctrl-names = "default";*/ + /* pinctrl-0 = <&i2c3_master_pins2>;*/ +}; + +&pinctrl_periphs { + bl_pwm_off_pins:bl_pwm_off_pin { + mux { + groups = "GPIOH_5"; + function = "gpio_periphs"; + output-high; + }; + }; +}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-sc2-pxp.dtsi b/arch/arm/dts/meson-sc2-pxp.dtsi new file mode 100644 index 0000000..adcb3ae --- /dev/null +++ b/arch/arm/dts/meson-sc2-pxp.dtsi
@@ -0,0 +1,243 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>. + * Based on meson-gx-p23x-q20x.dtsi: + * - Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * - Copyright (c) 2016 BayLibre, SAS. + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +/* Common DTSI for devices which are based on the P212 reference board. */ + +#include "meson-sc2-s905x4.dtsi" + +/ { + aliases { + serial0 = &uart_b; + serial1 = &uart_a; + spi0 = &spifc; + spi1 = &spicc0; + spi2 = &spicc1; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + vddio_boot: regulator-vddio_boot { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vddio_ao18: regulator-vddio_ao18 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + /*reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;*/ + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; +}; + +ðmac { + status = "okay"; + internal_phy = <1>; + mc_val = <0x4be04>; + /*mc_val = <0x1621>;*/ +}; + +&ir { + status = "disabled"; + /* pinctrl-0 = <&remote_input_ao_pins>; */ + /* pinctrl-names = "default"; */ +}; + +&saradc { + status = "okay"; + vref-supply = <&vddio_ao18>; +}; + +/* Wireless SDIO Module */ +&sd_emmc_a { + status = "disabled"; + /*pinctrl-0 = <&sdio_pins>;*/ + /*pinctrl-names = "default";*/ + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + + non-removable; + disable-wp; + card_type = <3>; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_pins>; + pinctrl-1 = <&sdcard_pins &to_sduart_pins>; + pinctrl-names = "sd_all_pins", "sd_uart"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>; + cd-inverted; + + card_type = <5>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + sd_hs_co_phase = <2>; + sd_hs_to_phase = <0>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + cap-mmc-highspeed; +// mmc-hs200-1_8v; + max-frequency = <200000000>; + non-removable; + disable-wp; + /* mmc-ddr-1_8v; */ + card_type = <1>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + hs_co_phase = <2>; + hs_to_phase = <0>; + + hs2_co_phase = <2>; + hs2_to_phase = <0>; + + hw_reset = <&gpio GPIOB_9 GPIO_ACTIVE_HIGH>; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* nand */ +&nand { + status = "okay"; + pinctrl-names = "default", "nand_cs_only"; + pinctrl-0 = <&all_nand_pins>; + pinctrl-1 = <&nand_cs_pins>; +}; + +&dwc3 { + status = "okay"; + dr_mode = "host"; +}; + +&usb2_phy_v2 { + status = "okay"; + portnum = <2>; +}; + +&usb3_phy_v2 { + status = "okay"; + portnum = <0>; + gpio-vbus-power = "GPIOH_6"; + gpios = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>; +}; + +&pwm_ef { + status = "okay"; + /* pinctrl-0 = <&pwm_e_pins>; */ + /* pinctrl-names = "default"; */ +}; + +/* This is connected to the Bluetooth module: */ +&uart_a { + status = "okay"; + /* pinctrl-0 = <&a_uart_pins>; */ + /* pinctrl-names = "default"; */ + uart-has-rtscts; +}; + +&spifc { + status = "disabled"; + cs-gpios = <&gpio GPIOB_14 GPIO_ACTIVE_HIGH>; + spi-flash@0 { + status = "disabled"; + }; +}; + +&spicc0 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc0_pins_x>; + cs-gpios = <&gpio GPIOX_10 0>; +}; + +&spicc1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc1_pins_h>; + cs-gpios = <&gpio GPIOH_6 0>; +};
diff --git a/arch/arm/dts/meson-sc2-s905c2-ah232.dts b/arch/arm/dts/meson-sc2-s905c2-ah232.dts new file mode 100644 index 0000000..f11b5b1 --- /dev/null +++ b/arch/arm/dts/meson-sc2-s905c2-ah232.dts
@@ -0,0 +1,83 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "meson-sc2-s905c2-ah232.dtsi" +#include "meson-sc2_skt-panel.dtsi" + +/ { + compatible = "amlogic,sc2-s905c2-ah232", "amlogic,s905c2", "amlogic,meson-sc2"; + model = "Amlogic Meson SC2 S905C2 AH232 Board"; +}; + +/* This UART is brought out to the DB9 connector */ +&uart_a { + status = "okay"; +}; + +&uart_b { + status = "okay"; +}; + +&saradc { + status = "okay"; +}; + +/* demo for i2c user */ +&i2c3 { + status= "disabled"; + clock-frequency = <100000>; + /* pinctrl-names = "default";*/ + /* pinctrl-0 = <&i2c3_master_pins2>;*/ +}; + +&pinctrl_periphs { + bl_pwm_off_pins:bl_pwm_off_pin { + mux { + groups = "GPIOH_5"; + function = "gpio_periphs"; + output-high; + }; + }; +}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-sc2-s905c2-ah232.dtsi b/arch/arm/dts/meson-sc2-s905c2-ah232.dtsi new file mode 100644 index 0000000..f99d931 --- /dev/null +++ b/arch/arm/dts/meson-sc2-s905c2-ah232.dtsi
@@ -0,0 +1,244 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>. + * Based on meson-gx-p23x-q20x.dtsi: + * - Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * - Copyright (c) 2016 BayLibre, SAS. + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +/* Common DTSI for devices which are based on the P212 reference board. */ + +#include "meson-sc2-s905c2.dtsi" + +/ { + aliases { + serial0 = &uart_b; + serial1 = &uart_a; + spi0 = &spifc; + spi1 = &spicc0; + spi2 = &spicc1; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c_gpio_0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + vddio_boot: regulator-vddio_boot { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vddio_ao18: regulator-vddio_ao18 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + /*reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;*/ + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; + + tee: tee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; +}; + +ðmac { + status = "okay"; + internal_phy = <1>; + mc_val = <0x4be04>; + /*mc_val = <0x1621>;*/ +}; + +&saradc { + status = "okay"; + vref-supply = <&vddio_ao18>; +}; + +/* Wireless SDIO Module */ +&sd_emmc_a { + status = "disabled"; + /*pinctrl-0 = <&sdio_pins>;*/ + /*pinctrl-names = "default";*/ + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + + non-removable; + disable-wp; + card_type = <3>; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_pins>; + pinctrl-1 = <&sdcard_pins &to_sduart_pins>; + pinctrl-names = "sd_all_pins", "sd_uart"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>; + cd-inverted; + + card_type = <5>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + sd_hs_co_phase = <2>; + sd_hs_to_phase = <0>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + max-frequency = <200000000>; + non-removable; + disable-wp; + /* mmc-ddr-1_8v; */ + card_type = <1>; + + init_co_phase = <3>; + init_tx_phase = <0>; + + hs_co_phase = <3>; + hs_to_phase = <0>; + + hs2_co_phase = <2>; + hs2_to_phase = <0>; + + hw_reset = <&gpio GPIOB_12 GPIO_ACTIVE_HIGH>; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* nand */ +&nand { + status = "okay"; + pinctrl-names = "default", "nand_cs_only"; + pinctrl-0 = <&all_nand_pins>; + pinctrl-1 = <&nand_cs_pins>; +}; + +&dwc3 { + status = "okay"; + dr_mode = "host"; +}; + +&usb2_phy_v2 { + status = "okay"; + portnum = <2>; +}; + +&usb3_phy_v2 { + status = "okay"; + portnum = <0>; +}; + +&pwm_ef { + status = "okay"; + /* pinctrl-0 = <&pwm_e_pins>; */ + /* pinctrl-names = "default"; */ +}; + +/* This is connected to the Bluetooth module: */ +&uart_a { + status = "okay"; + /* pinctrl-0 = <&a_uart_pins>; */ + /* pinctrl-names = "default"; */ + uart-has-rtscts; +}; + +&spifc { + status = "okay"; + cs-gpios = <&gpio GPIOB_14 GPIO_ACTIVE_HIGH>; + spi-flash@0 { + status = "okay"; + }; + spi-nand@1 { + status = "okay"; + }; +}; + +&spicc0 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc0_pins_x>; + cs-gpios = <&gpio GPIOX_10 0>; +}; + +&spicc1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc1_pins_h>; + cs-gpios = <&gpio GPIOH_6 0>; +};
diff --git a/arch/arm/dts/meson-sc2-s905c2.dtsi b/arch/arm/dts/meson-sc2-s905c2.dtsi new file mode 100644 index 0000000..fc192b6 --- /dev/null +++ b/arch/arm/dts/meson-sc2-s905c2.dtsi
@@ -0,0 +1,60 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "meson-sc2.dtsi" +#include "meson-sc2-mali.dtsi" + +/ { + compatible = "amlogic,s905c2", "amlogic,meson-sc2"; +}; + +ðmac { + phy-mode = "rmii"; + phy-handle = <&internal_phy>; +}; + +&ir { + status= "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&remote_pins>; +};
diff --git a/arch/arm/dts/meson-sc2-s905x4-ah212-ddr3.dts b/arch/arm/dts/meson-sc2-s905x4-ah212-ddr3.dts new file mode 100644 index 0000000..f3dae71 --- /dev/null +++ b/arch/arm/dts/meson-sc2-s905x4-ah212-ddr3.dts
@@ -0,0 +1,83 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "meson-sc2-s905x4-ah212-ddr3.dtsi" +#include "meson-sc2_skt-panel.dtsi" + +/ { + compatible = "amlogic,sc2-s905x4-ah212-dd3", "amlogic,s905x4", "amlogic,meson-sc2"; + model = "Amlogic Meson SC2 S905X4 AH212 DDR3 Board"; +}; + +/* This UART is brought out to the DB9 connector */ +&uart_a { + status = "okay"; +}; + +&uart_b { + status = "okay"; +}; + +&saradc { + status = "okay"; +}; + +/* demo for i2c user */ +&i2c3 { + status= "disabled"; + clock-frequency = <100000>; + /* pinctrl-names = "default";*/ + /* pinctrl-0 = <&i2c3_master_pins2>;*/ +}; + +&pinctrl_periphs { + bl_pwm_off_pins:bl_pwm_off_pin { + mux { + groups = "GPIOH_5"; + function = "gpio_periphs"; + output-high; + }; + }; +}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-sc2-s905x4-ah212-ddr3.dtsi b/arch/arm/dts/meson-sc2-s905x4-ah212-ddr3.dtsi new file mode 100644 index 0000000..47d358e --- /dev/null +++ b/arch/arm/dts/meson-sc2-s905x4-ah212-ddr3.dtsi
@@ -0,0 +1,239 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>. + * Based on meson-gx-p23x-q20x.dtsi: + * - Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * - Copyright (c) 2016 BayLibre, SAS. + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +/* Common DTSI for devices which are based on the P212 reference board. */ + +#include "meson-sc2-s905x4.dtsi" + +/ { + aliases { + serial0 = &uart_b; + serial1 = &uart_a; + spi0 = &spifc; + spi1 = &spicc0; + spi2 = &spicc1; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c_gpio_0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + vddio_boot: regulator-vddio_boot { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vddio_ao18: regulator-vddio_ao18 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + /*reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;*/ + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; +}; + +ðmac { + status = "okay"; + internal_phy = <1>; + mc_val = <0x4be04>; + /*mc_val = <0x1621>;*/ +}; + +&saradc { + status = "okay"; + vref-supply = <&vddio_ao18>; +}; + +/* Wireless SDIO Module */ +&sd_emmc_a { + status = "disabled"; + /*pinctrl-0 = <&sdio_pins>;*/ + /*pinctrl-names = "default";*/ + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + + non-removable; + disable-wp; + card_type = <3>; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_pins>; + pinctrl-1 = <&sdcard_pins &to_sduart_pins>; + pinctrl-names = "sd_all_pins", "sd_uart"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>; + cd-inverted; + + card_type = <5>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + sd_hs_co_phase = <2>; + sd_hs_to_phase = <0>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + max-frequency = <200000000>; + non-removable; + disable-wp; + /* mmc-ddr-1_8v; */ + card_type = <1>; + + init_co_phase = <3>; + init_tx_phase = <0>; + + hs_co_phase = <3>; + hs_to_phase = <0>; + + hs2_co_phase = <2>; + hs2_to_phase = <0>; + + hw_reset = <&gpio GPIOB_12 GPIO_ACTIVE_HIGH>; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* nand */ +&nand { + status = "okay"; + pinctrl-names = "default", "nand_cs_only"; + pinctrl-0 = <&all_nand_pins>; + pinctrl-1 = <&nand_cs_pins>; +}; + +&dwc3 { + status = "okay"; + dr_mode = "host"; +}; + +&usb2_phy_v2 { + status = "okay"; + portnum = <2>; +}; + +&usb3_phy_v2 { + status = "okay"; + portnum = <0>; +}; + +&pwm_ef { + status = "okay"; + /* pinctrl-0 = <&pwm_e_pins>; */ + /* pinctrl-names = "default"; */ +}; + +/* This is connected to the Bluetooth module: */ +&uart_a { + status = "okay"; + /* pinctrl-0 = <&a_uart_pins>; */ + /* pinctrl-names = "default"; */ + uart-has-rtscts; +}; + +&spifc { + status = "okay"; + cs-gpios = <&gpio GPIOB_14 GPIO_ACTIVE_HIGH>; + spi-flash@0 { + status = "okay"; + }; + spi-nand@1 { + status = "okay"; + }; +}; + +&spicc0 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc0_pins_x>; + cs-gpios = <&gpio GPIOX_10 0>; +}; + +&spicc1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc1_pins_h>; + cs-gpios = <&gpio GPIOH_6 0>; +};
diff --git a/arch/arm/dts/meson-sc2-s905x4-ah212.dts b/arch/arm/dts/meson-sc2-s905x4-ah212.dts new file mode 100644 index 0000000..d0237ae --- /dev/null +++ b/arch/arm/dts/meson-sc2-s905x4-ah212.dts
@@ -0,0 +1,83 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "meson-sc2-s905x4-ah212.dtsi" +#include "meson-sc2_skt-panel.dtsi" + +/ { + compatible = "amlogic,sc2-s905x4-ah212", "amlogic,s905x4", "amlogic,meson-sc2"; + model = "Amlogic Meson SC2 S905X4 AH212 Board"; +}; + +/* This UART is brought out to the DB9 connector */ +&uart_a { + status = "okay"; +}; + +&uart_b { + status = "okay"; +}; + +&saradc { + status = "okay"; +}; + +/* demo for i2c user */ +&i2c3 { + status= "disabled"; + clock-frequency = <100000>; + /* pinctrl-names = "default";*/ + /* pinctrl-0 = <&i2c3_master_pins2>;*/ +}; + +&pinctrl_periphs { + bl_pwm_off_pins:bl_pwm_off_pin { + mux { + groups = "GPIOH_5"; + function = "gpio_periphs"; + output-high; + }; + }; +}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-sc2-s905x4-ah212.dtsi b/arch/arm/dts/meson-sc2-s905x4-ah212.dtsi new file mode 100644 index 0000000..ba3f3b5 --- /dev/null +++ b/arch/arm/dts/meson-sc2-s905x4-ah212.dtsi
@@ -0,0 +1,244 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>. + * Based on meson-gx-p23x-q20x.dtsi: + * - Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * - Copyright (c) 2016 BayLibre, SAS. + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +/* Common DTSI for devices which are based on the P212 reference board. */ + +#include "meson-sc2-s905x4.dtsi" + +/ { + aliases { + serial0 = &uart_b; + serial1 = &uart_a; + spi0 = &spifc; + spi1 = &spicc0; + spi2 = &spicc1; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c_gpio_0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + vddio_boot: regulator-vddio_boot { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vddio_ao18: regulator-vddio_ao18 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + /*reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;*/ + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; + + tee: tee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; +}; + +ðmac { + status = "okay"; + internal_phy = <1>; + mc_val = <0x4be04>; + /*mc_val = <0x1621>;*/ +}; + +&saradc { + status = "okay"; + vref-supply = <&vddio_ao18>; +}; + +/* Wireless SDIO Module */ +&sd_emmc_a { + status = "disabled"; + /*pinctrl-0 = <&sdio_pins>;*/ + /*pinctrl-names = "default";*/ + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + + non-removable; + disable-wp; + card_type = <3>; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_pins>; + pinctrl-1 = <&sdcard_pins &to_sduart_pins>; + pinctrl-names = "sd_all_pins", "sd_uart"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>; + cd-inverted; + + card_type = <5>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + sd_hs_co_phase = <2>; + sd_hs_to_phase = <0>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + max-frequency = <200000000>; + non-removable; + disable-wp; + /* mmc-ddr-1_8v; */ + card_type = <1>; + + init_co_phase = <3>; + init_tx_phase = <0>; + + hs_co_phase = <3>; + hs_to_phase = <0>; + + hs2_co_phase = <2>; + hs2_to_phase = <0>; + + hw_reset = <&gpio GPIOB_12 GPIO_ACTIVE_HIGH>; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* nand */ +&nand { + status = "okay"; + pinctrl-names = "default", "nand_cs_only"; + pinctrl-0 = <&all_nand_pins>; + pinctrl-1 = <&nand_cs_pins>; +}; + +&dwc3 { + status = "okay"; + dr_mode = "host"; +}; + +&usb2_phy_v2 { + status = "okay"; + portnum = <2>; +}; + +&usb3_phy_v2 { + status = "okay"; + portnum = <0>; +}; + +&pwm_ef { + status = "okay"; + /* pinctrl-0 = <&pwm_e_pins>; */ + /* pinctrl-names = "default"; */ +}; + +/* This is connected to the Bluetooth module: */ +&uart_a { + status = "okay"; + /* pinctrl-0 = <&a_uart_pins>; */ + /* pinctrl-names = "default"; */ + uart-has-rtscts; +}; + +&spifc { + status = "okay"; + cs-gpios = <&gpio GPIOB_14 GPIO_ACTIVE_HIGH>; + spi-flash@0 { + status = "okay"; + }; + spi-nand@1 { + status = "okay"; + }; +}; + +&spicc0 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc0_pins_x>; + cs-gpios = <&gpio GPIOX_10 0>; +}; + +&spicc1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc1_pins_h>; + cs-gpios = <&gpio GPIOH_6 0>; +};
diff --git a/arch/arm/dts/meson-sc2-s905x4-ah219.dts b/arch/arm/dts/meson-sc2-s905x4-ah219.dts new file mode 100644 index 0000000..87f3efd --- /dev/null +++ b/arch/arm/dts/meson-sc2-s905x4-ah219.dts
@@ -0,0 +1,83 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "meson-sc2-s905x4-ah219.dtsi" +#include "meson-sc2_skt-panel.dtsi" + +/ { + compatible = "amlogic,sc2-s905x4-ah219", "amlogic,s905x4", "amlogic,meson-sc2"; + model = "Amlogic Meson SC2 S905X4 AH219 Board"; +}; + +/* This UART is brought out to the DB9 connector */ +&uart_a { + status = "okay"; +}; + +&uart_b { + status = "okay"; +}; + +&saradc { + status = "okay"; +}; + +/* demo for i2c user */ +&i2c3 { + status= "disabled"; + clock-frequency = <100000>; + /* pinctrl-names = "default";*/ + /* pinctrl-0 = <&i2c3_master_pins2>;*/ +}; + +&pinctrl_periphs { + bl_pwm_off_pins:bl_pwm_off_pin { + mux { + groups = "GPIOH_5"; + function = "gpio_periphs"; + output-high; + }; + }; +}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-sc2-s905x4-ah219.dtsi b/arch/arm/dts/meson-sc2-s905x4-ah219.dtsi new file mode 100644 index 0000000..d9197aa --- /dev/null +++ b/arch/arm/dts/meson-sc2-s905x4-ah219.dtsi
@@ -0,0 +1,250 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>. + * Based on meson-gx-p23x-q20x.dtsi: + * - Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * - Copyright (c) 2016 BayLibre, SAS. + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +/* Common DTSI for devices which are based on the P212 reference board. */ + +#include "meson-sc2-s905x4.dtsi" + +/ { + aliases { + serial0 = &uart_b; + serial1 = &uart_a; + spi0 = &spifc; + spi1 = &spicc0; + spi2 = &spicc1; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c_gpio_0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + vddio_boot: regulator-vddio_boot { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vddio_ao18: regulator-vddio_ao18 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + /*reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;*/ + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; + + tee: tee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; +}; + +ðmac { + status = "okay"; + internal_phy = <1>; + mc_val = <0x4be04>; +/*exphy setting*/ +// pinctrl-names = "external_eth_rgmii_pins"; +// pinctrl-0 = <&external_eth_rgmii_pins>; +// internal_phy = <0>; +// mc_val = <0x1621>; +}; + +&saradc { + status = "okay"; + vref-supply = <&vddio_ao18>; +}; + +/* Wireless SDIO Module */ +&sd_emmc_a { + status = "disabled"; + /*pinctrl-0 = <&sdio_pins>;*/ + /*pinctrl-names = "default";*/ + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + + non-removable; + disable-wp; + card_type = <3>; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_pins>; + pinctrl-1 = <&sdcard_pins &to_sduart_pins>; + pinctrl-names = "sd_all_pins", "sd_uart"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>; + cd-inverted; + + card_type = <5>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + sd_hs_co_phase = <2>; + sd_hs_to_phase = <0>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + max-frequency = <200000000>; + non-removable; + disable-wp; + /* mmc-ddr-1_8v; */ + card_type = <1>; + + init_co_phase = <3>; + init_tx_phase = <0>; + + hs_co_phase = <3>; + hs_to_phase = <0>; + + hs2_co_phase = <2>; + hs2_to_phase = <0>; + + hw_reset = <&gpio GPIOB_12 GPIO_ACTIVE_HIGH>; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* nand */ +&nand { + status = "okay"; + pinctrl-names = "default", "nand_cs_only"; + pinctrl-0 = <&all_nand_pins>; + pinctrl-1 = <&nand_cs_pins>; +}; + +&dwc3 { + status = "okay"; + dr_mode = "host"; +}; + +&usb2_phy_v2 { + status = "okay"; + portnum = <2>; +}; + +&usb3_phy_v2 { + status = "okay"; + portnum = <0>; + gpio-vbus-power = "GPIOH_6"; + gpios = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>; +}; + +&pwm_ef { + status = "okay"; + /* pinctrl-0 = <&pwm_e_pins>; */ + /* pinctrl-names = "default"; */ +}; + +/* This is connected to the Bluetooth module: */ +&uart_a { + status = "okay"; + /* pinctrl-0 = <&a_uart_pins>; */ + /* pinctrl-names = "default"; */ + uart-has-rtscts; +}; + +&spifc { + status = "okay"; + cs-gpios = <&gpio GPIOB_14 GPIO_ACTIVE_HIGH>; + spi-flash@0 { + status = "okay"; + }; + spi-nand@1 { + status = "okay"; + }; +}; + +&spicc0 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc0_pins_x>; + cs-gpios = <&gpio GPIOX_10 0>; +}; + +&spicc1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc1_pins_h>; + cs-gpios = <&gpio GPIOH_6 0>; +};
diff --git a/arch/arm/dts/meson-sc2-s905x4.dtsi b/arch/arm/dts/meson-sc2-s905x4.dtsi new file mode 100644 index 0000000..ee227fe --- /dev/null +++ b/arch/arm/dts/meson-sc2-s905x4.dtsi
@@ -0,0 +1,60 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "meson-sc2.dtsi" +#include "meson-sc2-mali.dtsi" + +/ { + compatible = "amlogic,s905x4", "amlogic,meson-sc2"; +}; + +ðmac { + phy-mode = "rmii"; + phy-handle = <&internal_phy>; +}; + +&ir { + status= "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&remote_pins>; +};
diff --git a/arch/arm/dts/meson-sc2-series.dtsi b/arch/arm/dts/meson-sc2-series.dtsi new file mode 100644 index 0000000..d498ad8 --- /dev/null +++ b/arch/arm/dts/meson-sc2-series.dtsi
@@ -0,0 +1,513 @@ +/* + * Copyright (c) 2016 Andreas Färber + * + * Copyright (c) 2016 BayLibre, SAS. + * Author: Neil Armstrong <narmstrong@baylibre.com> + * + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/pwm/pwm.h> +#include <dt-bindings/pwm/meson.h> +#include <dt-bindings/clock/sc2-clkc.h> +#include <dt-bindings/input/meson_rc.h> + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* 16 MiB reserved for Hardware ROM Firmware */ + hwrom_reserved: hwrom@0 { + reg = <0x0 0x0 0x0 0x1000000>; + no-map; + }; + + /* 2 MiB reserved for ARM Trusted Firmware (BL31) */ + secmon_reserved: secmon@10000000 { + reg = <0x0 0x10000000 0x0 0x200000>; + no-map; + }; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0xbc00000>; + alignment = <0x0 0x400000>; + linux,cma-default; + }; + }; + + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&l2>; + clocks = <&scpi_dvfs 0>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + next-level-cache = <&l2>; + clocks = <&scpi_dvfs 0>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x2>; + enable-method = "psci"; + next-level-cache = <&l2>; + clocks = <&scpi_dvfs 0>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x3>; + enable-method = "psci"; + next-level-cache = <&l2>; + clocks = <&scpi_dvfs 0>; + }; + + l2: l2-cache0 { + compatible = "cache"; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; + }; + + xtal: xtal-clk { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xtal"; + #clock-cells = <0>; + }; + + firmware { + sm: secure-monitor { + compatible = "amlogic,meson-gx-sm", "amlogic,meson-gxbb-sm"; + }; + }; + + efuse: efuse { + compatible = "amlogic,meson-sc2-efuse", "amlogic,meson-sc2-efuse"; + #address-cells = <1>; + #size-cells = <1>; + + }; + + scpi { + compatible = "amlogic,meson-gxbb-scpi", "arm,scpi-pre-1.0"; + mboxes = <&mailbox 1 &mailbox 2>; + shmem = <&cpu_scp_lpri &cpu_scp_hpri>; + + scpi_clocks: clocks { + compatible = "arm,scpi-clocks"; + + scpi_dvfs: scpi_clocks@0 { + compatible = "arm,scpi-dvfs-clocks"; + #clock-cells = <1>; + clock-indices = <0>; + clock-output-names = "vcpu"; + }; + }; + + scpi_sensors: sensors { + compatible = "amlogic,meson-gxbb-scpi-sensors", "arm,scpi-sensors"; + #thermal-sensor-cells = <1>; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic: interrupt-controller@2c001000 { + compatible = "arm,gic-400"; + reg = <0x0 0xffc01000 0 0x1000>, + <0x0 0xffc02000 0 0x2000>, + <0x0 0xffc04000 0 0x2000>, + <0x0 0xffc06000 0 0x2000>; + interrupt-controller; + interrupts = <GIC_PPI 9 + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; + #interrupt-cells = <3>; + #address-cells = <0>; + }; + + sram: sram@f7000000 { + compatible = "amlogic,meson-sc2-sram", "amlogic,meson-sc2-sram", "mmio-sram"; + reg = <0x0 0xf7000000 0x0 0x48000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0xf7000000 0x48000>; + + cpu_scp_lpri: scp-shmem@0 { + compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem"; + reg = <0x47000 0x400>; + }; + + cpu_scp_hpri: scp-shmem@200 { + compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem"; + reg = <0x47400 0x400>; + }; + }; + + cbus: cbus@fe070000 { + compatible = "simple-bus"; + reg = <0x0 0xfe070000 0x0 0xF000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xfe070000 0x0 0xF000>; + + uart_a: serial@8000 { + compatible = "amlogic,meson-uart"; + reg = <0x0 0x8000 0x0 0x18>; + clocks = <&xtal>; + status = "disabled"; + }; + + uart_b: serial@a000 { + compatible = "amlogic,meson-uart"; + reg = <0x0 0xa000 0x0 0x18>; + clocks = <&xtal>; + status = "disabled"; + }; + + reset: reset-controller@1000 { + compatible = "amlogic,meson-gx-reset", "amlogic,meson-gxbb-reset"; + reg = <0x0 0x01000 0x0 0x1000>; + #reset-cells = <1>; + }; + + uart_c: serial@22000 { + compatible = "amlogic,meson-uart"; + reg = <0x0 0x22000 0x0 0x18>; + interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>; + clocks = <&xtal>; + status = "disabled"; + }; + + jtag { + compatible = "amlogic, jtag"; + status = "okay"; + select = "disable"; /* disable/jtag-a/jtag-b */ + pinctrl-names="jtag_a_pins", "jtag_b_pins"; + pinctrl-0=<&jtag_a_pins>; + pinctrl-1=<&jtag_b_pins>; + }; + }; + + periphs: periphs@ff634000 { + compatible = "simple-bus"; + reg = <0x0 0xff634000 0x0 0x2000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>; + + hwrng: rng { + compatible = "amlogic,meson-rng"; + reg = <0x0 0x0 0x0 0x4>; + }; + }; + + hiubus: hiubus@ff63c000 { + compatible = "simple-bus"; + reg = <0x0 0xff63c000 0x0 0x2000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x2000>; + + mailbox: mailbox@404 { + compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu"; + reg = <0 0x404 0 0x4c>; + interrupts = <0 208 IRQ_TYPE_EDGE_RISING>, + <0 209 IRQ_TYPE_EDGE_RISING>, + <0 210 IRQ_TYPE_EDGE_RISING>; + #mbox-cells = <1>; + }; + }; + + clkc: clock-controller@0 { + compatible = "amlogic,sc2-clkc"; + #clock-cells = <1>; + reg = <0x0 0xfe000000 0x0 0x82e8>; + clocks = <&xtal>; + clock-names = "xtal"; + }; + + i2c0: i2c@fe001400 { + compatible = "amlogic,meson-i2c"; + reg = <0x0 0xfe066000 0x0 0x24>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@fe005c00 { + compatible = "amlogic,meson-i2c"; + reg = <0x0 0xfe068000 0x0 0x24>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@fe006800 { + compatible = "amlogic,meson-i2c"; + reg = <0x0 0xfe06a000 0x0 0x24>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@fe006c00 { + compatible = "amlogic,meson-i2c"; + reg = <0x0 0xfe06c000 0x0 0x24>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@fe06e000 { + compatible = "amlogic,meson-i2c"; + reg = <0x0 0xfe06e000 0x0 0x24>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spicc0: spi@fe050000 { + compatible = "amlogic,meson-g12a-spicc"; + reg = <0x0 0xfe050000 0x0 0x44>; + interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spicc1: spi@fe052000 { + compatible = "amlogic,meson-g12a-spicc"; + reg = <0x0 0xfe052000 0x0 0x44>; + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spifc: spi@fe056000 { + compatible = "amlogic,spifc"; + status = "disabled"; + reg = <0x0 0xfe056000 0x0 0x80>; + /* clocks = <&clkc CLKID_CLK81>; */ + /* clock-names = "core"; */ + pinctrl-names = "default"; + pinctrl-0 = <&spifc_pins>; + #address-cells = <1>; + #size-cells = <0>; + spi-flash@0 { + compatible = "spi-flash"; + reg = <0>; + spi-max-frequency = <20000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + status = "disabled"; + }; + spi-nand@1 { + compatible = "spi-nand"; + reg = <1>; + spi-max-frequency = <20000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + status = "disabled"; + }; + }; + + ethmac: ethernet@ff3f0000 { + compatible = "amlogic,g12a-eth-dwmac"; + phy_cntl1 = <0x41054147>; + pll_val = <0x9c0040a 0x927e0000 0xac5f49e5>; + analog_val = <0x20200000 0x0000c000 0x00000023>; + status = "disabled"; + }; + + saradc: adc@fe026000 { + compatible = "amlogic,meson-saradc"; + reg = <0x0 0xfe026000 0x0 0x48>; + status = "disabled"; + }; + + nand: nfc@fe08c800 { + compatible = "amlogic,meson-nfc"; + reg = <0x0 0xfe08c800 0x0 0x200>; + interrupts = <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + clk_reg = <0 0xfe08c000>; + }; + + apb: apb@fe000000 { + compatible = "simple-bus"; + reg = <0x0 0xfe000000 0x0 0x1000000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x1000000>; + + watchdog@2100 { + compatible = "amlogic,meson-sc2-wdt"; + reg = <0x0 0x2100 0x0 0x10>; + clocks = <&xtal>; + clock-names = "wdt-clk"; + }; + + sd_emmc_a: sdio { + compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; + reg = <0x0 0x88000 0x0 0x800>; + interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + pinname = "sdio"; + }; + + sd_emmc_b: sd { + compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; + reg = <0x0 0x8a000 0x0 0x800>; + interrupts = <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + pinname = "sd"; + }; + + sd_emmc_c: emmc { + compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; + reg = <0x0 0x8c000 0x0 0x800>; + interrupts = <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + pinname = "emmc"; + }; + }; + + dwc3: dwc3@fde00000 { + compatible = "snps,dwc3","synopsys,xhci-dwc3"; + status = "disable"; + reg = <0x0 0xfde00000 0x0 0x100000>; + phys = <&usb2_phy_v2>, <&usb3_phy_v2>; + phy-names = "usb2-phy", "usb3-phy"; + }; + + usb2_phy_v2: usb2phy@fe03a000 { + compatible = "amlogic, amlogic-new-usb2-v2"; + status = "disable"; + #address-cells = <2>; + #size-cells = <2>; + phy-version = <2>; + reg = <0x0 0xfe03a000 0x0 0x80 + 0x0 0xFE002000 0x0 0x100 + 0x0 0xfe03c000 0x0 0x2000 + 0x0 0xfe03e000 0x0 0x2000>; + dwc2_a_reg = <0xfdd00000>; + #phy-cells = <0>; + }; + + usb3_phy_v2: usb3phy@fe03a080 { + compatible = "amlogic, amlogic-new-usb3-v2"; + status = "disable"; + #address-cells = <2>; + #size-cells = <2>; + phy-version = <3>; + reg = <0x0 0xfe03a080 0x0 0x20>; + phy-reg = <0xfe03c000>; + phy-reg-size = <0x2000>; + usb2-phy-reg = <0xfe03a000>; + usb2-phy-reg-size = <0x80>; + #phy-cells = <0>; + }; + + ir: meson-ir { + compatible = "amlogic, meson-ir"; + reg = <0x0 0xfe084040 0x44 0x0>, /*Multi-format IR controller*/ + <0x0 0xfe084000 0x20 0x0>; /*Legacy IR controller*/ + protocol = <REMOTE_TYPE_NEC>; + status = "disabled"; + }; + }; +};
diff --git a/arch/arm/dts/meson-sc2.dtsi b/arch/arm/dts/meson-sc2.dtsi new file mode 100644 index 0000000..e7aaaa1 --- /dev/null +++ b/arch/arm/dts/meson-sc2.dtsi
@@ -0,0 +1,826 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "meson-sc2-series.dtsi" +#include <dt-bindings/gpio/meson-sc2-gpio.h> +#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h> +#include <dt-bindings/pwm/pwm.h> +#include <dt-bindings/pwm/meson.h> + +/ { + compatible = "amlogic,meson-sc2"; + + vpu { + compatible = "amlogic, vpu-g12a"; + status = "okay"; + /*clocks = <&clkc CLKID_VAPB_MUX>, + * <&clkc CLKID_VPU_INTR>, + * <&clkc CLKID_VPU_P0_COMP>, + * <&clkc CLKID_VPU_P1_COMP>, + * <&clkc CLKID_VPU_MUX>; + *clock-names = "vapb_clk", + * "vpu_intr_gate", + * "vpu_clk0", + * "vpu_clk1", + * "vpu_clk"; + */ + clk_level = <7>; + /* 0: 100.0M 1: 166.7M 2: 200.0M 3: 250.0M */ + /* 4: 333.3M 5: 400.0M 6: 500.0M 7: 666.7M */ + }; + + fb { + status = "okay"; + logo_addr = "0x7f800000"; + }; + + pinctrl_periphs: pinctrl@fe004000 { + compatible = "amlogic,meson-sc2-periphs-pinctrl"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio: bank@fe004000 { + reg = <0x0 0xfe004000 0x0 0x004c>, + <0x0 0xfe0040c0 0x0 0x0220>; + reg-names = "mux", + "gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_periphs 0 0 87>; + }; + }; + + i2c_gpio_0: i2c-gpio-0 { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "i2c-gpio"; + status = "okay"; + gpios = <&gpio GPIOH_0 GPIO_ACTIVE_HIGH>, /* SDA */ + <&gpio GPIOH_1 GPIO_ACTIVE_HIGH>; /* CLK */ + + i2c-gpio,delay-us = <5>; + is_odpin = <1>; + }; + + pwm_ab: pwm@fe058000 { + compatible = "amlogic,meson-v2-pwm"; + reg = <0x0 0xfe058000 0x0 0x20>, + <0x0 0xfe000180 0x0 0x04>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm_cd: pwm@fe05a000 { + compatible = "amlogic,meson-v2-pwm"; + reg = <0x0 0xfe05a000 0x0 0x20>, + <0x0 0xfe000184 0x0 0x04>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm_ef: pwm@fe05c000 { + compatible = "amlogic,meson-v2-pwm"; + reg = <0x0 0xfe05c000 0x0 0x20>, + <0x0 0xfe000188 0x0 0x04>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm_gh: pwm@fe05e000 { + compatible = "amlogic,meson-v2-pwm"; + reg = <0x0 0xfe05e000 0x0 0x20>, + <0x0 0xfe00018c 0x0 0x04>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm_ij: pwm@fe060000 { + compatible = "amlogic,meson-v2-pwm"; + reg = <0x0 0xfe060000 0x0 0x20>, + <0x0 0xfe000190 0x0 0x04>; + #pwm-cells = <3>; + status = "disabled"; + }; +}; + +ðmac { + compatible = "amlogic,g12a-eth-dwmac"; + reg = <0x0 0xfdc00000 0x0 0x10000 + 0x0 0xFE024000 0x0 0x8 + 0x0 0xFE028000 0x0 0xa0>; + reg-names = "eth_base", "eth_top", "eth_cfg"; + phy_cntl1 = <0x41054147>; + internal_phy = <1>; + mc_val = <0x4be04>; + cali_val = <0x80000>; + reset-gpios = <&gpio GPIOZ_15 GPIO_ACTIVE_HIGH>; + analog_ver = <1>; /*1:c1; 2:c2*/ + pll_val = <0x9c0040a 0x927e0000 0xac5f49e5>; + analog_val = <0x20200000 0x0000c000 0x00000023>; + chip_num = <3>; + //tx_amp_src = <0xfe005b30>; +// clocks = <&clkc CLKID_ETH_CORE>, +// <&clkc CLKID_FCLK_DIV2>, +// <&clkc CLKID_MPLL2>; +// clock-names = "stmmaceth", "clkin0", "clkin1"; + + mdio0: mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + }; +}; + +&periphs { + + eth-phy-mux { + compatible = "mdio-mux-mmioreg", "mdio-mux"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x15c 0x0 0x4>; + mux-mask = <0xffffffff>; + mdio-parent-bus = <&mdio0>; + + internal_mdio: mdio@e40908ff { + reg = <0xe40908ff>; + #address-cells = <1>; + #size-cells = <0>; + + internal_phy: ethernet-phy@8 { + compatible = "ethernet-phy-id0181.4400", "ethernet-phy-ieee802.3-c22"; + reg = <8>; + max-speed = <100>; + }; + }; + + external_mdio: mdio@2009087f { + reg = <0x2009087f>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&saradc { + compatible = "amlogic,meson-g12a-saradc", "amlogic,meson-saradc"; + clocks = <&xtal>, + <&clkc CLKID_SARADC_MUX>, + <&clkc CLKID_SARADC_DIV>, + <&clkc CLKID_SAR_ADC_GATE>; + clock-names = "xtal", "adc_mux", "adc_div", "adc_gate"; +}; + +&sd_emmc_a { + clocks = <&clkc CLKID_SD_EMMC_A_MUX>, + <&clkc CLKID_SD_EMMC_A_DIV>, + <&clkc CLKID_SD_EMMC_A_GATE>, + <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_XTAL>; + clock-names = "mux", "div", "gate", "clkin", "xtal"; +}; + +&sd_emmc_b { + clocks = <&clkc CLKID_SD_EMMC_B_MUX>, + <&clkc CLKID_SD_EMMC_B_DIV>, + <&clkc CLKID_SD_EMMC_B_GATE>, + <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_XTAL>; + clock-names = "mux", "div", "gate", "clkin", "xtal"; +}; + +&sd_emmc_c { + clocks = <&clkc CLKID_SD_EMMC_C_MUX>, + <&clkc CLKID_SD_EMMC_C_DIV>, + <&clkc CLKID_SD_EMMC_C_GATE>, + <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_XTAL>; + clock-names = "mux", "div", "gate", "clkin", "xtal"; +}; + +&nand { + clocks = <&clkc CLKID_SD_EMMC_C_MUX>, + <&clkc CLKID_SD_EMMC_C_DIV>, + <&clkc CLKID_SD_EMMC_C_GATE>, + <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_XTAL>; + clock-names = "mux", "div", "gate", "fdiv2", "xtal"; +}; + +&spicc0 { + clocks = <&clkc CLKID_SPICC_A_DIV>, <&clkc CLKID_SPICC_A_GATE>; + clock-names = "async", "async-gate"; + assigned-clocks = <&clkc CLKID_SPICC_A_MUX>, <&clkc CLKID_SPICC_A_DIV>; + assigned-clock-parents = <&clkc CLKID_FCLK_DIV2>; + assigned-clock-rates = <0>, <200000000>; + /* =PM_SPICC, no set for power on already */ + /* pm-id = <22>; */ +}; + +&spicc1 { + clocks = <&clkc CLKID_SPICC_B_DIV>, <&clkc CLKID_SPICC_B_GATE>; + clock-names = "async", "async-gate"; + assigned-clocks = <&clkc CLKID_SPICC_B_MUX>, <&clkc CLKID_SPICC_B_DIV>; + assigned-clock-parents = <&clkc CLKID_FCLK_DIV2>; + assigned-clock-rates = <0>, <200000000>; + /* =PM_SPICC_B, no set for power on already */ + /* pm-id = <39>; */ +}; + +&pinctrl_periphs { + i2c0_master_pins1:i2c0_pins1 { + mux { + groups = "i2c_a_sda_c", + "i2c_a_scl_c"; + function = "i2c_a"; + drive-strength = <3>; + bias-disable; + }; + }; + + i2c0_master_pins2:i2c0_pins2 { + mux { + groups = "i2c_a_sda_h", + "i2c_a_scl_h"; + function = "i2c_a"; + drive-strength = <3>; + bias-disable; + }; + }; + + i2c0_master_pins3:i2c0_pins3 { + mux { + groups = "i2c_a_sda_z0", + "i2c_a_scl_z1"; + function = "i2c_a"; + drive-strength = <3>; + bias-disable; + }; + }; + + i2c0_master_pins4:i2c0_pins4 { + mux { + groups = "i2c_a_sda_z7", + "i2c_a_scl_z8"; + function = "i2c_a"; + drive-strength = <3>; + bias-disable; + + }; + }; + + i2c1_master_pins1:i2c1_pins1 { + mux { + groups = "i2c_b_sda_z", + "i2c_b_scl_z"; + function = "i2c_b"; + drive-strength = <3>; + bias-disable; + }; + }; + + i2c1_master_pins2:i2c1_pins2 { + mux { + groups = "i2c_b_sda_x", + "i2c_b_scl_x"; + function = "i2c_b"; + drive-strength = <3>; + bias-disable; + }; + }; + + i2c1_master_pins3:i2c1_pins3 { + mux { + groups = "i2c_b_sda_h2", + "i2c_b_scl_h3"; + function = "i2c_b"; + drive-strength = <3>; + bias-disable; + }; + }; + + i2c1_master_pins4:i2c1_pins4 { + mux { + groups = "i2c_b_sda_h6", + "i2c_b_scl_h7"; + function = "i2c_b"; + drive-strength = <3>; + bias-disable; + }; + }; + + i2c2_master_pins1:i2c2_pins1 { + mux { + groups = "i2c_c_sda_x", + "i2c_c_scl_x"; + function = "i2c_c"; + drive-strength = <3>; + bias-disable; + }; + }; + + i2c2_master_pins2:i2c2_pins2 { + mux { + groups = "i2c_c_sda_z10", + "i2c_c_scl_z11"; + function = "i2c_c"; + drive-strength = <3>; + bias-disable; + }; + }; + + i2c2_master_pins3:i2c2_pins3 { + mux { + groups = "i2c_c_sda_z14", + "i2c_c_scl_z15"; + function = "i2c_c"; + drive-strength = <3>; + bias-disable; + }; + }; + + i2c3_master_pins1:i2c3_pins1 { + mux { + groups = "i2c_d_sda_h", + "i2c_d_scl_h"; + function = "i2c_d"; + drive-strength = <3>; + bias-disable; + }; + }; + + i2c3_master_pins2:i2c3_pins2 { + mux { + groups = "i2c_d_sda_a", + "i2c_d_scl_a"; + function = "i2c_d"; + drive-strength = <3>; + bias-disable; + }; + }; + + i2c4_master_pin1:i2c4_pins1 { + mux { + groups = "i2c_e_sda_d", + "i2c_e_scl_d"; + function = "i2c_e"; + drive-strength = <3>; + bias-disable; + }; + }; + + i2c4_master_pin2:i2c4_pins2 { + mux { + groups = "i2c_e_sda_e", + "i2c_e_scl_e"; + function = "i2c_e"; + drive-strength = <3>; + bias-disable; + }; + }; + + jtag_a_pins:jtag_a_pin { + mux { + groups = "jtag_1_clk", + "jtag_1_tms", + "jtag_1_tdi", + "jtag_1_tdo"; + function = "jtag_1"; + }; + }; + + jtag_b_pins:jtag_b_pin { + mux { + groups = "jtag_2_clk", + "jtag_2_tms", + "jtag_2_tdi", + "jtag_2_tdo"; + function = "jtag_2"; + }; + }; + + swd_a_pins:swd_a_pin { + mux { + groups = "swclk", + "swdio"; + function = "sw"; + }; + }; + + emmc_pins: emmc { + mux { + groups = "emmc_nand_d0", + "emmc_nand_d1", + "emmc_nand_d2", + "emmc_nand_d3", + "emmc_nand_d4", + "emmc_nand_d5", + "emmc_nand_d6", + "emmc_nand_d7", + "emmc_clk", + "emmc_cmd"; + function = "emmc"; + bias-pull-up; + input-enable; + }; + mux1 { + groups = "emmc_nand_ds"; + function = "emmc"; + input-enable; + bias-pull-down; + }; + }; + + emmc_clk_gate_pins: emmc_clk_gate { + mux { + groups = "emmc_clk"; + function = "emmc"; + bias-pull-down; + }; + }; + + all_nand_pins: all_nand_pins { + mux { + groups = "emmc_nand_d0", + "emmc_nand_d1", + "emmc_nand_d2", + "emmc_nand_d3", + "emmc_nand_d4", + "emmc_nand_d5", + "emmc_nand_d6", + "emmc_nand_d7", + "nand_ce0", + "nand_ale", + "nand_cle", + "nand_wen_clk", + "nand_ren_wr"; + function = "nand"; + input-enable; + }; + }; + + nand_cs_pins: nand_cs { + mux { + groups = "nand_ce0"; + function = "nand"; + }; + }; + + sdcard_pins: sdcard { + mux { + groups = "sdcard_d0_c", + "sdcard_d1_c", + "sdcard_d2_c", + "sdcard_d3_c", + "sdcard_cmd_c"; + function = "sdcard"; + bias-pull-up; + input-enable; + drive-strength = <4>; + }; + mux1 { + groups ="sdcard_clk_c"; + function = "sdcard"; + bias-pull-up; + output-high; + drive-strength = <4>; + }; + }; + + sdcard_clk_gate_pins: sdcard_clk_gate { + mux { + groups = "sdcard_clk_c"; + function = "sdcard"; + bias-pull-down; + }; + }; + + to_sduart_pins: to_sduart_pins{ + mux { + groups = "uart_b_rx_c", "uart_b_tx_c"; + function = "uart_b"; + bias-pull-up; + input-enable; + }; + }; + + sd_to_uart_pins: sd_to_uart_pins{ + mux { + groups = "uart_b_rx_d", "uart_b_tx_d"; + function = "uart_b"; + bias-pull-up; + input-enable; + }; + }; + + spicc0_pins_x: spicc0_pins_x { + mux { + groups = "spi_a_mosi_x", + "spi_a_miso_x", + //"spi_a_ss0_x", + "spi_a_sclk_x"; + function = "spi_a"; + drive-strength = <1>; + }; + }; + + spicc0_pins_c: spicc0_pins_c { + mux { + groups = "spi_a_mosi_c", + "spi_a_miso_c", + //"spi_a_ss0_c", + "spi_a_sclk_c"; + function = "spi_a"; + drive-strength = <1>; + }; + }; + + spicc1_pins_h: spicc1_pins_h { + mux { + groups = "spi_b_mosi_h", + "spi_b_miso_h", + //"spi_b_ss0_h", + "spi_b_sclk_h"; + function = "spi_b"; + drive-strength = <1>; + }; + }; + + spifc_pins: spifc_pins { + mux { + groups = "nor_d", + "nor_q", + "nor_c", + //"nor_cs", + "nor_hold", + "nor_wp"; + function = "nor"; + drive-strength = <3>; + }; + }; + + pwm_a_pins1: pwm_a_pins1 { + mux { + groups = "pwm_a_e"; + function = "pwm_a"; + }; + }; + + pwm_a_pins2: pwm_a_pins2 { + mux { + groups = "pwm_a_x"; + function = "pwm_a"; + }; + }; + + pwm_b_pins1: pwm_b_pins1 { + mux { + groups = "pwm_b_h"; + function = "pwm_b"; + }; + }; + + pwm_b_pins2: pwm_b_pins2 { + mux { + groups = "pwm_b_z0"; + function = "pwm_b"; + }; + }; + + pwm_b_pins3: pwm_b_pins3 { + mux { + groups = "pwm_b_z13"; + function = "pwm_b"; + }; + }; + + pwm_b_pins4: pwm_b_pins4 { + mux { + groups = "pwm_b_x7"; + function = "pwm_b"; + }; + }; + + pwm_b_pins5: pwm_b_pins5 { + mux { + groups = "pwm_b_x19"; + function = "pwm_b"; + }; + }; + + pwm_c_pins1: pwm_c_pins1 { + mux { + groups = "pwm_c_c"; + function = "pwm_c"; + }; + }; + + pwm_c_pins2: pwm_c_pins2 { + mux { + groups = "pwm_c_x"; + function = "pwm_c"; + }; + }; + + pwm_c_pins3: pwm_c_pins3 { + mux { + groups = "pwm_c_z"; + function = "pwm_c"; + }; + }; + + pwm_d_pins1: pwm_d_pins1 { + mux { + groups = "pwm_d_z"; + function = "pwm_d"; + }; + }; + + pwm_d_pins2: pwm_d_pins2 { + mux { + groups = "pwm_d_x3"; + function = "pwm_d"; + }; + }; + + pwm_d_pins3: pwm_d_pins3 { + mux { + groups = "pwm_d_x6"; + function = "pwm_d"; + }; + }; + + pwm_e_pins: pwm_e { + mux { + groups = "pwm_e"; + function = "pwm_e"; + }; + }; + + pwm_f_pins1: pwm_f_pins1 { + mux { + groups = "pwm_f_x"; + function = "pwm_f"; + }; + }; + + pwm_f_pins2: pwm_f_pins2 { + mux { + groups = "pwm_f_h"; + function = "pwm_f"; + }; + }; + + pwm_f_pins3: pwm_f_pins3 { + mux { + groups = "pwm_f_z"; + function = "pwm_f"; + }; + }; + + pwm_g_pins1: pwm_g_pins1 { + mux { + groups = "pwm_g"; + function = "pwm_g"; + }; + }; + + pwm_h_pins1: pwm_h_pins1 { + mux { + groups = "pwm_h"; + function = "pwm_h"; + }; + }; + + pwm_i_pins1: pwm_i_pins1 { + mux { + groups = "pwm_i_d4"; + function = "pwm_i"; + }; + }; + + pwm_i_pins2: pwm_i_pins2 { + mux { + groups = "pwm_i_d6"; + function = "pwm_i"; + }; + }; + + pwm_j_pins1: pwm_j_pins1 { + mux { + groups = "pwm_j_e"; + function = "pwm_j"; + }; + }; + + pwm_j_pins2: pwm_j_pins2 { + mux { + groups = "pwm_j_d5"; + function = "pwm_j"; + }; + }; + + pwm_j_pins3: pwm_j_pins3 { + mux { + groups = "pwm_j_d10"; + function = "pwm_j"; + }; + }; + + pwm_i_hiz_pins1: pwm_i_hiz_pins1 { + mux { + groups = "pwm_i_hiz"; + function = "pwm_i_hiz"; + }; + }; + + pwm_g_hiz_pins1: pwm_g_hiz_pins1 { + mux { + groups = "pwm_g_hiz"; + function = "pwm_g_hiz"; + }; + }; + external_eth_rmii_pins: external_eth_rmii_pins { + mux { + groups = "eth_mdio", + "eth_mdc", + "eth_rgmii_rx_clk", + "eth_rx_dv", + "eth_rxd0", + "eth_rxd1", + "eth_txen", + "eth_txd0", + "eth_txd1"; + function = "eth"; + drive-strength = <3>; + }; + }; + external_eth_rgmii_pins: external_eth_rgmii_pins { + mux { + groups = "eth_mdio", + "eth_mdc", + "eth_rgmii_rx_clk", + "eth_rx_dv", + "eth_rxd0", + "eth_rxd1", + "eth_rxd2_rgmii", + "eth_rxd3_rgmii", + "eth_rgmii_tx_clk", + "eth_txen", + "eth_txd0", + "eth_txd1", + "eth_txd2_rgmii", + "eth_txd3_rgmii"; + function = "eth"; + drive-strength = <3>; + }; + }; + + remote_pins: remote_pin { + mux { + groups = "remote_input_d5"; + function = "remote_input"; + }; + }; +};
diff --git a/arch/arm/dts/meson-sc2_skt-panel.dtsi b/arch/arm/dts/meson-sc2_skt-panel.dtsi new file mode 100644 index 0000000..fbb676c --- /dev/null +++ b/arch/arm/dts/meson-sc2_skt-panel.dtsi
@@ -0,0 +1,742 @@ +/* + * arch/arm64/boot/dts/amlogic/mesong12a_skt-panel.dtsi + * + * Copyright (C) 2016 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/ { + lcd{ + compatible = "amlogic, lcd-g12a"; + mode = "tablet"; + status = "okay"; + key_valid = <0>; + /* + clocks = <&clkc CLKID_MIPI_DSI_HOST + &clkc CLKID_MIPI_DSI_PHY + &clkc CLKID_DSI_MEAS_COMP + &clkc CLKID_VCLK2_ENCL + &clkc CLKID_VCLK2_VENCL + &clkc CLKID_GP0_PLL>; + clock-names = "dsi_host_gate", + "dsi_phy_gate", + "dsi_meas", + "encl_top_gate", + "encl_int_gate", + "gp0_pll"; + */ + reg = <0x0 0xffd07000 0x0 0x400 /* dsi_host */ + 0x0 0xff644000 0x0 0x200>; /* dsi_phy */ + interrupts = <0 3 1 + 0 56 1>; + interrupt-names = "vsync","vsync2"; + pinctrl_version = <2>; /* for uboot */ + + /* power type: + * (0=cpu_gpio, 1=pmu_gpio, 2=signal,3=extern, 0xff=ending) + * power index: + * (point gpios_index, or extern_index,0xff=invalid) + * power value:(0=output low, 1=output high, 2=input) + * power delay:(unit in ms) + */ + + /*lcd_cpu-gpios = <&gpio GPIOZ_9 GPIO_ACTIVE_HIGH + &gpio GPIOZ_8 GPIO_ACTIVE_HIGH>; + */ + lcd_cpu_gpio_names = "GPIOZ_9","GPIOZ_8"; + + lcd_0{ + model_name = "B080XAN01"; + interface = "mipi"; + basic_setting = <768 1024 /*h_active, v_active*/ + 948 1140 /*h_period, v_period*/ + 8 /*lcd_bits*/ + 119 159>; /*screen_widht, screen_height*/ + lcd_timing = <64 56 0 /*hs_width, hs_bp, hs_pol*/ + 50 30 0>; /*vs_width, vs_bp, vs_pol*/ + clk_attr = <0 /*fr_adj_type(0=clk, 1=htotal, 2=vtotal)*/ + 0 /*clk_ss_level */ + 1 /*clk_auto_generate*/ + 64843200>; /*pixel_clk(unit in Hz)*/ + mipi_attr = <4 /*lane_num*/ + 550 /*bit_rate_max(MHz)*/ + 0 /*factor(*100, default 0 for auto)*/ + 1 /*operation_mode_init(0=video, 1=command)*/ + 0 /*operation_mode_display(0=video, 1=command)*/ + 2 /* + *video_mode_type + *(0=sync_pulse,1=sync_event,2=burst) + */ + 1 /*clk_always_hs(0=disable,1=enable)*/ + 0>; /*phy_switch(0=auto,1=standard,2=slow)*/ + + /* dsi_init: data_type, num, data... */ + dsi_init_on = <0x05 1 0x11 + 0xfd 1 20 /*delay(ms)*/ + 0x05 1 0x29 + 0xfd 1 20 /*delay(ms)*/ + 0xff 0>; /*ending*/ + dsi_init_off = <0x05 1 0x28 + 0xfd 1 10 /*delay(ms)*/ + 0x05 1 0x10 + 0xfd 1 10 /*delay(ms)*/ + 0xff 0>; /*ending*/ + extern_init = <0xff>; /*0xff for invalid*/ + + /* power step: type, index, value, delay(ms) */ + power_on_step = < + 0 1 0 100 + 0 0 0 10 + 0 0 1 20 + 2 0 0 0 + 0xff 0 0 0>; /*ending*/ + power_off_step = < + 2 0 0 50 + 0 0 0 10 + 0 1 1 100 + 0xff 0 0 0>; /*ending*/ + backlight_index = <0>; + }; + + lcd_1{ + model_name = "P070ACB_FT"; + interface = "mipi"; + basic_setting = <600 1024 /*h_active, v_active*/ + 770 1070 /*h_period, v_period*/ + 8 /*lcd_bits*/ + 3 5>; /*screen_widht, screen_height*/ + lcd_timing = <10 80 0 /*hs_width,hs_bp,hs_pol*/ + 6 20 0>; /*vs_width,vs_bp,vs_pol*/ + clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/ + 0 /*clk_ss_level*/ + 1 /*clk_auto_generate*/ + 49434000>; /*pixel_clk(unit in Hz)*/ + mipi_attr = <4 /*lane_num*/ + 400 /*bit_rate_max(MHz)*/ + 0 /*factor(*100, default 0 for auto)*/ + 1 /*operation_mode_init(0=video, 1=command)*/ + 0 /*operation_mode_display(0=video, 1=command)*/ + 2 /* + *video_mode_type + *(0=sync_pulse,1=sync_event,2=burst) + */ + 0 /*clk_always_hs(0=disable,1=enable)*/ + 0>; /*phy_switch(0=auto,1=standard,2=slow)*/ + /* dsi_init: data_type, num, data... */ + dsi_init_on = < + 0xff 10 + 0xf0 3 0 1 30 /* reset high, delay 30ms */ + 0xf0 3 0 0 10 /* reset low, delay 10ms */ + 0xf0 3 0 1 30 /* reset high, delay 30ms */ + 0xfc 2 0x04 3 /* check_reg, check_cnt */ + 0xff 0>; /* ending flag */ + dsi_init_off = <0xff 0>; /* ending flag */ + /* extern_init: 0xff for invalid */ + extern_init = <2>; + /* power step: type,index,value,delay(ms) */ + power_on_step = < + 0 1 0 200 /* panel power on */ + 2 0 0 0 + 0xff 0 0 0>; + power_off_step = < + 2 0 0 0 + 0 0 0 20 /* reset low */ + 0 1 1 100 /* panel power off */ + 0xff 0 0 0>; + backlight_index = <0>; + }; + + lcd_3{ + model_name = "TL050FHV02CT"; + interface = "mipi"; + basic_setting = <1080 1920 /*h_active, v_active*/ + 1125 2100 /*h_period, v_period*/ + 8 /*lcd_bits*/ + 65 119>; /*screen_widht, screen_height*/ + lcd_timing = <5 30 0 /*hs_width,hs_bp,hs_pol*/ + 44 108 0>; /*vs_width,vs_bp,vs_pol*/ + clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/ + 0 /*clk_ss_level*/ + 1 /*clk_auto_generate*/ + 118125000>; /*pixel_clk(unit in Hz)*/ + mipi_attr = <4 /*lane_num*/ + 960 /*bit_rate_max(MHz)*/ + 0 /*factor(*100, default 0 for auto)*/ + 1 /*operation_mode_init(0=video, 1=command)*/ + 0 /*operation_mode_display(0=video, 1=command)*/ + 2 /* + *video_mode_type + *(0=sync_pulse,1=sync_event,2=burst) + */ + 1 /*clk_always_hs(0=disable,1=enable)*/ + 0>; /*phy_switch(0=auto,1=standard,2=slow)*/ + /* dsi_init: data_type, num, data... */ + dsi_init_on = <0xff 0>; /* ending flag */ + dsi_init_off = <0xff 0>; /* ending flag */ + /* extern_init: 0xff for invalid */ + extern_init = <3>; + /* power step: type,index,value,delay(ms) */ + power_on_step = < + 0 1 0 200 + 0 0 1 20 + 0 0 0 10 + 0 0 1 20 + 2 0 0 0 + 0xff 0 0 0>; + power_off_step = < + 2 0 0 0 + 0 0 0 20 + 0 1 1 100 + 0xff 0 0 0>; + backlight_index = <0>; + }; + + lcd_4{ + model_name = "TL070WSH27"; + interface = "mipi"; + basic_setting = <1024 600 /*h_active, v_active*/ + 1250 630 /*h_period, v_period*/ + 8 /*lcd_bits*/ + 154 86>; /*screen_widht, screen_height*/ + lcd_timing = <80 100 0 /*hs_width, hs_bp, hs_pol*/ + 5 20 0>; /*vs_width, vs_bp, vs_pol*/ + clk_attr = <0 /*fr_adj_type(0=clk, 1=htotal, 2=vtotal)*/ + 0 /*clk_ss_level */ + 1 /*clk_auto_generate*/ + 47250000>; /*pixel_clk(unit in Hz)*/ + mipi_attr = <4 /*lane_num*/ + 300 /*bit_rate_max(MHz)*/ + 0 /*factor(*100, default 0 for auto)*/ + 1 /*operation_mode_init(0=video, 1=command)*/ + 0 /*operation_mode_display(0=video, 1=command)*/ + 2 /* + *video_mode_type + *(0=sync_pulse,1=sync_event,2=burst) + */ + 1 /*clk_always_hs(0=disable,1=enable)*/ + 0>; /*phy_switch(0=auto,1=standard,2=slow)*/ + + /* dsi_init: data_type, num, data... */ + dsi_init_on = <0x05 1 0x11 + 0xfd 1 20 /*delay(ms)*/ + 0x05 1 0x29 + 0xfd 1 20 /*delay(ms)*/ + 0xff 0>; /*ending*/ + dsi_init_off = <0x05 1 0x28 + 0xfd 1 10 /*delay(ms)*/ + 0x05 1 0x10 + 0xfd 1 10 /*delay(ms)*/ + 0xff 0>; /*ending*/ + extern_init = <0xff>; /*0xff for invalid*/ + + /* power step: type, index, value, delay(ms) */ + power_on_step = < + 0 1 0 100 + 0 0 0 10 + 0 0 1 20 + 2 0 0 0 + 0xff 0 0 0>; /*ending*/ + power_off_step = < + 2 0 0 50 + 0 0 0 10 + 0 1 1 100 + 0xff 0 0 0>; /*ending*/ + backlight_index = <0>; + }; + }; + + lcd_extern{ + compatible = "amlogic, lcd_extern"; + status = "okay"; + i2c_bus = "i2c_bus_0"; + key_valid = <0>; + + extern_0{ + index = <0>; + extern_name = "mipi_default";/*default*/ + status = "okay"; + type = <2>; /* 0=i2c, 1=spi, 2=mipi */ + cmd_size = <0xff>; + init_on = < + 0xfd 1 10 + 0x05 1 0x11 + 0xfd 1 120 /* delay 120ms */ + 0x05 1 0x29 + 0xff 0>; /*ending*/ + init_off = < + 0x05 1 0x28 /* display off */ + 0xfd 1 10 /* delay 10ms */ + 0x05 1 0x10 /* sleep in */ + 0xfd 1 150 /* delay 150ms */ + 0xff 0>; /*ending*/ + }; + + extern_2{ + index = <2>; + extern_name = "mipi_default";/*P070ACB_FT*/ + status = "okay"; + type = <2>; /* 0=i2c, 1=spi, 2=mipi */ + cmd_size = <0xff>; + init_on = < + 0x23 2 0xE0 0x00 /* Page 0 */ + 0x23 2 0xE1 0x93 /* PASSWORD */ + 0x23 2 0xE2 0x65 + 0x23 2 0xE3 0xF8 + 0x23 2 0x80 0x03 + 0x23 2 0xE0 0x01 /* Page 01 */ + 0x23 2 0x0C 0x74 /* Set PWRIC */ + 0x23 2 0x17 0x00 /* Set Gamma Power */ + 0x23 2 0x18 0xEF /* VGMP=5.1V */ + 0x23 2 0x19 0x00 + 0x23 2 0x1A 0x00 + 0x23 2 0x1B 0xEF /* VGMN=-5.1V */ + 0x23 2 0x1C 0x00 + 0x23 2 0x1F 0x70 /* Set Gate Power */ + 0x23 2 0x20 0x2D + 0x23 2 0x21 0x2D + 0x23 2 0x22 0x7E + 0x23 2 0x26 0xF3 /* VDDD from IOVCC */ + 0x23 2 0x37 0x09 /* SetPanel */ + 0x23 2 0x38 0x04 /* SET RGBCYC */ + 0x23 2 0x39 0x00 + 0x23 2 0x3A 0x01 + 0x23 2 0x3C 0x90 + 0x23 2 0x3D 0xFF + 0x23 2 0x3E 0xFF + 0x23 2 0x3F 0xFF + 0x23 2 0x40 0x02 /* Set TCON */ + 0x23 2 0x41 0x80 + 0x23 2 0x42 0x99 + 0x23 2 0x43 0x14 + 0x23 2 0x44 0x19 + 0x23 2 0x45 0x5A + 0x23 2 0x4B 0x04 + 0x23 2 0x55 0x02 /* power voltage */ + 0x23 2 0x56 0x01 + 0x23 2 0x57 0x69 + 0x23 2 0x58 0x0A + 0x23 2 0x59 0x0A + 0x23 2 0x5A 0x2E /* VGH = 16.2V */ + 0x23 2 0x5B 0x19 /* VGL = -12V */ + 0x23 2 0x5C 0x15 + 0x23 2 0x5D 0x77 /* Gamma */ + 0x23 2 0x5E 0x56 + 0x23 2 0x5F 0x45 + 0x23 2 0x60 0x38 + 0x23 2 0x61 0x35 + 0x23 2 0x62 0x27 + 0x23 2 0x63 0x2D + 0x23 2 0x64 0x18 + 0x23 2 0x65 0x33 + 0x23 2 0x66 0x34 + 0x23 2 0x67 0x35 + 0x23 2 0x68 0x56 + 0x23 2 0x69 0x45 + 0x23 2 0x6A 0x4F + 0x23 2 0x6B 0x42 + 0x23 2 0x6C 0x40 + 0x23 2 0x6D 0x34 + 0x23 2 0x6E 0x25 + 0x23 2 0x6F 0x02 + 0x23 2 0x70 0x77 + 0x23 2 0x71 0x56 + 0x23 2 0x72 0x45 + 0x23 2 0x73 0x38 + 0x23 2 0x74 0x35 + 0x23 2 0x75 0x27 + 0x23 2 0x76 0x2D + 0x23 2 0x77 0x18 + 0x23 2 0x78 0x33 + 0x23 2 0x79 0x34 + 0x23 2 0x7A 0x35 + 0x23 2 0x7B 0x56 + 0x23 2 0x7C 0x45 + 0x23 2 0x7D 0x4F + 0x23 2 0x7E 0x42 + 0x23 2 0x7F 0x40 + 0x23 2 0x80 0x34 + 0x23 2 0x81 0x25 + 0x23 2 0x82 0x02 + 0x23 2 0xE0 0x02 /* Page2 */ + 0x23 2 0x00 0x53 + /* GIP_L Pin mapping RESET_EVEN */ + 0x23 2 0x01 0x55 /* VSSG_EVEN */ + 0x23 2 0x02 0x55 /* VSSA_EVEN */ + 0x23 2 0x03 0x51 /* STV2_EVEN */ + 0x23 2 0x04 0x77 /* VDD2_EVEN */ + 0x23 2 0x05 0x57 /* VDD1_EVEN */ + 0x23 2 0x06 0x1F + 0x23 2 0x07 0x4F /* CK12 */ + 0x23 2 0x08 0x4D /* CK10 */ + 0x23 2 0x09 0x1F + 0x23 2 0x0A 0x4B /* CK8 */ + 0x23 2 0x0B 0x49 /* CK6 */ + 0x23 2 0x0C 0x1F + 0x23 2 0x0D 0x47 /* CK4 */ + 0x23 2 0x0E 0x45 /* CK2 */ + 0x23 2 0x0F 0x41 /* STV1_EVEN */ + 0x23 2 0x10 0x1F + 0x23 2 0x11 0x1F + 0x23 2 0x12 0x1F + 0x23 2 0x13 0x55 /* VGG */ + 0x23 2 0x14 0x1F + 0x23 2 0x15 0x1F + 0x23 2 0x16 0x52 + /* GIP_R Pin mapping RESET_ODD */ + 0x23 2 0x17 0x55 /* VSSG_ODD */ + 0x23 2 0x18 0x55 /* VSSA_ODD */ + 0x23 2 0x19 0x50 /* STV2_ODD */ + 0x23 2 0x1A 0x77 /* VDD2_ODD */ + 0x23 2 0x1B 0x57 /* VDD1_ODD */ + 0x23 2 0x1C 0x1F + 0x23 2 0x1D 0x4E /* CK11 */ + 0x23 2 0x1E 0x4C /* CK9 */ + 0x23 2 0x1F 0x1F + 0x23 2 0x20 0x4A /* CK7 */ + 0x23 2 0x21 0x48 /* CK5 */ + 0x23 2 0x22 0x1F + 0x23 2 0x23 0x46 /* CK3 */ + 0x23 2 0x24 0x44 /* CK1 */ + 0x23 2 0x25 0x40 /* STV1_ODD */ + 0x23 2 0x26 0x1F + 0x23 2 0x27 0x1F + 0x23 2 0x28 0x1F + 0x23 2 0x29 0x1F + 0x23 2 0x2A 0x1F + 0x23 2 0x2B 0x55 /* VGG */ + 0x23 2 0x2C 0x12 /* GIP_L_GS Pin mapping */ + 0x23 2 0x2D 0x15 + 0x23 2 0x2E 0x15 + 0x23 2 0x2F 0x00 + 0x23 2 0x30 0x37 + 0x23 2 0x31 0x17 + 0x23 2 0x32 0x1F + 0x23 2 0x33 0x08 + 0x23 2 0x34 0x0A + 0x23 2 0x35 0x1F + 0x23 2 0x36 0x0C + 0x23 2 0x37 0x0E + 0x23 2 0x38 0x1F + 0x23 2 0x39 0x04 + 0x23 2 0x3A 0x06 + 0x23 2 0x3B 0x10 + 0x23 2 0x3C 0x1F + 0x23 2 0x3D 0x1F + 0x23 2 0x3E 0x1F + 0x23 2 0x3F 0x15 + 0x23 2 0x40 0x1F + 0x23 2 0x41 0x1F + 0x23 2 0x42 0x13 /* GIP_R_GS Pin mapping */ + 0x23 2 0x43 0x15 + 0x23 2 0x44 0x15 + 0x23 2 0x45 0x01 + 0x23 2 0x46 0x37 + 0x23 2 0x47 0x17 + 0x23 2 0x48 0x1F + 0x23 2 0x49 0x09 + 0x23 2 0x4A 0x0B + 0x23 2 0x4B 0x1F + 0x23 2 0x4C 0x0D + 0x23 2 0x4D 0x0F + 0x23 2 0x4E 0x1F + 0x23 2 0x4F 0x05 + 0x23 2 0x50 0x07 + 0x23 2 0x51 0x11 + 0x23 2 0x52 0x1F + 0x23 2 0x53 0x1F + 0x23 2 0x54 0x1F + 0x23 2 0x55 0x1F + 0x23 2 0x56 0x1F + 0x23 2 0x57 0x15 + 0x23 2 0x58 0x40 /* GIP Timing */ + 0x23 2 0x59 0x00 + 0x23 2 0x5A 0x00 + 0x23 2 0x5B 0x10 + 0x23 2 0x5C 0x14 + 0x23 2 0x5D 0x40 + 0x23 2 0x5E 0x01 + 0x23 2 0x5F 0x02 + 0x23 2 0x60 0x40 + 0x23 2 0x61 0x03 + 0x23 2 0x62 0x04 + 0x23 2 0x63 0x7A + 0x23 2 0x64 0x7A + 0x23 2 0x65 0x74 + 0x23 2 0x66 0x16 + 0x23 2 0x67 0xB4 + 0x23 2 0x68 0x16 + 0x23 2 0x69 0x7A + 0x23 2 0x6A 0x7A + 0x23 2 0x6B 0x0C + 0x23 2 0x6C 0x00 + 0x23 2 0x6D 0x04 + 0x23 2 0x6E 0x04 + 0x23 2 0x6F 0x88 + 0x23 2 0x70 0x00 + 0x23 2 0x71 0x00 + 0x23 2 0x72 0x06 + 0x23 2 0x73 0x7B + 0x23 2 0x74 0x00 + 0x23 2 0x75 0xBC + 0x23 2 0x76 0x00 + 0x23 2 0x77 0x04 + 0x23 2 0x78 0x2C + 0x23 2 0x79 0x00 + 0x23 2 0x7A 0x00 + 0x23 2 0x7B 0x00 + 0x23 2 0x7C 0x00 + 0x23 2 0x7D 0x03 + 0x23 2 0x7E 0x7B + 0x23 2 0xE0 0x04 /* Page4 */ + 0x23 2 0x09 0x11 /* Set RGBCYC2 */ + 0x23 2 0x0E 0x48 + 0x23 2 0x2B 0x2B /* ESD Protect */ + 0x23 2 0x2E 0x44 + 0x23 2 0xE0 0x00 /* Page0 */ + 0x23 2 0xE6 0x02 /* Watch dog */ + 0x23 2 0xE7 0x0C + 0x05 1 0x11 /* sleep out */ + 0xfd 1 120 + 0x05 1 0x29 /* display on */ + 0x05 1 0x35 + 0xfd 1 20 /* delay(ms) */ + 0xFF 0>; /*ending*/ + init_off = < + 0x05 1 0x28 /* display off */ + 0xfd 1 10 /* delay 10ms */ + 0x05 1 0x10 /* sleep in */ + 0xfd 1 150 /* delay 150ms */ + 0xff 0>; /*ending*/ + }; + + extern_3{ + index = <3>; + extern_name = "mipi_default";/*TL050FHV02CT*/ + status = "okay"; + type = <2>; /* 0=i2c, 1=spi, 2=mipi */ + cmd_size = <0xff>; + init_on = < + 0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x03 + 0x29 10 0x90 0x03 0x14 0x09 0x00 0x00 + 0x00 0x38 0x00 0x00 + 0x29 10 0x91 0x00 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 + 0x29 12 0x92 0x40 0x0B 0x0C 0x0D 0x0E + 0x00 0x38 0x00 0x10 0x03 0x04 + 0x29 9 0x94 0x00 0x08 0x0B 0x03 0xD2 + 0x03 0xD3 0x0C + 0x29 17 0x95 0x00 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 + 0x29 3 0x99 0x00 0x00 + 0x29 12 0x9A 0x00 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 0x00 0x00 + 0x29 7 0x9B 0x01 0x38 0x00 0x00 0x00 0x00 + 0x29 3 0x9C 0x00 0x00 + 0x29 9 0x9D 0x10 0x10 0x10 0x10 0x10 + 0x10 0x00 0x00 + 0x29 3 0x9E 0x00 0x00 + 0x29 11 0xA0 0x9F 0x1F 0x08 0x1F 0x0A + 0x1F 0x00 0x1F 0x14 0x1F + 0x29 11 0xA1 0x15 0x1F 0x1F 0x1F 0x1F + 0x1F 0x1F 0x1F 0x1F 0x1F + 0x29 11 0xA2 0x1F 0x1F 0x1F 0x1F 0x1F + 0x1F 0x1F 0x1F 0x1F 0x1F + 0x29 11 0xA4 0x1F 0x1F 0x1F 0x1F 0x1F + 0x1F 0x1F 0x1F 0x1F 0x1F + 0x29 11 0xA5 0x1F 0x1F 0x1F 0x1F 0x1F + 0x1F 0x1F 0x1F 0x1F 0x15 + 0x29 11 0xA6 0x1F 0x14 0x1F 0x01 0x1F + 0x0B 0x1F 0x09 0x1F 0x1F + 0x29 11 0xA7 0x1F 0x1F 0x0B 0x1F 0x09 + 0x1F 0x01 0x1F 0x15 0x1F + 0x29 11 0xA8 0x14 0x1F 0x1F 0x1F 0x1F + 0x1F 0x1F 0x1F 0x1F 0x1F + 0x29 11 0xA9 0x1F 0x1F 0x1F 0x1F 0x1F + 0x1F 0x1F 0x1F 0x1F 0x1F + 0x29 11 0xAB 0x1F 0x1F 0x1F 0x1F 0x1F + 0x1F 0x1F 0x1F 0x1F 0x1F + 0x29 11 0xAC 0x1F 0x1F 0x1F 0x1F 0x1F + 0x1F 0x1F 0x1F 0x1F 0x14 + 0x29 11 0xAD 0x1F 0x15 0x1F 0x00 0x1F + 0x08 0x1F 0x0A 0x1F 0x1F + 0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x00 + 0x29 4 0xBC 0x00 0x00 0x00 + 0x29 5 0xB8 0x01 0xAF 0x8F 0x8F + 0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x01 + 0x29 17 0xD1 0x00 0x00 0x00 0x09 0x00 + 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D + 0x00 0x79 0x00 0xA7 + 0x29 17 0xD2 0x00 0xCF 0x01 0x12 0x01 + 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED + 0x02 0x2F 0x02 0x74 + 0x29 17 0xD3 0x02 0x9F 0x02 0xD5 0x02 + 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73 + 0x03 0x8C 0x03 0xA5 + 0x29 5 0xD4 0x03 0xC5 0x03 0xFF + 0x29 17 0xD5 0x00 0x00 0x00 0x09 0x00 + 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D + 0x00 0x79 0x00 0xA7 + 0x29 17 0xD6 0x00 0xCF 0x01 0x12 0x01 + 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED + 0x02 0x2F 0x02 0x74 + 0x29 17 0xD7 0x02 0x9F 0x02 0xD5 0x02 + 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73 + 0x03 0x8C 0x03 0xA5 + 0x29 5 0xD8 0x03 0xC5 0x03 0xFF + 0x29 17 0xD9 0x00 0x00 0x00 0x09 0x00 + 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D + 0x00 0x79 0x00 0xA7 + 0x29 17 0xDD 0x00 0xCF 0x01 0x12 0x01 + 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED + 0x02 0x2F 0x02 0x74 + 0x29 17 0xDE 0x02 0x9F 0x02 0xD5 0x02 + 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73 + 0x03 0x8C 0x03 0xA5 + 0x29 5 0xDF 0x03 0xC5 0x03 0xFF + 0x29 17 0xE0 0x00 0x00 0x00 0x09 0x00 + 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D + 0x00 0x79 0x00 0xA7 + 0x29 17 0xE1 0x00 0xCF 0x01 0x12 0x01 + 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED + 0x02 0x2F 0x02 0x74 + 0x29 17 0xE2 0x02 0x9F 0x02 0xD5 0x02 + 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73 + 0x03 0x8C 0x03 0xA5 + 0x29 5 0xE3 0x03 0xC5 0x03 0xFF + 0x29 17 0xE4 0x00 0x00 0x00 0x09 0x00 + 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D + 0x00 0x79 0x00 0xA7 + 0x29 17 0xE5 0x00 0xCF 0x01 0x12 0x01 + 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED + 0x02 0x2F 0x02 0x74 + 0x29 17 0xE6 0x02 0x9F 0x02 0xD5 0x02 + 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73 + 0x03 0x8C 0x03 0xA5 + 0x29 5 0xE7 0x03 0xC5 0x03 0xFF + 0x29 17 0xE8 0x00 0x00 0x00 0x09 0x00 + 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D + 0x00 0x79 0x00 0xA7 + 0x29 17 0xE9 0x00 0xCF 0x01 0x12 0x01 + 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED + 0x02 0x2F 0x02 0x74 + 0x29 17 0xEA 0x02 0x9F 0x02 0xD5 0x02 + 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73 + 0x03 0x8C 0x03 0xA5 + 0x29 5 0xEB 0x03 0xC5 0x03 0xFF + 0x29 4 0xB0 0x05 0x05 0x05 + 0x29 4 0xB1 0x05 0x05 0x05 + 0x29 4 0xB3 0x10 0x10 0x10 + 0x29 4 0xB4 0x06 0x06 0x06 + 0x29 4 0xB6 0x44 0x44 0x44 + 0x29 4 0xB7 0x34 0x34 0x34 + 0x29 4 0xB8 0x34 0x34 0x34 + 0x29 4 0xB9 0x24 0x24 0x24 + 0x29 4 0xBA 0x24 0x24 0x24 + 0x29 4 0xBC 0x00 0x70 0x00 + 0x29 4 0xBD 0x00 0x70 0x00 + 0x23 2 0xBE 0x50 + 0x23 2 0x35 0x00 + 0x13 1 0x11 + 0xfd 1 200 + 0x13 1 0x29 + 0xfd 1 200 + 0xFF 0>; /*ending*/ + init_off = < + 0x05 1 0x28 /* display off */ + 0xfd 1 10 /* delay 10ms */ + 0x05 1 0x10 /* sleep in */ + 0xfd 1 150 /* delay 150ms */ + 0xff 0>; /*ending*/ + }; + }; + + backlight{ + compatible = "amlogic, backlight-g12a"; + status = "okay"; + key_valid = <0>; + pinctrl-names = "pwm_on","pwm_off"; + /* pinctrl-0 = <&pwm_f_pins2>; */ + /* pinctrl-1 = <&bl_pwm_off_pins>; */ + pinctrl_version = <2>; /* for uboot */ + bl_pwm_config = <&bl_pwm_conf>; + /*bl-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_HIGH + &gpio GPIOH_5 GPIO_ACTIVE_HIGH>;*/ + bl_gpio_names = "GPIOH_4","GPIOH_5"; + + /* pwm port: PWM_A, PWM_B, PWM_C, PWM_D, PWM_E, PWM_F, PWM_VS*/ + /* power index:(point gpios_index, 0xff=invalid) + * power value:(0=output low, 1=output high, 2=input) + * power delay:(unit in ms) + */ + + backlight_0{ + index = <0>; + bl_name = "backlight_pwm"; + bl_level_default_uboot_kernel = <100 100>; + bl_level_attr = <255 10 /*max, min*/ + 128 128>; /*mid, mid_mapping*/ + bl_ctrl_method = <1>; /* 1=pwm, 2=pwm_combo, 4=extern */ + bl_power_attr = <0 /*en_gpio_index*/ + 1 0 /*on_value, off_value*/ + 200 200>; /*on_delay(ms), off_delay(ms)*/ + bl_pwm_port = "PWM_F"; + bl_pwm_attr = <0 /*pwm_method*/ + 180 /*pwm_freq(pwm:Hz, pwm_vs:multiple of vs)*/ + 100 25>; /*duty_max(%), duty_min(%)*/ + bl_pwm_power = <1 1 /*pwm_gpio_index, pwm_gpio_off*/ + 10 10>; /*pwm_on_delay(ms), pwm_off_delay(ms)*/ + bl_pwm_en_sequence_reverse = <0>; /* 1 for reverse */ + }; + backlight_1{ + index = <1>; + bl_name = "bl_extern"; + bl_level_default_uboot_kernel = <100 100>; + bl_level_attr = <255 10 /*max, min*/ + 128 128>; /*mid, mid_mapping*/ + bl_ctrl_method = <4>; /*1=pwm, 2=pwm_combo, 4=extern*/ + bl_power_attr = <1 /*en_gpio_index*/ + 1 0 /*on_value, off_value*/ + 200 200>; /*on_delay(ms), off_delay(ms)*/ + bl_extern_index = <0>; + }; + }; + bl_pwm_conf:bl_pwm_conf{ + pwm_channel_0 { + pwm_port_index = <5>; + pwms = <&pwm_ef MESON_PWM_1 30040 0>; + }; + }; + + bl_extern{ + compatible = "amlogic, bl_extern"; + status = "disabled"; + i2c_bus = "i2c_bus_3"; + + extern_0{ + index = <0>; + extern_name = "i2c_lp8556"; + type = <0>; /*0=i2c, 1=spi, 2=mipi*/ + i2c_address = <0x2c>; /*7bit i2c address*/ + dim_max_min = <255 10>; + }; + + extern_1{ + index = <1>; + extern_name = "mipi_lt070me05"; + type = <2>; /*0=i2c, 1=spi, 2=mipi*/ + dim_max_min = <255 10>; + }; + }; +};/* end of panel */ +
diff --git a/arch/arm/dts/meson-sm1-s905d3-ac200.dts b/arch/arm/dts/meson-sm1-s905d3-ac200.dts new file mode 100644 index 0000000..a891205 --- /dev/null +++ b/arch/arm/dts/meson-sm1-s905d3-ac200.dts
@@ -0,0 +1,79 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "meson-sm1-s905d3-ac200.dtsi" +#include "meson-g12a_skt-panel.dtsi" + +/ { + compatible = "amlogic,u200", "amlogic,s905d2", "amlogic,meson-g12a"; + model = "Amlogic Meson G12A (S905D2) U200 Development Board"; +}; + +/* This UART is brought out to the DB9 connector */ +&uart_AO { + status = "okay"; +}; + +&saradc { + status = "okay"; +}; + +/* demo for i2c user */ +&i2c3 { + status= "disabled"; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_master_pins2>; +}; + +&pinctrl_periphs { + bl_pwm_off_pins:bl_pwm_off_pin { + mux { + groups = "GPIOH_5"; + function = "gpio_periphs"; + output-high; + }; + }; +}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-sm1-s905d3-ac200.dtsi b/arch/arm/dts/meson-sm1-s905d3-ac200.dtsi new file mode 100755 index 0000000..839642b --- /dev/null +++ b/arch/arm/dts/meson-sm1-s905d3-ac200.dtsi
@@ -0,0 +1,291 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>. + * Based on meson-gx-p23x-q20x.dtsi: + * - Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * - Copyright (c) 2016 BayLibre, SAS. + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +/* Common DTSI for devices which are based on the P212 reference board. */ + +#include "meson-g12a-s905d2.dtsi" + +/ { + aliases { + serial0 = &uart_AO; + serial1 = &uart_A; + spi0 = &spifc; + spi1 = &spicc0; + spi2 = &spicc1; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c_AO; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + vddio_boot: regulator-vddio_boot { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vddio_ao18: regulator-vddio_ao18 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; +}; + +ðmac { + status = "okay"; + internal_phy = <1>; + mc_val = <0x4be04>; + /*mc_val = <0x1621>;*/ +}; + +&ir { + status = "disabled"; + /* pinctrl-0 = <&remote_input_ao_pins>; */ + /* pinctrl-names = "default"; */ +}; + +&saradc { + status = "okay"; + vref-supply = <&vddio_ao18>; +}; + +/* Wireless SDIO Module */ +&sd_emmc_a { + status = "disabled"; + /* pinctrl-0 = <&sdio_pins>; */ + /* pinctrl-names = "default"; */ + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + + non-removable; + disable-wp; + + pinname = "sdio"; + card_type = <3>; + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sd_all_pins>; + pinctrl-names = "default"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + + pinname = "sd"; + card_type = <5>; + init_co_phase = <3>; + init_tx_phase = <0>; + sd_hs_co_phase = <2>; + sd_hs_tx_phase = <0>; + sdr104_co_phase = <2>; + sdr104_hs_tx_phase = <0>; + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>; + /* cd-inverted; */ + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_conf_pull_up &emmc_conf_pull_done>; + pinctrl-names = "default"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <200000000>; + non-removable; + disable-wp; + /* mmc-ddr-1_8v; */ + mmc-hs200-1_8v; + + pinname = "emmc"; + card_type = <1>; + init_co_phase = <3>; + init_tx_phase = <0>; + hs_co_phase = <3>; + hs_tx_phase = <0>; + ddr_co_phase = <2>; + ddr_tx_phase = <0>; + hs2_co_phase = <3>; + hs2_tx_phase = <0>; + + hw_reset = <&gpio BOOT_12 GPIO_ACTIVE_HIGH>; + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* nand */ +&nand { + status = "okay"; + pinctrl-names = "default", "nand_all_pins", "nand_cs_only"; + pinctrl-0 = <&all_nand_pins>; + pinctrl-1 = <&all_nand_pins>; + pinctrl-2 = <&nand_cs_pins>; + + /* + #address-cells = <1>; + #size-cells = <0>; + + nand@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + nand-on-flash-bbt; + nand-ecc-mode = "hw"; + nand-ecc-strength = <8>; + nand-ecc-step-size = <1024>; + + meson-nand-user-mode = <2>; + meson-nand-ran-mode = <1>; + + partition@0 { + label = "boot"; + reg = <0x00000000 0x00200000>; + read-only; + }; + partition@200000 { + label = "env"; + reg = <0x00200000 0x00400000>; + }; + partition@600000 { + label = "system"; + reg = <0x00600000 0x00a00000>; + }; + partition@1000000 { + label = "rootfs"; + reg = <0x01000000 0x03000000>; + }; + partition@4000000 { + label = "media"; + reg = <0x04000000 0x8000000>; + }; + };*/ + +}; + +&dwc3 { + status = "okay"; + dr_mode = "host"; +}; + +&usb2_phy_v2 { + status = "okay"; + portnum = <2>; + dwc2_a_reg = <0xff400000>; +}; + +&usb3_phy_v2 { + status = "okay"; + portnum = <0>; + gpio-vbus-power = "GPIOH_6"; + gpios = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>; +}; + +&pwm_ef { + status = "okay"; + /* pinctrl-0 = <&pwm_e_pins>; */ + pinctrl-names = "default"; +}; + +/* This is connected to the Bluetooth module: */ +&uart_A { + status = "okay"; + pinctrl-0 = <&a_uart_pins>; + pinctrl-names = "default"; + uart-has-rtscts; +}; + +&uart_AO { + status = "okay"; + pinctrl-0 = <&ao_uart_pins>; + pinctrl-names = "default"; +}; + +&spifc { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spifc_all_pins>; + max-frequency = <80000000>; + max-io = <4>; + max-cs = <2>; + cs-gpios = <&gpio BOOT_14 GPIO_ACTIVE_HIGH>; + clocks = <&clkc CLKID_CLK81>; + clock-names = "core"; +}; + +&spicc1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc1_pins>; + cs-gpios = <&gpio GPIOH_6 0>; +};
diff --git a/arch/arm/dts/meson-t7-an400-lpddr4x.dts b/arch/arm/dts/meson-t7-an400-lpddr4x.dts new file mode 100644 index 0000000..1fb3395 --- /dev/null +++ b/arch/arm/dts/meson-t7-an400-lpddr4x.dts
@@ -0,0 +1,83 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "meson-t7-an400-lpddr4x.dtsi" +#include "meson-t7_skt-panel.dtsi" + +/ { + compatible = "amlogic,t7-an400-lpddr4x", "amlogic,t7-txxx", "amlogic,meson-t7"; + model = "Amlogic Meson T7 PXP Board"; +}; + +/* This UART is brought out to the DB9 connector */ +&uart_a { + status = "okay"; +}; + +&uart_b { + status = "disabled"; +}; + +&saradc { + status = "okay"; +}; + +/* demo for i2c user */ +&i2c3 { + status= "disabled"; + clock-frequency = <100000>; + /* pinctrl-names = "default";*/ + /* pinctrl-0 = <&i2c3_master_pins2>;*/ +}; + +&pinctrl_periphs { + bl_pwm_off_pins:bl_pwm_off_pin { + mux { + groups = "GPIOH_5"; + function = "gpio_periphs"; + output-high; + }; + }; +}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-t7-an400-lpddr4x.dtsi b/arch/arm/dts/meson-t7-an400-lpddr4x.dtsi new file mode 100644 index 0000000..8c45dc1 --- /dev/null +++ b/arch/arm/dts/meson-t7-an400-lpddr4x.dtsi
@@ -0,0 +1,308 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>. + * Based on meson-gx-p23x-q20x.dtsi: + * - Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * - Copyright (c) 2016 BayLibre, SAS. + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +/* Common DTSI for devices which are based on the P212 reference board. */ + +#include "meson-t7-txxx.dtsi" + +/ { + aliases { + serial0 = &uart_a; + serial1 = &uart_b; + spi0 = &spifc; + spi1 = &spicc0; + spi2 = &spicc1; + spi3 = &spicc2; + spi4 = &spicc3; + spi5 = &spicc4; + spi6 = &spicc5; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c_AO_A; + i2c7 = &i2c_AO_B; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + vddio_boot: regulator-vddio_boot { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vddio_ao18: regulator-vddio_ao18 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + /*reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;*/ + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; + + tee: tee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; +}; + +ðmac { + status = "okay"; + internal_phy = <1>; + mc_val = <0x4be04>; + /*mc_val = <0x1621>;*/ +}; + +&ir { + status = "disabled"; + /* pinctrl-0 = <&remote_input_ao_pins>; */ + /* pinctrl-names = "default"; */ +}; + +&saradc { + status = "disabled"; + vref-supply = <&vddio_ao18>; +}; + +/* Wireless SDIO Module */ +&sd_emmc_a { + status = "disabled"; + /*pinctrl-0 = <&sdio_pins>;*/ + /*pinctrl-names = "default";*/ + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + + non-removable; + disable-wp; + card_type = <3>; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_pins>; + pinctrl-1 = <&sdcard_pins &to_sduart_pins>; + pinctrl-names = "sd_all_pins", "sd_uart"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>; + cd-inverted; + + card_type = <5>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + sd_hs_co_phase = <2>; + sd_hs_to_phase = <0>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + max-frequency = <200000000>; + non-removable; + disable-wp; + /* mmc-ddr-1_8v; */ + card_type = <1>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + hs_co_phase = <2>; + hs_to_phase = <0>; + + hs2_co_phase = <2>; + hs2_to_phase = <0>; + + hw_reset = <&gpio GPIOB_12 GPIO_ACTIVE_HIGH>; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* nand */ +&nand { + status = "okay"; + pinctrl-names = "default", "nand_cs_only"; + pinctrl-0 = <&all_nand_pins>; + pinctrl-1 = <&nand_cs_pins>; +}; + +&crg { + status = "okay"; + dr_mode = "host"; +}; + +&crg2 { + status = "okay"; + dr_mode = "host"; +}; + +&usb2_phy_v2 { + status = "okay"; + portnum = <1>; +}; + +&usb3_phy_v2 { + status = "okay"; + portnum = <0>; + gpio-vbus-power = "GPIOM_8"; + gpios = <&gpio GPIOM_8 GPIO_ACTIVE_HIGH>; +}; + +&usb2_phy2_v2 { + status = "okay"; + portnum = <1>; +}; + +&usb3_phy2_v2 { + status = "okay"; + portnum = <0>; + gpio-vbus-power = "GPIOM_9"; + gpios = <&gpio GPIOM_9 GPIO_ACTIVE_HIGH>; +}; + +&pwm_ef { + status = "okay"; + /* pinctrl-0 = <&pwm_e_pins>; */ + /* pinctrl-names = "default"; */ +}; + +/* This is connected to the Bluetooth module: */ +&uart_b { + status = "okay"; + /* pinctrl-0 = <&a_uart_pins>; */ + /* pinctrl-names = "default"; */ + uart-has-rtscts; +}; + +&spifc { + status = "okay"; + cs-gpios = <&gpio GPIOB_12 GPIO_ACTIVE_HIGH>; + spi-flash@0 { + status = "okay"; + }; +}; + +&spicc0 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc0_pins>; + cs-gpios = <&gpio GPIOT_21 0>; +}; + +&spicc1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc1_pins_1>; + cs-gpios = <&gpio GPIOC_3 0>; +}; + +&spicc2 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc2_pins>; + cs-gpios = <&gpio GPIOY_3 0>; +}; + +&spicc3 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc3_pins>; + cs-gpios = <&gpio GPIOT_9 0>; + spi-flash@0 { + compatible = "spi-flash"; + reg = <0>; + spi-max-frequency = <16000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + status = "disabled"; + }; +}; + +&spicc4 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc4_pins>; + cs-gpios = <&gpio GPIOZ_3 0>; +}; + +&spicc5 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc5_pins>; + cs-gpios = <&gpio GPIOZ_7 0>; +};
diff --git a/arch/arm/dts/meson-t7-an400p-lpddr4x.dts b/arch/arm/dts/meson-t7-an400p-lpddr4x.dts new file mode 100644 index 0000000..708054c --- /dev/null +++ b/arch/arm/dts/meson-t7-an400p-lpddr4x.dts
@@ -0,0 +1,90 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "meson-t7-an400p-lpddr4x.dtsi" +#include "meson-t7_skt-panel.dtsi" + +/ { + compatible = "amlogic,t7-an400p-lpddr4x", "amlogic,t7-txxx", "amlogic,meson-t7"; + model = "Amlogic Meson T7 PXP Board"; +}; + +/* This UART is brought out to the DB9 connector */ +&uart_a { + status = "okay"; +}; + +&uart_b { + status = "disabled"; +}; + +&saradc { + status = "okay"; +}; + +/* demo for i2c user */ +&i2c3 { + status= "disabled"; + clock-frequency = <100000>; + /* pinctrl-names = "default";*/ + /* pinctrl-0 = <&i2c3_master_pins2>;*/ +}; + +&i2c_AO_A { + status= "okay"; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_ao_pins1>; +}; + +&pinctrl_periphs { + bl_pwm_off_pins:bl_pwm_off_pin { + mux { + groups = "GPIOH_5"; + function = "gpio_periphs"; + output-high; + }; + }; +}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-t7-an400p-lpddr4x.dtsi b/arch/arm/dts/meson-t7-an400p-lpddr4x.dtsi new file mode 100644 index 0000000..26abb32 --- /dev/null +++ b/arch/arm/dts/meson-t7-an400p-lpddr4x.dtsi
@@ -0,0 +1,312 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>. + * Based on meson-gx-p23x-q20x.dtsi: + * - Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * - Copyright (c) 2016 BayLibre, SAS. + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +/* Common DTSI for devices which are based on the P212 reference board. */ + +#include "meson-t7-txxx.dtsi" + +/ { + aliases { + serial0 = &uart_a; + serial1 = &uart_b; + spi0 = &spifc; + spi1 = &spicc0; + spi2 = &spicc1; + spi3 = &spicc2; + spi4 = &spicc3; + spi5 = &spicc4; + spi6 = &spicc5; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c_AO_A; + i2c7 = &i2c_AO_B; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + vddio_boot: regulator-vddio_boot { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vddio_ao18: regulator-vddio_ao18 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + /*reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;*/ + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; + + tee: tee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; +}; + +ðmac { + status = "okay"; + internal_phy = <1>; + mc_val = <0x4be04>; +/*exphy setting*/ +// pinctrl-names = "external_eth_rgmii_pins"; +// pinctrl-0 = <&external_eth_rgmii_pins>; +// internal_phy = <0>; +// mc_val = <0x1601>; +}; + +&ir { + status = "disabled"; + /* pinctrl-0 = <&remote_input_ao_pins>; */ + /* pinctrl-names = "default"; */ +}; + +&saradc { + status = "disabled"; + vref-supply = <&vddio_ao18>; +}; + +/* Wireless SDIO Module */ +&sd_emmc_a { + status = "disabled"; + /*pinctrl-0 = <&sdio_pins>;*/ + /*pinctrl-names = "default";*/ + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + + non-removable; + disable-wp; + card_type = <3>; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_pins>; + pinctrl-1 = <&sdcard_pins &to_sduart_pins>; + pinctrl-names = "sd_all_pins", "sd_uart"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>; + cd-inverted; + + card_type = <5>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + sd_hs_co_phase = <2>; + sd_hs_to_phase = <0>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + max-frequency = <200000000>; + non-removable; + disable-wp; + /* mmc-ddr-1_8v; */ + card_type = <1>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + hs_co_phase = <2>; + hs_to_phase = <0>; + + hs2_co_phase = <2>; + hs2_to_phase = <0>; + + hw_reset = <&gpio GPIOB_12 GPIO_ACTIVE_HIGH>; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* nand */ +&nand { + status = "okay"; + pinctrl-names = "default", "nand_cs_only"; + pinctrl-0 = <&all_nand_pins>; + pinctrl-1 = <&nand_cs_pins>; +}; + +&crg { + status = "okay"; + dr_mode = "host"; +}; + +&crg2 { + status = "okay"; + dr_mode = "host"; +}; + +&usb2_phy_v2 { + status = "okay"; + portnum = <1>; +}; + +&usb3_phy_v2 { + status = "okay"; + portnum = <0>; + gpio-vbus-power = "GPIOM_8"; + gpios = <&gpio GPIOM_8 GPIO_ACTIVE_HIGH>; +}; + +&usb2_phy2_v2 { + status = "okay"; + portnum = <1>; +}; + +&usb3_phy2_v2 { + status = "okay"; + portnum = <0>; + gpio-vbus-power = "GPIOM_9"; + gpios = <&gpio GPIOM_9 GPIO_ACTIVE_HIGH>; +}; + +&pwm_ef { + status = "okay"; + /* pinctrl-0 = <&pwm_e_pins>; */ + /* pinctrl-names = "default"; */ +}; + +/* This is connected to the Bluetooth module: */ +&uart_b { + status = "okay"; + /* pinctrl-0 = <&a_uart_pins>; */ + /* pinctrl-names = "default"; */ + uart-has-rtscts; +}; + +&spifc { + status = "okay"; + cs-gpios = <&gpio GPIOB_12 GPIO_ACTIVE_HIGH>; + spi-flash@0 { + status = "okay"; + }; +}; + +&spicc0 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc0_pins>; + cs-gpios = <&gpio GPIOT_21 0>; +}; + +&spicc1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc1_pins_1>; + cs-gpios = <&gpio GPIOC_3 0>; +}; + +&spicc2 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc2_pins>; + cs-gpios = <&gpio GPIOY_3 0>; +}; + +&spicc3 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc3_pins>; + cs-gpios = <&gpio GPIOT_9 0>; + spi-flash@0 { + compatible = "spi-flash"; + reg = <0>; + spi-max-frequency = <16000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + status = "disabled"; + }; +}; + +&spicc4 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc4_pins>; + cs-gpios = <&gpio GPIOZ_3 0>; +}; + +&spicc5 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc5_pins>; + cs-gpios = <&gpio GPIOZ_7 0>; +};
diff --git a/arch/arm/dts/meson-t7-an408-lpddr4x.dts b/arch/arm/dts/meson-t7-an408-lpddr4x.dts new file mode 100644 index 0000000..2bc36d3 --- /dev/null +++ b/arch/arm/dts/meson-t7-an408-lpddr4x.dts
@@ -0,0 +1,83 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "meson-t7-an408-lpddr4x.dtsi" +#include "meson-t7_skt-panel.dtsi" + +/ { + compatible = "amlogic,t7-an408-lpddr4x", "amlogic,t7-txxx", "amlogic,meson-t7"; + model = "Amlogic Meson T7 PXP Board"; +}; + +/* This UART is brought out to the DB9 connector */ +&uart_a { + status = "okay"; +}; + +&uart_b { + status = "disabled"; +}; + +&saradc { + status = "okay"; +}; + +/* demo for i2c user */ +&i2c3 { + status= "disabled"; + clock-frequency = <100000>; + /* pinctrl-names = "default";*/ + /* pinctrl-0 = <&i2c3_master_pins2>;*/ +}; + +&pinctrl_periphs { + bl_pwm_off_pins:bl_pwm_off_pin { + mux { + groups = "GPIOH_5"; + function = "gpio_periphs"; + output-high; + }; + }; +}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-t7-an408-lpddr4x.dtsi b/arch/arm/dts/meson-t7-an408-lpddr4x.dtsi new file mode 100644 index 0000000..8c45dc1 --- /dev/null +++ b/arch/arm/dts/meson-t7-an408-lpddr4x.dtsi
@@ -0,0 +1,308 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>. + * Based on meson-gx-p23x-q20x.dtsi: + * - Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * - Copyright (c) 2016 BayLibre, SAS. + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +/* Common DTSI for devices which are based on the P212 reference board. */ + +#include "meson-t7-txxx.dtsi" + +/ { + aliases { + serial0 = &uart_a; + serial1 = &uart_b; + spi0 = &spifc; + spi1 = &spicc0; + spi2 = &spicc1; + spi3 = &spicc2; + spi4 = &spicc3; + spi5 = &spicc4; + spi6 = &spicc5; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c_AO_A; + i2c7 = &i2c_AO_B; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + vddio_boot: regulator-vddio_boot { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vddio_ao18: regulator-vddio_ao18 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + /*reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;*/ + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; + + tee: tee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; +}; + +ðmac { + status = "okay"; + internal_phy = <1>; + mc_val = <0x4be04>; + /*mc_val = <0x1621>;*/ +}; + +&ir { + status = "disabled"; + /* pinctrl-0 = <&remote_input_ao_pins>; */ + /* pinctrl-names = "default"; */ +}; + +&saradc { + status = "disabled"; + vref-supply = <&vddio_ao18>; +}; + +/* Wireless SDIO Module */ +&sd_emmc_a { + status = "disabled"; + /*pinctrl-0 = <&sdio_pins>;*/ + /*pinctrl-names = "default";*/ + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + + non-removable; + disable-wp; + card_type = <3>; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_pins>; + pinctrl-1 = <&sdcard_pins &to_sduart_pins>; + pinctrl-names = "sd_all_pins", "sd_uart"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>; + cd-inverted; + + card_type = <5>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + sd_hs_co_phase = <2>; + sd_hs_to_phase = <0>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + max-frequency = <200000000>; + non-removable; + disable-wp; + /* mmc-ddr-1_8v; */ + card_type = <1>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + hs_co_phase = <2>; + hs_to_phase = <0>; + + hs2_co_phase = <2>; + hs2_to_phase = <0>; + + hw_reset = <&gpio GPIOB_12 GPIO_ACTIVE_HIGH>; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* nand */ +&nand { + status = "okay"; + pinctrl-names = "default", "nand_cs_only"; + pinctrl-0 = <&all_nand_pins>; + pinctrl-1 = <&nand_cs_pins>; +}; + +&crg { + status = "okay"; + dr_mode = "host"; +}; + +&crg2 { + status = "okay"; + dr_mode = "host"; +}; + +&usb2_phy_v2 { + status = "okay"; + portnum = <1>; +}; + +&usb3_phy_v2 { + status = "okay"; + portnum = <0>; + gpio-vbus-power = "GPIOM_8"; + gpios = <&gpio GPIOM_8 GPIO_ACTIVE_HIGH>; +}; + +&usb2_phy2_v2 { + status = "okay"; + portnum = <1>; +}; + +&usb3_phy2_v2 { + status = "okay"; + portnum = <0>; + gpio-vbus-power = "GPIOM_9"; + gpios = <&gpio GPIOM_9 GPIO_ACTIVE_HIGH>; +}; + +&pwm_ef { + status = "okay"; + /* pinctrl-0 = <&pwm_e_pins>; */ + /* pinctrl-names = "default"; */ +}; + +/* This is connected to the Bluetooth module: */ +&uart_b { + status = "okay"; + /* pinctrl-0 = <&a_uart_pins>; */ + /* pinctrl-names = "default"; */ + uart-has-rtscts; +}; + +&spifc { + status = "okay"; + cs-gpios = <&gpio GPIOB_12 GPIO_ACTIVE_HIGH>; + spi-flash@0 { + status = "okay"; + }; +}; + +&spicc0 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc0_pins>; + cs-gpios = <&gpio GPIOT_21 0>; +}; + +&spicc1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc1_pins_1>; + cs-gpios = <&gpio GPIOC_3 0>; +}; + +&spicc2 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc2_pins>; + cs-gpios = <&gpio GPIOY_3 0>; +}; + +&spicc3 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc3_pins>; + cs-gpios = <&gpio GPIOT_9 0>; + spi-flash@0 { + compatible = "spi-flash"; + reg = <0>; + spi-max-frequency = <16000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + status = "disabled"; + }; +}; + +&spicc4 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc4_pins>; + cs-gpios = <&gpio GPIOZ_3 0>; +}; + +&spicc5 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc5_pins>; + cs-gpios = <&gpio GPIOZ_7 0>; +};
diff --git a/arch/arm/dts/meson-t7-an409-ddr4.dts b/arch/arm/dts/meson-t7-an409-ddr4.dts new file mode 100644 index 0000000..1e3e0c8 --- /dev/null +++ b/arch/arm/dts/meson-t7-an409-ddr4.dts
@@ -0,0 +1,83 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "meson-t7-an409-ddr4.dtsi" +#include "meson-t7_skt-panel.dtsi" + +/ { + compatible = "amlogic,t7-an409-ddr4", "amlogic,t7-txxx", "amlogic,meson-t7"; + model = "Amlogic Meson T7 PXP Board"; +}; + +/* This UART is brought out to the DB9 connector */ +&uart_a { + status = "okay"; +}; + +&uart_b { + status = "disabled"; +}; + +&saradc { + status = "okay"; +}; + +/* demo for i2c user */ +&i2c3 { + status= "disabled"; + clock-frequency = <100000>; + /* pinctrl-names = "default";*/ + /* pinctrl-0 = <&i2c3_master_pins2>;*/ +}; + +&pinctrl_periphs { + bl_pwm_off_pins:bl_pwm_off_pin { + mux { + groups = "GPIOH_5"; + function = "gpio_periphs"; + output-high; + }; + }; +}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-t7-an409-ddr4.dtsi b/arch/arm/dts/meson-t7-an409-ddr4.dtsi new file mode 100644 index 0000000..8c45dc1 --- /dev/null +++ b/arch/arm/dts/meson-t7-an409-ddr4.dtsi
@@ -0,0 +1,308 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>. + * Based on meson-gx-p23x-q20x.dtsi: + * - Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * - Copyright (c) 2016 BayLibre, SAS. + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +/* Common DTSI for devices which are based on the P212 reference board. */ + +#include "meson-t7-txxx.dtsi" + +/ { + aliases { + serial0 = &uart_a; + serial1 = &uart_b; + spi0 = &spifc; + spi1 = &spicc0; + spi2 = &spicc1; + spi3 = &spicc2; + spi4 = &spicc3; + spi5 = &spicc4; + spi6 = &spicc5; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c_AO_A; + i2c7 = &i2c_AO_B; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + vddio_boot: regulator-vddio_boot { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vddio_ao18: regulator-vddio_ao18 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + /*reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;*/ + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; + + tee: tee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; +}; + +ðmac { + status = "okay"; + internal_phy = <1>; + mc_val = <0x4be04>; + /*mc_val = <0x1621>;*/ +}; + +&ir { + status = "disabled"; + /* pinctrl-0 = <&remote_input_ao_pins>; */ + /* pinctrl-names = "default"; */ +}; + +&saradc { + status = "disabled"; + vref-supply = <&vddio_ao18>; +}; + +/* Wireless SDIO Module */ +&sd_emmc_a { + status = "disabled"; + /*pinctrl-0 = <&sdio_pins>;*/ + /*pinctrl-names = "default";*/ + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + + non-removable; + disable-wp; + card_type = <3>; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_pins>; + pinctrl-1 = <&sdcard_pins &to_sduart_pins>; + pinctrl-names = "sd_all_pins", "sd_uart"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>; + cd-inverted; + + card_type = <5>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + sd_hs_co_phase = <2>; + sd_hs_to_phase = <0>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + max-frequency = <200000000>; + non-removable; + disable-wp; + /* mmc-ddr-1_8v; */ + card_type = <1>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + hs_co_phase = <2>; + hs_to_phase = <0>; + + hs2_co_phase = <2>; + hs2_to_phase = <0>; + + hw_reset = <&gpio GPIOB_12 GPIO_ACTIVE_HIGH>; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* nand */ +&nand { + status = "okay"; + pinctrl-names = "default", "nand_cs_only"; + pinctrl-0 = <&all_nand_pins>; + pinctrl-1 = <&nand_cs_pins>; +}; + +&crg { + status = "okay"; + dr_mode = "host"; +}; + +&crg2 { + status = "okay"; + dr_mode = "host"; +}; + +&usb2_phy_v2 { + status = "okay"; + portnum = <1>; +}; + +&usb3_phy_v2 { + status = "okay"; + portnum = <0>; + gpio-vbus-power = "GPIOM_8"; + gpios = <&gpio GPIOM_8 GPIO_ACTIVE_HIGH>; +}; + +&usb2_phy2_v2 { + status = "okay"; + portnum = <1>; +}; + +&usb3_phy2_v2 { + status = "okay"; + portnum = <0>; + gpio-vbus-power = "GPIOM_9"; + gpios = <&gpio GPIOM_9 GPIO_ACTIVE_HIGH>; +}; + +&pwm_ef { + status = "okay"; + /* pinctrl-0 = <&pwm_e_pins>; */ + /* pinctrl-names = "default"; */ +}; + +/* This is connected to the Bluetooth module: */ +&uart_b { + status = "okay"; + /* pinctrl-0 = <&a_uart_pins>; */ + /* pinctrl-names = "default"; */ + uart-has-rtscts; +}; + +&spifc { + status = "okay"; + cs-gpios = <&gpio GPIOB_12 GPIO_ACTIVE_HIGH>; + spi-flash@0 { + status = "okay"; + }; +}; + +&spicc0 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc0_pins>; + cs-gpios = <&gpio GPIOT_21 0>; +}; + +&spicc1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc1_pins_1>; + cs-gpios = <&gpio GPIOC_3 0>; +}; + +&spicc2 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc2_pins>; + cs-gpios = <&gpio GPIOY_3 0>; +}; + +&spicc3 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc3_pins>; + cs-gpios = <&gpio GPIOT_9 0>; + spi-flash@0 { + compatible = "spi-flash"; + reg = <0>; + spi-max-frequency = <16000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + status = "disabled"; + }; +}; + +&spicc4 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc4_pins>; + cs-gpios = <&gpio GPIOZ_3 0>; +}; + +&spicc5 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc5_pins>; + cs-gpios = <&gpio GPIOZ_7 0>; +};
diff --git a/arch/arm/dts/meson-t7-an40a1.dts b/arch/arm/dts/meson-t7-an40a1.dts new file mode 100644 index 0000000..909ccf9 --- /dev/null +++ b/arch/arm/dts/meson-t7-an40a1.dts
@@ -0,0 +1,90 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "meson-t7-an40a1.dtsi" +#include "meson-t7_skt-panel.dtsi" + +/ { + compatible = "amlogic,t7-an40a1", "amlogic,t7-txxx", "amlogic,meson-t7"; + model = "Amlogic Meson T7 PXP Board"; +}; + +/* This UART is brought out to the DB9 connector */ +&uart_a { + status = "okay"; +}; + +&uart_b { + status = "disabled"; +}; + +&saradc { + status = "okay"; +}; + +/* demo for i2c user */ +&i2c3 { + status= "disabled"; + clock-frequency = <100000>; + /* pinctrl-names = "default";*/ + /* pinctrl-0 = <&i2c3_master_pins2>;*/ +}; + +&i2c_AO_A { + status= "okay"; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_ao_pins1>; +}; + +&pinctrl_periphs { + bl_pwm_off_pins:bl_pwm_off_pin { + mux { + groups = "GPIOH_5"; + function = "gpio_periphs"; + output-high; + }; + }; +}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-t7-an40a1.dtsi b/arch/arm/dts/meson-t7-an40a1.dtsi new file mode 100644 index 0000000..3fb3cb1 --- /dev/null +++ b/arch/arm/dts/meson-t7-an40a1.dtsi
@@ -0,0 +1,308 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>. + * Based on meson-gx-p23x-q20x.dtsi: + * - Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * - Copyright (c) 2016 BayLibre, SAS. + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +/* Common DTSI for devices which are based on the P212 reference board. */ + +#include "meson-t7-txxx.dtsi" + +/ { + aliases { + serial0 = &uart_a; + serial1 = &uart_b; + spi0 = &spifc; + spi1 = &spicc0; + spi2 = &spicc1; + spi3 = &spicc2; + spi4 = &spicc3; + spi5 = &spicc4; + spi6 = &spicc5; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c_AO_A; + i2c7 = &i2c_AO_B; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + vddio_boot: regulator-vddio_boot { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vddio_ao18: regulator-vddio_ao18 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + /*reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;*/ + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; + + tee: tee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; +}; + +ðmac { + status = "okay"; + internal_phy = <1>; + mc_val = <0x4be04>; + /*mc_val = <0x1621>;*/ +}; + +&ir { + status = "disabled"; + /* pinctrl-0 = <&remote_input_ao_pins>; */ + /* pinctrl-names = "default"; */ +}; + +&saradc { + status = "disabled"; + vref-supply = <&vddio_ao18>; +}; + +/* Wireless SDIO Module */ +&sd_emmc_a { + status = "disabled"; + /*pinctrl-0 = <&sdio_pins>;*/ + /*pinctrl-names = "default";*/ + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + + non-removable; + disable-wp; + card_type = <3>; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_pins>; + pinctrl-1 = <&sdcard_pins &to_sduart_pins>; + pinctrl-names = "sd_all_pins", "sd_uart"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>; + cd-inverted; + + card_type = <5>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + sd_hs_co_phase = <2>; + sd_hs_to_phase = <0>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + max-frequency = <200000000>; + non-removable; + disable-wp; + /* mmc-ddr-1_8v; */ + card_type = <1>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + hs_co_phase = <2>; + hs_to_phase = <0>; + + hs2_co_phase = <2>; + hs2_to_phase = <0>; + + hw_reset = <&gpio GPIOB_12 GPIO_ACTIVE_HIGH>; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* nand */ +&nand { + status = "okay"; + pinctrl-names = "default", "nand_cs_only"; + pinctrl-0 = <&all_nand_pins>; + pinctrl-1 = <&nand_cs_pins>; +}; + +&crg { + status = "okay"; + dr_mode = "host"; +}; + +&crg2 { + status = "okay"; + dr_mode = "host"; +}; + +&usb2_phy_v2 { + status = "okay"; + portnum = <1>; +}; + +&usb3_phy_v2 { + status = "okay"; + portnum = <0>; + gpio-vbus-power = "GPIOM_8"; + gpios = <&gpio GPIOM_8 GPIO_ACTIVE_HIGH>; +}; + +&usb2_phy2_v2 { + status = "okay"; + portnum = <1>; +}; + +&usb3_phy2_v2 { + status = "okay"; + portnum = <0>; + gpio-vbus-power = "GPIOM_9"; + gpios = <&gpio GPIOM_9 GPIO_ACTIVE_HIGH>; +}; + +&pwm_ef { + status = "okay"; + /* pinctrl-0 = <&pwm_e_pins>; */ + /* pinctrl-names = "default"; */ +}; + +/* This is connected to the Bluetooth module: */ +&uart_b { + status = "okay"; + /* pinctrl-0 = <&a_uart_pins>; */ + /* pinctrl-names = "default"; */ + uart-has-rtscts; +}; + +&spifc { + status = "disabled"; + //cs-gpios = <&gpio GPIOB_14 GPIO_ACTIVE_HIGH>; + spi-flash@0 { + status = "disabled"; + }; +}; + +&spicc0 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc0_pins>; + cs-gpios = <&gpio GPIOT_21 0>; +}; + +&spicc1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc1_pins_1>; + cs-gpios = <&gpio GPIOC_3 0>; +}; + +&spicc2 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc2_pins>; + cs-gpios = <&gpio GPIOY_3 0>; +}; + +&spicc3 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc3_pins>; + cs-gpios = <&gpio GPIOT_9 0>; + spi-flash@0 { + compatible = "spi-flash"; + reg = <0>; + spi-max-frequency = <16000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + status = "disabled"; + }; +}; + +&spicc4 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc4_pins>; + cs-gpios = <&gpio GPIOZ_3 0>; +}; + +&spicc5 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc5_pins>; + cs-gpios = <&gpio GPIOZ_7 0>; +};
diff --git a/arch/arm/dts/meson-t7-mali.dtsi b/arch/arm/dts/meson-t7-mali.dtsi new file mode 100644 index 0000000..2655b42 --- /dev/null +++ b/arch/arm/dts/meson-t7-mali.dtsi
@@ -0,0 +1,43 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 BayLibre SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +&apb { + mali: gpu@40000 { + compatible = "amlogic,meson-gxbb-mali", "arm,mali-450"; + reg = <0x0 0x40000 0x0 0x40000>; + interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "gp", "gpmmu", "pp", "pmu", + "pp0", "ppmmu0", "pp1", "ppmmu1", + "pp2", "ppmmu2"; + /*clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;*/ + clock-names = "bus", "core"; + + /* + * Mali clocking is provided by two identical clock paths + * MALI_0 and MALI_1 muxed to a single clock by a glitch + * free mux to safely change frequency while running. + */ + /* + assigned-clocks = <&clkc CLKID_MALI_0_SEL>, + <&clkc CLKID_MALI_0>, + <&clkc CLKID_MALI>; *//* Glitch free mux */ + /*assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, + <0>, *//* Do Nothing */ + //<&clkc CLKID_MALI_0>; + /*assigned-clock-rates = <0>,*/ /* Do Nothing */ + /* <666666666>, + <0>;*/ /* Do Nothing */ + }; +};
diff --git a/arch/arm/dts/meson-t7-pxp.dts b/arch/arm/dts/meson-t7-pxp.dts new file mode 100644 index 0000000..35b7ec0 --- /dev/null +++ b/arch/arm/dts/meson-t7-pxp.dts
@@ -0,0 +1,83 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "meson-t7-pxp.dtsi" +#include "meson-t7_skt-panel.dtsi" + +/ { + compatible = "amlogic,t7-pxp", "amlogic,t7-txxx", "amlogic,meson-t7"; + model = "Amlogic Meson T7 PXP Board"; +}; + +/* This UART is brought out to the DB9 connector */ +&uart_a { + status = "okay"; +}; + +&uart_b { + status = "disabled"; +}; + +&saradc { + status = "disabled"; +}; + +/* demo for i2c user */ +&i2c3 { + status= "disabled"; + clock-frequency = <100000>; + /* pinctrl-names = "default";*/ + /* pinctrl-0 = <&i2c3_master_pins2>;*/ +}; + +&pinctrl_periphs { + bl_pwm_off_pins:bl_pwm_off_pin { + mux { + groups = "GPIOH_5"; + function = "gpio_periphs"; + output-high; + }; + }; +}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-t7-pxp.dtsi b/arch/arm/dts/meson-t7-pxp.dtsi new file mode 100644 index 0000000..a1142bd --- /dev/null +++ b/arch/arm/dts/meson-t7-pxp.dtsi
@@ -0,0 +1,303 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>. + * Based on meson-gx-p23x-q20x.dtsi: + * - Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * - Copyright (c) 2016 BayLibre, SAS. + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +/* Common DTSI for devices which are based on the P212 reference board. */ + +#include "meson-t7-txxx.dtsi" + +/ { + aliases { + serial0 = &uart_a; + serial1 = &uart_b; + spi0 = &spifc; + spi1 = &spicc0; + spi2 = &spicc1; + spi3 = &spicc2; + spi4 = &spicc3; + spi5 = &spicc4; + spi6 = &spicc5; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c_AO_A; + i2c7 = &i2c_AO_B; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + vddio_boot: regulator-vddio_boot { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vddio_ao18: regulator-vddio_ao18 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + /*reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;*/ + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; +}; + +ðmac { + status = "okay"; + internal_phy = <1>; + mc_val = <0x4be04>; + /*mc_val = <0x1621>;*/ +}; + +&ir { + status = "disabled"; + /* pinctrl-0 = <&remote_input_ao_pins>; */ + /* pinctrl-names = "default"; */ +}; + +&saradc { + status = "disabled"; + vref-supply = <&vddio_ao18>; +}; + +/* Wireless SDIO Module */ +&sd_emmc_a { + status = "disabled"; + /*pinctrl-0 = <&sdio_pins>;*/ + /*pinctrl-names = "default";*/ + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + + non-removable; + disable-wp; + card_type = <3>; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_pins>; + pinctrl-1 = <&sdcard_pins &to_sduart_pins>; + pinctrl-names = "sd_all_pins", "sd_uart"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>; + cd-inverted; + + card_type = <5>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + sd_hs_co_phase = <2>; + sd_hs_to_phase = <0>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + cap-mmc-highspeed; +// mmc-hs200-1_8v; + max-frequency = <200000000>; + non-removable; + disable-wp; + /* mmc-ddr-1_8v; */ + card_type = <1>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + hs_co_phase = <2>; + hs_to_phase = <0>; + + hs2_co_phase = <2>; + hs2_to_phase = <0>; + + hw_reset = <&gpio GPIOB_9 GPIO_ACTIVE_HIGH>; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* nand */ +&nand { + status = "okay"; + pinctrl-names = "default", "nand_cs_only"; + pinctrl-0 = <&all_nand_pins>; + pinctrl-1 = <&nand_cs_pins>; +}; + +&crg { + status = "okay"; + dr_mode = "host"; +}; + +&crg2 { + status = "okay"; + dr_mode = "host"; +}; + +&usb2_phy_v2 { + status = "okay"; + portnum = <1>; +}; + +&usb3_phy_v2 { + status = "okay"; + portnum = <0>; + gpio-vbus-power = "GPIOM_8"; + gpios = <&gpio GPIOM_8 GPIO_ACTIVE_HIGH>; +}; + +&usb2_phy2_v2 { + status = "okay"; + portnum = <1>; +}; + +&usb3_phy2_v2 { + status = "okay"; + portnum = <0>; + gpio-vbus-power = "GPIOM_9"; + gpios = <&gpio GPIOM_9 GPIO_ACTIVE_HIGH>; +}; + +&pwm_ef { + status = "okay"; + /* pinctrl-0 = <&pwm_e_pins>; */ + /* pinctrl-names = "default"; */ +}; + +/* This is connected to the Bluetooth module: */ +&uart_b { + status = "okay"; + /* pinctrl-0 = <&a_uart_pins>; */ + /* pinctrl-names = "default"; */ + uart-has-rtscts; +}; + +&spifc { + status = "disabled"; + //cs-gpios = <&gpio GPIOB_14 GPIO_ACTIVE_HIGH>; + spi-flash@0 { + status = "disabled"; + }; +}; + +&spicc0 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc0_pins>; + cs-gpios = <&gpio GPIOT_21 0>; +}; + +&spicc1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc1_pins_1>; + cs-gpios = <&gpio GPIOC_3 0>; +}; + +&spicc2 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc2_pins>; + cs-gpios = <&gpio GPIOY_3 0>; +}; + +&spicc3 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc3_pins>; + cs-gpios = <&gpio GPIOT_9 0>; + spi-flash@0 { + compatible = "spi-flash"; + reg = <0>; + spi-max-frequency = <16000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + status = "disabled"; + }; +}; + +&spicc4 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc4_pins>; + cs-gpios = <&gpio GPIOZ_3 0>; +}; + +&spicc5 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc5_pins>; + cs-gpios = <&gpio GPIOZ_7 0>; +};
diff --git a/arch/arm/dts/meson-t7-series.dtsi b/arch/arm/dts/meson-t7-series.dtsi new file mode 100644 index 0000000..c63a2ed --- /dev/null +++ b/arch/arm/dts/meson-t7-series.dtsi
@@ -0,0 +1,601 @@ +/* + * Copyright (c) 2016 Andreas Färber + * + * Copyright (c) 2016 BayLibre, SAS. + * Author: Neil Armstrong <narmstrong@baylibre.com> + * + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/pwm/pwm.h> +#include <dt-bindings/pwm/meson.h> +#include <dt-bindings/clock/t7-clkc.h> + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* 16 MiB reserved for Hardware ROM Firmware */ + hwrom_reserved: hwrom@0 { + reg = <0x0 0x0 0x0 0x1000000>; + no-map; + }; + + /* 2 MiB reserved for ARM Trusted Firmware (BL31) */ + secmon_reserved: secmon@10000000 { + reg = <0x0 0x10000000 0x0 0x200000>; + no-map; + }; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0xbc00000>; + alignment = <0x0 0x400000>; + linux,cma-default; + }; + }; + + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&l2>; + clocks = <&scpi_dvfs 0>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + next-level-cache = <&l2>; + clocks = <&scpi_dvfs 0>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x2>; + enable-method = "psci"; + next-level-cache = <&l2>; + clocks = <&scpi_dvfs 0>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x3>; + enable-method = "psci"; + next-level-cache = <&l2>; + clocks = <&scpi_dvfs 0>; + }; + + l2: l2-cache0 { + compatible = "cache"; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; + }; + + xtal: xtal-clk { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xtal"; + #clock-cells = <0>; + }; + + firmware { + sm: secure-monitor { + compatible = "amlogic,meson-gx-sm", "amlogic,meson-gxbb-sm"; + }; + }; + + efuse: efuse { + compatible = "amlogic,meson-sc2-efuse", "amlogic,meson-sc2-efuse"; + #address-cells = <1>; + #size-cells = <1>; + + }; + + scpi { + compatible = "amlogic,meson-gxbb-scpi", "arm,scpi-pre-1.0"; + mboxes = <&mailbox 1 &mailbox 2>; + shmem = <&cpu_scp_lpri &cpu_scp_hpri>; + + scpi_clocks: clocks { + compatible = "arm,scpi-clocks"; + + scpi_dvfs: scpi_clocks@0 { + compatible = "arm,scpi-dvfs-clocks"; + #clock-cells = <1>; + clock-indices = <0>; + clock-output-names = "vcpu"; + }; + }; + + scpi_sensors: sensors { + compatible = "amlogic,meson-gxbb-scpi-sensors", "arm,scpi-sensors"; + #thermal-sensor-cells = <1>; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic: interrupt-controller@2c001000 { + compatible = "arm,gic-400"; + reg = <0x0 0xffc01000 0 0x1000>, + <0x0 0xffc02000 0 0x2000>, + <0x0 0xffc04000 0 0x2000>, + <0x0 0xffc06000 0 0x2000>; + interrupt-controller; + interrupts = <GIC_PPI 9 + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; + #interrupt-cells = <3>; + #address-cells = <0>; + }; + + sram: sram@f7000000 { + compatible = "amlogic,meson-sc2-sram", "amlogic,meson-sc2-sram", "mmio-sram"; + reg = <0x0 0xf7000000 0x0 0x48000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0xf7000000 0x48000>; + + cpu_scp_lpri: scp-shmem@0 { + compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem"; + reg = <0x47000 0x400>; + }; + + cpu_scp_hpri: scp-shmem@200 { + compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem"; + reg = <0x47400 0x400>; + }; + }; + + cbus: cbus@fe070000 { + compatible = "simple-bus"; + reg = <0x0 0xfe070000 0x0 0xF000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xfe070000 0x0 0xF000>; + + uart_a: serial@8000 { + compatible = "amlogic,meson-uart"; + reg = <0x0 0x8000 0x0 0x18>; + clocks = <&xtal>; + status = "disabled"; + }; + + uart_b: serial@a000 { + compatible = "amlogic,meson-uart"; + reg = <0x0 0xa000 0x0 0x18>; + clocks = <&xtal>; + status = "disabled"; + }; + + ir: ir@8040 { + compatible = "amlogic,meson-gx-ir", "amlogic,meson-gxbb-ir"; + reg = <0x0 0x8040 0x0 0x40>; + interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + }; + + reset: reset-controller@1000 { + compatible = "amlogic,meson-gx-reset", "amlogic,meson-gxbb-reset"; + reg = <0x0 0x01000 0x0 0x1000>; + #reset-cells = <1>; + }; + + uart_c: serial@22000 { + compatible = "amlogic,meson-uart"; + reg = <0x0 0x22000 0x0 0x18>; + interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>; + clocks = <&xtal>; + status = "disabled"; + }; + + jtag { + compatible = "amlogic, jtag"; + status = "okay"; + select = "disable"; /* disable/jtag-a/jtag-b */ + pinctrl-names="jtag_a_pins", "jtag_b_pins"; + pinctrl-0=<&jtag_a_pins>; + pinctrl-1=<&jtag_b_pins>; + }; + }; + + periphs: periphs@ff634000 { + compatible = "simple-bus"; + reg = <0x0 0xff634000 0x0 0x2000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>; + + hwrng: rng { + compatible = "amlogic,meson-rng"; + reg = <0x0 0x0 0x0 0x4>; + }; + }; + + hiubus: hiubus@ff63c000 { + compatible = "simple-bus"; + reg = <0x0 0xff63c000 0x0 0x2000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x2000>; + + mailbox: mailbox@404 { + compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu"; + reg = <0 0x404 0 0x4c>; + interrupts = <0 208 IRQ_TYPE_EDGE_RISING>, + <0 209 IRQ_TYPE_EDGE_RISING>, + <0 210 IRQ_TYPE_EDGE_RISING>; + #mbox-cells = <1>; + }; + }; + + clkc: clock-controller@0 { + compatible = "amlogic,t7-clkc"; + #clock-cells = <1>; + reg = <0x0 0xfe000000 0x0 0x82e8>; + clocks = <&xtal>; + clock-names = "xtal"; + }; + + i2c0: i2c@fe001400 { + compatible = "amlogic,meson-i2c"; + reg = <0x0 0xfe066000 0x0 0x24>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@fe005c00 { + compatible = "amlogic,meson-i2c"; + reg = <0x0 0xfe068000 0x0 0x24>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@fe006800 { + compatible = "amlogic,meson-i2c"; + reg = <0x0 0xfe06a000 0x0 0x24>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@fe006c00 { + compatible = "amlogic,meson-i2c"; + reg = <0x0 0xfe06c000 0x0 0x24>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@fe06e000 { + compatible = "amlogic,meson-i2c"; + reg = <0x0 0xfe06e000 0x0 0x24>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@fe070000 { + compatible = "amlogic,meson-i2c"; + reg = <0x0 0xfe070000 0x0 0x24>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c_AO_A: i2c@fe076000 { + compatible = "amlogic,meson-i2c"; + reg = <0x0 0xfe076000 0x0 0x24>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c_AO_B: i2c@fe086000 { + compatible = "amlogic,meson-i2c"; + reg = <0x0 0xfe086000 0x0 0x24>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spifc: spi@fe056000 { + compatible = "amlogic,spifc"; + status = "disabled"; + reg = <0x0 0xfe056000 0x0 0x80>; + /* clocks = <&clkc CLKID_CLK81>; */ + /* clock-names = "core"; */ + pinctrl-names = "default"; + pinctrl-0 = <&spifc_pins>; + #address-cells = <1>; + #size-cells = <0>; + spi-flash@0 { + compatible = "spi-flash"; + reg = <0>; + spi-max-frequency = <20000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + status = "disabled"; + }; + spi-nand@1 { + compatible = "spi-nand"; + reg = <1>; + spi-max-frequency = <20000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + status = "disabled"; + }; + }; + + ethmac: ethernet@fdc00000 { + compatible = "amlogic,g12a-eth-dwmac"; + phy_cntl1 = <0x41054147>; + pll_val = <0x9c0040a 0x927e0000 0xac5f49e5>; + analog_val = <0x20200000 0x0000c000 0x00000023>; + status = "disabled"; + }; + + saradc: adc@fe026000 { + compatible = "amlogic,meson-saradc"; + reg = <0x0 0xfe026000 0x0 0x48>; + status = "disabled"; + }; + + nand: nfc@fe08c800 { + compatible = "amlogic,meson-nfc"; + reg = <0x0 0xfe08c800 0x0 0x200>; + interrupts = <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + clk_reg = <0 0xfe08c000>; + }; + + apb: apb@fe000000 { + compatible = "simple-bus"; + reg = <0x0 0xfe000000 0x0 0x1000000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x1000000>; + + watchdog@2100 { + compatible = "amlogic,meson-sc2-wdt"; + reg = <0x0 0x2100 0x0 0x10>; + clocks = <&xtal>; + clock-names = "wdt-clk"; + }; + + sd_emmc_a: sdio { + compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; + reg = <0x0 0x88000 0x0 0x800>; + interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + pinname = "sdio"; + }; + + sd_emmc_b: sd { + compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; + reg = <0x0 0x8a000 0x0 0x800>; + interrupts = <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + pinname = "sd"; + }; + + sd_emmc_c: emmc { + compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; + reg = <0x0 0x8c000 0x0 0x800>; + interrupts = <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + pinname = "emmc"; + source-clock = <1152000000>; + }; + + spicc0: spi@50000 { + compatible = "amlogic,meson-g12a-spicc"; + reg = <0x0 0x50000 0x0 0x44>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spicc1: spi@52000 { + compatible = "amlogic,meson-g12a-spicc"; + reg = <0x0 0x52000 0x0 0x44>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spicc2: spi@54000 { + compatible = "amlogic,meson-g12a-spicc"; + reg = <0x0 0x54000 0x0 0x44>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spicc3: spi@4a000 { + compatible = "amlogic,meson-g12a-spicc"; + reg = <0x0 0x4a000 0x0 0x44>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spicc4: spi@4c000 { + compatible = "amlogic,meson-g12a-spicc"; + reg = <0x0 0x4c000 0x0 0x44>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spicc5: spi@4e000 { + compatible = "amlogic,meson-g12a-spicc"; + reg = <0x0 0x4e000 0x0 0x44>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + crg: crg@fdd00000 { + compatible = "crg-xhci"; + status = "disable"; + reg = <0x0 0xfdd00000 0x0 0x100000>; + phys = <&usb2_phy_v2>, <&usb3_phy_v2>; + phy-names = "usb2-phy", "usb3-phy"; + }; + + crg2: crg@fde00000 { + compatible = "crg-xhci"; + status = "disable"; + reg = <0x0 0xfde00000 0x0 0x100000>; + phys = <&usb2_phy2_v2>, <&usb3_phy2_v2>; + phy-names = "usb2-phy", "usb3-phy"; + }; + + usb2_phy_v2: usb2phy@fe03a000 { + compatible = "amlogic, amlogic-new-usb2-v2"; + status = "disable"; + #address-cells = <2>; + #size-cells = <2>; + phy-version = <2>; + reg = <0x0 0xfe03a000 0x0 0x80 + 0x0 0xFE002000 0x0 0x100 + 0x0 0xfe03e000 0x0 0x2000>; + dwc2_a_reg = <0xfdd00000>; + #phy-cells = <0>; + }; + + usb3_phy_v2: usb3phy@fe03a080 { + compatible = "amlogic, amlogic-new-usb3-v2"; + status = "disable"; + #address-cells = <2>; + #size-cells = <2>; + phy-version = <3>; + reg = <0x0 0xfe03a080 0x0 0x20>; + phy-reg = <0xfe03c000>; + phy-reg-size = <0x2000>; + usb2-phy-reg = <0xfe03a000>; + usb2-phy-reg-size = <0x80>; + #phy-cells = <0>; + }; + + usb2_phy2_v2: usb2phy2@fe03a000 { + compatible = "amlogic, amlogic-new-usb2-v2"; + status = "disable"; + #address-cells = <2>; + #size-cells = <2>; + phy-version = <2>; + reg = <0x0 0xfe03a000 0x0 0x80 + 0x0 0xFE002000 0x0 0x100 + 0x0 0xfe03c000 0x0 0x2000>; + dwc2_a_reg = <0xfdd00000>; + #phy-cells = <0>; + }; + + usb3_phy2_v2: usb3phy2@fe03a080 { + compatible = "amlogic, amlogic-new-usb3-v2"; + status = "disable"; + #address-cells = <2>; + #size-cells = <2>; + phy-version = <3>; + reg = <0x0 0xfe03a080 0x0 0x20>; + phy-reg = <0xfe03c000>; + phy-reg-size = <0x2000>; + usb2-phy-reg = <0xfe03a000>; + usb2-phy-reg-size = <0x80>; + #phy-cells = <0>; + }; + + }; +};
diff --git a/arch/arm/dts/meson-t7-t319.dts b/arch/arm/dts/meson-t7-t319.dts new file mode 100644 index 0000000..38b4e14 --- /dev/null +++ b/arch/arm/dts/meson-t7-t319.dts
@@ -0,0 +1,90 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "meson-t7-t319.dtsi" +#include "meson-t7_skt-panel.dtsi" + +/ { + compatible = "amlogic,t7-t319", "amlogic,t7-txxx", "amlogic,meson-t7"; + model = "Amlogic Meson T7 PXP Board"; +}; + +/* This UART is brought out to the DB9 connector */ +&uart_a { + status = "okay"; +}; + +&uart_b { + status = "disabled"; +}; + +&saradc { + status = "okay"; +}; + +/* demo for i2c user */ +&i2c3 { + status= "disabled"; + clock-frequency = <100000>; + /* pinctrl-names = "default";*/ + /* pinctrl-0 = <&i2c3_master_pins2>;*/ +}; + +&i2c_AO_A { + status= "okay"; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_ao_pins1>; +}; + +&pinctrl_periphs { + bl_pwm_off_pins:bl_pwm_off_pin { + mux { + groups = "GPIOH_5"; + function = "gpio_periphs"; + output-high; + }; + }; +}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-t7-t319.dtsi b/arch/arm/dts/meson-t7-t319.dtsi new file mode 100644 index 0000000..8c45dc1 --- /dev/null +++ b/arch/arm/dts/meson-t7-t319.dtsi
@@ -0,0 +1,308 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>. + * Based on meson-gx-p23x-q20x.dtsi: + * - Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * - Copyright (c) 2016 BayLibre, SAS. + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +/* Common DTSI for devices which are based on the P212 reference board. */ + +#include "meson-t7-txxx.dtsi" + +/ { + aliases { + serial0 = &uart_a; + serial1 = &uart_b; + spi0 = &spifc; + spi1 = &spicc0; + spi2 = &spicc1; + spi3 = &spicc2; + spi4 = &spicc3; + spi5 = &spicc4; + spi6 = &spicc5; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c_AO_A; + i2c7 = &i2c_AO_B; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + vddio_boot: regulator-vddio_boot { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vddio_ao18: regulator-vddio_ao18 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + /*reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;*/ + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; + + tee: tee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; +}; + +ðmac { + status = "okay"; + internal_phy = <1>; + mc_val = <0x4be04>; + /*mc_val = <0x1621>;*/ +}; + +&ir { + status = "disabled"; + /* pinctrl-0 = <&remote_input_ao_pins>; */ + /* pinctrl-names = "default"; */ +}; + +&saradc { + status = "disabled"; + vref-supply = <&vddio_ao18>; +}; + +/* Wireless SDIO Module */ +&sd_emmc_a { + status = "disabled"; + /*pinctrl-0 = <&sdio_pins>;*/ + /*pinctrl-names = "default";*/ + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + + non-removable; + disable-wp; + card_type = <3>; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_pins>; + pinctrl-1 = <&sdcard_pins &to_sduart_pins>; + pinctrl-names = "sd_all_pins", "sd_uart"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>; + cd-inverted; + + card_type = <5>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + sd_hs_co_phase = <2>; + sd_hs_to_phase = <0>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + max-frequency = <200000000>; + non-removable; + disable-wp; + /* mmc-ddr-1_8v; */ + card_type = <1>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + hs_co_phase = <2>; + hs_to_phase = <0>; + + hs2_co_phase = <2>; + hs2_to_phase = <0>; + + hw_reset = <&gpio GPIOB_12 GPIO_ACTIVE_HIGH>; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* nand */ +&nand { + status = "okay"; + pinctrl-names = "default", "nand_cs_only"; + pinctrl-0 = <&all_nand_pins>; + pinctrl-1 = <&nand_cs_pins>; +}; + +&crg { + status = "okay"; + dr_mode = "host"; +}; + +&crg2 { + status = "okay"; + dr_mode = "host"; +}; + +&usb2_phy_v2 { + status = "okay"; + portnum = <1>; +}; + +&usb3_phy_v2 { + status = "okay"; + portnum = <0>; + gpio-vbus-power = "GPIOM_8"; + gpios = <&gpio GPIOM_8 GPIO_ACTIVE_HIGH>; +}; + +&usb2_phy2_v2 { + status = "okay"; + portnum = <1>; +}; + +&usb3_phy2_v2 { + status = "okay"; + portnum = <0>; + gpio-vbus-power = "GPIOM_9"; + gpios = <&gpio GPIOM_9 GPIO_ACTIVE_HIGH>; +}; + +&pwm_ef { + status = "okay"; + /* pinctrl-0 = <&pwm_e_pins>; */ + /* pinctrl-names = "default"; */ +}; + +/* This is connected to the Bluetooth module: */ +&uart_b { + status = "okay"; + /* pinctrl-0 = <&a_uart_pins>; */ + /* pinctrl-names = "default"; */ + uart-has-rtscts; +}; + +&spifc { + status = "okay"; + cs-gpios = <&gpio GPIOB_12 GPIO_ACTIVE_HIGH>; + spi-flash@0 { + status = "okay"; + }; +}; + +&spicc0 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc0_pins>; + cs-gpios = <&gpio GPIOT_21 0>; +}; + +&spicc1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc1_pins_1>; + cs-gpios = <&gpio GPIOC_3 0>; +}; + +&spicc2 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc2_pins>; + cs-gpios = <&gpio GPIOY_3 0>; +}; + +&spicc3 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc3_pins>; + cs-gpios = <&gpio GPIOT_9 0>; + spi-flash@0 { + compatible = "spi-flash"; + reg = <0>; + spi-max-frequency = <16000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + status = "disabled"; + }; +}; + +&spicc4 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc4_pins>; + cs-gpios = <&gpio GPIOZ_3 0>; +}; + +&spicc5 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc5_pins>; + cs-gpios = <&gpio GPIOZ_7 0>; +};
diff --git a/arch/arm/dts/meson-t7-txxx.dtsi b/arch/arm/dts/meson-t7-txxx.dtsi new file mode 100644 index 0000000..a92ec95 --- /dev/null +++ b/arch/arm/dts/meson-t7-txxx.dtsi
@@ -0,0 +1,54 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "meson-t7.dtsi" +#include "meson-t7-mali.dtsi" + +/ { + compatible = "amlogic,txxx", "amlogic,meson-t7"; +}; + +ðmac { + phy-mode = "rmii"; + phy-handle = <&internal_phy>; +};
diff --git a/arch/arm/dts/meson-t7.dtsi b/arch/arm/dts/meson-t7.dtsi new file mode 100644 index 0000000..e36f82d --- /dev/null +++ b/arch/arm/dts/meson-t7.dtsi
@@ -0,0 +1,867 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "meson-t7-series.dtsi" +#include <dt-bindings/gpio/meson-t7-gpio.h> +#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h> +#include <dt-bindings/pwm/pwm.h> +#include <dt-bindings/pwm/meson.h> + +/ { + compatible = "amlogic,meson-t7"; + + vpu { + compatible = "amlogic, vpu-t7"; + status = "okay"; + /*clocks = <&clkc CLKID_VAPB_MUX>, + * <&clkc CLKID_VPU_INTR>, + * <&clkc CLKID_VPU_P0_COMP>, + * <&clkc CLKID_VPU_P1_COMP>, + * <&clkc CLKID_VPU_MUX>; + *clock-names = "vapb_clk", + * "vpu_intr_gate", + * "vpu_clk0", + * "vpu_clk1", + * "vpu_clk"; + */ + clk_level = <7>; + /* 0: 100.0M 1: 166.7M 2: 200.0M 3: 250.0M */ + /* 4: 333.3M 5: 400.0M 6: 500.0M 7: 666.7M */ + }; + + fb { + status = "okay"; + logo_addr = "0x7f800000"; + }; + + pinctrl_periphs: pinctrl@fe004000 { + compatible = "amlogic,meson-t7-periphs-pinctrl"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio: bank@fe004000 { + reg = <0x0 0xfe004000 0x0 0x0064>, + <0x0 0xfe0040c0 0x0 0x0220>; + reg-names = "mux", + "gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_periphs 0 0 157>; + }; + }; + + i2c_gpio_0: i2c-gpio-0 { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "i2c-gpio"; + status = "okay"; + gpios = <&gpio GPIOH_0 GPIO_ACTIVE_HIGH>, /* SDA */ + <&gpio GPIOH_1 GPIO_ACTIVE_HIGH>; /* CLK */ + + i2c-gpio,delay-us = <5>; + is_odpin = <1>; + }; + + pwm_ab: pwm@fe058000 { + compatible = "amlogic,meson-v2-pwm"; + reg = <0x0 0xfe058000 0x0 0x20>, + <0x0 0xfe000180 0x0 0x04>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm_cd: pwm@fe05a000 { + compatible = "amlogic,meson-v2-pwm"; + reg = <0x0 0xfe05a000 0x0 0x20>, + <0x0 0xfe000184 0x0 0x04>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm_ef: pwm@fe05c000 { + compatible = "amlogic,meson-v2-pwm"; + reg = <0x0 0xfe05c000 0x0 0x20>, + <0x0 0xfe000188 0x0 0x04>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwmao_ab: pwm@fe05e000 { + compatible = "amlogic,meson-v2-pwm"; + reg = <0x0 0xfe05e000 0x0 0x20>, + <0x0 0xfe0001a0 0x0 0x04>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwmao_cd: pwm@fe060000 { + compatible = "amlogic,meson-v2-pwm"; + reg = <0x0 0xfe060000 0x0 0x20>, + <0x0 0xfe0001a4 0x0 0x04>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwmao_ef: pwm@fe030000 { + compatible = "amlogic,meson-v2-pwm"; + reg = <0x0 0xfe030000 0x0 0x20>, + <0x0 0xfe0001a8 0x0 0x04>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwmao_gh: pwm@fe032000 { + compatible = "amlogic,meson-v2-pwm"; + reg = <0x0 0xfe032000 0x0 0x20>, + <0x0 0xfe0001ac 0x0 0x04>; + #pwm-cells = <3>; + status = "disabled"; + }; +}; + +ðmac { + compatible = "amlogic,t7-eth-dwmac"; + reg = <0x0 0xfdc00000 0x0 0x10000 + 0x0 0xFE024000 0x0 0x8 + 0x0 0xFE028000 0x0 0xa0>; + reg-names = "eth_base", "eth_top", "eth_cfg"; + phy_cntl1 = <0x41054147>; + internal_phy = <1>; + mc_val = <0x4be04>; + cali_val = <0x80000>; + reset-gpios = <&gpio GPIOH_7 GPIO_ACTIVE_HIGH>; + analog_ver = <1>; + pll_val = <0x9c0040a 0x927e0000 0xac5f49e5>; + analog_val = <0x20200000 0x0000c000 0x00000023>; + chip_num = <3>; + //tx_amp_src = <0xfe005b30>; +// clocks = <&clkc CLKID_ETH_CORE>, +// <&clkc CLKID_FCLK_DIV2>, +// <&clkc CLKID_MPLL2>; +// clock-names = "stmmaceth", "clkin0", "clkin1"; + + mdio0: mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + }; +}; + +&periphs { + + eth-phy-mux { + compatible = "mdio-mux-mmioreg", "mdio-mux"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x15c 0x0 0x4>; + mux-mask = <0xffffffff>; + mdio-parent-bus = <&mdio0>; + + internal_mdio: mdio@e40908ff { + reg = <0xe40908ff>; + #address-cells = <1>; + #size-cells = <0>; + + internal_phy: ethernet-phy@8 { + compatible = "ethernet-phy-id0181.4400", "ethernet-phy-ieee802.3-c22"; + reg = <8>; + max-speed = <100>; + }; + }; + + external_mdio: mdio@2009087f { + reg = <0x2009087f>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&saradc { + compatible = "amlogic,meson-g12a-saradc", "amlogic,meson-saradc"; + clocks = <&xtal>, + <&clkc CLKID_SARADC_MUX>, + <&clkc CLKID_SARADC_DIV>, + <&clkc CLKID_SAR_ADC_GATE>; + clock-names = "xtal", "adc_mux", "adc_div", "adc_gate"; +}; + +&sd_emmc_a { + clocks = <&clkc CLKID_SD_EMMC_A_MUX>, + <&clkc CLKID_SD_EMMC_A_DIV>, + <&clkc CLKID_SD_EMMC_A_GATE>, + <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_XTAL>; + clock-names = "mux", "div", "gate", "clkin", "xtal"; +}; + +&sd_emmc_b { + clocks = <&clkc CLKID_SD_EMMC_B_MUX>, + <&clkc CLKID_SD_EMMC_B_DIV>, + <&clkc CLKID_SD_EMMC_B_GATE>, + <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_XTAL>; + clock-names = "mux", "div", "gate", "clkin", "xtal"; +}; + +&sd_emmc_c { + clocks = <&clkc CLKID_SD_EMMC_C_MUX>, + <&clkc CLKID_SD_EMMC_C_DIV>, + <&clkc CLKID_SD_EMMC_C_GATE>, + <&clkc CLKID_GP0_PLL>, + <&clkc CLKID_XTAL>; + clock-names = "mux", "div", "gate", "clkin", "xtal"; +}; + +&nand { + clocks = <&clkc CLKID_SD_EMMC_C_MUX>, + <&clkc CLKID_SD_EMMC_C_DIV>, + <&clkc CLKID_SD_EMMC_C_GATE>, + <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_XTAL>; + clock-names = "mux", "div", "gate", "fdiv2", "xtal"; +}; + +&spicc0 { + clocks = <&clkc CLKID_SPICC_A_DIV>, <&clkc CLKID_SPICC_A_GATE>; + clock-names = "async", "async-gate"; + assigned-clocks = <&clkc CLKID_SPICC_A_MUX>, <&clkc CLKID_SPICC_A_DIV>; + assigned-clock-parents = <&clkc CLKID_FCLK_DIV2>; + assigned-clock-rates = <0>, <200000000>; + /* =PM_SPICC0, must set to power on */ + pm-id = <42>; +}; + +&spicc1 { + clocks = <&clkc CLKID_SPICC_B_DIV>, <&clkc CLKID_SPICC_B_GATE>; + clock-names = "async", "async-gate"; + assigned-clocks = <&clkc CLKID_SPICC_B_MUX>, <&clkc CLKID_SPICC_B_DIV>; + assigned-clock-parents = <&clkc CLKID_FCLK_DIV2>; + assigned-clock-rates = <0>, <200000000>; + /* =PM_SPICC1, must set to power on */ + pm-id = <43>; +}; + +&spicc2 { + clocks = <&clkc CLKID_SPICC_C_DIV>, <&clkc CLKID_SPICC_C_GATE>; + clock-names = "async", "async-gate"; + assigned-clocks = <&clkc CLKID_SPICC_C_MUX>, <&clkc CLKID_SPICC_C_DIV>; + assigned-clock-parents = <&clkc CLKID_FCLK_DIV2>; + assigned-clock-rates = <0>, <200000000>; + /* =PM_SPICC2, must set to power on */ + pm-id = <44>; +}; + +&spicc3 { + clocks = <&clkc CLKID_SPICC_D_DIV>, <&clkc CLKID_SPICC_D_GATE>; + clock-names = "async", "async-gate"; + assigned-clocks = <&clkc CLKID_SPICC_D_MUX>, <&clkc CLKID_SPICC_D_DIV>; + assigned-clock-parents = <&clkc CLKID_FCLK_DIV2>; + assigned-clock-rates = <0>, <200000000>; + /* =PM_SPICC3, must set to power on */ + pm-id = <45>; +}; + +&spicc4 { + clocks = <&clkc CLKID_SPICC_E_DIV>, <&clkc CLKID_SPICC_E_GATE>; + clock-names = "async", "async-gate"; + assigned-clocks = <&clkc CLKID_SPICC_E_MUX>, <&clkc CLKID_SPICC_E_DIV>; + assigned-clock-parents = <&clkc CLKID_FCLK_DIV2>; + assigned-clock-rates = <0>, <200000000>; + /* =PM_SPICC4, must set to power on */ + pm-id = <46>; +}; + +&spicc5 { + clocks = <&clkc CLKID_SPICC_F_DIV>, <&clkc CLKID_SPICC_F_GATE>; + clock-names = "async", "async-gate"; + assigned-clocks = <&clkc CLKID_SPICC_F_MUX>, <&clkc CLKID_SPICC_F_DIV>; + assigned-clock-parents = <&clkc CLKID_FCLK_DIV2>; + assigned-clock-rates = <0>, <200000000>; + /* =PM_SPICC5, must set to power on */ + pm-id = <47>; +}; + +&pinctrl_periphs { + i2c0_pins1:i2c0_pins1 { + mux { + groups = "i2c0_sda_t", + "i2c0_sck_t"; + function = "i2c0"; + drive-strength = <3>; + bias-disable; + }; + }; + + i2c0_pins2:i2c0_pins2 { + mux { + groups = "i2c0_sda_h", + "i2c0_sck_h"; + function = "i2c0"; + drive-strength = <3>; + bias-disable; + }; + }; + + i2c1_pins1:i2c1_pins1 { + mux { + groups = "i2c1_sda", + "i2c1_sck"; + function = "i2c1"; + drive-strength = <3>; + bias-disable; + }; + }; + + i2c2_pins1:i2c2_pins1 { + mux { + groups = "i2c2_sda_x", + "i2c2_sck_x"; + function = "i2c2"; + drive-strength = <3>; + bias-disable; + }; + }; + + i2c2_pins2:i2c2_pins2 { + mux { + groups = "i2c2_sda_t", + "i2c2_sck_t"; + function = "i2c2"; + drive-strength = <3>; + bias-disable; + }; + }; + + i2c2_pins3:i2c2_pins3 { + mux { + groups = "i2c2_sda_m", + "i2c2_sck_m"; + function = "i2c2"; + drive-strength = <3>; + bias-disable; + }; + }; + + i2c3_pins1:i2c3_pins1 { + mux { + groups = "i2c3_sda_m", + "i2c3_sck_m"; + function = "i2c3"; + drive-strength = <3>; + bias-disable; + }; + }; + + i2c3_pins2:i2c3_pins2 { + mux { + groups = "i2c3_sda_h", + "i2c3_sck_h"; + function = "i2c3"; + drive-strength = <3>; + bias-disable; + }; + }; + + i2c4_pins1:i2c4_pins1 { + mux { + groups = "i2c4_sda_y", + "i2c4_sck_y"; + function = "i2c4"; + drive-strength = <3>; + bias-disable; + }; + }; + + i2c4_pins2:i2c4_pins2 { + mux { + groups = "i2c4_sda_h", + "i2c4_sck_h"; + function = "i2c4"; + drive-strength = <3>; + bias-disable; + }; + }; + + i2c5_pins1:i2c5_pins1 { + mux { + groups = "i2c5_sda", + "i2c5_sck"; + function = "i2c5"; + drive-strength = <3>; + bias-disable; + }; + }; + + i2c0_ao_pins1:i2c0_ao_pins1 { + mux { + groups = "i2c0_ao_sda_d", + "i2c0_ao_sck_d"; + function = "i2c0_ao"; + drive-strength = <3>; + bias-disable; + }; + }; + + i2c0_ao_pins2:i2c0_ao_pins2 { + mux { + groups = "i2c0_ao_sda_e", + "i2c0_ao_sck_e"; + function = "i2c0_ao"; + drive-strength = <3>; + bias-disable; + }; + }; + + i2c1_ao_pins1:i2c1_ao_pins1 { + mux { + groups = "i2c1_ao_sda", + "i2c1_ao_sck"; + function = "i2c1_ao"; + drive-strength = <3>; + bias-disable; + }; + }; + + jtag_a_pins:jtag_a_pin { + mux { + groups = "jtag_a_clk", + "jtag_a_tms", + "jtag_a_tdi", + "jtag_a_tdo"; + function = "jtag_a"; + }; + }; + + jtag_b_pins:jtag_b_pin { + mux { + groups = "jtag_b_clk", + "jtag_b_tms", + "jtag_b_tdi", + "jtag_b_tdo"; + function = "jtag_b"; + }; + }; + + swd_a_pins:swd_a_pin { + mux { + groups = "swclk", + "swdio"; + function = "sw"; + }; + }; + + emmc_pins: emmc { + mux { + groups = "emmc_nand_d0", + "emmc_nand_d1", + "emmc_nand_d2", + "emmc_nand_d3", + "emmc_nand_d4", + "emmc_nand_d5", + "emmc_nand_d6", + "emmc_nand_d7", + "emmc_clk", + "emmc_cmd"; + function = "emmc"; + bias-pull-up; + input-enable; + }; + mux1 { + groups = "emmc_nand_ds"; + function = "emmc"; + input-enable; + bias-pull-down; + }; + }; + + emmc_clk_gate_pins: emmc_clk_gate { + mux { + groups = "emmc_clk"; + function = "emmc"; + bias-pull-down; + }; + }; + + all_nand_pins: all_nand_pins { + mux { + groups = "emmc_nand_d0", + "emmc_nand_d1", + "emmc_nand_d2", + "emmc_nand_d3", + "emmc_nand_d4", + "emmc_nand_d5", + "emmc_nand_d6", + "emmc_nand_d7", + "nand_ce0", + "nand_ale", + "nand_cle", + "nand_wen_clk", + "nand_ren_wr"; + function = "nand"; + input-enable; + }; + }; + + nand_cs_pins: nand_cs { + mux { + groups = "nand_ce0"; + function = "nand"; + }; + }; + + sdcard_pins: sdcard { + mux { + groups = "sdcard_d0", + "sdcard_d1", + "sdcard_d2", + "sdcard_d3", + "sdcard_cmd"; + function = "sdcard"; + bias-pull-up; + input-enable; + drive-strength = <4>; + }; + mux1 { + groups ="sdcard_clk"; + function = "sdcard"; + bias-pull-up; + output-high; + drive-strength = <4>; + }; + }; + + sdcard_clk_gate_pins: sdcard_clk_gate { + mux { + groups = "sdcard_clk"; + function = "sdcard"; + bias-pull-down; + }; + }; + + to_sduart_pins: to_sduart_pins{ + mux { + groups = "uart_b_rx_c", "uart_b_tx_c"; + function = "uart_b"; + bias-pull-up; + input-enable; + }; + }; + + sd_to_uart_pins: sd_to_uart_pins{ + mux { + groups = "uart_b_rx_d", "uart_b_tx_d"; + function = "uart_b"; + bias-pull-up; + input-enable; + }; + }; + + spicc0_pins: spicc0_pins { + mux { + groups = "spi0_mosi", + "spi0_miso", + //"spi0_ss0",used as GPIOT_21 + "spi0_sclk"; + function = "spi0"; + drive-strength = <2>; + }; + }; + + spicc1_pins_1: spicc1_pins_1 { + mux { + groups = "spi1_mosi_c", + "spi1_miso_c", + //"spi1_ss0_c",used as GPIOC_3 + "spi1_sclk_c"; + function = "spi1"; + drive-strength = <2>; + }; + }; + + spicc1_pins_2: spicc1_pins_2 { + mux { + groups = "spi1_mosi_m", + "spi1_miso_m", + //"spi1_ss0_m",used as GPIOM_11 + "spi1_sclk_m"; + function = "spi1"; + drive-strength = <2>; + }; + }; + + spicc2_pins: spicc2_pins { + mux { + groups = "spi2_mosi", + "spi2_miso", + //"spi2_ss0",used as GPIOY_3 + "spi2_sclk"; + function = "spi2"; + drive-strength = <2>; + }; + }; + + spicc3_pins: spicc3_pins { + mux { + groups = "spi3_mosi", + "spi3_miso", + //"spi3_ss0",used as GPIOT_9 + "spi3_sclk"; + function = "spi3"; + drive-strength = <2>; + }; + }; + + spicc4_pins: spicc4_pins { + mux { + groups = "spi4_mosi", + "spi4_miso", + //"spi4_ss0",used as GPIOZ_3 + "spi4_sclk"; + function = "spi4"; + drive-strength = <2>; + }; + }; + + spicc5_pins: spicc5_pins { + mux { + groups = "spi5_mosi", + "spi5_miso", + //"spi5_ss0",used as GPIOZ_7 + "spi5_sclk"; + function = "spi5"; + drive-strength = <2>; + }; + }; + + spifc_pins: spifc_pins { + mux { + groups = "nor_d", + "nor_q", + "nor_c", + "nor_hold", + "nor_wp"; + function = "nor"; + drive-strength = <3>; + }; + }; + + pwm_a_pins: pwm_a_pins { + mux { + groups = "pwm_a"; + function = "pwm_a"; + }; + }; + + pwm_b_pins: pwm_b_pins { + mux { + groups = "pwm_b"; + function = "pwm_b"; + }; + }; + + pwm_c_pins: pwm_c_pins { + mux { + groups = "pwm_c"; + function = "pwm_c"; + }; + }; + + pwm_d_pins: pwm_d_pins { + mux { + groups = "pwm_d"; + function = "pwm_d"; + }; + }; + + pwm_e_pins: pwm_e_pins { + mux { + groups = "pwm_e"; + function = "pwm_e"; + }; + }; + + pwm_f_pins: pwm_f_pins { + mux { + groups = "pwm_f"; + function = "pwm_f"; + }; + }; + + pwm_ao_a_pins: pwm_ao_a_pins { + mux { + groups = "pwm_ao_a"; + function = "pwm_ao_a"; + }; + }; + + pwm_ao_b_pins: pwm_ao_b_pins { + mux { + groups = "pwm_ao_b"; + function = "pwm_ao_b"; + }; + }; + + pwm_ao_c_pins1: pwm_ao_c_pins1 { + mux { + groups = "pwm_ao_c_d"; + function = "pwm_ao_c"; + }; + }; + + pwm_ao_c_pins2: pwm_ao_c_pins2 { + mux { + groups = "pwm_ao_c_e"; + function = "pwm_ao_c"; + }; + }; + + pwm_ao_c_hiz_pins: pwm_ao_c_hiz_pins { + mux { + groups = "pwm_ao_c_hiz"; + function = "pwm_ao_c"; + }; + }; + + pwm_ao_d_pins: pwm_ao_d_pins { + mux { + groups = "pwm_ao_d"; + function = "pwm_ao_d"; + }; + }; + + pwm_ao_e_pins: pwm_ao_e_pins { + mux { + groups = "pwm_ao_e"; + function = "pwm_ao_e"; + }; + }; + + pwm_ao_f_pins: pwm_ao_f_pins { + mux { + groups = "pwm_ao_f"; + function = "pwm_ao_f"; + }; + }; + + pwm_ao_g_pins1: pwm_ao_g_pins1 { + mux { + groups = "pwm_ao_g_d11"; + function = "pwm_ao_g"; + }; + }; + + pwm_ao_g_pins2: pwm_ao_g_pins2 { + mux { + groups = "pwm_ao_g_d7"; + function = "pwm_ao_g"; + }; + }; + + pwm_ao_g_pins3: pwm_ao_g_pins3 { + mux { + groups = "pwm_ao_g_e"; + function = "pwm_ao_g"; + }; + }; + + pwm_ao_g_hiz_pins: pwm_ao_g_hiz_pins { + mux { + groups = "pwm_ao_g_hiz"; + function = "pwm_ao_g"; + }; + }; + + pwm_ao_h_pins1: pwm_ao_h_pins1 { + mux { + groups = "pwm_ao_h_d5"; + function = "pwm_ao_h"; + }; + }; + + pwm_ao_h_pins2: pwm_ao_d_pins2 { + mux { + groups = "pwm_ao_h_d10"; + function = "pwm_ao_h"; + }; + }; + + external_eth_rmii_pins: external_eth_rmii_pins { + mux { + groups = "eth_mdio", + "eth_mdc", + "eth_rgmii_rx_clk", + "eth_rx_dv", + "eth_rxd0", + "eth_rxd1", + "eth_txen", + "eth_txd0", + "eth_txd1"; + function = "eth"; + drive-strength = <3>; + }; + }; + + external_eth_rgmii_pins: external_eth_rgmii_pins { + mux { + groups = "eth_mdio", + "eth_mdc", + "eth_rgmii_rx_clk", + "eth_rx_dv", + "eth_rxd0", + "eth_rxd1", + "eth_rxd2_rgmii", + "eth_rxd3_rgmii", + "eth_rgmii_tx_clk", + "eth_txen", + "eth_txd0", + "eth_txd1", + "eth_txd2_rgmii", + "eth_txd3_rgmii"; + function = "eth"; + drive-strength = <3>; + }; + }; +};
diff --git a/arch/arm/dts/meson-t7_skt-panel.dtsi b/arch/arm/dts/meson-t7_skt-panel.dtsi new file mode 100644 index 0000000..fbb676c --- /dev/null +++ b/arch/arm/dts/meson-t7_skt-panel.dtsi
@@ -0,0 +1,742 @@ +/* + * arch/arm64/boot/dts/amlogic/mesong12a_skt-panel.dtsi + * + * Copyright (C) 2016 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/ { + lcd{ + compatible = "amlogic, lcd-g12a"; + mode = "tablet"; + status = "okay"; + key_valid = <0>; + /* + clocks = <&clkc CLKID_MIPI_DSI_HOST + &clkc CLKID_MIPI_DSI_PHY + &clkc CLKID_DSI_MEAS_COMP + &clkc CLKID_VCLK2_ENCL + &clkc CLKID_VCLK2_VENCL + &clkc CLKID_GP0_PLL>; + clock-names = "dsi_host_gate", + "dsi_phy_gate", + "dsi_meas", + "encl_top_gate", + "encl_int_gate", + "gp0_pll"; + */ + reg = <0x0 0xffd07000 0x0 0x400 /* dsi_host */ + 0x0 0xff644000 0x0 0x200>; /* dsi_phy */ + interrupts = <0 3 1 + 0 56 1>; + interrupt-names = "vsync","vsync2"; + pinctrl_version = <2>; /* for uboot */ + + /* power type: + * (0=cpu_gpio, 1=pmu_gpio, 2=signal,3=extern, 0xff=ending) + * power index: + * (point gpios_index, or extern_index,0xff=invalid) + * power value:(0=output low, 1=output high, 2=input) + * power delay:(unit in ms) + */ + + /*lcd_cpu-gpios = <&gpio GPIOZ_9 GPIO_ACTIVE_HIGH + &gpio GPIOZ_8 GPIO_ACTIVE_HIGH>; + */ + lcd_cpu_gpio_names = "GPIOZ_9","GPIOZ_8"; + + lcd_0{ + model_name = "B080XAN01"; + interface = "mipi"; + basic_setting = <768 1024 /*h_active, v_active*/ + 948 1140 /*h_period, v_period*/ + 8 /*lcd_bits*/ + 119 159>; /*screen_widht, screen_height*/ + lcd_timing = <64 56 0 /*hs_width, hs_bp, hs_pol*/ + 50 30 0>; /*vs_width, vs_bp, vs_pol*/ + clk_attr = <0 /*fr_adj_type(0=clk, 1=htotal, 2=vtotal)*/ + 0 /*clk_ss_level */ + 1 /*clk_auto_generate*/ + 64843200>; /*pixel_clk(unit in Hz)*/ + mipi_attr = <4 /*lane_num*/ + 550 /*bit_rate_max(MHz)*/ + 0 /*factor(*100, default 0 for auto)*/ + 1 /*operation_mode_init(0=video, 1=command)*/ + 0 /*operation_mode_display(0=video, 1=command)*/ + 2 /* + *video_mode_type + *(0=sync_pulse,1=sync_event,2=burst) + */ + 1 /*clk_always_hs(0=disable,1=enable)*/ + 0>; /*phy_switch(0=auto,1=standard,2=slow)*/ + + /* dsi_init: data_type, num, data... */ + dsi_init_on = <0x05 1 0x11 + 0xfd 1 20 /*delay(ms)*/ + 0x05 1 0x29 + 0xfd 1 20 /*delay(ms)*/ + 0xff 0>; /*ending*/ + dsi_init_off = <0x05 1 0x28 + 0xfd 1 10 /*delay(ms)*/ + 0x05 1 0x10 + 0xfd 1 10 /*delay(ms)*/ + 0xff 0>; /*ending*/ + extern_init = <0xff>; /*0xff for invalid*/ + + /* power step: type, index, value, delay(ms) */ + power_on_step = < + 0 1 0 100 + 0 0 0 10 + 0 0 1 20 + 2 0 0 0 + 0xff 0 0 0>; /*ending*/ + power_off_step = < + 2 0 0 50 + 0 0 0 10 + 0 1 1 100 + 0xff 0 0 0>; /*ending*/ + backlight_index = <0>; + }; + + lcd_1{ + model_name = "P070ACB_FT"; + interface = "mipi"; + basic_setting = <600 1024 /*h_active, v_active*/ + 770 1070 /*h_period, v_period*/ + 8 /*lcd_bits*/ + 3 5>; /*screen_widht, screen_height*/ + lcd_timing = <10 80 0 /*hs_width,hs_bp,hs_pol*/ + 6 20 0>; /*vs_width,vs_bp,vs_pol*/ + clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/ + 0 /*clk_ss_level*/ + 1 /*clk_auto_generate*/ + 49434000>; /*pixel_clk(unit in Hz)*/ + mipi_attr = <4 /*lane_num*/ + 400 /*bit_rate_max(MHz)*/ + 0 /*factor(*100, default 0 for auto)*/ + 1 /*operation_mode_init(0=video, 1=command)*/ + 0 /*operation_mode_display(0=video, 1=command)*/ + 2 /* + *video_mode_type + *(0=sync_pulse,1=sync_event,2=burst) + */ + 0 /*clk_always_hs(0=disable,1=enable)*/ + 0>; /*phy_switch(0=auto,1=standard,2=slow)*/ + /* dsi_init: data_type, num, data... */ + dsi_init_on = < + 0xff 10 + 0xf0 3 0 1 30 /* reset high, delay 30ms */ + 0xf0 3 0 0 10 /* reset low, delay 10ms */ + 0xf0 3 0 1 30 /* reset high, delay 30ms */ + 0xfc 2 0x04 3 /* check_reg, check_cnt */ + 0xff 0>; /* ending flag */ + dsi_init_off = <0xff 0>; /* ending flag */ + /* extern_init: 0xff for invalid */ + extern_init = <2>; + /* power step: type,index,value,delay(ms) */ + power_on_step = < + 0 1 0 200 /* panel power on */ + 2 0 0 0 + 0xff 0 0 0>; + power_off_step = < + 2 0 0 0 + 0 0 0 20 /* reset low */ + 0 1 1 100 /* panel power off */ + 0xff 0 0 0>; + backlight_index = <0>; + }; + + lcd_3{ + model_name = "TL050FHV02CT"; + interface = "mipi"; + basic_setting = <1080 1920 /*h_active, v_active*/ + 1125 2100 /*h_period, v_period*/ + 8 /*lcd_bits*/ + 65 119>; /*screen_widht, screen_height*/ + lcd_timing = <5 30 0 /*hs_width,hs_bp,hs_pol*/ + 44 108 0>; /*vs_width,vs_bp,vs_pol*/ + clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/ + 0 /*clk_ss_level*/ + 1 /*clk_auto_generate*/ + 118125000>; /*pixel_clk(unit in Hz)*/ + mipi_attr = <4 /*lane_num*/ + 960 /*bit_rate_max(MHz)*/ + 0 /*factor(*100, default 0 for auto)*/ + 1 /*operation_mode_init(0=video, 1=command)*/ + 0 /*operation_mode_display(0=video, 1=command)*/ + 2 /* + *video_mode_type + *(0=sync_pulse,1=sync_event,2=burst) + */ + 1 /*clk_always_hs(0=disable,1=enable)*/ + 0>; /*phy_switch(0=auto,1=standard,2=slow)*/ + /* dsi_init: data_type, num, data... */ + dsi_init_on = <0xff 0>; /* ending flag */ + dsi_init_off = <0xff 0>; /* ending flag */ + /* extern_init: 0xff for invalid */ + extern_init = <3>; + /* power step: type,index,value,delay(ms) */ + power_on_step = < + 0 1 0 200 + 0 0 1 20 + 0 0 0 10 + 0 0 1 20 + 2 0 0 0 + 0xff 0 0 0>; + power_off_step = < + 2 0 0 0 + 0 0 0 20 + 0 1 1 100 + 0xff 0 0 0>; + backlight_index = <0>; + }; + + lcd_4{ + model_name = "TL070WSH27"; + interface = "mipi"; + basic_setting = <1024 600 /*h_active, v_active*/ + 1250 630 /*h_period, v_period*/ + 8 /*lcd_bits*/ + 154 86>; /*screen_widht, screen_height*/ + lcd_timing = <80 100 0 /*hs_width, hs_bp, hs_pol*/ + 5 20 0>; /*vs_width, vs_bp, vs_pol*/ + clk_attr = <0 /*fr_adj_type(0=clk, 1=htotal, 2=vtotal)*/ + 0 /*clk_ss_level */ + 1 /*clk_auto_generate*/ + 47250000>; /*pixel_clk(unit in Hz)*/ + mipi_attr = <4 /*lane_num*/ + 300 /*bit_rate_max(MHz)*/ + 0 /*factor(*100, default 0 for auto)*/ + 1 /*operation_mode_init(0=video, 1=command)*/ + 0 /*operation_mode_display(0=video, 1=command)*/ + 2 /* + *video_mode_type + *(0=sync_pulse,1=sync_event,2=burst) + */ + 1 /*clk_always_hs(0=disable,1=enable)*/ + 0>; /*phy_switch(0=auto,1=standard,2=slow)*/ + + /* dsi_init: data_type, num, data... */ + dsi_init_on = <0x05 1 0x11 + 0xfd 1 20 /*delay(ms)*/ + 0x05 1 0x29 + 0xfd 1 20 /*delay(ms)*/ + 0xff 0>; /*ending*/ + dsi_init_off = <0x05 1 0x28 + 0xfd 1 10 /*delay(ms)*/ + 0x05 1 0x10 + 0xfd 1 10 /*delay(ms)*/ + 0xff 0>; /*ending*/ + extern_init = <0xff>; /*0xff for invalid*/ + + /* power step: type, index, value, delay(ms) */ + power_on_step = < + 0 1 0 100 + 0 0 0 10 + 0 0 1 20 + 2 0 0 0 + 0xff 0 0 0>; /*ending*/ + power_off_step = < + 2 0 0 50 + 0 0 0 10 + 0 1 1 100 + 0xff 0 0 0>; /*ending*/ + backlight_index = <0>; + }; + }; + + lcd_extern{ + compatible = "amlogic, lcd_extern"; + status = "okay"; + i2c_bus = "i2c_bus_0"; + key_valid = <0>; + + extern_0{ + index = <0>; + extern_name = "mipi_default";/*default*/ + status = "okay"; + type = <2>; /* 0=i2c, 1=spi, 2=mipi */ + cmd_size = <0xff>; + init_on = < + 0xfd 1 10 + 0x05 1 0x11 + 0xfd 1 120 /* delay 120ms */ + 0x05 1 0x29 + 0xff 0>; /*ending*/ + init_off = < + 0x05 1 0x28 /* display off */ + 0xfd 1 10 /* delay 10ms */ + 0x05 1 0x10 /* sleep in */ + 0xfd 1 150 /* delay 150ms */ + 0xff 0>; /*ending*/ + }; + + extern_2{ + index = <2>; + extern_name = "mipi_default";/*P070ACB_FT*/ + status = "okay"; + type = <2>; /* 0=i2c, 1=spi, 2=mipi */ + cmd_size = <0xff>; + init_on = < + 0x23 2 0xE0 0x00 /* Page 0 */ + 0x23 2 0xE1 0x93 /* PASSWORD */ + 0x23 2 0xE2 0x65 + 0x23 2 0xE3 0xF8 + 0x23 2 0x80 0x03 + 0x23 2 0xE0 0x01 /* Page 01 */ + 0x23 2 0x0C 0x74 /* Set PWRIC */ + 0x23 2 0x17 0x00 /* Set Gamma Power */ + 0x23 2 0x18 0xEF /* VGMP=5.1V */ + 0x23 2 0x19 0x00 + 0x23 2 0x1A 0x00 + 0x23 2 0x1B 0xEF /* VGMN=-5.1V */ + 0x23 2 0x1C 0x00 + 0x23 2 0x1F 0x70 /* Set Gate Power */ + 0x23 2 0x20 0x2D + 0x23 2 0x21 0x2D + 0x23 2 0x22 0x7E + 0x23 2 0x26 0xF3 /* VDDD from IOVCC */ + 0x23 2 0x37 0x09 /* SetPanel */ + 0x23 2 0x38 0x04 /* SET RGBCYC */ + 0x23 2 0x39 0x00 + 0x23 2 0x3A 0x01 + 0x23 2 0x3C 0x90 + 0x23 2 0x3D 0xFF + 0x23 2 0x3E 0xFF + 0x23 2 0x3F 0xFF + 0x23 2 0x40 0x02 /* Set TCON */ + 0x23 2 0x41 0x80 + 0x23 2 0x42 0x99 + 0x23 2 0x43 0x14 + 0x23 2 0x44 0x19 + 0x23 2 0x45 0x5A + 0x23 2 0x4B 0x04 + 0x23 2 0x55 0x02 /* power voltage */ + 0x23 2 0x56 0x01 + 0x23 2 0x57 0x69 + 0x23 2 0x58 0x0A + 0x23 2 0x59 0x0A + 0x23 2 0x5A 0x2E /* VGH = 16.2V */ + 0x23 2 0x5B 0x19 /* VGL = -12V */ + 0x23 2 0x5C 0x15 + 0x23 2 0x5D 0x77 /* Gamma */ + 0x23 2 0x5E 0x56 + 0x23 2 0x5F 0x45 + 0x23 2 0x60 0x38 + 0x23 2 0x61 0x35 + 0x23 2 0x62 0x27 + 0x23 2 0x63 0x2D + 0x23 2 0x64 0x18 + 0x23 2 0x65 0x33 + 0x23 2 0x66 0x34 + 0x23 2 0x67 0x35 + 0x23 2 0x68 0x56 + 0x23 2 0x69 0x45 + 0x23 2 0x6A 0x4F + 0x23 2 0x6B 0x42 + 0x23 2 0x6C 0x40 + 0x23 2 0x6D 0x34 + 0x23 2 0x6E 0x25 + 0x23 2 0x6F 0x02 + 0x23 2 0x70 0x77 + 0x23 2 0x71 0x56 + 0x23 2 0x72 0x45 + 0x23 2 0x73 0x38 + 0x23 2 0x74 0x35 + 0x23 2 0x75 0x27 + 0x23 2 0x76 0x2D + 0x23 2 0x77 0x18 + 0x23 2 0x78 0x33 + 0x23 2 0x79 0x34 + 0x23 2 0x7A 0x35 + 0x23 2 0x7B 0x56 + 0x23 2 0x7C 0x45 + 0x23 2 0x7D 0x4F + 0x23 2 0x7E 0x42 + 0x23 2 0x7F 0x40 + 0x23 2 0x80 0x34 + 0x23 2 0x81 0x25 + 0x23 2 0x82 0x02 + 0x23 2 0xE0 0x02 /* Page2 */ + 0x23 2 0x00 0x53 + /* GIP_L Pin mapping RESET_EVEN */ + 0x23 2 0x01 0x55 /* VSSG_EVEN */ + 0x23 2 0x02 0x55 /* VSSA_EVEN */ + 0x23 2 0x03 0x51 /* STV2_EVEN */ + 0x23 2 0x04 0x77 /* VDD2_EVEN */ + 0x23 2 0x05 0x57 /* VDD1_EVEN */ + 0x23 2 0x06 0x1F + 0x23 2 0x07 0x4F /* CK12 */ + 0x23 2 0x08 0x4D /* CK10 */ + 0x23 2 0x09 0x1F + 0x23 2 0x0A 0x4B /* CK8 */ + 0x23 2 0x0B 0x49 /* CK6 */ + 0x23 2 0x0C 0x1F + 0x23 2 0x0D 0x47 /* CK4 */ + 0x23 2 0x0E 0x45 /* CK2 */ + 0x23 2 0x0F 0x41 /* STV1_EVEN */ + 0x23 2 0x10 0x1F + 0x23 2 0x11 0x1F + 0x23 2 0x12 0x1F + 0x23 2 0x13 0x55 /* VGG */ + 0x23 2 0x14 0x1F + 0x23 2 0x15 0x1F + 0x23 2 0x16 0x52 + /* GIP_R Pin mapping RESET_ODD */ + 0x23 2 0x17 0x55 /* VSSG_ODD */ + 0x23 2 0x18 0x55 /* VSSA_ODD */ + 0x23 2 0x19 0x50 /* STV2_ODD */ + 0x23 2 0x1A 0x77 /* VDD2_ODD */ + 0x23 2 0x1B 0x57 /* VDD1_ODD */ + 0x23 2 0x1C 0x1F + 0x23 2 0x1D 0x4E /* CK11 */ + 0x23 2 0x1E 0x4C /* CK9 */ + 0x23 2 0x1F 0x1F + 0x23 2 0x20 0x4A /* CK7 */ + 0x23 2 0x21 0x48 /* CK5 */ + 0x23 2 0x22 0x1F + 0x23 2 0x23 0x46 /* CK3 */ + 0x23 2 0x24 0x44 /* CK1 */ + 0x23 2 0x25 0x40 /* STV1_ODD */ + 0x23 2 0x26 0x1F + 0x23 2 0x27 0x1F + 0x23 2 0x28 0x1F + 0x23 2 0x29 0x1F + 0x23 2 0x2A 0x1F + 0x23 2 0x2B 0x55 /* VGG */ + 0x23 2 0x2C 0x12 /* GIP_L_GS Pin mapping */ + 0x23 2 0x2D 0x15 + 0x23 2 0x2E 0x15 + 0x23 2 0x2F 0x00 + 0x23 2 0x30 0x37 + 0x23 2 0x31 0x17 + 0x23 2 0x32 0x1F + 0x23 2 0x33 0x08 + 0x23 2 0x34 0x0A + 0x23 2 0x35 0x1F + 0x23 2 0x36 0x0C + 0x23 2 0x37 0x0E + 0x23 2 0x38 0x1F + 0x23 2 0x39 0x04 + 0x23 2 0x3A 0x06 + 0x23 2 0x3B 0x10 + 0x23 2 0x3C 0x1F + 0x23 2 0x3D 0x1F + 0x23 2 0x3E 0x1F + 0x23 2 0x3F 0x15 + 0x23 2 0x40 0x1F + 0x23 2 0x41 0x1F + 0x23 2 0x42 0x13 /* GIP_R_GS Pin mapping */ + 0x23 2 0x43 0x15 + 0x23 2 0x44 0x15 + 0x23 2 0x45 0x01 + 0x23 2 0x46 0x37 + 0x23 2 0x47 0x17 + 0x23 2 0x48 0x1F + 0x23 2 0x49 0x09 + 0x23 2 0x4A 0x0B + 0x23 2 0x4B 0x1F + 0x23 2 0x4C 0x0D + 0x23 2 0x4D 0x0F + 0x23 2 0x4E 0x1F + 0x23 2 0x4F 0x05 + 0x23 2 0x50 0x07 + 0x23 2 0x51 0x11 + 0x23 2 0x52 0x1F + 0x23 2 0x53 0x1F + 0x23 2 0x54 0x1F + 0x23 2 0x55 0x1F + 0x23 2 0x56 0x1F + 0x23 2 0x57 0x15 + 0x23 2 0x58 0x40 /* GIP Timing */ + 0x23 2 0x59 0x00 + 0x23 2 0x5A 0x00 + 0x23 2 0x5B 0x10 + 0x23 2 0x5C 0x14 + 0x23 2 0x5D 0x40 + 0x23 2 0x5E 0x01 + 0x23 2 0x5F 0x02 + 0x23 2 0x60 0x40 + 0x23 2 0x61 0x03 + 0x23 2 0x62 0x04 + 0x23 2 0x63 0x7A + 0x23 2 0x64 0x7A + 0x23 2 0x65 0x74 + 0x23 2 0x66 0x16 + 0x23 2 0x67 0xB4 + 0x23 2 0x68 0x16 + 0x23 2 0x69 0x7A + 0x23 2 0x6A 0x7A + 0x23 2 0x6B 0x0C + 0x23 2 0x6C 0x00 + 0x23 2 0x6D 0x04 + 0x23 2 0x6E 0x04 + 0x23 2 0x6F 0x88 + 0x23 2 0x70 0x00 + 0x23 2 0x71 0x00 + 0x23 2 0x72 0x06 + 0x23 2 0x73 0x7B + 0x23 2 0x74 0x00 + 0x23 2 0x75 0xBC + 0x23 2 0x76 0x00 + 0x23 2 0x77 0x04 + 0x23 2 0x78 0x2C + 0x23 2 0x79 0x00 + 0x23 2 0x7A 0x00 + 0x23 2 0x7B 0x00 + 0x23 2 0x7C 0x00 + 0x23 2 0x7D 0x03 + 0x23 2 0x7E 0x7B + 0x23 2 0xE0 0x04 /* Page4 */ + 0x23 2 0x09 0x11 /* Set RGBCYC2 */ + 0x23 2 0x0E 0x48 + 0x23 2 0x2B 0x2B /* ESD Protect */ + 0x23 2 0x2E 0x44 + 0x23 2 0xE0 0x00 /* Page0 */ + 0x23 2 0xE6 0x02 /* Watch dog */ + 0x23 2 0xE7 0x0C + 0x05 1 0x11 /* sleep out */ + 0xfd 1 120 + 0x05 1 0x29 /* display on */ + 0x05 1 0x35 + 0xfd 1 20 /* delay(ms) */ + 0xFF 0>; /*ending*/ + init_off = < + 0x05 1 0x28 /* display off */ + 0xfd 1 10 /* delay 10ms */ + 0x05 1 0x10 /* sleep in */ + 0xfd 1 150 /* delay 150ms */ + 0xff 0>; /*ending*/ + }; + + extern_3{ + index = <3>; + extern_name = "mipi_default";/*TL050FHV02CT*/ + status = "okay"; + type = <2>; /* 0=i2c, 1=spi, 2=mipi */ + cmd_size = <0xff>; + init_on = < + 0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x03 + 0x29 10 0x90 0x03 0x14 0x09 0x00 0x00 + 0x00 0x38 0x00 0x00 + 0x29 10 0x91 0x00 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 + 0x29 12 0x92 0x40 0x0B 0x0C 0x0D 0x0E + 0x00 0x38 0x00 0x10 0x03 0x04 + 0x29 9 0x94 0x00 0x08 0x0B 0x03 0xD2 + 0x03 0xD3 0x0C + 0x29 17 0x95 0x00 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 + 0x29 3 0x99 0x00 0x00 + 0x29 12 0x9A 0x00 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 0x00 0x00 + 0x29 7 0x9B 0x01 0x38 0x00 0x00 0x00 0x00 + 0x29 3 0x9C 0x00 0x00 + 0x29 9 0x9D 0x10 0x10 0x10 0x10 0x10 + 0x10 0x00 0x00 + 0x29 3 0x9E 0x00 0x00 + 0x29 11 0xA0 0x9F 0x1F 0x08 0x1F 0x0A + 0x1F 0x00 0x1F 0x14 0x1F + 0x29 11 0xA1 0x15 0x1F 0x1F 0x1F 0x1F + 0x1F 0x1F 0x1F 0x1F 0x1F + 0x29 11 0xA2 0x1F 0x1F 0x1F 0x1F 0x1F + 0x1F 0x1F 0x1F 0x1F 0x1F + 0x29 11 0xA4 0x1F 0x1F 0x1F 0x1F 0x1F + 0x1F 0x1F 0x1F 0x1F 0x1F + 0x29 11 0xA5 0x1F 0x1F 0x1F 0x1F 0x1F + 0x1F 0x1F 0x1F 0x1F 0x15 + 0x29 11 0xA6 0x1F 0x14 0x1F 0x01 0x1F + 0x0B 0x1F 0x09 0x1F 0x1F + 0x29 11 0xA7 0x1F 0x1F 0x0B 0x1F 0x09 + 0x1F 0x01 0x1F 0x15 0x1F + 0x29 11 0xA8 0x14 0x1F 0x1F 0x1F 0x1F + 0x1F 0x1F 0x1F 0x1F 0x1F + 0x29 11 0xA9 0x1F 0x1F 0x1F 0x1F 0x1F + 0x1F 0x1F 0x1F 0x1F 0x1F + 0x29 11 0xAB 0x1F 0x1F 0x1F 0x1F 0x1F + 0x1F 0x1F 0x1F 0x1F 0x1F + 0x29 11 0xAC 0x1F 0x1F 0x1F 0x1F 0x1F + 0x1F 0x1F 0x1F 0x1F 0x14 + 0x29 11 0xAD 0x1F 0x15 0x1F 0x00 0x1F + 0x08 0x1F 0x0A 0x1F 0x1F + 0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x00 + 0x29 4 0xBC 0x00 0x00 0x00 + 0x29 5 0xB8 0x01 0xAF 0x8F 0x8F + 0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x01 + 0x29 17 0xD1 0x00 0x00 0x00 0x09 0x00 + 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D + 0x00 0x79 0x00 0xA7 + 0x29 17 0xD2 0x00 0xCF 0x01 0x12 0x01 + 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED + 0x02 0x2F 0x02 0x74 + 0x29 17 0xD3 0x02 0x9F 0x02 0xD5 0x02 + 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73 + 0x03 0x8C 0x03 0xA5 + 0x29 5 0xD4 0x03 0xC5 0x03 0xFF + 0x29 17 0xD5 0x00 0x00 0x00 0x09 0x00 + 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D + 0x00 0x79 0x00 0xA7 + 0x29 17 0xD6 0x00 0xCF 0x01 0x12 0x01 + 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED + 0x02 0x2F 0x02 0x74 + 0x29 17 0xD7 0x02 0x9F 0x02 0xD5 0x02 + 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73 + 0x03 0x8C 0x03 0xA5 + 0x29 5 0xD8 0x03 0xC5 0x03 0xFF + 0x29 17 0xD9 0x00 0x00 0x00 0x09 0x00 + 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D + 0x00 0x79 0x00 0xA7 + 0x29 17 0xDD 0x00 0xCF 0x01 0x12 0x01 + 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED + 0x02 0x2F 0x02 0x74 + 0x29 17 0xDE 0x02 0x9F 0x02 0xD5 0x02 + 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73 + 0x03 0x8C 0x03 0xA5 + 0x29 5 0xDF 0x03 0xC5 0x03 0xFF + 0x29 17 0xE0 0x00 0x00 0x00 0x09 0x00 + 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D + 0x00 0x79 0x00 0xA7 + 0x29 17 0xE1 0x00 0xCF 0x01 0x12 0x01 + 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED + 0x02 0x2F 0x02 0x74 + 0x29 17 0xE2 0x02 0x9F 0x02 0xD5 0x02 + 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73 + 0x03 0x8C 0x03 0xA5 + 0x29 5 0xE3 0x03 0xC5 0x03 0xFF + 0x29 17 0xE4 0x00 0x00 0x00 0x09 0x00 + 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D + 0x00 0x79 0x00 0xA7 + 0x29 17 0xE5 0x00 0xCF 0x01 0x12 0x01 + 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED + 0x02 0x2F 0x02 0x74 + 0x29 17 0xE6 0x02 0x9F 0x02 0xD5 0x02 + 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73 + 0x03 0x8C 0x03 0xA5 + 0x29 5 0xE7 0x03 0xC5 0x03 0xFF + 0x29 17 0xE8 0x00 0x00 0x00 0x09 0x00 + 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D + 0x00 0x79 0x00 0xA7 + 0x29 17 0xE9 0x00 0xCF 0x01 0x12 0x01 + 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED + 0x02 0x2F 0x02 0x74 + 0x29 17 0xEA 0x02 0x9F 0x02 0xD5 0x02 + 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73 + 0x03 0x8C 0x03 0xA5 + 0x29 5 0xEB 0x03 0xC5 0x03 0xFF + 0x29 4 0xB0 0x05 0x05 0x05 + 0x29 4 0xB1 0x05 0x05 0x05 + 0x29 4 0xB3 0x10 0x10 0x10 + 0x29 4 0xB4 0x06 0x06 0x06 + 0x29 4 0xB6 0x44 0x44 0x44 + 0x29 4 0xB7 0x34 0x34 0x34 + 0x29 4 0xB8 0x34 0x34 0x34 + 0x29 4 0xB9 0x24 0x24 0x24 + 0x29 4 0xBA 0x24 0x24 0x24 + 0x29 4 0xBC 0x00 0x70 0x00 + 0x29 4 0xBD 0x00 0x70 0x00 + 0x23 2 0xBE 0x50 + 0x23 2 0x35 0x00 + 0x13 1 0x11 + 0xfd 1 200 + 0x13 1 0x29 + 0xfd 1 200 + 0xFF 0>; /*ending*/ + init_off = < + 0x05 1 0x28 /* display off */ + 0xfd 1 10 /* delay 10ms */ + 0x05 1 0x10 /* sleep in */ + 0xfd 1 150 /* delay 150ms */ + 0xff 0>; /*ending*/ + }; + }; + + backlight{ + compatible = "amlogic, backlight-g12a"; + status = "okay"; + key_valid = <0>; + pinctrl-names = "pwm_on","pwm_off"; + /* pinctrl-0 = <&pwm_f_pins2>; */ + /* pinctrl-1 = <&bl_pwm_off_pins>; */ + pinctrl_version = <2>; /* for uboot */ + bl_pwm_config = <&bl_pwm_conf>; + /*bl-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_HIGH + &gpio GPIOH_5 GPIO_ACTIVE_HIGH>;*/ + bl_gpio_names = "GPIOH_4","GPIOH_5"; + + /* pwm port: PWM_A, PWM_B, PWM_C, PWM_D, PWM_E, PWM_F, PWM_VS*/ + /* power index:(point gpios_index, 0xff=invalid) + * power value:(0=output low, 1=output high, 2=input) + * power delay:(unit in ms) + */ + + backlight_0{ + index = <0>; + bl_name = "backlight_pwm"; + bl_level_default_uboot_kernel = <100 100>; + bl_level_attr = <255 10 /*max, min*/ + 128 128>; /*mid, mid_mapping*/ + bl_ctrl_method = <1>; /* 1=pwm, 2=pwm_combo, 4=extern */ + bl_power_attr = <0 /*en_gpio_index*/ + 1 0 /*on_value, off_value*/ + 200 200>; /*on_delay(ms), off_delay(ms)*/ + bl_pwm_port = "PWM_F"; + bl_pwm_attr = <0 /*pwm_method*/ + 180 /*pwm_freq(pwm:Hz, pwm_vs:multiple of vs)*/ + 100 25>; /*duty_max(%), duty_min(%)*/ + bl_pwm_power = <1 1 /*pwm_gpio_index, pwm_gpio_off*/ + 10 10>; /*pwm_on_delay(ms), pwm_off_delay(ms)*/ + bl_pwm_en_sequence_reverse = <0>; /* 1 for reverse */ + }; + backlight_1{ + index = <1>; + bl_name = "bl_extern"; + bl_level_default_uboot_kernel = <100 100>; + bl_level_attr = <255 10 /*max, min*/ + 128 128>; /*mid, mid_mapping*/ + bl_ctrl_method = <4>; /*1=pwm, 2=pwm_combo, 4=extern*/ + bl_power_attr = <1 /*en_gpio_index*/ + 1 0 /*on_value, off_value*/ + 200 200>; /*on_delay(ms), off_delay(ms)*/ + bl_extern_index = <0>; + }; + }; + bl_pwm_conf:bl_pwm_conf{ + pwm_channel_0 { + pwm_port_index = <5>; + pwms = <&pwm_ef MESON_PWM_1 30040 0>; + }; + }; + + bl_extern{ + compatible = "amlogic, bl_extern"; + status = "disabled"; + i2c_bus = "i2c_bus_3"; + + extern_0{ + index = <0>; + extern_name = "i2c_lp8556"; + type = <0>; /*0=i2c, 1=spi, 2=mipi*/ + i2c_address = <0x2c>; /*7bit i2c address*/ + dim_max_min = <255 10>; + }; + + extern_1{ + index = <1>; + extern_name = "mipi_lt070me05"; + type = <2>; /*0=i2c, 1=spi, 2=mipi*/ + dim_max_min = <255 10>; + }; + }; +};/* end of panel */ +
diff --git a/arch/arm/dts/newman-panel.dtsi b/arch/arm/dts/newman-panel.dtsi deleted file mode 100644 index b96a004..0000000 --- a/arch/arm/dts/newman-panel.dtsi +++ /dev/null
@@ -1,1269 +0,0 @@ -/* - * arch/arm64/boot/dts/amlogic/newman-panel.dtsi - * - * Copyright (C) 2016 Amlogic, Inc. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - */ - -/ { - lcd{ - compatible = "amlogic, lcd-g12a"; - dev_name = "lcd"; - mode = "tablet"; - status = "okay"; - key_valid = <0>; - clocks = <&clkc CLKID_MIPI_DSI_HOST - &clkc CLKID_MIPI_DSI_PHY - &clkc CLKID_DSI_MEAS_COMP - &clkc CLKID_VCLK2_ENCL - &clkc CLKID_VCLK2_VENCL>; - clock-names = "dsi_host_gate", - "dsi_phy_gate", - "dsi_meas", - "encl_top_gate", - "encl_int_gate"; - reg = <0x0 0xffd07000 0x0 0x400 - 0x0 0xff644000 0x0 0x2000>; - interrupts = <0 3 1>; - interrupt-names = "vsync"; - pinctrl_version = <2>; /* for uboot */ - - /* power type: - * (0=cpu_gpio, 1=pmu_gpio, 2=signal,3=extern, 0xff=ending) - * power index: - * (point gpios_index, or extern_index,0xff=invalid) - * power value:(0=output low, 1=output high, 2=input) - * power delay:(unit in ms) - */ - lcd_cpu-gpios = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>; - lcd_cpu_gpio_names = "GPIOH_6"; - - lcd_0{ - model_name = "B080XAN01"; - interface = "mipi"; - basic_setting = <768 1024 /*h_active, v_active*/ - 948 1140 /*h_period, v_period*/ - 8 /*lcd_bits*/ - 119 159>; /*screen_width, screen_height*/ - lcd_timing = <64 56 0 /*hs_width, hs_bp, hs_pol*/ - 50 30 0>; /*vs_width, vs_bp, vs_pol*/ - clk_attr = <0 /*fr_adj_type(0=clk, 1=htotal, 2=vtotal)*/ - 0 /*clk_ss_level */ - 1 /*clk_auto_generate*/ - 64843200>; /*pixel_clk(unit in Hz)*/ - mipi_attr = <4 /*lane_num*/ - 550 /*bit_rate_max(MHz)*/ - 0 /*factor(*100, default 0 for auto)*/ - 1 /*operation_mode_init(0=video, 1=command)*/ - 0 /*operation_mode_display(0=video, 1=command)*/ - 2 /* - *video_mode_type - *(0=sync_pulse,1=sync_event,2=burst) - */ - 1 /*clk_lp_continuous(0=stop,1=continue)*/ - 0>; /*phy_stop_wait(0=auto,1=standard,2=slow)*/ - - /* dsi_init: data_type, num, data... */ - dsi_init_on = <0x05 1 0x11 - 0xff 20 /*delay(ms)*/ - 0x05 1 0x29 - 0xff 20 /*delay(ms)*/ - 0xff 0xff>; /*ending*/ - dsi_init_off = <0x05 1 0x28 - 0xff 10 /*delay(ms)*/ - 0x05 1 0x10 - 0xff 10 /*delay(ms)*/ - 0xff 0xff>; /*ending*/ - extern_init = <0xff>; /*0xff for invalid*/ - - /* power step: type, index, value, delay(ms) */ - power_on_step = < - 0 0 0 10 - 0 0 1 20 - 2 0 0 0 - 0xff 0 0 0>; /*ending*/ - power_off_step = < - 2 0 0 50 - 0 0 0 100 - 0xff 0 0 0>; /*ending*/ - backlight_index = <0>; - }; - - lcd_1{ - model_name = "TV070WSM"; - interface = "mipi"; - basic_setting = <600 1024 /*h_active, v_active*/ - 700 1053 /*h_period, v_period*/ - 8 /*lcd_bits*/ - 95 163>; /*screen_width, screen_height*/ - lcd_timing = <24 36 0 /*hs_width,hs_bp,hs_pol*/ - 2 8 0>; /*vs_width,vs_bp,vs_pol*/ - clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/ - 0 /*clk_ss_level*/ - 1 /*clk_auto_generate*/ - 44250000>; /*pixel_clk(unit in Hz)*/ - mipi_attr = <4 /*lane_num*/ - 360 /*bit_rate_max(MHz)*/ - 0 /*factor(*100, default 0 for auto)*/ - 1 /*operation_mode_init(0=video, 1=command)*/ - 0 /*operation_mode_display(0=video, 1=command)*/ - 2 /* - *video_mode_type - *(0=sync_pulse,1=sync_event,2=burst) - */ - 0 /*clk_lp_continuous(0=stop,1=continue)*/ - 0>; /*phy_stop_wait(0=auto,1=standard,2=slow)*/ - /* dsi_init: data_type, num, data... */ - dsi_init_on = < - 0xff 10 /* delay 10 ms */ - 0xf0 3 0 1 30 /* reset high, delay 30ms */ - 0xf0 3 0 0 10 /* reset low, delay 10ms */ - 0xf0 3 0 1 30 /* reset high, delay 30ms */ - 0xfc 2 4 3 /* mipi state check */ - 0xff 10 /* delay 10 ms */ - 0xff 0xff>; /* ending flag */ - dsi_init_off = <0xff 0xff>; /* ending flag */ - /* extern_init: 0xff for invalid */ - extern_init = <1>; - /* power step: type,index,value,delay(ms) */ - power_on_step = < - 2 0 0 0 - 0xff 0 0 0>; - power_off_step = < - 2 0 0 50 - 0 0 0 100 - 0xff 0 0 0>; - backlight_index = <0>; - }; - - lcd_2{ - model_name = "P070ACB"; - interface = "mipi"; - basic_setting = <600 1024 /*h_active, v_active*/ - 680 1194 /*h_period, v_period*/ - 8 /*lcd_bits*/ - 3 5>; /*screen_width, screen_height*/ - lcd_timing = <24 36 0 /*hs_width,hs_bp,hs_pol*/ - 10 80 0>; /*vs_width,vs_bp,vs_pol*/ - clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/ - 0 /*clk_ss_level*/ - 1 /*clk_auto_generate*/ - 48715200>; /*pixel_clk(unit in Hz)*/ - mipi_attr = <4 /*lane_num*/ - 400 /*bit_rate_max(MHz)*/ - 0 /*factor(*100, default 0 for auto)*/ - 1 /*operation_mode_init(0=video, 1=command)*/ - 0 /*operation_mode_display(0=video, 1=command)*/ - 2 /* - *video_mode_type - *(0=sync_pulse,1=sync_event,2=burst) - */ - 0 /*clk_lp_continuous(0=stop,1=continue)*/ - 0>; /*phy_stop_wait(0=auto,1=standard,2=slow)*/ - /* dsi_init: data_type, num, data... */ - dsi_init_on = < - 0xff 10 /* delay 10ms */ - 0xf0 3 0 1 30 /* reset high, delay 30ms */ - 0xf0 3 0 0 10 /* reset low, delay 10ms */ - 0xf0 3 0 1 30 /* reset high, delay 30ms */ - 0xfc 2 4 3 /* mipi state check */ - 0xff 10 /* delay 10 ms */ - 0xff 0xff>; /* ending flag */ - dsi_init_off = <0xff 0xff>; /* ending flag */ - /* extern_init: 0xff for invalid */ - extern_init = <2>; - /* power step: type,index,value,delay(ms) */ - power_on_step = < - 2 0 0 0 - 0xff 0 0 0>; - power_off_step = < - 2 0 0 50 - 0 0 0 100 - 0xff 0 0 0>; - backlight_index = <1>; - }; - boe_nvtk_10{ - model_name = "TV101WXM"; - interface = "mipi"; - basic_setting = <800 1280 /*h_active, v_active*/ - 900 1312 /*h_period, v_period*/ - 8 /*lcd_bits*/ - 800 1280>; /*screen_width, screen_height*/ - lcd_timing = <24 48 0 /*hs_width,hs_bp,hs_pol*/ - 4 12 0>; /*vs_width,vs_bp,vs_pol*/ - clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/ - 0 /*clk_ss_level*/ - 1 /*clk_auto_generate*/ - 70950000>; /*pixel_clk(unit in Hz)*/ - mipi_attr = <4 /*lane_num*/ - 568 /*bit_rate_max(MHz)*/ - 0 /*factor(*100, default 0 for auto)*/ - 1 /*operation_mode_init(0=video, 1=command)*/ - 0 /*operation_mode_display(0=video, 1=command)*/ - 2 /* - *video_mode_type - *(0=sync_pulse,1=sync_event,2=burst) - */ - 0 /*clk_lp_continuous(0=stop,1=continue)*/ - 0>; /*phy_stop_wait(0=auto,1=standard,2=slow)*/ - /* dsi_init: data_type, num, data... */ - dsi_init_on = < - 0xff 10 /* delay 10 ms */ - 0xf0 3 0 1 30 /* reset high, delay 30ms */ - 0xf0 3 0 0 10 /* reset low, delay 10ms */ - 0xf0 3 0 1 30 /* reset high, delay 30ms */ - 0xfc 2 4 3 /* mipi state check */ - 0xff 10 /* delay 10 ms */ - 0xff 0xff>; /* ending flag */ - dsi_init_off = <0xff 0xff>; /* ending flag */ - /* extern_init: 0xff for invalid */ - extern_init = <5>; - /* power step: type,index,value,delay(ms) */ - power_on_step = < - 2 0 0 0 - 0xff 0 0 0>; - power_off_step = < - 2 0 0 50 - 0 0 0 100 - 0xff 0 0 0>; - backlight_index = <0>; - }; - inx_nvtk_10{ - model_name = "G101B158"; - interface = "mipi"; - basic_setting = <800 1280 /*h_active, v_active*/ - 880 1314 /*h_period, v_period*/ - 8 /*lcd_bits*/ - 800 1280>; /*screen_width, screen_height*/ - lcd_timing = <18 18 0 /*hs_width,hs_bp,hs_pol*/ - 4 10 0>; /*vs_width,vs_bp,vs_pol*/ - clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/ - 0 /*clk_ss_level*/ - 1 /*clk_auto_generate*/ - 69380000>; /*pixel_clk(unit in Hz)*/ - mipi_attr = <4 /*lane_num*/ - 560 /*bit_rate_max(MHz)*/ - 0 /*factor(*100, default 0 for auto)*/ - 1 /*operation_mode_init(0=video, 1=command)*/ - 0 /*operation_mode_display(0=video, 1=command)*/ - 2 /* - *video_mode_type - *(0=sync_pulse,1=sync_event,2=burst) - */ - 0 /*clk_lp_continuous(0=stop,1=continue)*/ - 0>; /*phy_stop_wait(0=auto,1=standard,2=slow)*/ - /* dsi_init: data_type, num, data... */ - dsi_init_on = < - 0xff 10 /* delay 10ms */ - 0xf0 3 0 1 30 /* reset high, delay 30ms */ - 0xf0 3 0 0 10 /* reset low, delay 10ms */ - 0xf0 3 0 1 30 /* reset high, delay 30ms */ - 0xfc 2 4 3 /* mipi state check */ - 0xff 10 /* delay 10 ms */ - 0xff 0xff>; /* ending flag */ - dsi_init_off = <0xff 0xff>; /* ending flag */ - /* extern_init: 0xff for invalid */ - extern_init = <6>; - /* power step: type,index,value,delay(ms) */ - power_on_step = < - 2 0 0 0 - 0xff 0 0 0>; - power_off_step = < - 2 0 0 50 - 0 0 0 100 - 0xff 0 0 0>; - backlight_index = <1>; - }; - boe_fiti_10{ - model_name = "TV101WXM_FT"; - interface = "mipi"; - basic_setting = <800 1280 /*h_active, v_active*/ - 890 1324 /*h_period, v_period*/ - 8 /*lcd_bits*/ - 800 1280>; /*screen_width, screen_height*/ - lcd_timing = <20 50 0 /*hs_width,hs_bp,hs_pol*/ - 4 20 0>; /*vs_width,vs_bp,vs_pol*/ - clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/ - 0 /*clk_ss_level*/ - 1 /*clk_auto_generate*/ - 70701600>; /*pixel_clk(unit in Hz)*/ - mipi_attr = <4 /*lane_num*/ - 566 /*bit_rate_max(MHz)*/ - 0 /*factor(*100, default 0 for auto)*/ - 1 /*operation_mode_init(0=video, 1=command)*/ - 0 /*operation_mode_display(0=video, 1=command)*/ - 2 /* - *video_mode_type - *(0=sync_pulse,1=sync_event,2=burst) - */ - 0 /*clk_lp_continuous(0=stop,1=continue)*/ - 0>; /*phy_stop_wait(0=auto,1=standard,2=slow)*/ - /* dsi_init: data_type, num, data... */ - dsi_init_on = < - 0xff 10 /* delay 10ms */ - 0xf0 3 0 1 30 /* reset high, delay 30ms */ - 0xf0 3 0 0 10 /* reset low, delay 10ms */ - 0xf0 3 0 1 30 /* reset high, delay 30ms */ - 0xfc 2 4 3 /* mipi state check */ - 0xff 10 /* delay 10 ms */ - 0xff 0xff>; /* ending flag */ - dsi_init_off = <0xff 0xff>; /* ending flag */ - /* extern_init: 0xff for invalid */ - extern_init = <7>; - /* power step: type,index,value,delay(ms) */ - power_on_step = < - 2 0 0 0 - 0xff 0 0 0>; - power_off_step = < - 2 0 0 50 - 0 0 0 100 - 0xff 0 0 0>; - backlight_index = <1>; - }; - inx_fiti_10{ - model_name = "G101B158_FT"; - interface = "mipi"; - basic_setting = <800 1280 /*h_active, v_active*/ - 890 1324 /*h_period, v_period*/ - 8 /*lcd_bits*/ - 800 1280>; /*screen_width, screen_height*/ - lcd_timing = <24 20 0 /*hs_width,hs_bp,hs_pol*/ - 4 20 0>; /*vs_width,vs_bp,vs_pol*/ - clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/ - 0 /*clk_ss_level*/ - 1 /*clk_auto_generate*/ - 70701600>; /*pixel_clk(unit in Hz)*/ - mipi_attr = <4 /*lane_num*/ - 566 /*bit_rate_max(MHz)*/ - 0 /*factor(*100, default 0 for auto)*/ - 1 /*operation_mode_init(0=video, 1=command)*/ - 0 /*operation_mode_display(0=video, 1=command)*/ - 2 /* - *video_mode_type - *(0=sync_pulse,1=sync_event,2=burst) - */ - 0 /*clk_lp_continuous(0=stop,1=continue)*/ - 0>; /*phy_stop_wait(0=auto,1=standard,2=slow)*/ - /* dsi_init: data_type, num, data... */ - dsi_init_on = < - 0xff 10 /* delay 10ms */ - 0xf0 3 0 1 30 /* reset high, delay 30ms */ - 0xf0 3 0 0 10 /* reset low, delay 10ms */ - 0xf0 3 0 1 30 /* reset high, delay 30ms */ - 0xfc 2 4 3 /* mipi state check */ - 0xff 10 /* delay 10 ms */ - 0xff 0xff>; /* ending flag */ - dsi_init_off = <0xff 0xff>; /* ending flag */ - /* extern_init: 0xff for invalid */ - extern_init = <8>; - /* power step: type,index,value,delay(ms) */ - power_on_step = < - 2 0 0 0 - 0xff 0 0 0>; - power_off_step = < - 2 0 0 50 - 0 0 0 100 - 0xff 0 0 0>; - backlight_index = <1>; - }; - }; - - lcd_extern{ - compatible = "amlogic, lcd_extern"; - dev_name = "lcd_extern"; - status = "okay"; - key_valid = <0>; - - extern_0{ - index = <0>; - extern_name = "ext_default"; - status = "disabled"; - type = <0>; /*0=i2c, 1=spi, 2=mipi*/ - i2c_address = <0x37>; /*7bit i2c address*/ - i2c_second_address = <0xff>; /*0xff for none*/ - i2c_bus = "i2c_bus_c"; - cmd_size = <4>; - - /* init on/off: (type, value..., delay), - * must match cmd_size for every group - * type: 0x00=cmd(bit[3:0]=1 for second_addr), - * 0xf0=gpio, 0xff=ending - * value: i2c or spi cmd, or gpio index & level, - * fill 0x0 for no use - * delay: unit ms - */ - init_on = <0x00 0x00 0x00 0x00 - 0x00 0x08 0x01 0x00 - 0x00 0x10 0x3F 0x00 - 0x00 0x11 0x00 0x00 - 0x00 0x12 0x00 0x00 - 0x00 0x13 0xE4 0x00 - 0x00 0x14 0x02 0x00 - 0x00 0x15 0x02 0x00 - 0x00 0x16 0x24 0x00 - 0x00 0x17 0x00 0x00 - 0x00 0x18 0x21 0x00 - 0x00 0x20 0x3F 0x00 - 0x00 0x21 0xFF 0x00 - 0x00 0x22 0x00 0x00 - 0x00 0x23 0x00 0x00 - 0x00 0x24 0x00 0x00 - 0x00 0x25 0x00 0x00 - 0x00 0x26 0xE4 0x00 - 0x00 0x27 0x00 0x00 - 0x00 0x28 0x28 0x00 - 0x00 0x29 0x01 0x00 - 0x00 0x2A 0x00 0x00 - 0x00 0x2B 0x01 0x00 - 0x00 0x2C 0x0E 0x00 - 0x00 0x2D 0x00 0x00 - 0x00 0x2E 0x18 0x00 - 0x00 0x2F 0x02 0x00 - 0x00 0x30 0x02 0x00 - 0x00 0x31 0x00 0x00 - 0x00 0x32 0x63 0x00 - 0x00 0x40 0x00 0x00 - 0x00 0x41 0x00 0x00 - 0x00 0x42 0x00 0x00 - 0x00 0x12 0x00 0x00 - 0x00 0x13 0xE4 0x00 - 0x00 0x14 0x02 0x00 - 0x00 0x15 0x00 0x00 - 0x00 0x16 0x0D 0x00 - 0x00 0x17 0x00 0x00 - 0x00 0x18 0x21 0x00 - 0x00 0x41 0x06 0x00 - 0x00 0x00 0x01 0x00 - 0x00 0x08 0x00 0x00 - 0x00 0x10 0x00 0x00 - 0x00 0x11 0x0F 0x00 - 0xff 0x00 0x00 0x00>; /*ending*/ - init_off = <0x00 0x00 0x01 0x00 - 0x00 0x08 0x00 0x00 - 0x00 0x10 0x00 0x00 - 0x00 0x11 0x0F 0x00 - 0xff 0x00 0x00 0x00>; /*ending*/ - }; - - extern_1{ - index = <1>; - extern_name = "mipi_TV070WSM"; - status = "okay"; - type = <2>; /* 0=i2c, 1=spi, 2=mipi */ - }; - - extern_2{ - index = <2>; - extern_name = "mipi_P070ACB"; - status = "okay"; - type = <2>; /* 0=i2c, 1=spi, 2=mipi */ - }; - extern_5{ - /* TV101WXM (boe_nvtk_10) */ - index = <5>; - extern_name = "mipi_default"; - status = "okay"; - type = <2>; /*0=i2c, 1=spi, 2=mipi*/ - cmd_size = <0xff>; - - init_on = < - 0xFF 120 - 0x29 5 0xFF 0xAA 0x55 0x25 0x01 - 0x23 2 0xFC 0x08 - 0xFF 1 - 0x23 2 0xFC 0x00 - 0x29 5 0xFF 0xAA 0x55 0x25 0x00 - 0xFF 20 - 0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x00 - 0x29 3 0xB1 0x68 0x01 - 0x29 5 0xB8 0x01 0x02 0x02 0x02 - 0x23 2 0xB6 0x11 - 0x29 3 0xBB 0x63 0x63 - 0x29 3 0xBC 0x00 0x00 - 0x29 6 0xBD 0x02 0xBB 0x11 0x10 0x00 - 0x23 2 0xC8 0x80 - 0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x01 - 0x29 3 0xB3 0x28 0x28 - 0x29 3 0xB4 0x14 0x14 - 0x29 3 0xB9 0x44 0x44 - 0x29 3 0xBA 0x24 0x24 - 0x29 3 0xBC 0x70 0x00 - 0x29 3 0xBD 0x70 0x00 - 0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x02 - 0x23 2 0xEE 0x03 - 0x29 17 0xB0 0x01 0x04 0x01 0x08 0x01 - 0x11 0x01 0x19 0x01 0x21 0x01 - 0x30 0x01 0x3D 0x01 0x55 - 0x29 17 0xB1 0x01 0x6B 0x01 0x94 0x01 - 0xB5 0x01 0xED 0x02 0x20 0x02 - 0x22 0x02 0x53 0x02 0x8F - 0x29 17 0xB2 0x02 0xB4 0x02 0xE5 0x03 - 0x03 0x03 0x30 0x03 0x51 0x03 - 0x76 0x03 0x96 0x03 0xB8 - 0x29 5 0xB3 0x03 0xCF 0x03 0xD2 - 0x29 17 0xB4 0x00 0x00 0x00 0x13 0x00 - 0x31 0x00 0x4B 0x00 0x61 0x00 - 0x87 0x00 0xA7 0x00 0xDB - 0x29 17 0xB5 0x01 0x04 0x01 0x43 0x01 - 0x76 0x01 0xC9 0x02 0x05 0x02 - 0x06 0x02 0x3F 0x02 0x7D - 0x29 17 0xB6 0x02 0xA3 0x02 0xD3 0x02 - 0xF6 0x03 0x23 0x03 0x44 0x03 - 0x6C 0x03 0x8A 0x03 0xAE - 0x29 5 0xB7 0x03 0xCF 0x03 0xD2 - 0x29 17 0xB8 0x00 0x41 0x00 0x4A 0x00 - 0x5D 0x00 0x6D 0x00 0x7E 0x00 - 0x9A 0x00 0xB4 0x00 0xDF - 0x29 17 0xB9 0x01 0x04 0x01 0x43 0x01 - 0x74 0x01 0xC6 0x02 0x03 0x02 - 0x09 0x02 0x40 0x02 0x7E - 0x29 17 0xBA 0x02 0xA4 0x02 0xD6 0x02 - 0xF7 0x03 0x25 0x03 0x44 0x03 - 0x6C 0x03 0x88 0x03 0xA8 - 0x29 5 0xBB 0x03 0xD0 0x03 0xD2 - 0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x03 - 0x29 3 0xB0 0x00 0x00 - 0x29 3 0xB1 0x00 0x00 - 0x29 6 0xB2 0x05 0x01 0x55 0x00 0x1A - 0x29 6 0xB3 0x05 0x01 0x55 0x00 0x1A - 0x29 6 0xBA 0x53 0x01 0x55 0x00 0x3A - 0x23 2 0xC4 0x60 - 0x23 2 0xC5 0x40 - 0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x04 - 0x29 5 0xB1 0x03 0x02 0x05 0x07 - 0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x05 - 0x29 6 0xBD 0x01 0x03 0x00 0x00 0x03 - 0x23 2 0xC0 0x09 - 0x23 2 0xC1 0x07 - 0x29 3 0xC8 0x07 0x38 - 0x23 2 0xD0 0x00 - 0x23 2 0xE5 0x03 - 0x23 2 0xE6 0x03 - 0x23 2 0xE9 0x03 - 0x23 2 0xEA 0x03 - 0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x06 - 0x29 3 0xB0 0x2D 0x2D - 0x29 3 0xB1 0x01 0x01 - 0x29 3 0xB2 0x03 0x03 - 0x29 3 0xB3 0x2E 0x2E - 0x29 3 0xB4 0x2E 0x2D - 0x29 3 0xB5 0x2D 0x13 - 0x29 3 0xB6 0x13 0x11 - 0x29 3 0xB7 0x11 0x36 - 0x29 3 0xB8 0x36 0x15 - 0x29 3 0xB9 0x15 0x2E - 0x29 3 0xBA 0x2E 0x14 - 0x29 3 0xBB 0x14 0x35 - 0x29 3 0xBC 0x35 0x10 - 0x29 3 0xBD 0x10 0x12 - 0x29 3 0xBE 0x12 0x2D - 0x29 3 0xBF 0x2D 0x2E - 0x29 3 0xC0 0x2E 0x2E - 0x29 3 0xC1 0x02 0x02 - 0x29 3 0xC2 0x00 0x00 - 0x29 3 0xC3 0x2D 0x2D - 0x29 3 0xE5 0x34 0x34 - 0x29 3 0xC4 0x2E 0x2E - 0x29 3 0xC5 0x02 0x02 - 0x29 3 0xC6 0x00 0x00 - 0x29 3 0xC7 0x2D 0x2D - 0x29 3 0xC8 0x2E 0x2D - 0x29 3 0xC9 0x2D 0x14 - 0x29 3 0xCA 0x14 0x35 - 0x29 3 0xCB 0x35 0x10 - 0x29 3 0xCC 0x10 0x12 - 0x29 3 0xCD 0x12 0x2E - 0x29 3 0xCE 0x2E 0x13 - 0x29 3 0xCF 0x13 0x11 - 0x29 3 0xD0 0x11 0x36 - 0x29 3 0xD1 0x36 0x15 - 0x29 3 0xD2 0x15 0x2D - 0x29 3 0xD3 0x2D 0x2E - 0x29 3 0xD4 0x2D 0x2D - 0x29 3 0xD5 0x01 0x01 - 0x29 3 0xD6 0x03 0x03 - 0x29 3 0xD7 0x2E 0x2E - 0x29 3 0xE6 0x34 0x34 - 0x29 6 0xD8 0x00 0x00 0x00 0x00 0x00 - 0x29 6 0xD9 0x00 0x00 0x00 0x00 0x00 - 0x29 6 0xF0 0x55 0xAA 0x52 0x00 0x00 - 0x23 2 0x35 0x00 - 0x13 1 0x11 - 0xFF 120 - 0x13 1 0x29 - - 0xFF 0xFF>; /*ending*/ - init_off = < - 0XFF 5 /* delay 5ms */ - 0x05 1 0x28 /* display off */ - 0xFF 10 /* delay 10ms */ - 0x05 1 0x10 /* sleep in */ - 0xFF 150 /* delay 150ms */ - 0xFF 0xFF>; /*ending*/ - }; - extern_6{ - /* G101B158 (inx_nvtk_10) */ - index = <6>; - extern_name = "mipi_G101B158"; - status = "okay"; - type = <2>; /* 0=i2c, 1=spi, 2=mipi */ - }; - extern_7{ - /* TV101WXM_FT (boe_fiti_10) */ - index = <7>; - extern_name = "mipi_default"; - status = "okay"; - type = <2>; /*0=i2c, 1=spi, 2=mipi*/ - cmd_size = <0xff>; - - init_on = < - 0xFF 120 - 0x23 2 0xE0 0x00 - 0x23 2 0xE1 0x93 - 0x23 2 0xE2 0x65 - 0x23 2 0xE3 0xF8 - 0x23 2 0x80 0x03 - 0x23 2 0xE0 0x01 - 0x23 2 0x00 0x00 - 0x23 2 0x01 0x6F - 0x23 2 0x17 0x00 - 0x23 2 0x18 0xAF - 0x23 2 0x19 0x01 - 0x23 2 0x1A 0x00 - 0x23 2 0x1B 0xAF - 0x23 2 0x1C 0x01 - 0x23 2 0x1F 0x3E - 0x23 2 0x20 0x28 - 0x23 2 0x21 0x28 - 0x23 2 0x22 0x7E - 0x23 2 0x35 0x26 - 0x23 2 0x37 0x09 - 0x23 2 0x38 0x04 - 0x23 2 0x39 0x00 - 0x23 2 0x3A 0x01 - 0x23 2 0x3C 0x78 - 0x23 2 0x3D 0xFF - 0x23 2 0x3E 0xFF - 0x23 2 0x3F 0x7F - 0x23 2 0x40 0x06 - 0x23 2 0x41 0xA0 - 0x23 2 0x42 0x81 - 0x23 2 0x43 0x08 - 0x23 2 0x44 0x0B - 0x23 2 0x45 0x28 - 0x23 2 0x55 0x0F - 0x23 2 0x57 0x69 - 0x23 2 0x59 0x0A - 0x23 2 0x5A 0x28 - 0x23 2 0x5B 0x14 - 0x23 2 0x5D 0x7F - 0x23 2 0x5E 0x6A - 0x23 2 0x5F 0x5A - 0x23 2 0x60 0x4E - 0x23 2 0x61 0x4A - 0x23 2 0x62 0x3A - 0x23 2 0x63 0x3C - 0x23 2 0x64 0x23 - 0x23 2 0x65 0x39 - 0x23 2 0x66 0x35 - 0x23 2 0x67 0x34 - 0x23 2 0x68 0x51 - 0x23 2 0x69 0x3E - 0x23 2 0x6A 0x44 - 0x23 2 0x6B 0x34 - 0x23 2 0x6C 0x2E - 0x23 2 0x6D 0x21 - 0x23 2 0x6E 0x0E - 0x23 2 0x6F 0x00 - 0x23 2 0x70 0x7F - 0x23 2 0x71 0x6A - 0x23 2 0x72 0x5A - 0x23 2 0x73 0x4E - 0x23 2 0x74 0x4A - 0x23 2 0x75 0x3A - 0x23 2 0x76 0x3C - 0x23 2 0x77 0x23 - 0x23 2 0x78 0x39 - 0x23 2 0x79 0x35 - 0x23 2 0x7A 0x34 - 0x23 2 0x7B 0x51 - 0x23 2 0x7C 0x3E - 0x23 2 0x7D 0x44 - 0x23 2 0x7E 0x34 - 0x23 2 0x7F 0x2E - 0x23 2 0x80 0x21 - 0x23 2 0x81 0x0E - 0x23 2 0x82 0x00 - 0x23 2 0xE0 0x02 - 0x23 2 0x00 0x1E - 0x23 2 0x01 0x1E - 0x23 2 0x02 0x41 - 0x23 2 0x03 0x41 - 0x23 2 0x04 0x43 - 0x23 2 0x05 0x43 - 0x23 2 0x06 0x1F - 0x23 2 0x07 0x1F - 0x23 2 0x08 0x35 - 0x23 2 0x09 0x1F - 0x23 2 0x0A 0x15 - 0x23 2 0x0B 0x15 - 0x23 2 0x0C 0x1F - 0x23 2 0x0D 0x47 - 0x23 2 0x0E 0x47 - 0x23 2 0x0F 0x45 - 0x23 2 0x10 0x45 - 0x23 2 0x11 0x4B - 0x23 2 0x12 0x4B - 0x23 2 0x13 0x49 - 0x23 2 0x14 0x49 - 0x23 2 0x15 0x1F - 0x23 2 0x16 0x1E - 0x23 2 0x17 0x1E - 0x23 2 0x18 0x40 - 0x23 2 0x19 0x40 - 0x23 2 0x1A 0x42 - 0x23 2 0x1B 0x42 - 0x23 2 0x1C 0x1F - 0x23 2 0x1D 0x1F - 0x23 2 0x1E 0x35 - 0x23 2 0x1F 0x1F - 0x23 2 0x20 0x15 - 0x23 2 0x21 0x15 - 0x23 2 0x22 0x1F - 0x23 2 0x23 0x46 - 0x23 2 0x24 0x46 - 0x23 2 0x25 0x44 - 0x23 2 0x26 0x44 - 0x23 2 0x27 0x4A - 0x23 2 0x28 0x4A - 0x23 2 0x29 0x48 - 0x23 2 0x2A 0x48 - 0x23 2 0x2B 0x1F - 0x23 2 0x58 0x40 - 0x23 2 0x5B 0x30 - 0x23 2 0x5C 0x0F - 0x23 2 0x5D 0x30 - 0x23 2 0x5E 0x01 - 0x23 2 0x5F 0x02 - 0x23 2 0x63 0x14 - 0x23 2 0x64 0x6A - 0x23 2 0x67 0x73 - 0x23 2 0x68 0x11 - 0x23 2 0x69 0x14 - 0x23 2 0x6A 0x6A - 0x23 2 0x6B 0x08 - 0x23 2 0x6C 0x00 - 0x23 2 0x6D 0x00 - 0x23 2 0x6E 0x00 - 0x23 2 0x6F 0x88 - 0x23 2 0x77 0xDD - 0x23 2 0x79 0x0E - 0x23 2 0x7A 0x0F - 0x23 2 0x7D 0x14 - 0x23 2 0x7E 0x82 - 0x23 2 0xE0 0x04 - 0x23 2 0x09 0x11 - 0x23 2 0x0E 0x48 - 0x23 2 0x2B 0x2B - 0x23 2 0x2D 0x03 - 0x23 2 0x2E 0x44 - 0x23 2 0xE0 0x00 - 0x23 2 0xE6 0x02 - 0x23 2 0xE7 0x0C - 0x05 1 0x11 - 0xFF 100 - 0x23 2 0xE0 0x03 - 0x23 2 0x2B 0x01 - 0x23 2 0x2C 0x00 - 0x23 2 0x30 0x03 - 0x23 2 0x31 0xFC - 0x23 2 0x32 0x03 - 0x23 2 0x33 0xF8 - 0x23 2 0x34 0x03 - 0x23 2 0x35 0xF0 - 0x23 2 0x36 0x03 - 0x23 2 0x37 0xE8 - 0x23 2 0x38 0x03 - 0x23 2 0x39 0xE0 - 0x23 2 0x3A 0x03 - 0x23 2 0x3B 0xD0 - 0x23 2 0x3C 0x03 - 0x23 2 0x3D 0xC0 - 0x23 2 0x3E 0x03 - 0x23 2 0x3F 0xA0 - 0x23 2 0x40 0x03 - 0x23 2 0x41 0x80 - 0x23 2 0x42 0x03 - 0x23 2 0x43 0x40 - 0x23 2 0x44 0x03 - 0x23 2 0x45 0x00 - 0x23 2 0x46 0x02 - 0x23 2 0x47 0x80 - 0x23 2 0x48 0x02 - 0x23 2 0x49 0x00 - 0x23 2 0x4A 0x01 - 0x23 2 0x4B 0xFC - 0x23 2 0x4C 0x01 - 0x23 2 0x4D 0x7C - 0x23 2 0x4E 0x00 - 0x23 2 0x4F 0xFC - 0x23 2 0x50 0x00 - 0x23 2 0x51 0xBC - 0x23 2 0x52 0x00 - 0x23 2 0x53 0x7C - 0x23 2 0x54 0x00 - 0x23 2 0x55 0x5C - 0x23 2 0x56 0x00 - 0x23 2 0x57 0x3C - 0x23 2 0x58 0x00 - 0x23 2 0x59 0x2C - 0x23 2 0x5A 0x00 - 0x23 2 0x5B 0x1C - 0x23 2 0x5C 0x00 - 0x23 2 0x5D 0x14 - 0x23 2 0x5E 0x00 - 0x23 2 0x5F 0x0C - 0x23 2 0x60 0x00 - 0x23 2 0x61 0x04 - 0x23 2 0x62 0x00 - 0x23 2 0x63 0x00 - 0x23 2 0x64 0x03 - 0x23 2 0x65 0xC9 - 0x23 2 0x66 0x03 - 0x23 2 0x67 0xC6 - 0x23 2 0x68 0x03 - 0x23 2 0x69 0xBE - 0x23 2 0x6A 0x03 - 0x23 2 0x6B 0xB7 - 0x23 2 0x6C 0x03 - 0x23 2 0x6D 0xB1 - 0x23 2 0x6E 0x03 - 0x23 2 0x6F 0xA3 - 0x23 2 0x70 0x03 - 0x23 2 0x71 0x96 - 0x23 2 0x72 0x03 - 0x23 2 0x73 0x79 - 0x23 2 0x74 0x03 - 0x23 2 0x75 0x5D - 0x23 2 0x76 0x03 - 0x23 2 0x77 0x26 - 0x23 2 0x78 0x02 - 0x23 2 0x79 0xE9 - 0x23 2 0x7A 0x02 - 0x23 2 0x7B 0x6E - 0x23 2 0x7C 0x01 - 0x23 2 0x7D 0xF3 - 0x23 2 0x7E 0x01 - 0x23 2 0x7F 0xEF - 0x23 2 0x80 0x01 - 0x23 2 0x81 0x73 - 0x23 2 0x82 0x00 - 0x23 2 0x83 0xF5 - 0x23 2 0x84 0x00 - 0x23 2 0x85 0xB4 - 0x23 2 0x86 0x00 - 0x23 2 0x87 0x79 - 0x23 2 0x88 0x00 - 0x23 2 0x89 0x5D - 0x23 2 0x8A 0x00 - 0x23 2 0x8B 0x3C - 0x23 2 0x8C 0x00 - 0x23 2 0x8D 0x2B - 0x23 2 0x8E 0x00 - 0x23 2 0x8F 0x1C - 0x23 2 0x90 0x00 - 0x23 2 0x91 0x14 - 0x23 2 0x92 0x00 - 0x23 2 0x93 0x0C - 0x23 2 0x94 0x00 - 0x23 2 0x95 0x04 - 0x23 2 0x96 0x00 - 0x23 2 0x97 0x00 - 0x23 2 0xE0 0x00 - 0x05 1 0x29 - 0xFF 0xFF>; /*ending*/ - init_off = < - 0XFF 5 /* delay 5ms */ - 0x05 1 0x28 /* display off */ - 0xFF 50 /* delay 50ms */ - 0x05 1 0x10 /* sleep in */ - 0xFF 150 /* delay 150ms */ - 0xFF 0xFF>; /*ending*/ - }; - extern_8{ - /* G101B158_FT (inx_fiti_10) */ - index = <8>; - extern_name = "mipi_default"; - status = "okay"; - type = <2>; /*0=i2c, 1=spi, 2=mipi*/ - cmd_size = <0xff>; - - init_on = < - 0x23 2 0xE0 0x00 - 0x23 2 0xE1 0x93 - 0x23 2 0xE2 0x65 - 0x23 2 0xE3 0xF8 - 0x23 2 0x80 0x03 - - 0x23 2 0xE0 0x01 - 0x23 2 0x00 0x00 - 0x23 2 0x01 0x5D - 0x23 2 0x03 0x00 - 0x23 2 0x04 0x64 - - 0x23 2 0x17 0x00 - 0x23 2 0x18 0xC7 - 0x23 2 0x19 0x01 - 0x23 2 0x1A 0x00 - 0x23 2 0x1B 0xC7 - 0x23 2 0x1C 0x01 - - 0x23 2 0x1F 0x70 - 0x23 2 0x20 0x2D - 0x23 2 0x21 0x2D - 0x23 2 0x22 0x7E - - 0x23 2 0x35 0x28 - - 0x23 2 0x37 0x19 - - 0x23 2 0x38 0x05 - 0x23 2 0x39 0x00 - 0x23 2 0x3A 0x01 - 0x23 2 0x3C 0x7C - 0x23 2 0x3D 0xFF - 0x23 2 0x3E 0xFF - 0x23 2 0x3F 0x7F - - 0x23 2 0x40 0x06 - 0x23 2 0x41 0xA0 - 0x23 2 0x43 0x14 - 0x23 2 0x44 0x17 - 0x23 2 0x45 0x2C - - 0x23 2 0x55 0x0F - 0x23 2 0x57 0x68 - 0x23 2 0x59 0x0A - 0x23 2 0x5A 0x2E - 0x23 2 0x5B 0x1A - 0x23 2 0x5C 0x15 - - 0x23 2 0x5D 0x7F - 0x23 2 0x5E 0x61 - 0x23 2 0x5F 0x50 - 0x23 2 0x60 0x43 - 0x23 2 0x61 0x3E - 0x23 2 0x62 0x2E - 0x23 2 0x63 0x33 - 0x23 2 0x64 0x1C - 0x23 2 0x65 0x34 - 0x23 2 0x66 0x33 - 0x23 2 0x67 0x32 - 0x23 2 0x68 0x50 - 0x23 2 0x69 0x3E - 0x23 2 0x6A 0x46 - 0x23 2 0x6B 0x37 - 0x23 2 0x6C 0x32 - 0x23 2 0x6D 0x24 - 0x23 2 0x6E 0x12 - 0x23 2 0x6F 0x02 - 0x23 2 0x70 0x7F - 0x23 2 0x71 0x61 - 0x23 2 0x72 0x50 - 0x23 2 0x73 0x43 - 0x23 2 0x74 0x3E - 0x23 2 0x75 0x2E - 0x23 2 0x76 0x33 - 0x23 2 0x77 0x1C - 0x23 2 0x78 0x34 - 0x23 2 0x79 0x33 - 0x23 2 0x7A 0x32 - 0x23 2 0x7B 0x50 - 0x23 2 0x7C 0x3E - 0x23 2 0x7D 0x46 - 0x23 2 0x7E 0x37 - 0x23 2 0x7F 0x32 - 0x23 2 0x80 0x24 - 0x23 2 0x81 0x12 - 0x23 2 0x82 0x02 - - 0x23 2 0xE0 0x02 - 0x23 2 0x00 0x52 - 0x23 2 0x01 0x55 - 0x23 2 0x02 0x55 - 0x23 2 0x03 0x50 - 0x23 2 0x04 0x77 - 0x23 2 0x05 0x57 - 0x23 2 0x06 0x55 - 0x23 2 0x07 0x4E - 0x23 2 0x08 0x4C - 0x23 2 0x09 0x5F - 0x23 2 0x0A 0x4A - 0x23 2 0x0B 0x48 - 0x23 2 0x0C 0x55 - 0x23 2 0x0D 0x46 - 0x23 2 0x0E 0x44 - 0x23 2 0x0F 0x40 - 0x23 2 0x10 0x55 - 0x23 2 0x11 0x55 - 0x23 2 0x12 0x55 - 0x23 2 0x13 0x55 - 0x23 2 0x14 0x55 - 0x23 2 0x15 0x55 - - 0x23 2 0x16 0x53 - 0x23 2 0x17 0x55 - 0x23 2 0x18 0x55 - 0x23 2 0x19 0x51 - 0x23 2 0x1A 0x77 - 0x23 2 0x1B 0x57 - 0x23 2 0x1C 0x55 - 0x23 2 0x1D 0x4F - 0x23 2 0x1E 0x4D - 0x23 2 0x1F 0x5F - 0x23 2 0x20 0x4B - 0x23 2 0x21 0x49 - 0x23 2 0x22 0x55 - 0x23 2 0x23 0x47 - 0x23 2 0x24 0x45 - 0x23 2 0x25 0x41 - 0x23 2 0x26 0x55 - 0x23 2 0x27 0x55 - 0x23 2 0x28 0x55 - 0x23 2 0x29 0x55 - 0x23 2 0x2A 0x55 - 0x23 2 0x2B 0x55 - - 0x23 2 0x2C 0x13 - 0x23 2 0x2D 0x15 - 0x23 2 0x2E 0x15 - 0x23 2 0x2F 0x01 - 0x23 2 0x30 0x37 - 0x23 2 0x31 0x17 - 0x23 2 0x32 0x15 - 0x23 2 0x33 0x0D - 0x23 2 0x34 0x0F - 0x23 2 0x35 0x15 - 0x23 2 0x36 0x05 - 0x23 2 0x37 0x07 - 0x23 2 0x38 0x15 - 0x23 2 0x39 0x09 - 0x23 2 0x3A 0x0B - 0x23 2 0x3B 0x11 - 0x23 2 0x3C 0x15 - 0x23 2 0x3D 0x15 - 0x23 2 0x3E 0x15 - 0x23 2 0x3F 0x15 - 0x23 2 0x40 0x15 - 0x23 2 0x41 0x15 - - 0x23 2 0x42 0x12 - 0x23 2 0x43 0x15 - 0x23 2 0x44 0x15 - 0x23 2 0x45 0x00 - 0x23 2 0x46 0x37 - 0x23 2 0x47 0x17 - 0x23 2 0x48 0x15 - 0x23 2 0x49 0x0C - 0x23 2 0x4A 0x0E - 0x23 2 0x4B 0x15 - 0x23 2 0x4C 0x04 - 0x23 2 0x4D 0x06 - 0x23 2 0x4E 0x15 - 0x23 2 0x4F 0x08 - 0x23 2 0x50 0x0A - 0x23 2 0x51 0x10 - 0x23 2 0x52 0x15 - 0x23 2 0x53 0x15 - 0x23 2 0x54 0x15 - 0x23 2 0x55 0x15 - 0x23 2 0x56 0x15 - 0x23 2 0x57 0x15 - - 0x23 2 0x58 0x40 - 0x23 2 0x5B 0x10 - 0x23 2 0x5C 0x12 - 0x23 2 0x5D 0x40 - 0x23 2 0x5E 0x00 - 0x23 2 0x5F 0x00 - 0x23 2 0x60 0x40 - 0x23 2 0x61 0x03 - 0x23 2 0x62 0x04 - 0x23 2 0x63 0x6C - 0x23 2 0x64 0x6C - 0x23 2 0x65 0x75 - 0x23 2 0x66 0x14 - 0x23 2 0x67 0xB4 - 0x23 2 0x68 0x14 - 0x23 2 0x69 0x6C - 0x23 2 0x6A 0x6C - 0x23 2 0x6B 0x0C - 0x23 2 0x6D 0x04 - 0x23 2 0x6E 0x00 - 0x23 2 0x6F 0x88 - 0x23 2 0x75 0xBB - 0x23 2 0x76 0x02 - 0x23 2 0x77 0x00 - 0x23 2 0x78 0x02 - - 0x23 2 0xE0 0x03 - 0x23 2 0xAF 0x20 - - - 0x23 2 0xE0 0x04 - 0x23 2 0x09 0x11 - 0x23 2 0x0E 0x48 - 0x23 2 0x2B 0x2B - 0x23 2 0x2D 0x03 - 0x23 2 0x2E 0x44 - 0x23 2 0x41 0xFF - - 0x23 2 0xE0 0x05 - 0x23 2 0x12 0x72 - - 0x23 2 0xE0 0x00 - 0x23 2 0xE6 0x02 - 0x23 2 0xE7 0x0C - - 0x23 2 0x53 0x2C - - 0x05 1 0x11 - 0xff 120 - - 0x23 2 0xE0 0x03 - 0x23 2 0x2B 0x01 - 0xff 10 - 0x23 2 0x2C 0x01 - - 0x23 2 0x30 0x03 - 0x23 2 0x31 0xDE - 0x23 2 0x32 0x03 - 0x23 2 0x33 0xDA - 0x23 2 0x34 0x03 - 0x23 2 0x35 0xD1 - 0x23 2 0x36 0x03 - 0x23 2 0x37 0xC9 - 0x23 2 0x38 0x03 - 0x23 2 0x39 0xC1 - 0x23 2 0x3A 0x03 - 0x23 2 0x3B 0xB3 - 0x23 2 0x3C 0x03 - 0x23 2 0x3D 0xA4 - 0x23 2 0x3E 0x03 - 0x23 2 0x3F 0x83 - 0x23 2 0x40 0x03 - 0x23 2 0x41 0x62 - 0x23 2 0x42 0x03 - 0x23 2 0x43 0x23 - 0x23 2 0x44 0x02 - 0x23 2 0x45 0xE4 - 0x23 2 0x46 0x02 - 0x23 2 0x47 0x67 - 0x23 2 0x48 0x01 - 0x23 2 0x49 0xEC - 0x23 2 0x4A 0x01 - 0x23 2 0x4B 0xE8 - 0x23 2 0x4C 0x01 - 0x23 2 0x4D 0x6D - 0x23 2 0x4E 0x00 - 0x23 2 0x4F 0xF2 - 0x23 2 0x50 0x00 - 0x23 2 0x51 0xB2 - 0x23 2 0x52 0x00 - 0x23 2 0x53 0x76 - 0x23 2 0x54 0x00 - 0x23 2 0x55 0x58 - 0x23 2 0x56 0x00 - 0x23 2 0x57 0x39 - 0x23 2 0x58 0x00 - 0x23 2 0x59 0x2A - 0x23 2 0x5A 0x00 - 0x23 2 0x5B 0x1B - 0x23 2 0x5C 0x00 - 0x23 2 0x5D 0x13 - 0x23 2 0x5E 0x00 - 0x23 2 0x5F 0x0B - 0x23 2 0x60 0x00 - 0x23 2 0x61 0x04 - 0x23 2 0x62 0x00 - 0x23 2 0x63 0x00 - - 0x23 2 0x64 0x03 - 0x23 2 0x65 0xE7 - 0x23 2 0x66 0x03 - 0x23 2 0x67 0xE4 - 0x23 2 0x68 0x03 - 0x23 2 0x69 0xDD - 0x23 2 0x6A 0x03 - 0x23 2 0x6B 0xD5 - 0x23 2 0x6C 0x03 - 0x23 2 0x6D 0xCE - 0x23 2 0x6E 0x03 - 0x23 2 0x6F 0xBF - 0x23 2 0x70 0x03 - 0x23 2 0x71 0xB2 - 0x23 2 0x72 0x03 - 0x23 2 0x73 0x93 - 0x23 2 0x74 0x03 - 0x23 2 0x75 0x71 - 0x23 2 0x76 0x03 - 0x23 2 0x77 0x33 - 0x23 2 0x78 0x02 - 0x23 2 0x79 0xF4 - 0x23 2 0x7A 0x02 - 0x23 2 0x7B 0x75 - 0x23 2 0x7C 0x01 - 0x23 2 0x7D 0xF7 - 0x23 2 0x7E 0x01 - 0x23 2 0x7F 0xF3 - 0x23 2 0x80 0x01 - 0x23 2 0x81 0x75 - 0x23 2 0x82 0x00 - 0x23 2 0x83 0xF7 - 0x23 2 0x84 0x00 - 0x23 2 0x85 0xB6 - 0x23 2 0x86 0x00 - 0x23 2 0x87 0x7C - 0x23 2 0x88 0x00 - 0x23 2 0x89 0x5E - 0x23 2 0x8A 0x00 - 0x23 2 0x8B 0x3F - 0x23 2 0x8C 0x00 - 0x23 2 0x8D 0x2E - 0x23 2 0x8E 0x00 - 0x23 2 0x8F 0x1D - 0x23 2 0x90 0x00 - 0x23 2 0x91 0x15 - 0x23 2 0x92 0x00 - 0x23 2 0x93 0x0C - 0x23 2 0x94 0x00 - 0x23 2 0x95 0x04 - 0x23 2 0x96 0x00 - 0x23 2 0x97 0x00 - - 0x23 2 0xE0 0x00 - - 0x05 1 0x29 - 0xFF 5 - 0xFF 0xFF>; /*ending*/ - init_off = < - 0XFF 5 /* delay 5ms */ - 0x05 1 0x28 /* display off */ - 0xFF 50 /* delay 50ms */ - 0x05 1 0x10 /* sleep in */ - 0xFF 150 /* delay 150ms */ - 0xFF 0xFF>; /*ending*/ - }; - }; -};/* end of panel */ -
diff --git a/arch/arm/dts/puddy-panel.dtsi b/arch/arm/dts/puddy-panel.dtsi deleted file mode 100644 index a89cfb7..0000000 --- a/arch/arm/dts/puddy-panel.dtsi +++ /dev/null
@@ -1,120 +0,0 @@ -/* - * arch/arm64/boot/dts/amlogic/puddy-panel.dtsi - * - * Copyright (C) 2019 Amlogic, Inc. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - */ - -/ { - lcd{ - compatible = "amlogic, lcd-g12a"; - dev_name = "lcd"; - mode = "tablet"; - status = "okay"; - key_valid = <0>; - clocks = <&clkc CLKID_MIPI_DSI_HOST - &clkc CLKID_MIPI_DSI_PHY - &clkc CLKID_DSI_MEAS_COMP - &clkc CLKID_VCLK2_ENCL - &clkc CLKID_VCLK2_VENCL>; - clock-names = "dsi_host_gate", - "dsi_phy_gate", - "dsi_meas", - "encl_top_gate", - "encl_int_gate"; - reg = <0x0 0xffd07000 0x0 0x400 - 0x0 0xff644000 0x0 0x2000>; - interrupts = <0 3 1>; - interrupt-names = "vsync"; - pinctrl_version = <2>; /* for uboot */ - - /* power type: - * (0=cpu_gpio, 1=pmu_gpio, 2=signal,3=extern, 0xff=ending) - * power index: - * (point gpios_index, or extern_index,0xff=invalid) - * power value:(0=output low, 1=output high, 2=input) - * power delay:(unit in ms) - */ - lcd_cpu-gpios = <&gpio GPIOZ_11 GPIO_ACTIVE_HIGH>; - lcd_cpu_gpio_names = "GPIOZ_11"; - - inx_dzd_8{ - model_name = "P080DZD"; - interface = "mipi"; - basic_setting = <800 1280 /*h_active, v_active*/ - 864 1466 /*h_period, v_period*/ - 8 /*lcd_bits*/ - 800 1280>; /*screen_width, screen_height*/ - lcd_timing = <14 25 0 /*hs_width,hs_bp,hs_pol*/ - 8 32 0>; /*vs_width,vs_bp,vs_pol*/ - clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/ - 0 /*clk_ss_level*/ - 1 /*clk_auto_generate*/ - 76000000>; /*pixel_clk(unit in Hz)*/ - mipi_attr = <4 /*lane_num*/ - 486 /*bit_rate_max(MHz)*/ - 0 /*factor(*100, default 0 for auto)*/ - 1 /*operation_mode_init(0=video, 1=command)*/ - 0 /*operation_mode_display(0=video, 1=command)*/ - 2 /* - *video_mode_type - *(0=sync_pulse,1=sync_event,2=burst) - */ - 0 /*clk_lp_continuous(0=stop,1=continue)*/ - 0>; /*phy_stop_wait(0=auto,1=standard,2=slow)*/ - /* dsi_init: data_type, num, data... */ - dsi_init_on = < - 0xff 120 /* delay 10ms */ - 0xf0 3 0 1 40 /* reset high, delay 30ms */ - 0xfc 2 4 3 /* mipi state check */ - 0xff 10 /* delay 10 ms */ - 0x05 1 0x11 - 0xff 100 - 0x05 1 0x29 - 0xff 0xff>; /* ending flag */ - dsi_init_off = < - 0x05 1 0x28 - 0xff 100 - 0x05 1 0x10 - 0xff 100 - 0xf0 3 0 0 100 - 0xff 0xff>; /* ending flag */ - /* extern_init: 0xff for invalid */ - extern_init = <0xff>; - /* power step: type,index,value,delay(ms) */ - power_on_step = < - 2 0 0 0 - 0xff 0 0 0>; - power_off_step = < - 2 0 0 50 - 0 0 0 100 - 0xff 0 0 0>; - backlight_index = <1>; - }; - }; - - lcd_extern{ - compatible = "amlogic, lcd_extern"; - dev_name = "lcd_extern"; - status = "okay"; - key_valid = <0>; - - extern_0{ - index = <2>; - extern_name = "mipi_P070ACB"; - status = "okay"; - type = <2>; /* 0=i2c, 1=spi, 2=mipi */ - }; - }; -};/* end of panel */ -
diff --git a/arch/arm/dts/s5pc100-pinctrl.dtsi b/arch/arm/dts/s5pc100-pinctrl.dtsi deleted file mode 100644 index 290f4cf..0000000 --- a/arch/arm/dts/s5pc100-pinctrl.dtsi +++ /dev/null
@@ -1,181 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * U-Boot additions to enable a generic Exynos GPIO driver - * - * Copyright (c) 2014 Google, Inc - */ - -/ { - pinctrl@e0300000 { - gpa0: gpa0 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpa1: gpa1 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpb: gpb { - gpio-controller; - #gpio-cells = <2>; - }; - - gpc: gpc { - gpio-controller; - #gpio-cells = <2>; - }; - - gpd: gpd { - gpio-controller; - #gpio-cells = <2>; - }; - - gpe0: gpe0 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpe1: gpe1 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpf0: gpf0 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpf1: gpf1 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpf2: gpf2 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpf3: gpf3 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpg0: gpg0 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpg1: gpg1 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpg2: gpg2 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpg3: gpg3 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpi: gpi { - gpio-controller; - #gpio-cells = <2>; - }; - - gpj0: gpj0 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpj1: gpj1 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpj2: gpj2 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpj3: gpj3 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpj4: gpj4 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpk0: gpk0 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpk1: gpk1 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpk2: gpk2 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpk3: gpk3 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpl0: gpl0 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpl1: gpl1 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpl2: gpl2 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpl3: gpl3 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpl4: gpl4 { - gpio-controller; - #gpio-cells = <2>; - }; - - gph0: gph0 { - gpio-controller; - #gpio-cells = <2>; - }; - - gph1: gph1 { - gpio-controller; - #gpio-cells = <2>; - }; - - gph2: gph2 { - gpio-controller; - #gpio-cells = <2>; - }; - - gph3: gph3 { - gpio-controller; - #gpio-cells = <2>; - }; - - }; -};
diff --git a/arch/arm/include/asm/arch-a1/acs.h b/arch/arm/include/asm/arch-a1/acs.h new file mode 100644 index 0000000..e7190ab --- /dev/null +++ b/arch/arm/include/asm/arch-a1/acs.h
@@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __ACS_H +#define __ACS_H + +#ifndef __ASSEMBLY__ +typedef struct acs_setting{ + char acs_magic[5]; //acs setting magic word, make sure this piece of data was right. + unsigned char chip_type; //chip type + unsigned short version; //version of acs_setting struct, for PC tool use. + unsigned long acs_set_length; //length of current struct. + + //ddr setting part, 16 bytes + char ddr_magic[5]; //magic word to indicate that following 12 bytes was ddr setting. + unsigned char ddr_set_version; //struct version, for PC tool use. + unsigned short ddr_set_length; //length of ddr struct. + unsigned long ddr_set_addr; //address of ddr setting. + +#if 0 + char psram_magic[5]; + unsigned char psram_set_version; + unsigned short psram_set_length; + unsigned long psram_set_addr; +#endif + char ddr_reg_magic[5]; + unsigned char ddr_reg_version; + unsigned short ddr_reg_length; + unsigned long ddr_reg_addr; + + char pll_magic[5]; + unsigned char pll_set_version; + unsigned short pll_set_length; + unsigned long pll_set_addr; + + char sto_magic[5]; + unsigned char sto_set_version; + unsigned short sto_set_length; + unsigned long sto_set_addr; + + char bl2_regs_magic[5]; + unsigned char bl2_regs_version; + unsigned short bl2_regs_length; + unsigned long bl2_regs_addr; + +#if 1 + char psram_magic[5]; + unsigned char psram_set_version; + unsigned short psram_set_length; + unsigned long psram_set_addr; +#endif +#if 0 + char rsv_magic[5]; + unsigned char rsv_set_version; + unsigned short rsv_set_length; + unsigned long rsv_set_addr; +#endif + char board_id[12]; + unsigned short ddr_struct_size[12]; + unsigned long ddr_struct_org_size; +}__attribute__ ((packed)) acs_set_t; + +#endif +#endif
diff --git a/arch/arm/include/asm/arch-a1/bl31_apis.h b/arch/arm/include/asm/arch-a1/bl31_apis.h new file mode 100644 index 0000000..a0c78a5 --- /dev/null +++ b/arch/arm/include/asm/arch-a1/bl31_apis.h
@@ -0,0 +1,164 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +/* + * Trustzone API + * + * Copyright (C) 2012 Amlogic, Inc. + * + * Author: Platform-SH@amlogic.com + * + */ + +#ifndef __GXBB_BL31_APIS_H +#define __GXBB_BL31_APIS_H + +#include <asm/arch/io.h> + +/*#define SRAM_READ 0x82000010 +#define CORE_RD_REV1 0x82000011 +#define SRAM_ACS_READ 0x82000012 +#define SRAM_ACS_INDIRECT_READ 0x82000013*/ + +#define GET_SHARE_MEM_INPUT_BASE 0x82000020 +#define GET_SHARE_MEM_OUTPUT_BASE 0x82000021 +#define GET_REBOOT_REASON 0x82000022 +#define GET_SHARE_STORAGE_IN_BASE 0x82000023 +#define GET_SHARE_STORAGE_OUT_BASE 0x82000024 +#define GET_SHARE_STORAGE_BLOCK_BASE 0x82000025 +#define GET_SHARE_STORAGE_MESSAGE_BASE 0x82000026 +#define GET_SHARE_STORAGE_BLOCK_SIZE 0x82000027 +#define SET_STORAGE_INFO 0x82000028 +#define SET_REBOOT_REASON 0x82000049 + +/* Set Reboot Reason then Reboot*/ +#define PSCI_SYS_REBOOT 0x84000009 + +/* SECUREOS DEFINITION*/ +/* SMC Identifiers for non-secure world functions */ +#define CALL_TRUSTZONE_HAL_API 0x5 + +/* EFUSE */ +#define EFUSE_READ 0x82000030 +#define EFUSE_WRITE 0x82000031 +#define EFUSE_WRITE_PATTERN 0x82000032 +#define EFUSE_USER_MAX 0x82000033 + +#define DEBUG_EFUSE_WRITE_PATTERN 0x820000F0 +#define DEBUG_EFUSE_READ_PATTERN 0x820000F1 + +/* JTAG*/ +#define JTAG_ON 0x82000040 +#define JTAG_OFF 0x82000041 + +#define SET_USB_BOOT_FUNC 0x82000043 + /* USB BOOT FUNC sub command list*/ + #define CLEAR_USB_BOOT 1 + #define FORCE_USB_BOOT 2 + #define RUN_COMD_USB_BOOT 3 + #define PANIC_DUMP_USB_BOOT 4 + +#define GET_CHIP_ID 0x82000044 + +/* tsensor calibration data */ +#define TSENSOR_CALI_SET 0x8200004C + +/*oscring efuse value get */ +#define OSCRING_EFUSE_GET 0x8200004D +/* Security Key*/ +#define SECURITY_KEY_QUERY 0x82000060 +#define SECURITY_KEY_READ 0x82000061 +#define SECURITY_KEY_WRITE 0x82000062 +#define SECURITY_KEY_TELL 0x82000063 +#define SECURITY_KEY_VERIFY 0x82000064 +#define SECURITY_KEY_STATUS 0x82000065 +#define SECURITY_KEY_NOTIFY 0x82000066 +#define SECURITY_KEY_LIST 0x82000067 +#define SECURITY_KEY_REMOVE 0x82000068 +#define SECURITY_KEY_NOTIFY_EX 0x82000069 +#define SECURITY_KEY_SET_ENCTYPE 0x8200006A +#define SECURITY_KEY_GET_ENCTYPE 0x8200006B +#define SECURITY_KEY_VERSION 0x8200006C + +/*viu probe en*/ +#define VIU_PREOBE_EN 0x82000080 +/*set boot first timeout*/ +#define SET_BOOT_FIRST 0x82000087 + +/* KEYMASTER */ +#define SET_BOOT_PARAMS 0x82000072 +#define SHA256_DIGEST_SIZE 32 +typedef struct { + uint32_t device_locked; + uint32_t verified_boot_state; + uint8_t verified_boot_key[SHA256_DIGEST_SIZE]; + uint8_t verified_boot_hash[SHA256_DIGEST_SIZE]; +} keymaster_boot_params; + +/* Secure HAL APIs */ +#define TRUSTZONE_HAL_API_SRAM 0x400 + +/*start hifi4 */ +#define START_HIFI4 0x82000090 +#define DSP_SEC_POWERSET 0x82000092 + + +#define SRAM_HAL_API_CHECK_EFUSE 0x403 +struct sram_hal_api_arg { + unsigned int cmd; + unsigned int req_len; + unsigned int res_len; + unsigned long req_phy_addr; + unsigned long res_phy_addr; + unsigned long ret_phy_addr; +}; + +#define JTAG_STATE_ON 0 +#define JTAG_STATE_OFF 1 +#define JTAG_M3_AO 0 +#define JTAG_M3_EE 1 +#define JTAG_A53_AO 2 +#define JTAG_A53_EE 3 +#define CLUSTER_BIT 2 + + +///////////////////////////////////////////////////////////////////////////////// +#define AML_DATA_PROCESS (0x820000FF) + #define AML_D_P_W_EFUSE_SECURE_BOOT (0x10) + #define AML_D_P_W_EFUSE_PASSWORD (0x11) + #define AML_D_P_W_EFUSE_CUSTOMER_ID (0x12) + #define AML_D_P_W_EFUSE_AMLOGIC (0x20) + #define AML_D_P_IMG_DECRYPT (0x40) + #define AML_D_P_UPGRADE_CHECK (0x80) + +#define GXB_EFUSE_PATTERN_SIZE (0x500) +#define GXB_IMG_SIZE (24<<20) +#define GXB_IMG_LOAD_ADDR (0x1080000) + #define GXB_IMG_DEC_KNL (1<<0) + #define GXB_IMG_DEC_RMD (1<<1) + #define GXB_IMG_DEC_DTB (1<<2) + #define GXB_IMG_DEC_ALL (GXB_IMG_DEC_KNL|GXB_IMG_DEC_RMD|GXB_IMG_DEC_DTB) + +#define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t" + +void aml_set_jtag_state(unsigned state, unsigned select); +unsigned aml_get_reboot_reason(void); +unsigned aml_reboot(uint64_t function_id, uint64_t arg0, uint64_t arg1, uint64_t arg2); +void aml_set_reboot_reason(uint64_t function_id, uint64_t arg0, uint64_t arg1, uint64_t arg2); +unsigned long aml_sec_boot_check(unsigned long ,unsigned long ,unsigned long,unsigned long ); +long get_sharemem_info(unsigned long); +void set_usb_boot_function(unsigned long command); +void aml_system_off(void); + +void bl31_get_chipid(unsigned int *, unsigned int *, + unsigned int *, unsigned int *); +void set_viu_probe_enable(void); +void wdt_send_cmd_to_bl31(uint64_t cmd, uint64_t value); +void power_set_dsp(unsigned int id, unsigned int powerflag); +void init_dsp(unsigned int id,unsigned int addr,unsigned int cfg0); +void set_boot_first_timeout(uint64_t arg0); +int bl31_get_cornerinfo(uint8_t *outbuf, int size); +int32_t set_boot_params(const keymaster_boot_params*); +#endif
diff --git a/arch/arm/include/asm/arch-a1/board_id.h b/arch/arm/include/asm/arch-a1/board_id.h new file mode 100644 index 0000000..6488771 --- /dev/null +++ b/arch/arm/include/asm/arch-a1/board_id.h
@@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +unsigned int get_board_id(void); \ No newline at end of file
diff --git a/arch/arm/include/asm/arch-a1/clk_measure_tab.h b/arch/arm/include/asm/arch-a1/clk_measure_tab.h new file mode 100644 index 0000000..87a7941 --- /dev/null +++ b/arch/arm/include/asm/arch-a1/clk_measure_tab.h
@@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef _ARCH_MESON_A1_MEASURE_H_ +#define _ARCH_MESON_A1_MEASURE_H_ + +static const char* clk_msr_table[] = { + [0] = "tdmout_b_sclk", + [1] = "tdmout_a_sclk", + [2] = "tdmin_lb_sclk", + [3] = "tdmin_b_sclk", + [4] = "tdmin_a_sclk", + [5] = "vad_clk", + [6] = "resampleA_clk", + [7] = "pdm_sysclk", + [8] = "pdm_dclk", + [9] = "locker_out_clk", + [10] = "locker_in_clk", + [11] = "spdifin_clk", + [12] = "tdmin_vad_clk", + [13] = "au_adc_clk", + [14] = "au_dac_clk", + [16] = "spicc_a_clk", + [17] = "spifc_clk", + [18] = "sd_emmc_a_clk", + [19] = "dmcx4_clk", + [20] = "dmc_clk", + [21] = "psram_clk", + [22] = "cecb_clk", + [23] = "ceca_clk", + [24] = "ts_clk", + [25] = "pwm_f_clk", + [26] = "pwm_e_clk", + [27] = "pwm_d_clk", + [28] = "pwm_c_clk", + [29] = "pwm_b_clk", + [30] = "pwm_a_clk", + [31] = "saradc_clk", + [32] = "usb_bus", + [33] = "dsp_b_clk", + [34] = "dsu_a_clk", + [35] = "axi_clk", + [36] = "sys_clk", + [40] = "rng_ring_osc0", + [41] = "rng_ring_osc1", + [42] = "rng_ring_osc2", + [43] = "rng_ring_osc3", + [44] = "dds_out", + [45] = "cpu_clk_div16", + [46] = "gpio_msr", + [50] = "osc_ring_cpu0", + [51] = "osc_ring_cpu1", + [54] = "osc_ring_top0", + [55] = "osc_ring_top1", + [56] = "osc_ring_ddr", + [57] = "osc_ring_dmc", + [58] = "osc_ring_dspa", + [59] = "osc_ring_dspb", + [60] = "osc_ring_rama", + [61] = "osc_ring_ramb", +}; + +unsigned long clk_util_clk_msr(unsigned long clk_mux); +int clk_msr(int index); + +#endif
diff --git a/arch/arm/include/asm/arch-a1/clock.h b/arch/arm/include/asm/arch-a1/clock.h new file mode 100644 index 0000000..5fb3394 --- /dev/null +++ b/arch/arm/include/asm/arch-a1/clock.h
@@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef _ARCH_MESON_A1_CLOCK_H_ +#define _ARCH_MESON_A1_CLOCK_H_ + +/* + * Clock controller register address + * APB_BASE: APB0_BASE_ADDR = 0xfe000800 + */ +#define A1_SYS_OSCIN_CTRL 0x0 +#define A1_RTC_BY_OSCIN_CTRL0 0x4 +#define A1_RTC_BY_OSCIN_CTRL1 0x8 +#define A1_RTC_CTRL 0xc +#define A1_SYS_CLK_CTRL0 0x10 +#define A1_AXI_CLK_CTRL0 0x14 +#define A1_SYS_CLK_EN0 0x1c +#define A1_SYS_CLK_EN1 0x20 +#define A1_AXI_CLK_EN 0x24 +#define A1_DSPA_CLK_EN 0x28 +#define A1_DSPB_CLK_EN 0x2c +#define A1_DSPA_CLK_CTRL0 0x30 +#define A1_DSPB_CLK_CTRL0 0x34 +#define A1_CLK12_24_CTRL 0x38 +#define A1_GEN_CLK_CTRL 0x3c +#define A1_TIMESTAMP_CTRL0 0x40 +#define A1_TIMESTAMP_CTRL1 0x44 +#define A1_TIMESTAMP_CTRL2 0x48 +#define A1_TIMESTAMP_VAL0 0x4c +#define A1_TIMESTAMP_VAL1 0x50 +#define A1_TIMEBASE_CTRL0 0x54 +#define A1_TIMEBASE_CTRL1 0x58 +#define A1_SAR_ADC_CLK_CTRL 0xc0 +#define A1_PWM_CLK_AB_CTRL 0xc4 +#define A1_PWM_CLK_CD_CTRL 0xc8 +#define A1_PWM_CLK_EF_CTRL 0xcc +#define A1_SPICC_CLK_CTRL 0xd0 +#define A1_TS_CLK_CTRL 0xd4 +#define A1_SPIFC_CLK_CTRL 0xd8 +#define A1_USB_BUSCLK_CTRL 0xdc +#define A1_SD_EMMC_CLK_CTRL 0xe0 +#define A1_CECA_CLK_CTRL0 0xe4 +#define A1_CECA_CLK_CTRL1 0xe8 +#define A1_CECB_CLK_CTRL0 0xec +#define A1_CECB_CLK_CTRL1 0xf0 +#define A1_PSRAM_CLK_CTRL 0xf4 +#define A1_DMC_CLK_CTRL 0xf8 +#define A1_FCLK_DIV1_SEL 0xfc +#define A1_TST_CTRL 0x100 + +/* + * For PLl register offset + * APB_BASE: APB0_BASE_ADDR = 0xfe007c00 + */ +/* + * basic clocks and pll clocks address + * are not continuous, add 0x7400 for each clock + */ +#define A1_ANACTRL_FIXPLL_CTRL0 (0x80 + 0x7400) +#define A1_ANACTRL_FIXPLL_CTRL1 (0x84 + 0x7400) +#define A1_ANACTRL_FIXPLL_CTRL2 (0x88 + 0x7400) +#define A1_ANACTRL_FIXPLL_CTRL3 (0x8c + 0x7400) +#define A1_ANACTRL_FIXPLL_CTRL4 (0x90 + 0x7400) +#define A1_ANACTRL_FIXPLL_STS (0x94 + 0x7400) +#define A1_ANACTRL_SYSPLL_CTRL0 (0x100 + 0x7400) +#define A1_ANACTRL_SYSPLL_CTRL1 (0x104 + 0x7400) +#define A1_ANACTRL_SYSPLL_CTRL2 (0x108 + 0x7400) +#define A1_ANACTRL_SYSPLL_CTRL3 (0x10c + 0x7400) +#define A1_ANACTRL_SYSPLL_CTRL4 (0x110 + 0x7400) +#define A1_ANACTRL_SYSPLL_STS (0x114 + 0x7400) +#define A1_ANACTRL_HIFIPLL_CTRL0 (0x140 + 0x7400) +#define A1_ANACTRL_HIFIPLL_CTRL1 (0x144 + 0x7400) +#define A1_ANACTRL_HIFIPLL_CTRL2 (0x148 + 0x7400) +#define A1_ANACTRL_HIFIPLL_CTRL3 (0x14c + 0x7400) +#define A1_ANACTRL_HIFIPLL_CTRL4 (0x150 + 0x7400) +#define A1_ANACTRL_HIFIPLL_STS (0x154 + 0x7400) +#define A1_ANACTRL_AUDDDS_CTRL0 (0x180 + 0x7400) +#define A1_ANACTRL_AUDDDS_CTRL1 (0x184 + 0x7400) +#define A1_ANACTRL_AUDDDS_CTRL2 (0x188 + 0x7400) +#define A1_ANACTRL_AUDDDS_CTRL3 (0x18c + 0x7400) +#define A1_ANACTRL_AUDDDS_CTRL4 (0x190 + 0x7400) +#define A1_ANACTRL_AUDDDS_STS (0x194 + 0x7400) +#define A1_ANACTRL_MISCTOP_CTRL0 (0x1c0 + 0x7400) +#define A1_ANACTRL_POR_CNTL (0x208 + 0x7400) + +/* + * CPU clok register offset + * APB_BASE: APB1_BASE_ADDR = 0xfd000000 + */ +/* cpu clock will never be used in uboot +#define CPUCTRL_CLK_CTRL0 0x80 +#define CPUCTRL_CLK_CTRL1 0x84 +*/ + +#endif
diff --git a/arch/arm/include/asm/arch-a1/core.h b/arch/arm/include/asm/arch-a1/core.h new file mode 100644 index 0000000..97fd220 --- /dev/null +++ b/arch/arm/include/asm/arch-a1/core.h
@@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __CORE_H__ +#define __CORE_H__ + +int get_core_mpidr(unsigned int cpuid); +int get_core_idx(unsigned int mpidr); +int get_core_max(void); + +#endif
diff --git a/arch/arm/include/asm/arch-a1/cpu.h b/arch/arm/include/asm/arch-a1/cpu.h new file mode 100644 index 0000000..2a3b929 --- /dev/null +++ b/arch/arm/include/asm/arch-a1/cpu.h
@@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef _CPU_H +#define _CPU_H +/* #include <config.h> */ +/* #include <asm/plat-cpu.h> */ +/* #include <asm/arch/ddr.h> */ + +#if 0 +#define CONFIG_AML_MESON 1 +#define CONFIG_AML_MESON_GX 1 +#define CONFIG_AML_MESON_G12A 1 +#endif + +/*enable viu probe*/ +#if 0 +#define CONFIG_CMD_VIU_PROBE 1 +#endif + +/* for uboot envrionment use */ +/* #define CONFIG_DDR_SIZE 256 */ + +/* dram */ +#ifdef CONFIG_UBOOT_RUN_IN_SRAM +#define PHYS_SDRAM_1_BASE 0xFFE00000UL +#define PHYS_SDRAM_1_SIZE 0x00180000UL +#else +#define PHYS_SDRAM_1_BASE 0x00000000UL +#define PHYS_SDRAM_1_SIZE 0x10000000UL +#endif +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1_BASE + +#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1_BASE + CONFIG_SYS_TEXT_BASE) + +/* console/print buffer */ +#define CONFIG_SYS_CBSIZE 512 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY (0x1800000) /* 24MHz */ + +/* use "hush" command parser */ +#if 0 +#define CONFIG_SYS_HUSH_PARSER +#endif + +#if 0 +#define CONFIG_DTB_MEM_ADDR 0x1000000 +#endif + +#if 0 +#define CONFIG_AML_CUSTOMER_ID (0) +#endif + +#define AML_CUSTOMER_ID (0) + +/* #define CONFIG_SILENT_CONSOLE */ +#define CONFIG_SILENT_CONSOLE_UPDATE_ON_RELOC +#define CONFIG_SILENT_U_BOOT_ONLY + +/* 2018.03.19 new compress solution, only support BL33 LZ4 compress */ +#define CONFIG_AML_BL33_COMPRESS_ENABLE 1 + +/* 2018.03.19 G12A only support v3 format for normal & secure boot */ +#define CONFIG_AML_SECURE_BOOT_V3 1 + +#define NR_CPUS 4 + +#define CPU_ID_REG SYSCTRL_SEC_STATUS_REG0 +#define PACKAGE_ID_MASK 0xFF + +/*A1 SoC has problem to support AES for secure boot, here just disable it*/ +//#define CONFIG_AML_CRYPTO_AES 1 + + +/*Flag for enable AES key generate to EFUSE pattern, with this flag only +AES key will be generated to EFUSE pattern, it can be used for use case +like the AES key not ready when secure boot enabled for the first time. +*/ + +//#define CONFIG_AML_EFUSE_GEN_AES_ONLY 1 + +#endif /* _CPU_H */
diff --git a/arch/arm/include/asm/arch-a1/cpu_config.h b/arch/arm/include/asm/arch-a1/cpu_config.h new file mode 100644 index 0000000..45e7e80 --- /dev/null +++ b/arch/arm/include/asm/arch-a1/cpu_config.h
@@ -0,0 +1,85 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef _BOOT_ROM_CONFIG_H_ +#define _BOOT_ROM_CONFIG_H_ + +/*********************************************************** + * The following constants are GXBB definition + **********************************************************/ +#define ROMBOOT_START 0xD9040000 +#define ROM_SIZE (64*1024) +#define ROMBOOT_END (ROMBOOT_START+ROM_SIZE) + +/*********************************************************** + * AHB-SRAM Total Size 80KB, layout shown as below + * + * ROMCODE use the top 32KB + * + * [ 128] 0xD901_3F80 - 0xD901_3FFF Reserved + * [ 128] 0xD901_3F00 - 0xD901_3F7F CPUs Boot Entry + * [ 256] 0xD901_3E00 - 0xD901_3EFF Debug Info + * [ 512] 0xD901_3C00 - 0xD901_3DFF eFuse mirror + * [ 1K] 0xD901_3800 - 0xD901_3BFF Secure Mailbox (3) + * [ 1K] 0xD901_3400 - 0xD901_37FF High Mailbox (2) * + * [ 1K] 0xD901_3000 - 0xD901_33FF High Mailbox (1) * + * [ 26K] 0xD900_C800 - 0xD901_2FFF BL1 Stack, BSS + * [ 1K] 0xD900_C400 - 0xD900_C7FF NAND, USB Buffer + * [ 1K] 0xD900_C000 - 0xD900_C3FF Reserved + * + **********************************************************/ +#define RAM_START 0xD9000000 +#define RAM_SIZE (80 * 1024) +#define BL1_RAM_START (RAM_START + 0xC000) +#define BL1_RAM_SIZE (32 * 1024) +#define BL1_RAM_END (BL1_RAM_START + BL1_RAM_SIZE) +#define BSS_START (BL1_RAM_START + (2 * 1024)) +#define BSS_SIZE (18 * 1024) +#define _STACK_END (BSS_START + BSS_SIZE + 8*1024) +#define BL1_EFUSE_MIRROR (BL1_RAM_END - 1024) +#define P_SHARED_EFUSE_MIRROR (volatile uint32_t *)(BL1_EFUSE_MIRROR) +#define BL1_DEBUG_BUFFER (BL1_RAM_END - 512) +#define CPU_BOOT_ENTRY (BL1_DEBUG_BUFFER + 256) +#define P_SHARED_DEBUG_BUFF (volatile uint32_t *)(BL1_DEBUG_BUFFER) +#define BL1_SEC_MBX (BL1_RAM_END - 2*1024) +#define BL1_NAND_BUFF (BL1_RAM_START + 1024) +#define BL1_USB_BUFF (BL1_NAND_BUFF) + +#define MEMORY_LOC RAM_START + +#define SRAM_DEBUG_BUFF_SIZE 256 + +/* BL2 SPL size */ +#define BL2_SIZE (64 * 1024) + +//for signature test +//#define CONFIG_AML_SIG_TEST_BUILD + +/* Software SHA2 */ +#define CONFIG_SHA2_SW + +/* Hardware SHA2 */ +#define CONFIG_SHA2_HW +#define SHA2_HW_UPDATE_API + +/* Keep timer config in conf.h */ +#define CONFIG_TIMER + +/* Bootrom debug info */ +#define CONFIG_DEBUG_INFO + +/* Mincrypt RSA library */ +//#define CONFIG_MINCRYPT + +/* PolarSSL RSA library */ +#define CONFIG_POLARSSL_RSA + +#ifdef CONFIG_POLARSSL_RSA +#ifndef CONFIG_MALLOC +#define CONFIG_MALLOC +#endif /* ! CONFIG_MALLOC */ +#endif /* CONFIG_POLARSSL_RSA */ + +#endif /* _BOOT_ROM_CONFIG_H_ */
diff --git a/arch/arm/include/asm/arch-a1/cpu_reset.h b/arch/arm/include/asm/arch-a1/cpu_reset.h new file mode 100644 index 0000000..46f9abf --- /dev/null +++ b/arch/arm/include/asm/arch-a1/cpu_reset.h
@@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef _BOOT_ROM_WATCHDOG_H +#define _BOOT_ROM_WATCHDOG_H +#include <asm/arch/secure_apb.h> + +void reset_system(void); + +/* uboot reset interface */ +void reset_cpu(unsigned long flag); + +#endif /* _BOOT_ROM_WATCHDOG_H */
diff --git a/arch/arm/include/asm/arch-a1/cpu_sdio.h b/arch/arm/include/asm/arch-a1/cpu_sdio.h new file mode 100644 index 0000000..46f366a --- /dev/null +++ b/arch/arm/include/asm/arch-a1/cpu_sdio.h
@@ -0,0 +1,239 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __CPU_SDIO_H__ +#define __CPU_SDIO_H__ + +#define SD_EMMC_BASE_A 0xFFE03000 +#define SD_EMMC_BASE_B 0xFFE05000 +#define SD_EMMC_BASE_C 0xFFE07000 + +#define SDIO_PORT_A 0 +#define SDIO_PORT_B 1 +#define SDIO_PORT_C 2 + +struct sd_emmc_global_regs { + volatile uint32_t gclock; // 0x00 + volatile uint32_t gdelay; // 0x04 + volatile uint32_t gdelay1; //0x08 + volatile uint32_t gadjust; // 0x0c + volatile uint32_t gcalout; // 0x10 + volatile uint32_t reserved_14[11]; // 0x14~0x3c + volatile uint32_t gstart; // 0x40 + volatile uint32_t gcfg; // 0x44 + volatile uint32_t gstatus; // 0x48 + volatile uint32_t girq_en; // 0x4c + volatile uint32_t gcmd_cfg; // 0x50 + volatile uint32_t gcmd_arg; // 0x54 + volatile uint32_t gcmd_dat; // 0x58 + volatile uint32_t gcmd_rsp0; // 0x5c + volatile uint32_t gcmd_rsp1; // 0x60 + volatile uint32_t gcmd_rsp2; // 0x64 + volatile uint32_t gcmd_rsp3; // 0x68 + volatile uint32_t reserved_6c; // 0x6c + volatile uint32_t gcurr_cfg; // 0x70 + volatile uint32_t gcurr_arg; // 0x74 + volatile uint32_t gcurr_dat; // 0x78 + volatile uint32_t gcurr_rsp; // 0x7c + volatile uint32_t gnext_cfg; // 0x80 + volatile uint32_t gnext_arg; // 0x84 + volatile uint32_t gnext_dat; // 0x88 + volatile uint32_t gnext_rsp; // 0x8c + volatile uint32_t grxd; // 0x90 + volatile uint32_t gtxd; // 0x94 + volatile uint32_t reserved_98[90]; // 0x98~0x1fc + volatile uint32_t gdesc[128]; // 0x200 + volatile uint32_t gping[128]; // 0x400 + volatile uint32_t gpong[128]; // 0x800 +}; + +union sd_emmc_setup { + uint32_t d32; + struct { + unsigned bw:3; + unsigned fast:1; + unsigned par:3; + unsigned hcs:1; + unsigned sd:1; + unsigned sdhc:1; + unsigned type:6; + unsigned rca:16; + } b; +}; + +struct sd_emmc_desc_info{ + uint32_t cmd_info; + uint32_t cmd_arg; + uint32_t data_addr; + uint32_t resp_addr; +}; + +struct cmd_cfg{ + uint32_t length:9; + uint32_t block_mode:1; + uint32_t r1b:1; + uint32_t end_of_chain:1; + uint32_t timeout:4; + uint32_t no_resp:1; + uint32_t no_cmd:1; + uint32_t data_io:1; + uint32_t data_wr:1; + uint32_t resp_nocrc:1; + uint32_t resp_128:1; + uint32_t resp_num:1; + uint32_t data_num:1; + uint32_t cmd_index:6; + uint32_t error:1; + uint32_t owner:1; +}; + +struct sd_emmc_status{ + uint32_t rxd_err:8; /*[7:0] RX data CRC error per wire, for multiple block read, the CRC errors are ORed together.*/ + uint32_t txd_err:1; /*[8] TX data CRC error, for multiple block write, any one of blocks CRC error. */ + uint32_t desc_err:1; /*[9] SD/eMMC controller doesn¡¯t own descriptor. The owner bit is ¡°0¡±, set cfg_ignore_owner to ignore this error.*/ + uint32_t resp_err:1; /*[10] Response CRC error.*/ + uint32_t resp_timeout:1; /*[11] No response received before time limit. The timeout limit is set by cfg_resp_timeout.*/ + uint32_t desc_timeout:1; /*[12] Descriptor execution time over time limit. The timeout limit is set by descriptor itself.*/ + /* Consider the multiple block read/write, set the proper timeout limits.*/ + uint32_t end_of_chain:1; /*[13] End of Chain IRQ, Normal IRQ. */ + uint32_t desc_irq:1; /*[14] This descriptor requests an IRQ, Normal IRQ, the descriptor chain execution keeps going on.*/ + uint32_t irq_sdio:1; /*[15] SDIO device uses DAT[1] to request IRQ. */ + uint32_t dat_i:8; /*[23:16] Input data signals. */ + uint32_t cmd_i:1; /*[24] nput response signal. */ + uint32_t ds:1; /*[25] Input data strobe. */ + uint32_t bus_fsm:4; /*[29:26] BUS fsm */ + uint32_t desc_wr_rdy:1; /*[30] Descriptor write back process is done and it is ready for CPU to read.*/ + uint32_t core_rdy:1; /*[31] desc_busy or sd_emmc_irq or bus_fsm is not idle.*/ +};//__attribute__((__may_alias__)); + + +struct sd_emmc_clock{ + uint32_t div:6; /*[5:0] Clock divider. Frequency = clock source/cfg_div, Maximum divider 63. */ + /*Clock off: cfg_div==0, the clock is disabled */ + /*Divider bypass: cfg_div==1, clock source is used as core clock without divider. */ + uint32_t src:2; /*[7:6] Clock source, 0: Crystal 24MHz, 1: Fix PLL, 850MHz*/ + /* 2: MPLL, <637MHz, used for 400MHz exactly. 3: different PLL */ + uint32_t core_phase:2; /*[9:8] Core clock phase. 0: 0 phase, 1: 90 phase, 2: 180 phase, 3: 270 phase.*/ + uint32_t tx_phase:2; /*[11:10] TX clock phase. 0: 0 phase, 1: 90 phase, 2: 180 phase, 3: 270 phase.*/ + uint32_t rx_phase:2; /*[13:12] RX clock phase. 0: 0 phase, 1: 90 phase, 2: 180 phase, 3: 270 phase.*/ + uint32_t reserved14:2; + uint32_t tx_delay:6; /*[21:16] TX clock delay line. 0: no delay, n: delay n*200ps. Maximum delay 3ns.*/ + uint32_t rx_delay:6; /*[27:22] RX clock delay line. 0: no delay, n: delay n*200ps. Maximum delay 3ns.*/ + uint32_t always_on:1; /*[28] 1: Keep clock always on. 0: Clock on/off controlled by activities. */ + /*Any APB3 access or descriptor execution will keep clock on.*/ + uint32_t irq_sdio_sleep:1; /*[29] 1: enable IRQ sdio when in sleep mode. */ + uint32_t irq_sdio_sleep_ds:1;/*[30] 1:enable ds as irq*/ + uint32_t reserved26:1; +}; + +struct sd_emmc_delay{ + uint32_t dat0:6; /*[3:0] Data 0 delay line. */ + uint32_t dat1:6; /*[7:4] Data 1 delay line. */ + uint32_t dat2:6; /*[11:8] Data 2 delay line. */ + uint32_t dat3:6; /*[15:12] Data 3 delay line. */ + uint32_t dat4:6; /*[19:16] Data 4 delay line. */ + uint32_t spare:2; +}; + +struct sd_emmc_delay1{ + uint32_t dat5:6; /*[23:20] Data 5 delay line. */ + uint32_t dat6:6; /*[27:24] Data 6 delay line. */ + uint32_t dat7:6; /*[31:28] Data 7 delay line. */ + uint32_t dat8:6; /*[31:28] Data 7 delay line. */ + uint32_t dat9:6; /*[31:28] Data 7 delay line. */ + uint32_t spare:2; +}; + +struct sd_emmc_adjust{ + uint32_t cmd_delay:4; /*[3:0] Command delay line. */ + uint32_t ds_delay:4; /*[7:4] DS delay line. */ + uint32_t cali_sel:4; /*[11:8] Select one signal to be tested.*/ + /*Signals are labeled from 0 to 9 the same as delay lines. */ + uint32_t cali_enable:1; /*[12] Enable calibration. */ + uint32_t adj_enable:1; /*[13] Adjust interface timing by resampling the input signals. */ + uint32_t cali_rise:1; /*[14] 1: test the rising edge. 0: test the falling edge. */ + uint32_t ds_enable:1; /*[15] Sampling the DAT based on DS in HS400 mode*/ + uint32_t adj_delay:6; /*[21:16] Resample the input signals when clock index==adj_delay. */ + uint32_t adj_auto:1; /*[22] Use cali_dut first falling edge to adjust the timing */ + /*set cali_enable to 1 to use this function*/ + uint32_t reserved23:9; +}; + + +struct sd_emmc_calout{ + uint32_t cali_idx:6; /*[5:0] Calibration reading. The event happens at this index. */ + uint32_t reserved6:1; + uint32_t cali_vld:1; /*[7] The reading is valid. */ + uint32_t cali_setup:8; /*[15:8] Copied from BASE+0x8 [15:8] include cali_sel, cali_enable, adj_enable, cali_rise. */ + uint32_t reserved16:16; +}; + + +struct sd_emmc_start{ + uint32_t init:1; /*[0] 1: Read descriptor from internal SRAM, limited to 32 descriptors. */ + /* 0: Read descriptor from external DDR */ + uint32_t busy:1; /*[1] 1: Start command chain execution process. 0: Stop */ + uint32_t addr:30; /*[31:2] Descriptor address, the last 2 bits are 0, 4 bytes aligned. */ + /* When internal SRAM is used, the valid address range is from 0x200~0x3ff */ + /* When external DDR is used, the valid address is anywhere in DDR, the length of chain is unlimited.*/ +};//__attribute__((__may_alias__)); + + +struct sd_emmc_config{ + uint32_t bus_width:2; /*[1:0] 0: 1 bit, 1: 4 bits, 2: 8 bits, 3: 2 bits (not supported)*/ + uint32_t ddr:1; /*[2] 1: DDR mode, 0: SDR mode */ + uint32_t dc_ugt:1; /*[3] 1: DDR access urgent, 0: DDR access normal. */ + uint32_t bl_len:4; /*[7:4] Block length 2^cfg_bl_len, because internal buffer size is limited to 512 bytes, the cfg_bl_len <=9. */ + uint32_t resp_timeout:4; /*[11:8] Wait response till 2^cfg_resp_timeout core clock cycles. Maximum 32768 core cycles. */ + uint32_t rc_cc:4; /*[15:12] Wait response-command, command-command gap before next command, 2^cfg_rc_cc core clock cycles. */ + uint32_t out_fall:1; /*[16] DDR mode only. The command and TXD start from rising edge. Set 1 to start from falling edge. */ + uint32_t blk_gap_ip:1; /*[17] 1: Enable SDIO data block gap interrupt period. 0: Disabled.*/ + uint32_t spare:1; /*[18] Spare, ??? need check*/ + uint32_t ignore_owner:1; /*[19] Use this descriptor even if its owner bit is ¡°0¡±.*/ + uint32_t chk_ds:1; /*[20] Check data strobe in HS400.*/ + uint32_t cmd_low:1; /*[21] Hold CMD as output Low, eMMC boot mode.*/ + uint32_t stop_clk:1; /*[22] 1: stop clock. 0: normal clock.*/ + /*In normal mode, the clock is automatically on/off during reading mode to back off reading in case of*/ + /*DDR slow response, stop clock is used in voltage switch.*/ + uint32_t auto_clk:1; /*[23] 1: when BUS is idle and no descriptor is available, turn off clock, to save power.*/ + /* 0: core clock is always on.*/ + uint32_t txd_add_err:1; /*[24] TXD add error test*/ + /*Test feature, should not be used in normal condition.*/ + /*It will inverted the first CRC bits of the 3rd block.*/ + /*Block index starts from 0, 1, 2, ¡*/ + uint32_t txd_retry:1; /*[25] When TXD CRC error, host sends the block again.*/ + /*The total number of retries of one descriptor is limited to 15, */ + /*after 15 retries, the TXD_err is set to high.*/ + uint32_t revd:8; /*[31:26] reved*/ +};//__attribute__((__may_alias__)); + + +struct sd_emmc_irq_en{ + uint32_t rxd_err:8; /*[7:0] RX data CRC error per wire.*/ + uint32_t txd_err:1; /*[8] TX data CRC error. */ + uint32_t desc_err:1; /*[9] SD/eMMC controller doesn¡¯t own descriptor. */ + uint32_t resp_err:1; /*[10] Response CRC error.*/ + uint32_t resp_timeout:1; /*[11] No response received before time limit. */ + uint32_t desc_timeout:1; /*[12] Descriptor execution time over time limit. */ + uint32_t end_of_chain:1; /*[13] End of Chain IRQ. */ + uint32_t desc_irq:1; /*[14] This descriptor requests an IRQ. */ + uint32_t irq_sdio:1; /*[15] Enable sdio interrupt. */ + uint32_t revd:16; /*[31:16] reved*/ +}; + +struct sd_emmc_data_info{ + uint32_t cnt:10; /*[9:0] Rxd words received from BUS. Txd words received from DDR.*/ + uint32_t blk:9; /*[24:16] Rxd Blocks received from BUS. Txd blocks received from DDR.*/ + uint32_t revd:30; /*[31:17] Reved. */ +}; + + +struct sd_emmc_card_info{ + uint32_t txd_cnt:10; /*[9:0] Txd BUS cycle counter. */ + uint32_t txd_blk:9; /*[24:16] Txd BUS block counter.*/ + uint32_t revd:30; /*[31:17] Reved. */ +}; + +#endif
diff --git a/arch/arm/include/asm/arch-a1/ddr.h b/arch/arm/include/asm/arch-a1/ddr.h new file mode 100644 index 0000000..ad27855 --- /dev/null +++ b/arch/arm/include/asm/arch-a1/ddr.h
@@ -0,0 +1,100 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <config.h> +#include <io.h> +#include <stdint.h> +#include <asm/arch/ddr_define.h> + +/* io defines */ +//#define wr_reg(addr, data) (*((volatile uint32_t *)addr))=(uint32_t)(uint64_t)(data) +//#define rd_reg(addr) (*((volatile uint32_t *)(addr))) +#define wr_reg(addr, data) writel(data, addr) +#define rd_reg(addr) readl(addr) +/*clear [mask] 0 bits in [addr], set these 0 bits with [value] corresponding bits*/ +#define modify_reg(addr, value, mask) wr_reg(addr, ((rd_reg(addr) & (mask)) | (value))) +#define wait_set(addr, loc) do{}while(0 == (rd_reg(addr) & (1<<loc))); +#define wait_clr(addr, loc) do{}while(1 == (rd_reg(addr) & (1<<loc))); +#define wait_equal(addr, data) do{}while(data != (rd_reg(addr))); + +/* function defines */ +unsigned int ddr_init(void); +unsigned int ddr_init_pll(void); +unsigned int ddr_init_dmc(void); +unsigned int ddr_init_pctl(void); +unsigned int hot_boot(void); +void ddr_print_info(void); +void ddr_test(void); +void ddr_pre_init(void); +void ddr_debug(void); + +/* pctl status */ +#define UPCTL_STAT_MASK (7) +#define UPCTL_STAT_INIT (0) +#define UPCTL_STAT_CONFIG (1) +#define UPCTL_STAT_ACCESS (3) +#define UPCTL_STAT_LOW_POWER (5) + +/* pctl cmds */ +#define UPCTL_CMD_INIT (0) +#define UPCTL_CMD_CONFIG (1) +#define UPCTL_CMD_GO (2) +#define UPCTL_CMD_SLEEP (3) +#define UPCTL_CMD_WAKEUP (4) + +/* PUB PIR setting */ +#define PUB_PIR_INIT (1<<0) +#define PUB_PIR_ZCAL (1<<1) +#define PUB_PIR_CA (1<<2) +#define PUB_PIR_PLLINIT (1<<4) +#define PUB_PIR_DCAL (1<<5) +#define PUB_PIR_PHYRST (1<<6) +#define PUB_PIR_DRAMRST (1<<7) +#define PUB_PIR_DRAMINIT (1<<8) +#define PUB_PIR_WL (1<<9) +#define PUB_PIR_QSGATE (1<<10) +#define PUB_PIR_WLADJ (1<<11) +#define PUB_PIR_RDDSKW (1<<12) +#define PUB_PIR_WRDSKW (1<<13) +#define PUB_PIR_RDEYE (1<<14) +#define PUB_PIR_WREYE (1<<15) +#define PUB_PIR_ICPC (1<<16) +#define PUB_PIR_PLLBYP (1<<17) +#define PUB_PIR_CTLDINIT (1<<18) +#define PUB_PIR_RDIMMINIT (1<<19) +#define PUB_PIR_CLRSR (1<<27) +#define PUB_PIR_LOCKBYP (1<<28) +#define PUB_PIR_DCALBYP (1<<29) +#define PUB_PIR_ZCALBYP (1<<30) +#define PUB_PIR_INITBYP (1<<31) + +/* PHY initialize register (PIR) */ +#define DDR_PIR ((PUB_PIR_ZCAL) |\ + (PUB_PIR_PLLINIT) |\ + (PUB_PIR_DCAL) |\ + (PUB_PIR_PHYRST) |\ + (PUB_PIR_DRAMRST) |\ + (PUB_PIR_DRAMINIT) |\ + (PUB_PIR_WL) |\ + (PUB_PIR_QSGATE) |\ + (PUB_PIR_WLADJ) |\ + (PUB_PIR_RDDSKW) |\ + (PUB_PIR_WRDSKW) |\ + (PUB_PIR_RDEYE) |\ + (PUB_PIR_WREYE) \ + ) + +/* PHY general status register (PGSR0) */ +#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3) +#define DDR_PGSR0_CHECK() ((rd_reg(DDR0_PUB_PGSR0) != 0xC0000fff) && \ + (rd_reg(DDR0_PUB_PGSR0) != 0x80000fff)) +#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR2) +#define DDR_PGSR0_CHECK() +#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3) +#define DDR_PGSR0_CHECK() +#endif + +/* other regs */ +#define SCRATCH0 0xC1107D3C
diff --git a/arch/arm/include/asm/arch-a1/ddr_define.h b/arch/arm/include/asm/arch-a1/ddr_define.h new file mode 100644 index 0000000..2d2697e --- /dev/null +++ b/arch/arm/include/asm/arch-a1/ddr_define.h
@@ -0,0 +1,305 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#define CONFIG_BOARD_ID_MASK 0xFF +#define CONFIG_DDR_TYPE_DDR3 0 +#define CONFIG_DDR_TYPE_DDR4 1 +#define CONFIG_DDR_TYPE_LPDDR4 2 +#define CONFIG_DDR_TYPE_LPDDR3 3 +#define CONFIG_DDR_TYPE_LPDDR2 4 +#define CONFIG_DDR_TYPE_AUTO 0xf + +/* ddr channel defines */ +#define CONFIG_DDR0_16BIT 1 +#define CONFIG_DDR0_RANK0 2 +#define CONFIG_DDR0_RANK01 3 +#define CONFIG_DDR0_16BIT_2 4 +/* CONFIG_DDR_CHL_AUTO mode support RANK0 and RANK0+1 mode auto detect */ +#define CONFIG_DDR_CHL_AUTO 0xF +#define CONFIG_DDR0_16BIT_CH0 0x1 +#define CONFIG_DDR0_16BIT_RANK01_CH0 0x4 +#define CONFIG_DDR0_32BIT_RANK0_CH0 0x2 +#define CONFIG_DDR0_32BIT_RANK01_CH01 0x3 +#define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5 +#define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6 +#define CONFIG_DDR0_32BIT_RANK01_CH0 0x7 +#define CONFIG_DDR0_32BIT_RANK0_CH01 0x8 + +#define CFG_DDR_BASE_ADDR 0X0 +#define CFG_DDR_START_OFFSET 0X00000000 //TXLX SKIP 0MB + +/* ddr type identifier */ +#define CONFIG_DDR_TIMMING_LPDDR2 0x02 +#define CONFIG_DDR_TIMMING_LPDDR3 0x03 +#define CONFIG_DDR_TIMMING_DDR3_7 0x07 +#define CONFIG_DDR_TIMMING_DDR3_9 0x09 +#define CONFIG_DDR_TIMMING_DDR3_11 0x0B +#define CONFIG_DDR_TIMMING_DDR3_12 0x0C +#define CONFIG_DDR_TIMMING_DDR3_13 0x0D +#define CONFIG_DDR_TIMMING_DDR3_14 0x0E + +#define CONFIG_DDR_TIMMING_DDR4_1600 0x0F +#define CONFIG_DDR_TIMMING_DDR4_1866 0x10 +#define CONFIG_DDR_TIMMING_DDR4_2133 0x11 +#define CONFIG_DDR_TIMMING_DDR4_2400 0x12 +#define CONFIG_DDR_TIMMING_DDR4_2666 0x13 +#define CONFIG_DDR_TIMMING_DDR4_3200 0x14 + +#define LPDDR_DIE_ROW_COL_R13_C9 0 +#define LPDDR_DIE_ROW_COL_R14_C9 1 +#define LPDDR_DIE_ROW_COL_R14_C10 2 +#define LPDDR_DIE_ROW_COL_R13_C10 3 +#define LPDDR_DIE_ROW_COL_R14_C11 4 + +#define CONFIG_LPDDR3_CA_TRAINING_USE_LANE0 0 +#define CONFIG_LPDDR3_CA_TRAINING_USE_LANE1 1 +#define CONFIG_LPDDR3_CA_TRAINING_USE_LANE2 2 +#define CONFIG_LPDDR3_CA_TRAINING_USE_LANE3 3 + +#define CONFIG_DDR_FUNC_TEST (1<<0) + +#define CONFIG_DDR_INIT_RETRY_TOTAL (10) +#define CONFIG_DDR_PCTL_RETRY_TOTAL (100) + +#define DDR_USE_1_RANK(chl_set) ((chl_set == CONFIG_DDR0_RANK0) || \ + (chl_set == CONFIG_DDR0_16BIT)) +#define DDR_USE_2_RANK(chl_set) ((chl_set == CONFIG_DDR0_RANK01)) + +#define DMC_TEST_SLT_ENABLE_DDR_AUTO_FAST_BOOT 1<<5 +#define DMC_TEST_SLT_ENABLE_DDR_AUTO_WINDOW_TEST 1<<4 +/* DMC_DDR_CTRL defines */ +#define DDR_DDR4_ENABLE (1<<22) +#define DDR_RANK1_ENABLE (1<<21) +#define DDR_DDR4_BG_ENABLE (1<<20) +#define DDR_16BIT_ENABLE (1<<16) + +#define DDR_RANK1_SIZE_CTRL (3) +#define DDR_RANK0_SIZE_CTRL (0) + +/* dram cfg magic */ +#define DRAM_CFG_MAGIC 0x2e676663 + +#define DMC_TEST_SLT_SCAN_FREQUENCY 1 +#define DMC_TEST_SLT_OFFSET_DELAY (1<<1) +#define DMC_TEST_SLT_ENABLE_DDR_SKIP_TRAINING (1<<6) +#define DMC_TEST_SLT_ENABLE_DDR_DVFS (1<<7) + +/* ddr configs */ +#define DDR_RFC_TYPE_DDR3_512Mbx1 0 +#define DDR_RFC_TYPE_DDR3_512Mbx2 1 +#define DDR_RFC_TYPE_DDR3_512Mbx4 2 +#define DDR_RFC_TYPE_DDR3_512Mbx8 3 +#define DDR_RFC_TYPE_DDR3_512Mbx16 4 +#define DDR_RFC_TYPE_DDR4_2Gbx1 5 +#define DDR_RFC_TYPE_DDR4_2Gbx2 6 +#define DDR_RFC_TYPE_DDR4_2Gbx4 7 +#define DDR_RFC_TYPE_DDR4_2Gbx8 8 + +#define DDR_RFC_TYPE_LPDDR4_2Gbx1 9 +#define DDR_RFC_TYPE_LPDDR4_3Gbx1 10 +#define DDR_RFC_TYPE_LPDDR4_4Gbx1 11 +#define DDR_RFC_TYPE_LPDDR4_6Gbx1 12 +#define DDR_RFC_TYPE_LPDDR4_8Gbx1 13 + +#define DDR_ENABLE_FINE_TUNE_FLAG_AC_DELAY (1<<0) +#define DDR_ENABLE_FINE_TUNE_FLAG_WRITE_DQS (1<<1) +#define DDR_ENABLE_FINE_TUNE_FLAG_READ_DQS (1<<2) +#define DDR_ENABLE_FINE_TUNE_FLAG_WRITE_DQ (1<<3) +#define DDR_ENABLE_FINE_TUNE_FLAG_READ_DQ (1<<4) + +/* lpddr3 defines */ +#ifndef CONFIG_LPDDR_REMAP_SET +#define CONFIG_LPDDR_REMAP_SET LPDDR_DIE_ROW_COL_R14_C9 +#endif + +/* how to add a new ddr function? + 1. add CONFIG_DDR_FUNC_XXX in (config).h file + 2. add define in this file. + 2.1 add + #ifndef CONFIG_DDR_FUNC_XXX + #define CONFIG_DDR_FUNC_XXX 0 + #endif + 2.2 add + #define DDR_FUNC_XXX (CONFIG_FUNC_XXX<<X) + 2.3 add DDR_FUNC_XXX |\ in DDR_FUNC + 3. add same define and parser in bl2 code + */ +/* 2.1, 2,2, 2,3 example */ +/* +#ifndef CONFIG_CMD_DDR_D2PLL +#define CONFIG_CMD_DDR_D2PLL 0 +#endif +#define DDR_FUNC_D2PLL (CONFIG_CMD_DDR_D2PLL<<0) +#define DDR_FUNC (EXISTING_FUNCTIONS) |\ + (DDR_FUNC_D2PLL) +*/ + +/* d2pll support */ +#ifndef CONFIG_CMD_DDR_D2PLL +#define CONFIG_CMD_DDR_D2PLL 0 +#endif +#define DDR_FUNC_D2PLL (CONFIG_CMD_DDR_D2PLL<<0) + +/* ddr low power function support */ +#ifndef CONFIG_DDR_LOW_POWER +#define CONFIG_DDR_LOW_POWER 0 +#endif +#define DDR_FUNC_LP (CONFIG_DDR_LOW_POWER<<1) + +/* ddr zq power down support */ +#ifndef CONFIG_DDR_ZQ_PD +#define CONFIG_DDR_ZQ_PD 0 +#endif +#define DDR_FUNC_ZQ_PD (CONFIG_DDR_ZQ_PD<<2) + +/* ddr vref function */ +#ifndef CONFIG_DDR_USE_EXT_VREF +#define CONFIG_DDR_USE_EXT_VREF 0 +#endif +#define DDR_FUNC_EXT_VREF (CONFIG_DDR_USE_EXT_VREF<<3) + +/* ddr4 timing test function */ +#ifndef CONFIG_DDR4_TIMING_TEST +#define CONFIG_DDR4_TIMING_TEST 0 +#endif +#define DDR_FUNC_DDR4_TIMING_TEST (CONFIG_DDR4_TIMING_TEST<<4) + +/* ddr pll bypass */ +#ifndef CONFIG_DDR_PLL_BYPASS +#define CONFIG_DDR_PLL_BYPASS 0 +#endif +#define DDR_FUNC_DDR_PLL_BYPASS (CONFIG_DDR_PLL_BYPASS<<5) + +/* ddr rdbi function */ +#ifndef CONFIG_DDR_FUNC_RDBI +#define CONFIG_DDR_FUNC_RDBI 0 +#endif +#define DDR_FUNC_RDBI (CONFIG_DDR_FUNC_RDBI<<6) + +/* lpddr3 ca trainingi function */ +#ifndef CONFIG_DDR_FUNC_LPDDR3_CA +#define CONFIG_DDR_FUNC_LPDDR3_CA 0 +#endif +#define DDR_FUNC_LPDDR3_CA (CONFIG_DDR_FUNC_LPDDR3_CA<<7) + +/* print ddr training window */ +#ifndef CONFIG_DDR_FUNC_PRINT_WINDOW +#define CONFIG_DDR_FUNC_PRINT_WINDOW 0 +#endif +#define DDR_FUNC_PRINT_WINDOW (CONFIG_DDR_FUNC_PRINT_WINDOW<<8) + + +/* print ddr training window */ +//#ifndef CONFIG_DDR_FULL_TEST +//#define CONFIG_DDR_FULL_TEST 0 +//#endif +//#define DDR_FULL_TEST (CONFIG_DDR_FULL_TEST<<10) + +/* non-sec region scramble function */ +#ifndef CONFIG_DDR_NONSEC_SCRAMBLE +#define CONFIG_DDR_NONSEC_SCRAMBLE 0 +#endif +#define DDR_NONSEC_SCRAMBLE (CONFIG_DDR_NONSEC_SCRAMBLE<<11) + +#if(CONFIG_DDR_FUNC_LPDDR3_CA==1) +#if (CONFIG_LPDDR3_CA_TRAINING_CA0==CONFIG_LPDDR3_CA_TRAINING_USE_LANE0) +#define DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT0 (0<<20) +#define DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT1 (0<<21) +#elif (CONFIG_LPDDR3_CA_TRAINING_CA0==CONFIG_LPDDR3_CA_TRAINING_USE_LANE1) +#define DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT0 (1<<20) +#define DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT1 (0<<21) +#elif (CONFIG_LPDDR3_CA_TRAINING_CA0==CONFIG_LPDDR3_CA_TRAINING_USE_LANE2) +#define DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT0 (0<<20) +#define DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT1 (1<<21) +#elif (CONFIG_LPDDR3_CA_TRAINING_CA0==CONFIG_LPDDR3_CA_TRAINING_USE_LANE3) +#define DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT0 (1<<20) +#define DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT1 (1<<21) +#endif +#if (CONFIG_LPDDR3_CA_TRAINING_CA1==CONFIG_LPDDR3_CA_TRAINING_USE_LANE0) +#define DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT0 (0<<22) +#define DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT1 (0<<23) +#elif (CONFIG_LPDDR3_CA_TRAINING_CA1==CONFIG_LPDDR3_CA_TRAINING_USE_LANE1) +#define DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT0 (1<<22) +#define DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT1 (0<<23) +#elif (CONFIG_LPDDR3_CA_TRAINING_CA1==CONFIG_LPDDR3_CA_TRAINING_USE_LANE2) +#define DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT0 (0<<22) +#define DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT1 (1<<23) +#elif (CONFIG_LPDDR3_CA_TRAINING_CA1==CONFIG_LPDDR3_CA_TRAINING_USE_LANE3) +#define DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT0 (1<<22) +#define DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT1 (1<<23) +#endif +#else /* CONFIG_DDR_FUNC_LPDDR3_CA != 1 */ +#define DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT0 (0<<20) +#define DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT1 (0<<21) +#define DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT0 (0<<22) +#define DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT1 (0<<23) +#endif /* CONFIG_DDR_FUNC_LPDDR3_CA */ + +#if(CONFIG_DDR_FUNC_LPDDR3_SOC_ODT_ONLY_UP==1) +#define DDR_FUNC_LPDDR3_SOC_ODT_ONLY_UP (1<<25) +#else +#define DDR_FUNC_LPDDR3_SOC_ODT_ONLY_UP (0<<25) +#endif +#define DDR_FUNC_FAST_BOOT_CHECK_CHIP_ID (1<<30) +#define DDR_FUNC_CONFIG_DFE_FUNCTION (1<<29) +#define DDR_FUNC_CONFIG_DDR_DVFS_FUNCTION (1<<28) +#define DDR_FUNC (DDR_FUNC_D2PLL | \ + DDR_FUNC_LP | \ + DDR_FUNC_ZQ_PD | \ + DDR_FUNC_EXT_VREF | \ + DDR_FUNC_DDR4_TIMING_TEST | \ + DDR_FUNC_DDR_PLL_BYPASS | \ + DDR_FUNC_RDBI | \ + DDR_FUNC_LPDDR3_CA | \ + DDR_FUNC_PRINT_WINDOW | \ + DDR_FULL_TEST | \ + DDR_NONSEC_SCRAMBLE | \ + DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT0| \ + DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT1| \ + DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT0| \ + DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT1| \ + DDR_FUNC_LPDDR3_SOC_ODT_ONLY_UP | \ + (1 << 31) \ + ) + + + + +/* bl2 reg override stages define */ +#define BL2_INIT_STAGE_0 0 +#define BL2_INIT_STAGE_1 1 +#define BL2_INIT_STAGE_2 2 +#define BL2_INIT_STAGE_3 3 +#define BL2_INIT_STAGE_4 4 +#define BL2_INIT_STAGE_5 5 +#define BL2_INIT_STAGE_6 6 +#define BL2_INIT_STAGE_7 7 +#define BL2_INIT_STAGE_8 8 +#define BL2_INIT_STAGE_9 9 + + +/* ddr reg override stages define */ +#define DDR_OVERRIDE_STAGE_DDR3_PRE_INIT 0x10 +#define DDR_OVERRIDE_STAGE_DDR3_DMC_INIT 0x11 + +#define DDR_OVERRIDE_STAGE_DDR4_PRE_INIT 0x20 +#define DDR_OVERRIDE_STAGE_DDR4_DMC_INIT 0x21 + +#define DDR_OVERRIDE_STAGE_LPDDR3_PRE_INIT 0x30 +#define DDR_OVERRIDE_STAGE_LPDDR3_DMC_INIT 0x31 + +#define DDR_OVERRIDE_STAGE_LPDDR4_PRE_INIT 0x40 +#define DDR_OVERRIDE_STAGE_LPDDR4_DMC_INIT 0x41 + + +#define DWC_AC_PINMUX_TOTAL 28 +#define DWC_DFI_PINMUX_TOTAL 26 +#define DWC_DQ_PINMUX_TOTAL 32 + +/* diagnose function defines */ +#define CONFIG_DIAGNOSE_DISABLE 0x0 +#define CONFIG_DIAGNOSE_1D 0x1 +#define CONFIG_DIAGNOSE_2D 0x2 +#define CONFIG_DIAGNOSE_1D_2D 0x3
diff --git a/arch/arm/include/asm/arch-a1/efuse.h b/arch/arm/include/asm/arch-a1/efuse.h new file mode 100644 index 0000000..4a68e88 --- /dev/null +++ b/arch/arm/include/asm/arch-a1/efuse.h
@@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __EFUSE_H +#define __EFUSE_H + +#include <config.h> +#include <common.h> + +/* efuse HAL_API arg */ +struct efuse_hal_api_arg { + unsigned int cmd; /* R/W */ + unsigned int offset; + unsigned int size; + unsigned long buffer_phy; + unsigned long retcnt_phy; +}; + + +#define EFUSE_BYTES 512 /* (EFUSE_BITS/8) */ + +#define EFUSE_HAL_API_READ 0 +#define EFUSE_HAL_API_WRITE 1 +#define EFUSE_HAL_API_WRITE_PATTERN 2 +#define EFUSE_HAL_API_USER_MAX 3 + +#define EFUSE_USER_MASK (0x1 << 16) +#define EFUSE_THERMAL_MASK (0x1 << 17) +#define EFUSE_THERMAL_VERFLAG_MASK (0x1 << 18) +#define EFUSE_ENCRYPT_MASK (0x1 << 19) + +//#define ASSIST_HW_REV 0x1f53 + +int efuse_read_usr(char *buf, size_t count, loff_t *ppos); +int efuse_write_usr(char *buf, size_t count, loff_t *ppos); +uint32_t efuse_get_max(void); +ssize_t efuse_read(char *buf, size_t count, loff_t *ppos); +ssize_t efuse_write(const char *buf, size_t count, loff_t *ppos); + +int32_t meson_trustzone_efuse(struct efuse_hal_api_arg *arg); +int32_t meson_trustzone_efuse_get_max(struct efuse_hal_api_arg *arg); + +#endif +
diff --git a/arch/arm/include/asm/arch-a1/eth_setup.h b/arch/arm/include/asm/arch-a1/eth_setup.h new file mode 100644 index 0000000..6e643f6 --- /dev/null +++ b/arch/arm/include/asm/arch-a1/eth_setup.h
@@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <asm/arch/io.h> + +/* + *board configuration interface. + * */ +struct eth_clock_conf{ + int enable; + int clock_50MHZ_phase; + //add ... as you need. +}; + +struct eth_board_socket{ +char *name ; +int (*eth_clock_configure)(struct eth_clock_conf); +int (*eth_pinmux_setup)(void); +int (*eth_hw_reset)(void); + +}; + + + +/* + *clock define part + */ + +#define ETH_BASE (0xff3f0000) +#define ETH_PLL_CNTL CBUS_REG_ADDR(0x2050) + /* Ethernet ctrl */ +#define ETH_PLL_CNTL_DIVEN (1<<0) +#define ETH_PLL_CNTL_MACSPD (1<<1) +#define ETH_PLL_CNTL_DATEND (1<<2) +#define ETH_PLL_CNTL_DESEND (1<<3) + + +/* + please refer following doc for detail + @AppNote-M3-ClockTrees.docx + + select clk: -> CBUS_REG(0x1076) + + 7-sys_pll_div2 + 6-vid2_pll_clk + 5-vid_pll_clk + 4-aud_pll_clk + 3-ddr_pll_clk + 2-misc_pll_clk + 1-sys_pll_clk + 0-XTAL + + clk_freq:800MHz + output_clk:50MHz + aways,maybe changed for others? +*/ + +#define ETH_CLKSRC_XTAL (0) +#define ETH_CLKSRC_SYS_PLL_CLK (1) +#define ETH_CLKSRC_MISC_PLL_CLK (2) +#define ETH_CLKSRC_DDR_PLL_CLK (3) +#define ETH_CLKSRC_AUD_PLL_CLK ( +#define ETH_CLKSRC_VID_PLL_CLK (5) +#define ETH_CLKSRC_VID2_PLL_CLK (6) +#define ETH_CLKSRC_SYS_PLL_DIV2_CLK (7) +#define CLK_1M (1000000) + +typedef union eth_aml_reg0 { + /** raw register data */ + unsigned int d32; + /** register bits */ + struct { + unsigned phy_intf_sel:3; + unsigned rx_clk_rmii_invert:1; + unsigned rgmii_tx_clk_src:1; + unsigned rgmii_tx_clk_phase:2; + unsigned rgmii_tx_clk_ratio:3; + unsigned phy_ref_clk_enable:1; + unsigned clk_rmii_i_invert:1; + unsigned clk_en:1; + unsigned adj_enable:1; + unsigned adj_setup:1; + unsigned adj_delay:5; + unsigned adj_skew:5; + unsigned cali_start:1; + unsigned cali_rise:1; + unsigned cali_sel:3; + unsigned rgmii_rx_reuse:1; + unsigned eth_urgent:1; + } b; +} eth_aml_reg0_t; + +#define ETH_VALIDE_CLKSRC(clk,out_clk) ((clk%out_clk)==0) + +int eth_clk_set(int selectclk,unsigned long clk_freq,unsigned long out_clk); +
diff --git a/arch/arm/include/asm/arch-a1/gpio.h b/arch/arm/include/asm/arch-a1/gpio.h new file mode 100644 index 0000000..2467368 --- /dev/null +++ b/arch/arm/include/asm/arch-a1/gpio.h
@@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __ASM_ARCH_MESON_GPIO_H +#define __ASM_ARCH_MESON_GPIO_H + + +#endif /* __ASM_ARCH_MESON_GPIO_H */
diff --git a/arch/arm/include/asm/arch-a1/i2c.h b/arch/arm/include/asm/arch-a1/i2c.h new file mode 100644 index 0000000..a93a09d --- /dev/null +++ b/arch/arm/include/asm/arch-a1/i2c.h
@@ -0,0 +1,280 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __AML_MACH_I2C__ +#define __AML_MACH_I2C__ + +#include <asm/io.h> +#include <asm/arch/secure_apb.h> + +/** + * struct i2c_msg - an I2C transaction segment beginning with START + * @addr: Slave address, either seven or ten bits. When this is a ten + * bit address, I2C_M_TEN must be set in @flags and the adapter + * must support I2C_FUNC_10BIT_ADDR. + * @flags: I2C_M_RD is handled by all adapters. No other flags may be + * provided unless the adapter exported the relevant I2C_FUNC_* + * flags through i2c_check_functionality(). + * @len: Number of data bytes in @buf being read from or written to the + * I2C slave address. For read transactions where I2C_M_RECV_LEN + * is set, the caller guarantees that this buffer can hold up to + * 32 bytes in addition to the initial length byte sent by the + * slave (plus, if used, the SMBus PEC); and this value will be + * incremented by the number of block data bytes received. + * @buf: The buffer into which data is read, or from which it's written. + * + * An i2c_msg is the low level representation of one segment of an I2C + * transaction. It is visible to drivers in the @i2c_transfer() procedure, + * to userspace from i2c-dev, and to I2C adapter drivers through the + * @i2c_adapter.@master_xfer() method. + * + * Except when I2C "protocol mangling" is used, all I2C adapters implement + * the standard rules for I2C transactions. Each transaction begins with a + * START. That is followed by the slave address, and a bit encoding read + * versus write. Then follow all the data bytes, possibly including a byte + * with SMBus PEC. The transfer terminates with a NAK, or when all those + * bytes have been transferred and ACKed. If this is the last message in a + * group, it is followed by a STOP. Otherwise it is followed by the next + * @i2c_msg transaction segment, beginning with a (repeated) START. + * + * Alternatively, when the adapter supports I2C_FUNC_PROTOCOL_MANGLING then + * passing certain @flags may have changed those standard protocol behaviors. + * Those flags are only for use with broken/nonconforming slaves, and with + * adapters which are known to support the specific mangling options they + * need (one or more of IGNORE_NAK, NO_RD_ACK, NOSTART, and REV_DIR_ADDR). + */ +struct i2c_msg { + __u16 addr; /* slave address */ + __u16 flags; +#define I2C_M_TEN 0x0010 /* this is a ten bit chip address */ +#define I2C_M_RD 0x0001 /* read data, from slave to master */ +#define I2C_M_NOSTART 0x4000 /* if I2C_FUNC_PROTOCOL_MANGLING */ +#define I2C_M_REV_DIR_ADDR 0x2000 /* if I2C_FUNC_PROTOCOL_MANGLING */ +#define I2C_M_IGNORE_NAK 0x1000 /* if I2C_FUNC_PROTOCOL_MANGLING */ +#define I2C_M_NO_RD_ACK 0x0800 /* if I2C_FUNC_PROTOCOL_MANGLING */ +#define I2C_M_RECV_LEN 0x0400 /* length will be first received byte */ + __u16 len; /* msg length */ + __u8 *buf; /* pointer to msg data */ +}; + +#define MESON_I2C_MASTER_AO_START (AO_I2C_M_0_CONTROL_REG) +//#define MESON_I2C_MASTER_AO_END (0xc810051c+5) + +#define MESON_I2C_MASTER_A_START CBUS_REG_ADDR(I2C_M_0_CONTROL_REG) +#define MESON_I2C_MASTER_A_END (CBUS_REG_ADDR(I2C_M_0_RDATA_REG1+1)-1) + +#define MESON_I2C_MASTER_B_START CBUS_REG_ADDR(I2C_M_1_CONTROL_REG) +#define MESON_I2C_MASTER_B_END (CBUS_REG_ADDR(I2C_M_1_RDATA_REG1+1)-1) + +#define MESON_I2C_MASTER_C_START CBUS_REG_ADDR(I2C_M_2_CONTROL_REG) +#define MESON_I2C_MASTER_C_END (CBUS_REG_ADDR(I2C_M_2_RDATA_REG1+1)-1) + +#define MESON_I2C_MASTER_D_START CBUS_REG_ADDR(I2C_M_3_CONTROL_REG) +#define MESON_I2C_MASTER_D_END (CBUS_REG_ADDR(I2C_M_3_RDATA_REG1+1)-1) + +#define MESON_I2C_SLAVE_START CBUS_REG_ADDR(I2C_S_CONTROL_REG) +#define MESON_I2C_SLAVE_END (CBUS_REG_ADDR(I2C_S_CNTL1_REG+1)-1) + + +#define AML_I2C_MASTER_AO 0 +#define AML_I2C_MASTER_A 1 +#define AML_I2C_MASTER_B 2 +#define AML_I2C_MASTER_C 3 +#define AML_I2C_MASTER_D 4 + + +#define AML_I2C_SLAVE_ADDR 0x6c + +/*M1 i2c pinmux + * I/O I2C_MASTER_A I2C_MASTER_B I2C_SLAVE + * GPIO_JTAG_TMS SCK_A REG1[12] SCK_A REG1[13] + * GPIO_JTAG_TDI SDA_A REG1[12] SDA_A REG1[13] + * GPIO_JTAG_TCK SCK_B REG1[16] SCK_A REG1[17] + * GPIO_JTAG_TDO SDA_B REG1[20] SDA_A REG1[21] + * GPIOB_0 SCK_B REG2[5] SCK_A REG2[6] + * GPIOB_1 SDA_B REG2[2] SDA_A REG2[3] + * GPIOB_2 SCK_A REGS[13] SCK_A REG2[14] + * GPIOB_3 SDA_A REG2[9] SDA_A REG2[10] + * GPIOC_13 SCK_B REG3[28] SCK_A REG3[29] + * GPIOC_14 SDA_B REG3[25] SDA_A REG3[26] + * GPIOC_21 SCK_A REG7[9] SCK_A REG7[10] + * GPIOC_22 SDA_A REG7[6] SDA_A REG7[7] + * GPIOE_16 SCK_B REG5[27] SCK_A REG5[28] + * GPIOE_17 SDA_B REG5[25] SDA_A REG5[26] +*/ + +/*i2c master a*/ + + +#define MESON_I2C_MASTER_A_GPIOZ_17_REG (PERIPHS_PIN_MUX_9) +#define MESON_I2C_MASTER_A_GPIOZ_17_BIT (1<<7) +#define MESON_I2C_MASTER_A_GPIOZ_18_REG (PERIPHS_PIN_MUX_9) +#define MESON_I2C_MASTER_A_GPIOZ_18_BIT (1<<8) + +#define MESON_I2C_MASTER_A_GPIOW_0_REG (PERIPHS_PIN_MUX_5) +#define MESON_I2C_MASTER_A_GPIOW_0_BIT (1<<22) +#define MESON_I2C_MASTER_A_GPIOW_1_REG (PERIPHS_PIN_MUX_5) +#define MESON_I2C_MASTER_A_GPIOW_1_BIT (1<<23) + +/*i2c master b*/ + + +#define MESON_I2C_MASTER_B_GPIOH_3_REG (PERIPHS_PIN_MUX_7) +#define MESON_I2C_MASTER_B_GPIOH_3_BIT (1<<6) +#define MESON_I2C_MASTER_B_GPIOH_4_REG (PERIPHS_PIN_MUX_7) +#define MESON_I2C_MASTER_B_GPIOH_4_BIT (1<<7) + +#define MESON_I2C_MASTER_B_GPIOY_12_REG (PERIPHS_PIN_MUX_10) +#define MESON_I2C_MASTER_B_GPIOY_12_BIT (1<<14) +#define MESON_I2C_MASTER_B_GPIOY_13_REG (PERIPHS_PIN_MUX_10) +#define MESON_I2C_MASTER_B_GPIOY_13_BIT (1<<15) + +/*i2c master c*/ +#define MESON_I2C_MASTER_C_GPIOY_7_REG (PERIPHS_PIN_MUX_4) +#define MESON_I2C_MASTER_C_GPIOY_7_BIT (1<<28) +#define MESON_I2C_MASTER_C_GPIOY_8_REG (PERIPHS_PIN_MUX_4) +#define MESON_I2C_MASTER_C_GPIOY_8_BIT (1<<29) + +#define MESON_I2C_MASTER_C_GPIOX_0_REG (PERIPHS_PIN_MUX_1) +#define MESON_I2C_MASTER_C_GPIOX_0_BIT (1<<22) +#define MESON_I2C_MASTER_C_GPIOX_1_REG (PERIPHS_PIN_MUX_1) +#define MESON_I2C_MASTER_C_GPIOX_1_BIT (1<<23) + +/*i2c master d*/ + + +#define MESON_I2C_MASTER_D_GPIOY_10_REG (PERIPHS_PIN_MUX_10) +#define MESON_I2C_MASTER_D_GPIOY_10_BIT (1<<10) +#define MESON_I2C_MASTER_D_GPIOY_11_REG (PERIPHS_PIN_MUX_10) +#define MESON_I2C_MASTER_D_GPIOY_11_BIT (1<<11) + +#define MESON_I2C_MASTER_D_GPIOH_5_REG (PERIPHS_PIN_MUX_7) +#define MESON_I2C_MASTER_D_GPIOH_5_BIT (1<<23) +#define MESON_I2C_MASTER_D_GPIOH_6_REG (PERIPHS_PIN_MUX_7) +#define MESON_I2C_MASTER_D_GPIOH_6_BIT (1<<24) + +/*i2c master AO*/ + + +#define MESON_I2C_MASTER_AO_GPIOAO_4_REG (P_AO_RTI_PINMUX_REG0) /* P_AO_RTI_PIN_MUX_REG */ +#define MESON_I2C_MASTER_AO_GPIOAO_4_BIT (1<<8) +#define MESON_I2C_MASTER_AO_GPIOAO_5_REG (P_AO_RTI_PINMUX_REG0) /* P_AO_RTI_PIN_MUX_REG */ +#define MESON_I2C_MASTER_AO_GPIOAO_5_BIT (1<<9) + +/*i2c slave*/ +#define MESON_I2C_SLAVE_JTAG_TMS_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_1) +#define MESON_I2C_SLAVE_JTAG_TMS_BIT (1<<13) +#define MESON_I2C_SLAVE_JTAG_TDI_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_1) +#define MESON_I2C_SLAVE_JTAG_TDI_BIT (1<<13) + +#define MESON_I2C_SLAVE_GPIOB_2_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_2) +#define MESON_I2C_SLAVE_GPIOB_2_BIT (1<<14) +#define MESON_I2C_SLAVE_GPIOB_3_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_2) +#define MESON_I2C_SLAVE_GPIOB_3_BIT (1<<10) + +#define MESON_I2C_SLAVE_GPIOC_21_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_7) +#define MESON_I2C_SLAVE_GPIOC_21_BIT (1<<10) +#define MESON_I2C_SLAVE_GPIOC_22_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_7) +#define MESON_I2C_SLAVE_GPIOC_22_BIT (1<<7) + +#define MESON_I2C_SLAVE_JTAG_TCK_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_1) +#define MESON_I2C_SLAVE_JTAG_TCK_BIT (1<<17) +#define MESON_I2C_SLAVE_JTAG_TDO_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_1) +#define MESON_I2C_SLAVE_JTAG_TDO_BIT (1<<21) + +#define MESON_I2C_SLAVE_GPIOB_0_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_2) +#define MESON_I2C_SLAVE_GPIOB_0_BIT (1<<6) +#define MESON_I2C_SLAVE_GPIOB_1_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_2) +#define MESON_I2C_SLAVE_GPIOB_1_BIT (1<<3) + +#define MESON_I2C_SLAVE_GPIOC_13_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_3) +#define MESON_I2C_SLAVE_GPIOC_13_BIT (1<<29) +#define MESON_I2C_SLAVE_GPIOC_14_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_3) +#define MESON_I2C_SLAVE_GPIOC_14_BIT (1<<26) + +#define MESON_I2C_SLAVE_GPIOC_16_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_5) +#define MESON_I2C_SLAVE_GPIOC_16_BIT (1<<28) +#define MESON_I2C_SLAVE_GPIOC_17_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_5) +#define MESON_I2C_SLAVE_GPIOC_17_BIT (1<<26) + + +#define AML_I2C_SPPED_50K 50000 +#define AML_I2C_SPPED_100K 100000 +#define AML_I2C_SPPED_200K 200000 +#define AML_I2C_SPPED_300K 300000 +#define AML_I2C_SPPED_400K 400000 + +struct aml_pinmux_reg_bit { + unsigned long scl_reg; + unsigned long sda_reg; + unsigned int scl_bit; + unsigned int sda_bit; +}; + +struct aml_i2c_platform{ + unsigned int slave_addr;/*7bit addr*/ + unsigned int wait_count;/*i2c wait ack timeout = + wait_count * wait_ack_interval */ + unsigned int wait_ack_interval; + unsigned int wait_read_interval; + unsigned int wait_xfer_interval; + unsigned int master_no; + unsigned int use_pio;/*0: hardware i2c, 1: manual pio i2c*/ + unsigned int master_i2c_speed; + + /* only need 1 i2c master to comunicate with several devices, + * should I prepare 2 master interface to use simultaneously?*/ + struct resource * resource; + struct aml_pinmux_reg_bit master_ao_pinmux; + struct aml_pinmux_reg_bit master_a_pinmux; + struct aml_pinmux_reg_bit master_b_pinmux; + struct aml_pinmux_reg_bit master_c_pinmux; + struct aml_pinmux_reg_bit master_d_pinmux; + + struct aml_pinmux_reg_bit slave_reg_bit; +}; + +/**************i2c software gpio***************/ + +#define MESON_I2C_PREG_GPIOC_OE CBUS_REG_ADDR(PREG_FGPIO_EN_N) +#define MESON_I2C_PREG_GPIOC_OUTLVL CBUS_REG_ADDR(PREG_FGPIO_O) +#define MESON_I2C_PREG_GPIOC_INLVL CBUS_REG_ADDR(PREG_FGPIO_I) + +#define MESON_I2C_PREG_GPIOE_OE CBUS_REG_ADDR(PREG_HGPIO_EN_N) +#define MESON_I2C_PREG_GPIOE_OUTLVL CBUS_REG_ADDR(PREG_HGPIO_O) +#define MESON_I2C_PREG_GPIOE_INLVL CBUS_REG_ADDR(PREG_HGPIO_I) + +#define MESON_I2C_PREG_GPIOA_OE CBUS_REG_ADDR(PREG_EGPIO_EN_N) +#define MESON_I2C_PREG_GPIOA_OUTLVL CBUS_REG_ADDR(PREG_EGPIO_O) +#define MESON_I2C_PREG_GPIOA_INLVL CBUS_REG_ADDR(PREG_EGPIO_I) + +struct aml_sw_i2c_pins +{ + unsigned int scl_reg_out; + unsigned int scl_reg_in; + unsigned int scl_bit; + unsigned int scl_oe; + unsigned int sda_reg_out; + unsigned int sda_reg_in; + unsigned int sda_bit; + unsigned int sda_oe; +}; + + +struct aml_sw_i2c_platform { + struct aml_sw_i2c_pins sw_pins; + + /* local settings */ + int udelay; /* half clock cycle time in us, + minimum 2 us for fast-mode I2C, + minimum 5 us for standard-mode I2C and SMBus, + maximum 50 us for SMBus */ + int timeout; /* in jiffies */ +}; + + +#endif //__AML_MACH_I2C__ + +
diff --git a/arch/arm/include/asm/arch-a1/io.h b/arch/arm/include/asm/arch-a1/io.h new file mode 100644 index 0000000..fd3981a --- /dev/null +++ b/arch/arm/include/asm/arch-a1/io.h
@@ -0,0 +1,102 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __MACH_MESSON_REGS_IO_H +#define __MACH_MESSON_REGS_IO_H + +#ifndef __ASSEMBLY__ + +#include <asm/io.h> +#define IO_CBUS_BASE (0xFFD00000L) +#define IO_AXI_BUS_BASE (0xFFB00000L) /* gpv */ +#define IO_AHB_BUS_BASE (0xFF500000L) /* usb0 */ +#define IO_APB_BUS_BASE (0xFFFC0000L) /* AHB SRAM, sec/sys ahb? txlx_mem_map.xlsx */ +#define IO_APB_HDMI_BUS_BASE (0xFFE00000L) /* */ +#define IO_VPU_BUS_BASE (0xFF900000L) /* VPU */ + +#define CBUS_REG_OFFSET(reg) ((reg) << 2) +#define CBUS_REG_ADDR(reg) (IO_CBUS_BASE + CBUS_REG_OFFSET(reg)) + +#define AXI_REG_OFFSET(reg) ((reg) << 2) +#define AXI_REG_ADDR(reg) (IO_AXI_BUS_BASE + AXI_REG_OFFSET(reg)) + +#define AHB_REG_OFFSET(reg) ((reg) << 2) +#define AHB_REG_ADDR(reg) (IO_AHB_BUS_BASE + AHB_REG_OFFSET(reg)) + +#define VPU_REG_OFFSET(reg) ((reg) << 2) +#define VPU_REG_ADDR(reg) (IO_VPU_BUS_BASE + VPU_REG_OFFSET(reg)) + + +#define APB_REG_OFFSET(reg) (reg) +#define APB_REG_ADDR(reg) (IO_APB_BUS_BASE + APB_REG_OFFSET(reg)) +#define APB_REG_ADDR_VALID(reg) (((unsigned long)(reg) & 3) == 0) + +#define APB_HDMI_REG_OFFSET(reg) (reg) +#define APB_HDMI_REG_ADDR(reg) (IO_APB_HDMI_BUS_BASE + APB_HDMI_REG_OFFSET(reg)) +#define APB_HDMI_REG_ADDR_VALID(reg) (((unsigned long)(reg) & 3) == 0) + + +#define WRITE_CBUS_REG(reg, val) __raw_writel(val, CBUS_REG_ADDR(reg)) +#define READ_CBUS_REG(reg) (__raw_readl(CBUS_REG_ADDR(reg))) +#define WRITE_CBUS_REG_BITS(reg, val, start, len) \ + WRITE_CBUS_REG(reg, (READ_CBUS_REG(reg) & ~(((1L<<(len))-1)<<(start)) )| ((unsigned)((val)&((1L<<(len))-1)) << (start))) +#define READ_CBUS_REG_BITS(reg, start, len) \ + ((READ_CBUS_REG(reg) >> (start)) & ((1L<<(len))-1)) +#define CLEAR_CBUS_REG_MASK(reg, mask) WRITE_CBUS_REG(reg, (READ_CBUS_REG(reg)&(~(mask)))) +#define SET_CBUS_REG_MASK(reg, mask) WRITE_CBUS_REG(reg, (READ_CBUS_REG(reg)|(mask))) + +#define WRITE_AXI_REG(reg, val) __raw_writel(val, AXI_REG_ADDR(reg)) +#define READ_AXI_REG(reg) (__raw_readl(AXI_REG_ADDR(reg))) +#define WRITE_AXI_REG_BITS(reg, val, start, len) \ + WRITE_AXI_REG(reg, (READ_AXI_REG(reg) & ~(((1L<<(len))-1)<<(start)) )| ((unsigned)((val)&((1L<<(len))-1)) << (start))) +#define READ_AXI_REG_BITS(reg, start, len) \ + ((READ_AXI_REG(reg) >> (start)) & ((1L<<(len))-1)) +#define CLEAR_AXI_REG_MASK(reg, mask) WRITE_AXI_REG(reg, (READ_AXI_REG(reg)&(~(mask)))) +#define SET_AXI_REG_MASK(reg, mask) WRITE_AXI_REG(reg, (READ_AXI_REG(reg)|(mask))) + +#define WRITE_AHB_REG(reg, val) __raw_writel(val, AHB_REG_ADDR(reg)) +#define READ_AHB_REG(reg) (__raw_readl(AHB_REG_ADDR(reg))) +#define WRITE_AHB_REG_BITS(reg, val, start, len) \ + WRITE_AHB_REG(reg, (READ_AHB_REG(reg) & ~(((1L<<(len))-1)<<(start)) )| ((unsigned)((val)&((1L<<(len))-1)) << (start))) +#define READ_AHB_REG_BITS(reg, start, len) \ + ((READ_AHB_REG(reg) >> (start)) & ((1L<<(len))-1)) +#define CLEAR_AHB_REG_MASK(reg, mask) WRITE_AHB_REG(reg, (READ_AHB_REG(reg)&(~(mask)))) +#define SET_AHB_REG_MASK(reg, mask) WRITE_AHB_REG(reg, (READ_AHB_REG(reg)|(mask))) + +#define WRITE_APB_REG(reg, val) __raw_writel(val, APB_REG_ADDR(reg)) +#define READ_APB_REG(reg) (__raw_readl(APB_REG_ADDR(reg))) +#define WRITE_APB_REG_BITS(reg, val, start, len) \ + WRITE_APB_REG(reg, (READ_APB_REG(reg) & ~(((1L<<(len))-1)<<(start)) )| ((unsigned)((val)&((1L<<(len))-1)) << (start))) +#define READ_APB_REG_BITS(reg, start, len) \ + ((READ_APB_REG(reg) >> (start)) & ((1L<<(len))-1)) +#define CLEAR_APB_REG_MASK(reg, mask) WRITE_APB_REG(reg, (READ_APB_REG(reg)&(~(mask)))) +#define SET_APB_REG_MASK(reg, mask) WRITE_APB_REG(reg, (READ_APB_REG(reg)|(mask))) + +#define WRITE_APB_HDMI_REG(reg, val) __raw_writel(val, APB_HDMI_REG_ADDR(reg)) +#define READ_APB_HDMI_REG(reg) (__raw_readl(APB_HDMI_REG_ADDR(reg))) +#define WRITE_APB_HDMI_REG_BITS(reg, val, start, len) \ + WRITE_APB_HDMI_REG(reg, (READ_APB_HDMI_REG(reg) & ~(((1L<<(len))-1)<<(start)) )| ((unsigned)((val)&((1L<<(len))-1)) << (start))) +#define READ_APB_HDMI_REG_BITS(reg, start, len) \ + ((READ_APB_HDMI_REG(reg) >> (start)) & ((1L<<(len))-1)) +#define CLEAR_APB_HDMI_REG_MASK(reg, mask) WRITE_APB_HDMI_REG(reg, (READ_APB_HDMI_REG(reg)&(~(mask)))) +#define SET_APB_HDMI_REG_MASK(reg, mask) WRITE_APB_HDMI_REG(reg, (READ_APB_HDMI_REG(reg)|(mask))) + +/* for back compatible alias */ +#define WRITE_MPEG_REG(reg, val) \ + WRITE_CBUS_REG(reg, val) +#define READ_MPEG_REG(reg) \ + READ_CBUS_REG(reg) +#define WRITE_MPEG_REG_BITS(reg, val, start, len) \ + WRITE_CBUS_REG_BITS(reg, val, start, len) +#define READ_MPEG_REG_BITS(reg, start, len) \ + READ_CBUS_REG_BITS(reg, start, len) +#define CLEAR_MPEG_REG_MASK(reg, mask) \ + CLEAR_CBUS_REG_MASK(reg, mask) +#define SET_MPEG_REG_MASK(reg, mask) \ + SET_CBUS_REG_MASK(reg, mask) +#endif + + +#endif
diff --git a/arch/arm/include/asm/arch-a1/mailbox.h b/arch/arm/include/asm/arch-a1/mailbox.h new file mode 100644 index 0000000..04ae20f --- /dev/null +++ b/arch/arm/include/asm/arch-a1/mailbox.h
@@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + + /* + * + * Copyright (C) 2012 Amlogic, Inc. + * + * Author: Platform-SH@amlogic.com + * + */ + +#ifndef __GXBB_MAILBOX_H_ +#define __GXBB_MAILBOX_H_ + +#define SCPI_CMD_SENSOR_VALUE 0x1C +#define SCPI_CMD_SET_USR_DATA 0x20 +#define SCPI_CMD_OPEN_SCP_LOG 0xC4 +#define SCPI_CMD_THERMAL_CALIB 0xC5 + +#define SCPI_CMD_USB_BOOT 0xB0 +#define SCPI_CMD_USB_UNBOOT 0xB1 +#define SCPI_CMD_SDCARD_BOOT 0xB2 +#define SCPI_CMD_CLEAR_BOOT 0xB3 + +#define SCPI_CMD_REV_PWM_DELT 0x42 + +#define LOW_PRIORITY 0 +#define HIGH_PRIORITY 1 + +#define P_SHARE_SRAM_BASE 0xfffa0000 +#define SRAM_SIZE 0x48000 +#define MHU_HIGH_SCP_TO_AP_PAYLOAD (SRAM_SIZE - 0xc00) +#define MHU_HIGH_AP_TO_SCP_PAYLOAD (MHU_HIGH_SCP_TO_AP_PAYLOAD + 0x200) +#define MHU_LOW_SCP_TO_AP_PAYLOAD (SRAM_SIZE - 0x1000) +#define MHU_LOW_AP_TO_SCP_PAYLOAD (MHU_LOW_SCP_TO_AP_PAYLOAD + 0x200) + +enum scpi_client_id { + SCPI_CL_NONE, + SCPI_CL_CLOCKS, + SCPI_CL_DVFS, + SCPI_CL_POWER, + SCPI_CL_THERMAL, + SCPI_CL_REMOTE, + SCPI_CL_LED_TIMER, + SCPI_MAX = 0xff, +}; + +enum scpi_error_codes { + SCPI_SUCCESS = 0, /* Success */ + SCPI_ERR_PARAM = 1, /* Invalid parameter(s) */ + SCPI_ERR_ALIGN = 2, /* Invalid alignment */ + SCPI_ERR_SIZE = 3, /* Invalid size */ + SCPI_ERR_HANDLER = 4, /* Invalid handler/callback */ + SCPI_ERR_ACCESS = 5, /* Invalid access/permission denied */ + SCPI_ERR_RANGE = 6, /* Value out of range */ + SCPI_ERR_TIMEOUT = 7, /* Timeout has occurred */ + SCPI_ERR_NOMEM = 8, /* Invalid memory area or pointer */ + SCPI_ERR_PWRSTATE = 9, /* Invalid power state */ + SCPI_ERR_SUPPORT = 10, /* Not supported or disabled */ + SCPI_ERR_DEVICE = 11, /* Device error */ + SCPI_ERR_MAX +}; + +void open_scp_log(unsigned int channel); +int thermal_calibration(unsigned int type, unsigned int data); +int thermal_get_value(unsigned int sensor_id, unsigned int *value); +int send_usr_data(unsigned int clinet_id, unsigned int *val, unsigned int size); +void send_pwm_delt(int32_t vcck_delt, int32_t ee_delt); + #endif
diff --git a/arch/arm/include/asm/arch-a1/mnPmuSramMsgBlock_ddr3.h b/arch/arm/include/asm/arch-a1/mnPmuSramMsgBlock_ddr3.h new file mode 100644 index 0000000..c067367 --- /dev/null +++ b/arch/arm/include/asm/arch-a1/mnPmuSramMsgBlock_ddr3.h
@@ -0,0 +1,637 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +/** \brief DDR3U_1D training firmware message block structure + * + * Please refer to the Training Firmware App Note for futher information about + * the usage for Message Block. + */ +typedef struct _PMU_SMB_DDR3U_1D_t { + uint8_t Reserved00; // Byte offset 0x00, CSR Addr 0x54000, Direction=In + // Reserved00[0:4] RFU, must be zero + // + // Reserved00[5] = Train vrefDAC0 During Read Deskew + // 0x1 = Read Deskew will begin by enabling and roughly training the phy’s per-lane reference voltages. Training the vrefDACs CSRs will increase the maximum 1D training time by around half a millisecond, but will improve 1D training accuracy on systems with significant voltage-offsets between lane read eyes. + // 0X0 = Read Deskew will assume the messageblock’s phyVref setting will work for all lanes. + // + // Reserved00[6] = Enable High Effort WrDQ1D + // 0x1 = WrDQ1D will conditionally retry training at several extra RxClkDly Timings. This will increase the maximum 1D training time by up to 4 extra iterations of WrDQ1D. This is only required in systems that suffer from very large, asymmetric eye-collapse when receiving PRBS patterns. + // 0x0 = WrDQ1D assume rxClkDly values found by SI Friendly RdDqs1D will work for receiving PRBS patterns + // + // Reserved00[7] = Optimize for the special hard macros in TSMC28. + // 0x1 = set if the phy being trained was manufactured in any TSMC28 process node. + // 0x0 = otherwise, when not training a TSMC28 phy, leave this field as 0. + uint8_t MsgMisc; // Byte offset 0x01, CSR Addr 0x54000, Direction=In + // Contains various global options for training. + // + // Bit fields: + // + // MsgMisc[0] = MTESTEnable + // 0x1 = Pulse primary digital test output bump at the end of each major training stage. This enables observation of training stage completion by observing the digital test output. + // 0x0 = Do not pulse primary digital test output bump + // + // MsgMisc[1] = SimulationOnlyReset + // 0x1 = Verilog only simulation option to shorten duration of DRAM reset pulse length to 1ns. + // Must never be set to 1 in silicon. + // 0x0 = Use reset pulse length specifed by JEDEC standard + // + // MsgMisc[2] = SimulationOnlyTraining + // 0x1 = Verilog only simulation option to shorten the duration of the training steps by performing fewer iterations. + // Must never be set to 1 in silicon. + // 0x0 = Use standard training duration. + // + // MsgMisc[3] = RFU, must be zero (DDR4 UDIMM and RDIMM only, otherwise RFU, must be zero) + // + // + // + // MsgMisc[4] = Suppress streaming messages, including assertions, regardless of HdtCtrl setting. + // Stage Completion messages, as well as training completion and error messages are + // Still sent depending on HdtCtrl setting. + // + // MsgMisc[5] = PerByteMaxRdLat + // 0x1 = Each DBYTE will return dfi_rddata_valid at the lowest possible latency. This may result in unaligned data between bytes to be returned to the DFI. + // 0x0 = Every DBYTE will return dfi_rddata_valid simultaneously. This will ensure that data bytes will return aligned accesses to the DFI. + // + // MsgMisc[6] = PartialRank (DDR3 UDIMM and DDR4 UDIMM only, otherwise RFU, must be zero) + // 0x1 = Support rank populated with a subset of byte, but where even-odd pair of rank support all the byte + // 0x0 = All rank populated with all the byte (tyical configuration) + // + // MsgMisc[7] RFU, must be zero + // + // Notes: + // + // - SimulationOnlyReset and SimulationOnlyTraining can be used to speed up simulation run times, and must never be used in real silicon. Some VIPs may have checks on DRAM reset parameters that may need to be disabled when using SimulationOnlyReset. + uint16_t PmuRevision; // Byte offset 0x02, CSR Addr 0x54001, Direction=Out + // PMU firmware revision ID + // After training is run, this address will contain the revision ID of the firmware. + // Please reference this revision ID when filing support cases with Synopsys. + uint8_t Pstate; // Byte offset 0x04, CSR Addr 0x54002, Direction=In + // Must be set to the target Pstate to be trained + // 0x0 = Pstate 0 + // 0x1 = Pstate 1 + // 0x2 = Pstate 2 + // 0x3 = Pstate 3 + // All other encodings are reserved + uint8_t PllBypassEn; // Byte offset 0x05, CSR Addr 0x54002, Direction=In + // Set according to whether target Pstate uses PHY PLL bypass + // 0x0 = PHY PLL is enabled for target Pstate + // 0x1 = PHY PLL is bypassed for target Pstate + uint16_t DRAMFreq; // Byte offset 0x06, CSR Addr 0x54003, Direction=In + // DDR data rate for the target Pstate in units of MT/s. + // For example enter 0x0640 for DDR1600. + uint8_t DfiFreqRatio; // Byte offset 0x08, CSR Addr 0x54004, Direction=In + // Frequency ratio betwen DfiCtlClk and SDRAM memclk. + // 0x1 = 1:1 + // 0x2 = 1:2 + // 0x4 = 1:4 + uint8_t BPZNResVal ; // Byte offset 0x09, CSR Addr 0x54004, Direction=In + // Must be programmed to match the precision resistor connected to Phy BP_ZN + // 0x00 = Do not program. Use current CSR value. + // 0xf0 = 240 Ohm (recommended value) + // 0x78 = 120 Ohm + // 0x28 = 40 Ohm + // All other values are reserved. + // + uint8_t PhyOdtImpedance; // Byte offset 0x0a, CSR Addr 0x54005, Direction=In + // Must be programmed to the termination impedance in ohms used by PHY during reads. + // + // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start) + // + // See PHY databook for legal termination impedance values. + // + // For digital simulation, any legal value can be used. For silicon, the users must determine the correct value through SI simulation or other methods. + uint8_t PhyDrvImpedance; // Byte offset 0x0b, CSR Addr 0x54005, Direction=In + // Must be programmed to the driver impedance in ohms used by PHY during writes for all DBYTE drivers (DQ/DM/DBI/DQS). + // + // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start) + // + // See PHY databook for legal R_on driver impedance values. + // + // For digital simulation, any value can be used that is not Hi-Z. For silicon, the users must determine the correct value through SI simulation or other methods. + uint8_t PhyVref; // Byte offset 0x0c, CSR Addr 0x54006, Direction=In + // Must be programmed with the Vref level to be used by the PHY during reads + // + // The units of this field are a percentage of VDDQ according to the following equation: + // + // Receiver Vref = VDDQ*PhyVref[6:0]/128 + // + // For example to set Vref at 0.75*VDDQ, set this field to 0x60. + // + // For digital simulation, any legal value can be used. For silicon, the users must calculate the analytical Vref by using the impedances, terminations, and series resistance present in the system. + uint8_t DramType; // Byte offset 0x0d, CSR Addr 0x54006, Direction=In + // Module Type: + // 0x01 = DDR3 unbuffered + // 0x02 = Reserved + // 0x03 = Reserved + // 0x04 = Reserved + // 0x05 = Reserved + // + uint8_t DisabledDbyte; // Byte offset 0x0e, CSR Addr 0x54007, Direction=In + // Bitmap to indicate which Dbyte are not connected (for DByte 0 to 7): + // Set DisabledDbyte[i] to 1 only to specify that DByte i not need to be trained (DByte 8 can be disabled via EnabledDQs setting) + uint8_t EnabledDQs; // Byte offset 0x0f, CSR Addr 0x54007, Direction=In + // Total number of DQ bits enabled in PHY + uint8_t CsPresent; // Byte offset 0x10, CSR Addr 0x54008, Direction=In + // Indicates presence of DRAM at each chip select for PHY. Each bit corresponds to a logical CS. + // + // If the bit is set to 1, the CS is connected to DRAM. + // If the bit is set to 0, the CS is not connected to DRAM. + // + // CsPresent[0] = CS0 is populated with DRAM + // CsPresent[1] = CS1 is populated with DRAM + // CsPresent[2] = CS2 is populated with DRAM + // CsPresent[3] = CS3 is populated with DRAM + // CsPresent[7:4] = Reserved (must be programmed to 0) + // + // + uint8_t CsPresentD0; // Byte offset 0x11, CSR Addr 0x54008, Direction=In + // The CS signals from field CsPresent that are routed to DIMM connector 0 + uint8_t CsPresentD1; // Byte offset 0x12, CSR Addr 0x54009, Direction=In + // The CS signals from field CsPresent that are routed to DIMM connector 1 + uint8_t AddrMirror; // Byte offset 0x13, CSR Addr 0x54009, Direction=In + // Corresponds to CS[3:0] + // 1 = Address Mirror. + // 0 = No Address Mirror. + uint8_t CsTestFail; // Byte offset 0x14, CSR Addr 0x5400a, Direction=Out + // This field will be set if training fails on any rank. + // 0x0 = No failures + // non-zero = one or more ranks failed training + uint8_t PhyCfg; // Byte offset 0x15, CSR Addr 0x5400a, Direction=In + // Additional mode bits. + // + // Bit fields: + // [0] SlowAccessMode : + // 1 = 2T Address Timing. + // 0 = 1T Address Timing. + // [7-1] RFU, must be zero + uint16_t SequenceCtrl; // Byte offset 0x16, CSR Addr 0x5400b, Direction=In + // Controls the training steps to be run. Each bit corresponds to a training step. + // + // If the bit is set to 1, the training step will run. + // If the bit is set to 0, the training step will be skipped. + // + // Training step to bit mapping: + // SequenceCtrl[0] = Run DevInit - Device/phy initialization. Should always be set. + // SequenceCtrl[1] = Run WrLvl - Write leveling + // SequenceCtrl[2] = Run RxEn - Read gate training + // SequenceCtrl[3] = Run RdDQS1D - 1d read dqs training + // SequenceCtrl[4] = Run WrDQ1D - 1d write dq training + // SequenceCtrl[5] = RFU, must be zero + // SequenceCtrl[6] = RFU, must be zero + // SequenceCtrl[7] = RFU, must be zero + // SequenceCtrl[8] = Run RdDeskew - Per lane read dq deskew training + // SequenceCtrl[9] = Run MxRdLat - Max read latency training + // SequenceCtrl[10] = RFU, must be zero + // SequenceCtrl[11] = RFU, must be zero + // SequenceCtrl[12] = RFU, must be zero + // SequenceCtrl[13] = RFU, must be zero + // SequenceCtrl[15-14] = RFU, must be zero + uint8_t HdtCtrl; // Byte offset 0x18, CSR Addr 0x5400c, Direction=In + // To control the total number of debug messages, a verbosity subfield (HdtCtrl, Hardware Debug Trace Control) exists in the message block. Every message has a verbosity level associated with it, and as the HdtCtrl value is increased, less important s messages stop being sent through the mailboxes. The meanings of several major HdtCtrl thresholds are explained below: + // + // 0x05 = Detailed debug messages (e.g. Eye delays) + // 0x0A = Coarse debug messages (e.g. rank information) + // 0xC8 = Stage completion + // 0xC9 = Assertion messages + // 0xFF = Firmware completion messages only + // + // See Training App Note for more detailed information on what messages are included for each threshold. + // + uint8_t Reserved19; // Byte offset 0x19, CSR Addr 0x5400c, Direction=N/A + + + + + + + + + + + + + + + + + uint8_t Reserved1A; // Byte offset 0x1a, CSR Addr 0x5400d, Direction=N/A + + + + + + + + + + + + + + + + + + + + uint8_t Reserved1B; // Byte offset 0x1b, CSR Addr 0x5400d, Direction=N/A + + + + uint8_t Reserved1C; // Byte offset 0x1c, CSR Addr 0x5400e, Direction=N/A + + uint8_t Reserved1D; // Byte offset 0x1d, CSR Addr 0x5400e, Direction=N/A + + uint8_t Reserved1E; // Byte offset 0x1e, CSR Addr 0x5400f, Direction=In + // Input for constraining the range of vref(DQ) values training will collect data for, usually reducing training time. However, too large of a voltage range may cause longer 2D training times while too small of a voltage range may truncate passing regions. When in doubt, leave this field set to 0. + // Used by 2D training in: Rd2D, Wr2D + // + // Reserved1E[0-3]: Rd2D Voltage Range + // 0 = Training will search all phy vref(DQ) settings + // 1 = limit to +/-2 %VDDQ from phyVref + // 2 = limit to +/-4 %VDDQ from phyVref + // … + // 15 = limit to +/-30% VDDQ from phyVref + // + // Reserved1E[4-7]: Wr2D Voltage Range + // 0 = Training will search all dram vref(DQ) settings + // 1 = limit to +/-2 %VDDQ from MR6 + // 2 = limit to +/-4 %VDDQ from MR6 + // … + // 15 = limit to +/-30% VDDQ from MR6 + uint8_t Reserved1F; // Byte offset 0x1f, CSR Addr 0x5400f, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved20; // Byte offset 0x20, CSR Addr 0x54010, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved21; // Byte offset 0x21, CSR Addr 0x54010, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint16_t PhyConfigOverride; // Byte offset 0x22, CSR Addr 0x54011, Direction=In + // Override PhyConfig csr. + // 0x0: Use hardware csr value for PhyConfing (recommended) + // Other values: Use value for PhyConfig instead of Hardware value. + // + uint8_t DFIMRLMargin; // Byte offset 0x24, CSR Addr 0x54012, Direction=In + // Margin added to smallest passing trained DFI Max Read Latency value, in units of DFI clocks. Recommended to be >= 1. See the Training App Note for more details on the training process and the use of this value. + int8_t CDD_RR_3_2; // Byte offset 0x25, CSR Addr 0x54012, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 3 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_3_1; // Byte offset 0x26, CSR Addr 0x54013, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 3 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_3_0; // Byte offset 0x27, CSR Addr 0x54013, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 3 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_2_3; // Byte offset 0x28, CSR Addr 0x54014, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 2 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_2_1; // Byte offset 0x29, CSR Addr 0x54014, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 2 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_2_0; // Byte offset 0x2a, CSR Addr 0x54015, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 2 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_1_3; // Byte offset 0x2b, CSR Addr 0x54015, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 1 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_1_2; // Byte offset 0x2c, CSR Addr 0x54016, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 1 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_1_0; // Byte offset 0x2d, CSR Addr 0x54016, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 1 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_0_3; // Byte offset 0x2e, CSR Addr 0x54017, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 0 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_0_2; // Byte offset 0x2f, CSR Addr 0x54017, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 0 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_0_1; // Byte offset 0x30, CSR Addr 0x54018, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 0 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_3_2; // Byte offset 0x31, CSR Addr 0x54018, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 3 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_3_1; // Byte offset 0x32, CSR Addr 0x54019, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 3 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_3_0; // Byte offset 0x33, CSR Addr 0x54019, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 3 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_2_3; // Byte offset 0x34, CSR Addr 0x5401a, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 2 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_2_1; // Byte offset 0x35, CSR Addr 0x5401a, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 2 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_2_0; // Byte offset 0x36, CSR Addr 0x5401b, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 2 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_1_3; // Byte offset 0x37, CSR Addr 0x5401b, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 1 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_1_2; // Byte offset 0x38, CSR Addr 0x5401c, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 1 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_1_0; // Byte offset 0x39, CSR Addr 0x5401c, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 1 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_0_3; // Byte offset 0x3a, CSR Addr 0x5401d, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 0 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_0_2; // Byte offset 0x3b, CSR Addr 0x5401d, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 0 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_0_1; // Byte offset 0x3c, CSR Addr 0x5401e, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 0 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_3_3; // Byte offset 0x3d, CSR Addr 0x5401e, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 3 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_3_2; // Byte offset 0x3e, CSR Addr 0x5401f, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 3 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_3_1; // Byte offset 0x3f, CSR Addr 0x5401f, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 3 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_3_0; // Byte offset 0x40, CSR Addr 0x54020, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 3 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_2_3; // Byte offset 0x41, CSR Addr 0x54020, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 2 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_2_2; // Byte offset 0x42, CSR Addr 0x54021, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 2 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_2_1; // Byte offset 0x43, CSR Addr 0x54021, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 2 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_2_0; // Byte offset 0x44, CSR Addr 0x54022, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 2 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_1_3; // Byte offset 0x45, CSR Addr 0x54022, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_1_2; // Byte offset 0x46, CSR Addr 0x54023, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_1_1; // Byte offset 0x47, CSR Addr 0x54023, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_1_0; // Byte offset 0x48, CSR Addr 0x54024, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_0_3; // Byte offset 0x49, CSR Addr 0x54024, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 0 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_0_2; // Byte offset 0x4a, CSR Addr 0x54025, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 0 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_0_1; // Byte offset 0x4b, CSR Addr 0x54025, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 0 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_0_0; // Byte offset 0x4c, CSR Addr 0x54026, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 0 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_3_3; // Byte offset 0x4d, CSR Addr 0x54026, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 3 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_3_2; // Byte offset 0x4e, CSR Addr 0x54027, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 3 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_3_1; // Byte offset 0x4f, CSR Addr 0x54027, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 3 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_3_0; // Byte offset 0x50, CSR Addr 0x54028, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 3 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_2_3; // Byte offset 0x51, CSR Addr 0x54028, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 2 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_2_2; // Byte offset 0x52, CSR Addr 0x54029, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 2 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_2_1; // Byte offset 0x53, CSR Addr 0x54029, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 2 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_2_0; // Byte offset 0x54, CSR Addr 0x5402a, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 2 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_1_3; // Byte offset 0x55, CSR Addr 0x5402a, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_1_2; // Byte offset 0x56, CSR Addr 0x5402b, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_1_1; // Byte offset 0x57, CSR Addr 0x5402b, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_1_0; // Byte offset 0x58, CSR Addr 0x5402c, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_0_3; // Byte offset 0x59, CSR Addr 0x5402c, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_0_2; // Byte offset 0x5a, CSR Addr 0x5402d, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_0_1; // Byte offset 0x5b, CSR Addr 0x5402d, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_0_0; // Byte offset 0x5c, CSR Addr 0x5402e, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + uint8_t Reserved5D; // Byte offset 0x5d, CSR Addr 0x5402e, Direction=N/A + // This field is ignored if 0. If larger than 0, this value is used as is as the offset in fine-step applied at the end of DDR4 RxEnable training, instead of the default offset. + uint16_t MR0; // Byte offset 0x5e, CSR Addr 0x5402f, Direction=In + // Value of DDR mode register MR0 for all ranks for current pstate + uint16_t MR1; // Byte offset 0x60, CSR Addr 0x54030, Direction=In + // Value of DDR mode register MR1 for all ranks for current pstate + uint16_t MR2; // Byte offset 0x62, CSR Addr 0x54031, Direction=In + // Value of DDR mode register MR2 for all ranks for current pstate + uint8_t Reserved64; // Byte offset 0x64, CSR Addr 0x54032, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved65; // Byte offset 0x65, CSR Addr 0x54032, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved66; // Byte offset 0x66, CSR Addr 0x54033, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved67; // Byte offset 0x67, CSR Addr 0x54033, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved68; // Byte offset 0x68, CSR Addr 0x54034, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved69; // Byte offset 0x69, CSR Addr 0x54034, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved6A; // Byte offset 0x6a, CSR Addr 0x54035, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved6B; // Byte offset 0x6b, CSR Addr 0x54035, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved6C; // Byte offset 0x6c, CSR Addr 0x54036, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved6D; // Byte offset 0x6d, CSR Addr 0x54036, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved6E; // Byte offset 0x6e, CSR Addr 0x54037, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved6F; // Byte offset 0x6f, CSR Addr 0x54037, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved70; // Byte offset 0x70, CSR Addr 0x54038, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved71; // Byte offset 0x71, CSR Addr 0x54038, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved72; // Byte offset 0x72, CSR Addr 0x54039, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved73; // Byte offset 0x73, CSR Addr 0x54039, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t AcsmOdtCtrl0; // Byte offset 0x74, CSR Addr 0x5403a, Direction=In + // Odt pattern for accesses targeting rank 0. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl1; // Byte offset 0x75, CSR Addr 0x5403a, Direction=In + // Odt pattern for accesses targeting rank 1. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl2; // Byte offset 0x76, CSR Addr 0x5403b, Direction=In + // Odt pattern for accesses targeting rank 2. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl3; // Byte offset 0x77, CSR Addr 0x5403b, Direction=In + // Odt pattern for accesses targeting rank 3. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl4; // Byte offset 0x78, CSR Addr 0x5403c, Direction=In + // This field is reserved and must be programmed to 0x00. + uint8_t AcsmOdtCtrl5; // Byte offset 0x79, CSR Addr 0x5403c, Direction=In + // This field is reserved and must be programmed to 0x00. + uint8_t AcsmOdtCtrl6; // Byte offset 0x7a, CSR Addr 0x5403d, Direction=In + // This field is reserved and must be programmed to 0x00. + uint8_t AcsmOdtCtrl7; // Byte offset 0x7b, CSR Addr 0x5403d, Direction=In + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved7C; // Byte offset 0x7c, CSR Addr 0x5403e, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved7D; // Byte offset 0x7d, CSR Addr 0x5403e, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved7E; // Byte offset 0x7e, CSR Addr 0x5403f, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved7F; // Byte offset 0x7f, CSR Addr 0x5403f, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved80; // Byte offset 0x80, CSR Addr 0x54040, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved81; // Byte offset 0x81, CSR Addr 0x54040, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved82; // Byte offset 0x82, CSR Addr 0x54041, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved83; // Byte offset 0x83, CSR Addr 0x54041, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved84; // Byte offset 0x84, CSR Addr 0x54042, Direction=N/A + + uint8_t Reserved85; // Byte offset 0x85, CSR Addr 0x54042, Direction=N/A + + uint8_t Reserved86; // Byte offset 0x86, CSR Addr 0x54043, Direction=N/A + + uint8_t Reserved87; // Byte offset 0x87, CSR Addr 0x54043, Direction=N/A + + uint8_t Reserved88; // Byte offset 0x88, CSR Addr 0x54044, Direction=N/A + + uint8_t Reserved89; // Byte offset 0x89, CSR Addr 0x54044, Direction=N/A + + uint8_t Reserved8A; // Byte offset 0x8a, CSR Addr 0x54045, Direction=N/A + + uint8_t Reserved8B; // Byte offset 0x8b, CSR Addr 0x54045, Direction=N/A + + uint8_t Reserved8C; // Byte offset 0x8c, CSR Addr 0x54046, Direction=N/A + + uint8_t Reserved8D; // Byte offset 0x8d, CSR Addr 0x54046, Direction=N/A + + uint8_t Reserved8E; // Byte offset 0x8e, CSR Addr 0x54047, Direction=N/A + + uint8_t Reserved8F; // Byte offset 0x8f, CSR Addr 0x54047, Direction=N/A + + uint8_t Reserved90; // Byte offset 0x90, CSR Addr 0x54048, Direction=N/A + + uint8_t Reserved91; // Byte offset 0x91, CSR Addr 0x54048, Direction=N/A + + uint8_t Reserved92; // Byte offset 0x92, CSR Addr 0x54049, Direction=N/A + + uint8_t Reserved93; // Byte offset 0x93, CSR Addr 0x54049, Direction=N/A + + uint8_t Reserved94; // Byte offset 0x94, CSR Addr 0x5404a, Direction=N/A + + uint8_t Reserved95; // Byte offset 0x95, CSR Addr 0x5404a, Direction=N/A + + uint8_t Reserved96; // Byte offset 0x96, CSR Addr 0x5404b, Direction=N/A + + uint8_t Reserved97; // Byte offset 0x97, CSR Addr 0x5404b, Direction=N/A + + uint8_t Reserved98; // Byte offset 0x98, CSR Addr 0x5404c, Direction=N/A + + uint8_t Reserved99; // Byte offset 0x99, CSR Addr 0x5404c, Direction=N/A + + uint8_t Reserved9A; // Byte offset 0x9a, CSR Addr 0x5404d, Direction=N/A + + uint8_t Reserved9B; // Byte offset 0x9b, CSR Addr 0x5404d, Direction=N/A + + uint8_t Reserved9C; // Byte offset 0x9c, CSR Addr 0x5404e, Direction=N/A + + uint8_t Reserved9D; // Byte offset 0x9d, CSR Addr 0x5404e, Direction=N/A + + uint8_t Reserved9E; // Byte offset 0x9e, CSR Addr 0x5404f, Direction=N/A + + uint8_t Reserved9F; // Byte offset 0x9f, CSR Addr 0x5404f, Direction=N/A + + uint8_t ReservedA0; // Byte offset 0xa0, CSR Addr 0x54050, Direction=N/A + + uint8_t ReservedA1; // Byte offset 0xa1, CSR Addr 0x54050, Direction=N/A + + uint8_t ReservedA2; // Byte offset 0xa2, CSR Addr 0x54051, Direction=N/A + + uint8_t ReservedA3; // Byte offset 0xa3, CSR Addr 0x54051, Direction=N/A + +} __attribute__ ((packed)) PMU_SMB_DDR3U_1D_t;
diff --git a/arch/arm/include/asm/arch-a1/mnPmuSramMsgBlock_ddr4.h b/arch/arm/include/asm/arch-a1/mnPmuSramMsgBlock_ddr4.h new file mode 100644 index 0000000..6dfd4d0 --- /dev/null +++ b/arch/arm/include/asm/arch-a1/mnPmuSramMsgBlock_ddr4.h
@@ -0,0 +1,2380 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +/** \brief DDR4U_1D training firmware message block structure + * + * Please refer to the Training Firmware App Note for futher information about + * the usage for Message Block. + */ +typedef struct _PMU_SMB_DDR4U_1D_t { + uint8_t Reserved00; // Byte offset 0x00, CSR Addr 0x54000, Direction=In + // Reserved00[0:4] RFU, must be zero + // + // Reserved00[5] = Train vrefDAC0 During Read Deskew + // 0x1 = Read Deskew will begin by enabling and roughly training the phy’s per-lane reference voltages. Training the vrefDACs CSRs will increase the maximum 1D training time by around half a millisecond, but will improve 1D training accuracy on systems with significant voltage-offsets between lane read eyes. + // 0X0 = Read Deskew will assume the messageblock’s phyVref setting will work for all lanes. + // + // Reserved00[6] = Enable High Effort WrDQ1D + // 0x1 = WrDQ1D will conditionally retry training at several extra RxClkDly Timings. This will increase the maximum 1D training time by up to 4 extra iterations of WrDQ1D. This is only required in systems that suffer from very large, asymmetric eye-collapse when receiving PRBS patterns. + // 0x0 = WrDQ1D assume rxClkDly values found by SI Friendly RdDqs1D will work for receiving PRBS patterns + // + // Reserved00[7] = Optimize for the special hard macros in TSMC28. + // 0x1 = set if the phy being trained was manufactured in any TSMC28 process node. + // 0x0 = otherwise, when not training a TSMC28 phy, leave this field as 0. + uint8_t MsgMisc; // Byte offset 0x01, CSR Addr 0x54000, Direction=In + // Contains various global options for training. + // + // Bit fields: + // + // MsgMisc[0] = MTESTEnable + // 0x1 = Pulse primary digital test output bump at the end of each major training stage. This enables observation of training stage completion by observing the digital test output. + // 0x0 = Do not pulse primary digital test output bump + // + // MsgMisc[1] = SimulationOnlyReset + // 0x1 = Verilog only simulation option to shorten duration of DRAM reset pulse length to 1ns. + // Must never be set to 1 in silicon. + // 0x0 = Use reset pulse length specifed by JEDEC standard + // + // MsgMisc[2] = SimulationOnlyTraining + // 0x1 = Verilog only simulation option to shorten the duration of the training steps by performing fewer iterations. + // Must never be set to 1 in silicon. + // 0x0 = Use standard training duration. + // + // MsgMisc[3] = UseDdr4PerDeviceVrefDq (DDR4 UDIMM and RDIMM only, otherwise RFU, must be zero) + // 0x1 = Program user characterized Vref DQ values per DDR4 DRAM device. The message block VrefDqR*Nib* fields must be populated with the desired per device Vref DQs when using this option. Note: this option is not applicable in 2D training because these values are explicitly trained in 2D. + // 0x0 = Program Vref DQ for all DDR4 devices with the single value provided in MR6 message block field + // + // MsgMisc[4] = Suppress streaming messages, including assertions, regardless of HdtCtrl setting. + // Stage Completion messages, as well as training completion and error messages are + // Still sent depending on HdtCtrl setting. + // + // MsgMisc[5] = PerByteMaxRdLat + // 0x1 = Each DBYTE will return dfi_rddata_valid at the lowest possible latency. This may result in unaligned data between bytes to be returned to the DFI. + // 0x0 = Every DBYTE will return dfi_rddata_valid simultaneously. This will ensure that data bytes will return aligned accesses to the DFI. + // + // MsgMisc[6] = PartialRank (DDR3 UDIMM and DDR4 UDIMM only, otherwise RFU, must be zero) + // 0x1 = Support rank populated with a subset of byte, but where even-odd pair of rank support all the byte + // 0x0 = All rank populated with all the byte (tyical configuration) + // + // MsgMisc[7] RFU, must be zero + // + // Notes: + // + // - SimulationOnlyReset and SimulationOnlyTraining can be used to speed up simulation run times, and must never be used in real silicon. Some VIPs may have checks on DRAM reset parameters that may need to be disabled when using SimulationOnlyReset. + uint16_t PmuRevision; // Byte offset 0x02, CSR Addr 0x54001, Direction=Out + // PMU firmware revision ID + // After training is run, this address will contain the revision ID of the firmware. + // Please reference this revision ID when filing support cases with Synopsys. + uint8_t Pstate; // Byte offset 0x04, CSR Addr 0x54002, Direction=In + // Must be set to the target Pstate to be trained + // 0x0 = Pstate 0 + // 0x1 = Pstate 1 + // 0x2 = Pstate 2 + // 0x3 = Pstate 3 + // All other encodings are reserved + uint8_t PllBypassEn; // Byte offset 0x05, CSR Addr 0x54002, Direction=In + // Set according to whether target Pstate uses PHY PLL bypass + // 0x0 = PHY PLL is enabled for target Pstate + // 0x1 = PHY PLL is bypassed for target Pstate + uint16_t DRAMFreq; // Byte offset 0x06, CSR Addr 0x54003, Direction=In + // DDR data rate for the target Pstate in units of MT/s. + // For example enter 0x0640 for DDR1600. + uint8_t DfiFreqRatio; // Byte offset 0x08, CSR Addr 0x54004, Direction=In + // Frequency ratio betwen DfiCtlClk and SDRAM memclk. + // 0x1 = 1:1 + // 0x2 = 1:2 + // 0x4 = 1:4 + uint8_t BPZNResVal ; // Byte offset 0x09, CSR Addr 0x54004, Direction=In + // Must be programmed to match the precision resistor connected to Phy BP_ZN + // 0x00 = Do not program. Use current CSR value. + // 0xf0 = 240 Ohm (recommended value) + // 0x78 = 120 Ohm + // 0x28 = 40 Ohm + // All other values are reserved. + // + uint8_t PhyOdtImpedance; // Byte offset 0x0a, CSR Addr 0x54005, Direction=In + // Must be programmed to the termination impedance in ohms used by PHY during reads. + // + // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start) + // + // See PHY databook for legal termination impedance values. + // + // For digital simulation, any legal value can be used. For silicon, the users must determine the correct value through SI simulation or other methods. + uint8_t PhyDrvImpedance; // Byte offset 0x0b, CSR Addr 0x54005, Direction=In + // Must be programmed to the driver impedance in ohms used by PHY during writes for all DBYTE drivers (DQ/DM/DBI/DQS). + // + // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start) + // + // See PHY databook for legal R_on driver impedance values. + // + // For digital simulation, any value can be used that is not Hi-Z. For silicon, the users must determine the correct value through SI simulation or other methods. + uint8_t PhyVref; // Byte offset 0x0c, CSR Addr 0x54006, Direction=In + // Must be programmed with the Vref level to be used by the PHY during reads + // + // The units of this field are a percentage of VDDQ according to the following equation: + // + // Receiver Vref = VDDQ*PhyVref[6:0]/128 + // + // For example to set Vref at 0.75*VDDQ, set this field to 0x60. + // + // For digital simulation, any legal value can be used. For silicon, the users must calculate the analytical Vref by using the impedances, terminations, and series resistance present in the system. + uint8_t DramType; // Byte offset 0x0d, CSR Addr 0x54006, Direction=In + // Module Type: + // 0x01 = Reserved + // 0x02 = DDR4 unbuffered + // 0x03 = Reserved + // 0x04 = Reserved + // 0x05 = Reserved + // + uint8_t DisabledDbyte; // Byte offset 0x0e, CSR Addr 0x54007, Direction=In + // Bitmap to indicate which Dbyte are not connected (for DByte 0 to 7): + // Set DisabledDbyte[i] to 1 only to specify that DByte i not need to be trained (DByte 8 can be disabled via EnabledDQs setting) + uint8_t EnabledDQs; // Byte offset 0x0f, CSR Addr 0x54007, Direction=In + // Total number of DQ bits enabled in PHY + uint8_t CsPresent; // Byte offset 0x10, CSR Addr 0x54008, Direction=In + // Indicates presence of DRAM at each chip select for PHY. Each bit corresponds to a logical CS. + // + // If the bit is set to 1, the CS is connected to DRAM. + // If the bit is set to 0, the CS is not connected to DRAM. + // + // CsPresent[0] = CS0 is populated with DRAM + // CsPresent[1] = CS1 is populated with DRAM + // CsPresent[2] = CS2 is populated with DRAM + // CsPresent[3] = CS3 is populated with DRAM + // CsPresent[7:4] = Reserved (must be programmed to 0) + // + // + uint8_t CsPresentD0; // Byte offset 0x11, CSR Addr 0x54008, Direction=In + // The CS signals from field CsPresent that are routed to DIMM connector 0 + uint8_t CsPresentD1; // Byte offset 0x12, CSR Addr 0x54009, Direction=In + // The CS signals from field CsPresent that are routed to DIMM connector 1 + uint8_t AddrMirror; // Byte offset 0x13, CSR Addr 0x54009, Direction=In + // Corresponds to CS[3:0] + // 1 = Address Mirror. + // 0 = No Address Mirror. + uint8_t CsTestFail; // Byte offset 0x14, CSR Addr 0x5400a, Direction=Out + // This field will be set if training fails on any rank. + // 0x0 = No failures + // non-zero = one or more ranks failed training + uint8_t PhyCfg; // Byte offset 0x15, CSR Addr 0x5400a, Direction=In + // Additional mode bits. + // + // Bit fields: + // [0] SlowAccessMode : + // 1 = 2T Address Timing. + // 0 = 1T Address Timing. + // [7-1] RFU, must be zero + uint16_t SequenceCtrl; // Byte offset 0x16, CSR Addr 0x5400b, Direction=In + // Controls the training steps to be run. Each bit corresponds to a training step. + // + // If the bit is set to 1, the training step will run. + // If the bit is set to 0, the training step will be skipped. + // + // Training step to bit mapping: + // SequenceCtrl[0] = Run DevInit - Device/phy initialization. Should always be set. + // SequenceCtrl[1] = Run WrLvl - Write leveling + // SequenceCtrl[2] = Run RxEn - Read gate training + // SequenceCtrl[3] = Run RdDQS1D - 1d read dqs training + // SequenceCtrl[4] = Run WrDQ1D - 1d write dq training + // SequenceCtrl[5] = RFU, must be zero + // SequenceCtrl[6] = RFU, must be zero + // SequenceCtrl[7] = RFU, must be zero + // SequenceCtrl[8] = Run RdDeskew - Per lane read dq deskew training + // SequenceCtrl[9] = Run MxRdLat - Max read latency training + // SequenceCtrl[10] = Run Reserved + // SequenceCtrl[11] = Run Reserved + // SequenceCtrl[12] = Run Reserved + // SequenceCtrl[13] = Run Reserved + // SequenceCtrl[15-14] = RFU, must be zero + uint8_t HdtCtrl; // Byte offset 0x18, CSR Addr 0x5400c, Direction=In + // To control the total number of debug messages, a verbosity subfield (HdtCtrl, Hardware Debug Trace Control) exists in the message block. Every message has a verbosity level associated with it, and as the HdtCtrl value is increased, less important s messages stop being sent through the mailboxes. The meanings of several major HdtCtrl thresholds are explained below: + // + // 0x05 = Detailed debug messages (e.g. Eye delays) + // 0x0A = Coarse debug messages (e.g. rank information) + // 0xC8 = Stage completion + // 0xC9 = Assertion messages + // 0xFF = Firmware completion messages only + // + // See Training App Note for more detailed information on what messages are included for each threshold. + // + uint8_t Reserved19; // Byte offset 0x19, CSR Addr 0x5400c, Direction=N/A + + + + + + + + + + + + + + + + + uint8_t Reserved1A; // Byte offset 0x1a, CSR Addr 0x5400d, Direction=N/A + + + + + + + + + + + + + + + + + + + + uint8_t Reserved1B; // Byte offset 0x1b, CSR Addr 0x5400d, Direction=N/A + + + + uint8_t Reserved1C; // Byte offset 0x1c, CSR Addr 0x5400e, Direction=N/A + + uint8_t Reserved1D; // Byte offset 0x1d, CSR Addr 0x5400e, Direction=N/A + + uint8_t Reserved1E; // Byte offset 0x1e, CSR Addr 0x5400f, Direction=In + // Input for constraining the range of vref(DQ) values training will collect data for, usually reducing training time. However, too large of a voltage range may cause longer 2D training times while too small of a voltage range may truncate passing regions. When in doubt, leave this field set to 0. + // Used by 2D training in: Rd2D, Wr2D + // + // Reserved1E[0-3]: Rd2D Voltage Range + // 0 = Training will search all phy vref(DQ) settings + // 1 = limit to +/-2 %VDDQ from phyVref + // 2 = limit to +/-4 %VDDQ from phyVref + // … + // 15 = limit to +/-30% VDDQ from phyVref + // + // Reserved1E[4-7]: Wr2D Voltage Range + // 0 = Training will search all dram vref(DQ) settings + // 1 = limit to +/-2 %VDDQ from MR6 + // 2 = limit to +/-4 %VDDQ from MR6 + // … + // 15 = limit to +/-30% VDDQ from MR6 + uint8_t Reserved1F; // Byte offset 0x1f, CSR Addr 0x5400f, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved20; // Byte offset 0x20, CSR Addr 0x54010, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved21; // Byte offset 0x21, CSR Addr 0x54010, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint16_t PhyConfigOverride; // Byte offset 0x22, CSR Addr 0x54011, Direction=In + // Override PhyConfig csr. + // 0x0: Use hardware csr value for PhyConfing (recommended) + // Other values: Use value for PhyConfig instead of Hardware value. + // + uint8_t DFIMRLMargin; // Byte offset 0x24, CSR Addr 0x54012, Direction=In + // Margin added to smallest passing trained DFI Max Read Latency value, in units of DFI clocks. Recommended to be >= 1. See the Training App Note for more details on the training process and the use of this value. + int8_t CDD_RR_3_2; // Byte offset 0x25, CSR Addr 0x54012, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 3 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_3_1; // Byte offset 0x26, CSR Addr 0x54013, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 3 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_3_0; // Byte offset 0x27, CSR Addr 0x54013, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 3 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_2_3; // Byte offset 0x28, CSR Addr 0x54014, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 2 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_2_1; // Byte offset 0x29, CSR Addr 0x54014, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 2 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_2_0; // Byte offset 0x2a, CSR Addr 0x54015, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 2 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_1_3; // Byte offset 0x2b, CSR Addr 0x54015, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 1 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_1_2; // Byte offset 0x2c, CSR Addr 0x54016, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 1 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_1_0; // Byte offset 0x2d, CSR Addr 0x54016, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 1 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_0_3; // Byte offset 0x2e, CSR Addr 0x54017, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 0 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_0_2; // Byte offset 0x2f, CSR Addr 0x54017, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 0 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_0_1; // Byte offset 0x30, CSR Addr 0x54018, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 0 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_3_2; // Byte offset 0x31, CSR Addr 0x54018, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 3 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_3_1; // Byte offset 0x32, CSR Addr 0x54019, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 3 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_3_0; // Byte offset 0x33, CSR Addr 0x54019, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 3 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_2_3; // Byte offset 0x34, CSR Addr 0x5401a, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 2 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_2_1; // Byte offset 0x35, CSR Addr 0x5401a, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 2 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_2_0; // Byte offset 0x36, CSR Addr 0x5401b, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 2 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_1_3; // Byte offset 0x37, CSR Addr 0x5401b, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 1 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_1_2; // Byte offset 0x38, CSR Addr 0x5401c, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 1 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_1_0; // Byte offset 0x39, CSR Addr 0x5401c, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 1 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_0_3; // Byte offset 0x3a, CSR Addr 0x5401d, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 0 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_0_2; // Byte offset 0x3b, CSR Addr 0x5401d, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 0 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_0_1; // Byte offset 0x3c, CSR Addr 0x5401e, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 0 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_3_3; // Byte offset 0x3d, CSR Addr 0x5401e, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 3 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_3_2; // Byte offset 0x3e, CSR Addr 0x5401f, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 3 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_3_1; // Byte offset 0x3f, CSR Addr 0x5401f, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 3 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_3_0; // Byte offset 0x40, CSR Addr 0x54020, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 3 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_2_3; // Byte offset 0x41, CSR Addr 0x54020, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 2 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_2_2; // Byte offset 0x42, CSR Addr 0x54021, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 2 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_2_1; // Byte offset 0x43, CSR Addr 0x54021, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 2 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_2_0; // Byte offset 0x44, CSR Addr 0x54022, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 2 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_1_3; // Byte offset 0x45, CSR Addr 0x54022, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_1_2; // Byte offset 0x46, CSR Addr 0x54023, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_1_1; // Byte offset 0x47, CSR Addr 0x54023, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_1_0; // Byte offset 0x48, CSR Addr 0x54024, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_0_3; // Byte offset 0x49, CSR Addr 0x54024, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 0 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_0_2; // Byte offset 0x4a, CSR Addr 0x54025, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 0 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_0_1; // Byte offset 0x4b, CSR Addr 0x54025, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 0 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_0_0; // Byte offset 0x4c, CSR Addr 0x54026, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 0 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_3_3; // Byte offset 0x4d, CSR Addr 0x54026, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 3 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_3_2; // Byte offset 0x4e, CSR Addr 0x54027, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 3 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_3_1; // Byte offset 0x4f, CSR Addr 0x54027, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 3 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_3_0; // Byte offset 0x50, CSR Addr 0x54028, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 3 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_2_3; // Byte offset 0x51, CSR Addr 0x54028, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 2 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_2_2; // Byte offset 0x52, CSR Addr 0x54029, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 2 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_2_1; // Byte offset 0x53, CSR Addr 0x54029, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 2 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_2_0; // Byte offset 0x54, CSR Addr 0x5402a, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 2 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_1_3; // Byte offset 0x55, CSR Addr 0x5402a, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_1_2; // Byte offset 0x56, CSR Addr 0x5402b, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_1_1; // Byte offset 0x57, CSR Addr 0x5402b, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_1_0; // Byte offset 0x58, CSR Addr 0x5402c, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_0_3; // Byte offset 0x59, CSR Addr 0x5402c, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_0_2; // Byte offset 0x5a, CSR Addr 0x5402d, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_0_1; // Byte offset 0x5b, CSR Addr 0x5402d, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_0_0; // Byte offset 0x5c, CSR Addr 0x5402e, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + uint8_t Reserved5D; // Byte offset 0x5d, CSR Addr 0x5402e, Direction=N/A + // This field is ignored if 0. If larger than 0, this value is used as is as the offset in fine-step applied at the end of DDR4 RxEnable training, instead of the default offset. + uint16_t MR0; // Byte offset 0x5e, CSR Addr 0x5402f, Direction=In + // Value of DDR mode register MR0 for all ranks for current pstate + uint16_t MR1; // Byte offset 0x60, CSR Addr 0x54030, Direction=In + // Value of DDR mode register MR1 for all ranks for current pstate + uint16_t MR2; // Byte offset 0x62, CSR Addr 0x54031, Direction=In + // Value of DDR mode register MR2 for all ranks for current pstate + uint16_t MR3; // Byte offset 0x64, CSR Addr 0x54032, Direction=In + // Value of DDR mode register MR3 for all ranks for current pstate + uint16_t MR4; // Byte offset 0x66, CSR Addr 0x54033, Direction=In + // Value of DDR mode register MR4 for all ranks for current pstate + uint16_t MR5; // Byte offset 0x68, CSR Addr 0x54034, Direction=In + // Value of DDR mode register MR5 for all ranks for current pstate + uint16_t MR6; // Byte offset 0x6a, CSR Addr 0x54035, Direction=In + // Value of DDR mode register MR6 for all ranks for current pstate. Note: The initial VrefDq value and range must be set in A6:A0. + uint8_t X16Present; // Byte offset 0x6c, CSR Addr 0x54036, Direction=In + // X16 device map. Corresponds to CS[3:0]. + // X16Present[0] = CS0 is populated with X16 devices + // X16Present[1] = CS1 is populated with X16 devices + // X16Present[2] = CS2 is populated with X16 devices + // X16Present[3] = CS3 is populated with X16 devices + // X16Present[7:4] = Reserved (must be programmed to 0) + // + // Ranks may not contain mixed device types. + uint8_t CsSetupGDDec; // Byte offset 0x6d, CSR Addr 0x54036, Direction=In + // controls timing of chip select signals when DDR4 gear-down mode is active + // 0 - Leave delay of chip select timing group signal the same both before and after gear-down sync occurs + // 1 - Add 1UI of delay to chip select timing group signals when geardown-mode is active. This allows CS signals to have equal setup and hold time in gear-down mode + uint16_t RTT_NOM_WR_PARK0; // Byte offset 0x6e, CSR Addr 0x54037, Direction=In + // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 0 DRAM: + // RTT_NOM_WR_PARK0[0] = 1: Option is enable (otherwise, remaining bit fields are don't care) + // RTT_NOM_WR_PARK0[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 0 + // RTT_NOM_WR_PARK0[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 0 + // RTT_NOM_WR_PARK0[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 0 + uint16_t RTT_NOM_WR_PARK1; // Byte offset 0x70, CSR Addr 0x54038, Direction=In + // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 1 DRAM: + // RTT_NOM_WR_PARK1[0] = 1: Option is enable (otherwise, remaining bit fields are don't care) + // RTT_NOM_WR_PARK1[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 1 + // RTT_NOM_WR_PARK1[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 1 + // RTT_NOM_WR_PARK1[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 1 + uint16_t RTT_NOM_WR_PARK2; // Byte offset 0x72, CSR Addr 0x54039, Direction=In + // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 2 DRAM: + // RTT_NOM_WR_PARK2[0] = 1: Option is enable (otherwise, remaining bit fields are don't care) + // RTT_NOM_WR_PARK2[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 2 + // RTT_NOM_WR_PARK2[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 2 + // RTT_NOM_WR_PARK2[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 2 + uint16_t RTT_NOM_WR_PARK3; // Byte offset 0x74, CSR Addr 0x5403a, Direction=In + // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 3 DRAM: + // RTT_NOM_WR_PARK3[0] = 1: Option is enable (otherwise, remaining bit fields are don't care) + // RTT_NOM_WR_PARK3[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 3 + // RTT_NOM_WR_PARK3[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 3 + // RTT_NOM_WR_PARK3[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 3 + uint16_t RTT_NOM_WR_PARK4; // Byte offset 0x76, CSR Addr 0x5403b, Direction=In + // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 4 DRAM: + // RTT_NOM_WR_PARK4[0] = 1: Option is enable (otherwise, remaining bit fields are don't care) + // RTT_NOM_WR_PARK4[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 4 + // RTT_NOM_WR_PARK4[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 4 + // RTT_NOM_WR_PARK4[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 4 + uint16_t RTT_NOM_WR_PARK5; // Byte offset 0x78, CSR Addr 0x5403c, Direction=In + // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 5 DRAM: + // RTT_NOM_WR_PARK5[0] = 1: Option is enable (otherwise, remaining bit fields are don't care) + // RTT_NOM_WR_PARK5[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 5 + // RTT_NOM_WR_PARK5[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 5 + // RTT_NOM_WR_PARK5[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 5 + uint16_t RTT_NOM_WR_PARK6; // Byte offset 0x7a, CSR Addr 0x5403d, Direction=In + // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 6 DRAM: + // RTT_NOM_WR_PARK6[0] = 1: Option is enable (otherwise, remaining bit fields are don't care) + // RTT_NOM_WR_PARK6[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 6 + // RTT_NOM_WR_PARK6[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 6 + // RTT_NOM_WR_PARK6[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 6 + uint16_t RTT_NOM_WR_PARK7; // Byte offset 0x7c, CSR Addr 0x5403e, Direction=In + // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 7 DRAM: + // RTT_NOM_WR_PARK7[0] = 1: Option is enable (otherwise, remaining bit fields are don't care) + // RTT_NOM_WR_PARK7[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 7 + // RTT_NOM_WR_PARK7[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 7 + // RTT_NOM_WR_PARK7[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 7 + uint8_t AcsmOdtCtrl0; // Byte offset 0x7e, CSR Addr 0x5403f, Direction=In + // Odt pattern for accesses targeting rank 0. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl1; // Byte offset 0x7f, CSR Addr 0x5403f, Direction=In + // Odt pattern for accesses targeting rank 1. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl2; // Byte offset 0x80, CSR Addr 0x54040, Direction=In + // Odt pattern for accesses targeting rank 2. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl3; // Byte offset 0x81, CSR Addr 0x54040, Direction=In + // Odt pattern for accesses targeting rank 3. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl4; // Byte offset 0x82, CSR Addr 0x54041, Direction=In + // Odt pattern for accesses targeting rank 4. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl5; // Byte offset 0x83, CSR Addr 0x54041, Direction=In + // Odt pattern for accesses targeting rank 5. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl6; // Byte offset 0x84, CSR Addr 0x54042, Direction=In + // Odt pattern for accesses targeting rank 6. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl7; // Byte offset 0x85, CSR Addr 0x54042, Direction=In + // Odt pattern for accesses targeting rank 7. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t VrefDqR0Nib0; // Byte offset 0x86, CSR Addr 0x54043, Direction=InOut + // VrefDq for rank 0 nibble 0. Specifies MR6[6:0] + uint8_t VrefDqR0Nib1; // Byte offset 0x87, CSR Addr 0x54043, Direction=InOut + // VrefDq for rank 0 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR0Nib0 for x8 or x16 devices. + uint8_t VrefDqR0Nib2; // Byte offset 0x88, CSR Addr 0x54044, Direction=InOut + // VrefDq for rank 0 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR0Nib0 for x16 devices. + uint8_t VrefDqR0Nib3; // Byte offset 0x89, CSR Addr 0x54044, Direction=InOut + // VrefDq for rank 0 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR0Nib0 for x16 devices, or VrefDqR0Nib2 for x8 devices. + uint8_t VrefDqR0Nib4; // Byte offset 0x8a, CSR Addr 0x54045, Direction=InOut + // VrefDq for rank 0 nibble 4. Specifies MR6[6:0] + uint8_t VrefDqR0Nib5; // Byte offset 0x8b, CSR Addr 0x54045, Direction=InOut + // VrefDq for rank 0 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR0Nib4 for x8 or x16 devices. + uint8_t VrefDqR0Nib6; // Byte offset 0x8c, CSR Addr 0x54046, Direction=InOut + // VrefDq for rank 0 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR0Nib4 for x16 devices. + uint8_t VrefDqR0Nib7; // Byte offset 0x8d, CSR Addr 0x54046, Direction=InOut + // VrefDq for rank 0 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR0Nib4 for x16 devices, or VrefDqR0Nib6 for x8 devices. + uint8_t VrefDqR0Nib8; // Byte offset 0x8e, CSR Addr 0x54047, Direction=InOut + // VrefDq for rank 0 nibble 8. Specifies MR6[6:0] + uint8_t VrefDqR0Nib9; // Byte offset 0x8f, CSR Addr 0x54047, Direction=InOut + // VrefDq for rank 0 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR0Nib8 for x8 or x16 devices. + uint8_t VrefDqR0Nib10; // Byte offset 0x90, CSR Addr 0x54048, Direction=InOut + // VrefDq for rank 0 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR0Nib8 for x16 devices. + uint8_t VrefDqR0Nib11; // Byte offset 0x91, CSR Addr 0x54048, Direction=InOut + // VrefDq for rank 0 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR0Nib8 for x16 devices, or VrefDqR0Nib10 for x8 devices. + uint8_t VrefDqR0Nib12; // Byte offset 0x92, CSR Addr 0x54049, Direction=InOut + // VrefDq for rank 0 nibble 12. Specifies MR6[6:0] + uint8_t VrefDqR0Nib13; // Byte offset 0x93, CSR Addr 0x54049, Direction=InOut + // VrefDq for rank 0 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR0Nib12 for x8 or x16 devices. + uint8_t VrefDqR0Nib14; // Byte offset 0x94, CSR Addr 0x5404a, Direction=InOut + // VrefDq for rank 0 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR0Nib12 for x16 devices. + uint8_t VrefDqR0Nib15; // Byte offset 0x95, CSR Addr 0x5404a, Direction=InOut + // VrefDq for rank 0 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR0Nib12 for x16 devices, or VrefDqR0Nib14 for x8 devices. + uint8_t VrefDqR0Nib16; // Byte offset 0x96, CSR Addr 0x5404b, Direction=InOut + // VrefDq for rank 0 nibble 16. Specifies MR6[6:0] + uint8_t VrefDqR0Nib17; // Byte offset 0x97, CSR Addr 0x5404b, Direction=InOut + // VrefDq for rank 0 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR0Nib16 for x8 or x16 devices. + uint8_t VrefDqR0Nib18; // Byte offset 0x98, CSR Addr 0x5404c, Direction=InOut + // VrefDq for rank 0 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR0Nib16 for x16 devices. + uint8_t VrefDqR0Nib19; // Byte offset 0x99, CSR Addr 0x5404c, Direction=InOut + // VrefDq for rank 0 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR0Nib16 for x16 devices, or VrefDqR0Nib18 for x8 devices. + uint8_t VrefDqR1Nib0; // Byte offset 0x9a, CSR Addr 0x5404d, Direction=InOut + // VrefDq for rank 1 nibble 0. Specifies MR6[6:0] + uint8_t VrefDqR1Nib1; // Byte offset 0x9b, CSR Addr 0x5404d, Direction=InOut + // VrefDq for rank 1 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR1Nib0 for x8 or x16 devices. + uint8_t VrefDqR1Nib2; // Byte offset 0x9c, CSR Addr 0x5404e, Direction=InOut + // VrefDq for rank 1 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR1Nib0 for x16 devices. + uint8_t VrefDqR1Nib3; // Byte offset 0x9d, CSR Addr 0x5404e, Direction=InOut + // VrefDq for rank 1 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR1Nib0 for x16 devices, or VrefDqR1Nib2 for x8 devices. + uint8_t VrefDqR1Nib4; // Byte offset 0x9e, CSR Addr 0x5404f, Direction=InOut + // VrefDq for rank 1 nibble 4. Specifies MR6[6:0] + uint8_t VrefDqR1Nib5; // Byte offset 0x9f, CSR Addr 0x5404f, Direction=InOut + // VrefDq for rank 1 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR1Nib4 for x8 or x16 devices. + uint8_t VrefDqR1Nib6; // Byte offset 0xa0, CSR Addr 0x54050, Direction=InOut + // VrefDq for rank 1 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR1Nib4 for x16 devices. + uint8_t VrefDqR1Nib7; // Byte offset 0xa1, CSR Addr 0x54050, Direction=InOut + // VrefDq for rank 1 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR1Nib4 for x16 devices, or VrefDqR1Nib6 for x8 devices. + uint8_t VrefDqR1Nib8; // Byte offset 0xa2, CSR Addr 0x54051, Direction=InOut + // VrefDq for rank 1 nibble 8. Specifies MR6[6:0] + uint8_t VrefDqR1Nib9; // Byte offset 0xa3, CSR Addr 0x54051, Direction=InOut + // VrefDq for rank 1 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR1Nib8 for x8 or x16 devices. + uint8_t VrefDqR1Nib10; // Byte offset 0xa4, CSR Addr 0x54052, Direction=InOut + // VrefDq for rank 1 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR1Nib8 for x16 devices. + uint8_t VrefDqR1Nib11; // Byte offset 0xa5, CSR Addr 0x54052, Direction=InOut + // VrefDq for rank 1 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR1Nib8 for x16 devices, or VrefDqR1Nib10 for x8 devices. + uint8_t VrefDqR1Nib12; // Byte offset 0xa6, CSR Addr 0x54053, Direction=InOut + // VrefDq for rank 1 nibble 12. Specifies MR6[6:0] + uint8_t VrefDqR1Nib13; // Byte offset 0xa7, CSR Addr 0x54053, Direction=InOut + // VrefDq for rank 1 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR1Nib12 for x8 or x16 devices. + uint8_t VrefDqR1Nib14; // Byte offset 0xa8, CSR Addr 0x54054, Direction=InOut + // VrefDq for rank 1 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR1Nib12 for x16 devices. + uint8_t VrefDqR1Nib15; // Byte offset 0xa9, CSR Addr 0x54054, Direction=InOut + // VrefDq for rank 1 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR1Nib12 for x16 devices, or VrefDqR1Nib14 for x8 devices. + uint8_t VrefDqR1Nib16; // Byte offset 0xaa, CSR Addr 0x54055, Direction=InOut + // VrefDq for rank 1 nibble 16. Specifies MR6[6:0] + uint8_t VrefDqR1Nib17; // Byte offset 0xab, CSR Addr 0x54055, Direction=InOut + // VrefDq for rank 1 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR1Nib16 for x8 or x16 devices. + uint8_t VrefDqR1Nib18; // Byte offset 0xac, CSR Addr 0x54056, Direction=InOut + // VrefDq for rank 1 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR1Nib16 for x16 devices. + uint8_t VrefDqR1Nib19; // Byte offset 0xad, CSR Addr 0x54056, Direction=InOut + // VrefDq for rank 1 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR1Nib16 for x16 devices, or VrefDqR1Nib18 for x8 devices. + uint8_t VrefDqR2Nib0; // Byte offset 0xae, CSR Addr 0x54057, Direction=InOut + // VrefDq for rank 2 nibble 0. Specifies MR6[6:0] + uint8_t VrefDqR2Nib1; // Byte offset 0xaf, CSR Addr 0x54057, Direction=InOut + // VrefDq for rank 2 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR2Nib0 for x8 or x16 devices. + uint8_t VrefDqR2Nib2; // Byte offset 0xb0, CSR Addr 0x54058, Direction=InOut + // VrefDq for rank 2 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR2Nib0 for x16 devices. + uint8_t VrefDqR2Nib3; // Byte offset 0xb1, CSR Addr 0x54058, Direction=InOut + // VrefDq for rank 2 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR2Nib0 for x16 devices, or VrefDqR2Nib2 for x8 devices. + uint8_t VrefDqR2Nib4; // Byte offset 0xb2, CSR Addr 0x54059, Direction=InOut + // VrefDq for rank 2 nibble 4. Specifies MR6[6:0] + uint8_t VrefDqR2Nib5; // Byte offset 0xb3, CSR Addr 0x54059, Direction=InOut + // VrefDq for rank 2 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR2Nib4 for x8 or x16 devices. + uint8_t VrefDqR2Nib6; // Byte offset 0xb4, CSR Addr 0x5405a, Direction=InOut + // VrefDq for rank 2 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR2Nib4 for x16 devices. + uint8_t VrefDqR2Nib7; // Byte offset 0xb5, CSR Addr 0x5405a, Direction=InOut + // VrefDq for rank 2 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR2Nib4 for x16 devices, or VrefDqR2Nib6 for x8 devices. + uint8_t VrefDqR2Nib8; // Byte offset 0xb6, CSR Addr 0x5405b, Direction=InOut + // VrefDq for rank 2 nibble 8. Specifies MR6[6:0] + uint8_t VrefDqR2Nib9; // Byte offset 0xb7, CSR Addr 0x5405b, Direction=InOut + // VrefDq for rank 2 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR2Nib8 for x8 or x16 devices. + uint8_t VrefDqR2Nib10; // Byte offset 0xb8, CSR Addr 0x5405c, Direction=InOut + // VrefDq for rank 2 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR2Nib8 for x16 devices. + uint8_t VrefDqR2Nib11; // Byte offset 0xb9, CSR Addr 0x5405c, Direction=InOut + // VrefDq for rank 2 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR2Nib8 for x16 devices, or VrefDqR2Nib10 for x8 devices. + uint8_t VrefDqR2Nib12; // Byte offset 0xba, CSR Addr 0x5405d, Direction=InOut + // VrefDq for rank 2 nibble 12. Specifies MR6[6:0] + uint8_t VrefDqR2Nib13; // Byte offset 0xbb, CSR Addr 0x5405d, Direction=InOut + // VrefDq for rank 2 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR2Nib12 for x8 or x16 devices. + uint8_t VrefDqR2Nib14; // Byte offset 0xbc, CSR Addr 0x5405e, Direction=InOut + // VrefDq for rank 2 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR2Nib12 for x16 devices. + uint8_t VrefDqR2Nib15; // Byte offset 0xbd, CSR Addr 0x5405e, Direction=InOut + // VrefDq for rank 2 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR2Nib12 for x16 devices, or VrefDqR2Nib14 for x8 devices. + uint8_t VrefDqR2Nib16; // Byte offset 0xbe, CSR Addr 0x5405f, Direction=InOut + // VrefDq for rank 2 nibble 16. Specifies MR6[6:0] + uint8_t VrefDqR2Nib17; // Byte offset 0xbf, CSR Addr 0x5405f, Direction=InOut + // VrefDq for rank 2 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR2Nib16 for x8 or x16 devices. + uint8_t VrefDqR2Nib18; // Byte offset 0xc0, CSR Addr 0x54060, Direction=InOut + // VrefDq for rank 2 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR2Nib16 for x16 devices. + uint8_t VrefDqR2Nib19; // Byte offset 0xc1, CSR Addr 0x54060, Direction=InOut + // VrefDq for rank 2 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR2Nib16 for x16 devices, or VrefDqR2Nib18 for x8 devices. + uint8_t VrefDqR3Nib0; // Byte offset 0xc2, CSR Addr 0x54061, Direction=InOut + // VrefDq for rank 3 nibble 0. Specifies MR6[6:0] + uint8_t VrefDqR3Nib1; // Byte offset 0xc3, CSR Addr 0x54061, Direction=InOut + // VrefDq for rank 3 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR3Nib0 for x8 or x16 devices. + uint8_t VrefDqR3Nib2; // Byte offset 0xc4, CSR Addr 0x54062, Direction=InOut + // VrefDq for rank 3 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR3Nib0 for x16 devices. + uint8_t VrefDqR3Nib3; // Byte offset 0xc5, CSR Addr 0x54062, Direction=InOut + // VrefDq for rank 3 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR3Nib0 for x16 devices, or VrefDqR3Nib2 for x8 devices. + uint8_t VrefDqR3Nib4; // Byte offset 0xc6, CSR Addr 0x54063, Direction=InOut + // VrefDq for rank 3 nibble 4. Specifies MR6[6:0] + uint8_t VrefDqR3Nib5; // Byte offset 0xc7, CSR Addr 0x54063, Direction=InOut + // VrefDq for rank 3 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR3Nib4 for x8 or x16 devices. + uint8_t VrefDqR3Nib6; // Byte offset 0xc8, CSR Addr 0x54064, Direction=InOut + // VrefDq for rank 3 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR3Nib4 for x16 devices. + uint8_t VrefDqR3Nib7; // Byte offset 0xc9, CSR Addr 0x54064, Direction=InOut + // VrefDq for rank 3 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR3Nib4 for x16 devices, or VrefDqR3Nib6 for x8 devices. + uint8_t VrefDqR3Nib8; // Byte offset 0xca, CSR Addr 0x54065, Direction=InOut + // VrefDq for rank 3 nibble 8. Specifies MR6[6:0] + uint8_t VrefDqR3Nib9; // Byte offset 0xcb, CSR Addr 0x54065, Direction=InOut + // VrefDq for rank 3 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR3Nib8 for x8 or x16 devices. + uint8_t VrefDqR3Nib10; // Byte offset 0xcc, CSR Addr 0x54066, Direction=InOut + // VrefDq for rank 3 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR3Nib8 for x16 devices. + uint8_t VrefDqR3Nib11; // Byte offset 0xcd, CSR Addr 0x54066, Direction=InOut + // VrefDq for rank 3 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR3Nib8 for x16 devices, or VrefDqR3Nib10 for x8 devices. + uint8_t VrefDqR3Nib12; // Byte offset 0xce, CSR Addr 0x54067, Direction=InOut + // VrefDq for rank 3 nibble 12. Specifies MR6[6:0] + uint8_t VrefDqR3Nib13; // Byte offset 0xcf, CSR Addr 0x54067, Direction=InOut + // VrefDq for rank 3 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR3Nib12 for x8 or x16 devices. + uint8_t VrefDqR3Nib14; // Byte offset 0xd0, CSR Addr 0x54068, Direction=InOut + // VrefDq for rank 3 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR3Nib12 for x16 devices. + uint8_t VrefDqR3Nib15; // Byte offset 0xd1, CSR Addr 0x54068, Direction=InOut + // VrefDq for rank 3 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR3Nib12 for x16 devices, or VrefDqR3Nib14 for x8 devices. + uint8_t VrefDqR3Nib16; // Byte offset 0xd2, CSR Addr 0x54069, Direction=InOut + // VrefDq for rank 3 nibble 16. Specifies MR6[6:0] + uint8_t VrefDqR3Nib17; // Byte offset 0xd3, CSR Addr 0x54069, Direction=InOut + // VrefDq for rank 3 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR3Nib16 for x8 or x16 devices. + uint8_t VrefDqR3Nib18; // Byte offset 0xd4, CSR Addr 0x5406a, Direction=InOut + // VrefDq for rank 3 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR3Nib16 for x16 devices. + uint8_t VrefDqR3Nib19; // Byte offset 0xd5, CSR Addr 0x5406a, Direction=InOut + // VrefDq for rank 3 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR3Nib16 for x16 devices, or VrefDqR3Nib18 for x8 devices. + uint8_t ReservedD6; // Byte offset 0xd6, CSR Addr 0x5406b, Direction=N/A + + uint8_t ReservedD7; // Byte offset 0xd7, CSR Addr 0x5406b, Direction=N/A + + uint8_t ReservedD8; // Byte offset 0xd8, CSR Addr 0x5406c, Direction=N/A + + uint8_t ReservedD9; // Byte offset 0xd9, CSR Addr 0x5406c, Direction=N/A + + uint8_t ReservedDA; // Byte offset 0xda, CSR Addr 0x5406d, Direction=N/A + + uint8_t ReservedDB; // Byte offset 0xdb, CSR Addr 0x5406d, Direction=N/A + + uint8_t ReservedDC; // Byte offset 0xdc, CSR Addr 0x5406e, Direction=N/A + + uint8_t ReservedDD; // Byte offset 0xdd, CSR Addr 0x5406e, Direction=N/A + + uint8_t ReservedDE; // Byte offset 0xde, CSR Addr 0x5406f, Direction=N/A + + uint8_t ReservedDF; // Byte offset 0xdf, CSR Addr 0x5406f, Direction=N/A + + uint8_t ReservedE0; // Byte offset 0xe0, CSR Addr 0x54070, Direction=N/A + + uint8_t ReservedE1; // Byte offset 0xe1, CSR Addr 0x54070, Direction=N/A + + uint8_t ReservedE2; // Byte offset 0xe2, CSR Addr 0x54071, Direction=N/A + + uint8_t ReservedE3; // Byte offset 0xe3, CSR Addr 0x54071, Direction=N/A + + uint8_t ReservedE4; // Byte offset 0xe4, CSR Addr 0x54072, Direction=N/A + + uint8_t ReservedE5; // Byte offset 0xe5, CSR Addr 0x54072, Direction=N/A + + uint8_t ReservedE6; // Byte offset 0xe6, CSR Addr 0x54073, Direction=N/A + + uint8_t ReservedE7; // Byte offset 0xe7, CSR Addr 0x54073, Direction=N/A + + uint8_t ReservedE8; // Byte offset 0xe8, CSR Addr 0x54074, Direction=N/A + + uint8_t ReservedE9; // Byte offset 0xe9, CSR Addr 0x54074, Direction=N/A + + uint8_t ReservedEA; // Byte offset 0xea, CSR Addr 0x54075, Direction=N/A + + uint8_t ReservedEB; // Byte offset 0xeb, CSR Addr 0x54075, Direction=N/A + + uint8_t ReservedEC; // Byte offset 0xec, CSR Addr 0x54076, Direction=N/A + + uint8_t ReservedED; // Byte offset 0xed, CSR Addr 0x54076, Direction=N/A + + uint8_t ReservedEE; // Byte offset 0xee, CSR Addr 0x54077, Direction=N/A + + uint8_t ReservedEF; // Byte offset 0xef, CSR Addr 0x54077, Direction=N/A + + uint8_t ReservedF0; // Byte offset 0xf0, CSR Addr 0x54078, Direction=N/A + + uint8_t ReservedF1; // Byte offset 0xf1, CSR Addr 0x54078, Direction=N/A + + uint8_t ReservedF2; // Byte offset 0xf2, CSR Addr 0x54079, Direction=N/A + + uint8_t ReservedF3; // Byte offset 0xf3, CSR Addr 0x54079, Direction=N/A + + uint8_t ReservedF4; // Byte offset 0xf4, CSR Addr 0x5407a, Direction=N/A + + uint8_t ReservedF5; // Byte offset 0xf5, CSR Addr 0x5407a, Direction=N/A + + uint8_t ReservedF6; // Byte offset 0xf6, CSR Addr 0x5407b, Direction=N/A + + uint8_t ReservedF7; // Byte offset 0xf7, CSR Addr 0x5407b, Direction=N/A + + uint8_t ReservedF8; // Byte offset 0xf8, CSR Addr 0x5407c, Direction=N/A + + uint8_t ReservedF9; // Byte offset 0xf9, CSR Addr 0x5407c, Direction=N/A + + uint8_t ReservedFA; // Byte offset 0xfa, CSR Addr 0x5407d, Direction=N/A + + uint8_t ReservedFB; // Byte offset 0xfb, CSR Addr 0x5407d, Direction=N/A + + uint8_t ReservedFC; // Byte offset 0xfc, CSR Addr 0x5407e, Direction=N/A + + uint8_t ReservedFD; // Byte offset 0xfd, CSR Addr 0x5407e, Direction=N/A + + uint8_t ReservedFE; // Byte offset 0xfe, CSR Addr 0x5407f, Direction=N/A + + uint8_t ReservedFF; // Byte offset 0xff, CSR Addr 0x5407f, Direction=N/A + + uint8_t Reserved100; // Byte offset 0x100, CSR Addr 0x54080, Direction=N/A + + uint8_t Reserved101; // Byte offset 0x101, CSR Addr 0x54080, Direction=N/A + + uint8_t Reserved102; // Byte offset 0x102, CSR Addr 0x54081, Direction=N/A + + uint8_t Reserved103; // Byte offset 0x103, CSR Addr 0x54081, Direction=N/A + + uint8_t Reserved104; // Byte offset 0x104, CSR Addr 0x54082, Direction=N/A + + uint8_t Reserved105; // Byte offset 0x105, CSR Addr 0x54082, Direction=N/A + + uint8_t Reserved106; // Byte offset 0x106, CSR Addr 0x54083, Direction=N/A + + uint8_t Reserved107; // Byte offset 0x107, CSR Addr 0x54083, Direction=N/A + + uint8_t Reserved108; // Byte offset 0x108, CSR Addr 0x54084, Direction=N/A + + uint8_t Reserved109; // Byte offset 0x109, CSR Addr 0x54084, Direction=N/A + + uint8_t Reserved10A; // Byte offset 0x10a, CSR Addr 0x54085, Direction=N/A + + uint8_t Reserved10B; // Byte offset 0x10b, CSR Addr 0x54085, Direction=N/A + + uint8_t Reserved10C; // Byte offset 0x10c, CSR Addr 0x54086, Direction=N/A + + uint8_t Reserved10D; // Byte offset 0x10d, CSR Addr 0x54086, Direction=N/A + + uint8_t Reserved10E; // Byte offset 0x10e, CSR Addr 0x54087, Direction=N/A + + uint8_t Reserved10F; // Byte offset 0x10f, CSR Addr 0x54087, Direction=N/A + + uint8_t Reserved110; // Byte offset 0x110, CSR Addr 0x54088, Direction=N/A + + uint8_t Reserved111; // Byte offset 0x111, CSR Addr 0x54088, Direction=N/A + + uint8_t Reserved112; // Byte offset 0x112, CSR Addr 0x54089, Direction=N/A + + uint8_t Reserved113; // Byte offset 0x113, CSR Addr 0x54089, Direction=N/A + + uint8_t Reserved114; // Byte offset 0x114, CSR Addr 0x5408a, Direction=N/A + + uint8_t Reserved115; // Byte offset 0x115, CSR Addr 0x5408a, Direction=N/A + + uint8_t Reserved116; // Byte offset 0x116, CSR Addr 0x5408b, Direction=N/A + + uint8_t Reserved117; // Byte offset 0x117, CSR Addr 0x5408b, Direction=N/A + + uint8_t Reserved118; // Byte offset 0x118, CSR Addr 0x5408c, Direction=N/A + + uint8_t Reserved119; // Byte offset 0x119, CSR Addr 0x5408c, Direction=N/A + + uint8_t Reserved11A; // Byte offset 0x11a, CSR Addr 0x5408d, Direction=N/A + + uint8_t Reserved11B; // Byte offset 0x11b, CSR Addr 0x5408d, Direction=N/A + + uint8_t Reserved11C; // Byte offset 0x11c, CSR Addr 0x5408e, Direction=N/A + + uint8_t Reserved11D; // Byte offset 0x11d, CSR Addr 0x5408e, Direction=N/A + + uint8_t Reserved11E; // Byte offset 0x11e, CSR Addr 0x5408f, Direction=N/A + + uint8_t Reserved11F; // Byte offset 0x11f, CSR Addr 0x5408f, Direction=N/A + + uint8_t Reserved120; // Byte offset 0x120, CSR Addr 0x54090, Direction=N/A + + uint8_t Reserved121; // Byte offset 0x121, CSR Addr 0x54090, Direction=N/A + + uint8_t Reserved122; // Byte offset 0x122, CSR Addr 0x54091, Direction=N/A + + uint8_t Reserved123; // Byte offset 0x123, CSR Addr 0x54091, Direction=N/A + + uint8_t Reserved124; // Byte offset 0x124, CSR Addr 0x54092, Direction=N/A + + uint8_t Reserved125; // Byte offset 0x125, CSR Addr 0x54092, Direction=N/A + + uint8_t Reserved126; // Byte offset 0x126, CSR Addr 0x54093, Direction=N/A + + uint8_t Reserved127; // Byte offset 0x127, CSR Addr 0x54093, Direction=N/A + + uint8_t Reserved128; // Byte offset 0x128, CSR Addr 0x54094, Direction=N/A + + uint8_t Reserved129; // Byte offset 0x129, CSR Addr 0x54094, Direction=N/A + + uint8_t Reserved12A; // Byte offset 0x12a, CSR Addr 0x54095, Direction=N/A + + uint8_t Reserved12B; // Byte offset 0x12b, CSR Addr 0x54095, Direction=N/A + + uint8_t Reserved12C; // Byte offset 0x12c, CSR Addr 0x54096, Direction=N/A + + uint8_t Reserved12D; // Byte offset 0x12d, CSR Addr 0x54096, Direction=N/A + + uint8_t Reserved12E; // Byte offset 0x12e, CSR Addr 0x54097, Direction=N/A + + uint8_t Reserved12F; // Byte offset 0x12f, CSR Addr 0x54097, Direction=N/A + + uint8_t Reserved130; // Byte offset 0x130, CSR Addr 0x54098, Direction=N/A + + uint8_t Reserved131; // Byte offset 0x131, CSR Addr 0x54098, Direction=N/A + + uint8_t Reserved132; // Byte offset 0x132, CSR Addr 0x54099, Direction=N/A + + uint8_t Reserved133; // Byte offset 0x133, CSR Addr 0x54099, Direction=N/A + + uint8_t Reserved134; // Byte offset 0x134, CSR Addr 0x5409a, Direction=N/A + + uint8_t Reserved135; // Byte offset 0x135, CSR Addr 0x5409a, Direction=N/A + + uint8_t Reserved136; // Byte offset 0x136, CSR Addr 0x5409b, Direction=N/A + + uint8_t Reserved137; // Byte offset 0x137, CSR Addr 0x5409b, Direction=N/A + + uint8_t Reserved138; // Byte offset 0x138, CSR Addr 0x5409c, Direction=N/A + + uint8_t Reserved139; // Byte offset 0x139, CSR Addr 0x5409c, Direction=N/A + + uint8_t Reserved13A; // Byte offset 0x13a, CSR Addr 0x5409d, Direction=N/A + + uint8_t Reserved13B; // Byte offset 0x13b, CSR Addr 0x5409d, Direction=N/A + + uint8_t Reserved13C; // Byte offset 0x13c, CSR Addr 0x5409e, Direction=N/A + + uint8_t Reserved13D; // Byte offset 0x13d, CSR Addr 0x5409e, Direction=N/A + + uint8_t Reserved13E; // Byte offset 0x13e, CSR Addr 0x5409f, Direction=N/A + + uint8_t Reserved13F; // Byte offset 0x13f, CSR Addr 0x5409f, Direction=N/A + + uint8_t Reserved140; // Byte offset 0x140, CSR Addr 0x540a0, Direction=N/A + + uint8_t Reserved141; // Byte offset 0x141, CSR Addr 0x540a0, Direction=N/A + + uint8_t Reserved142; // Byte offset 0x142, CSR Addr 0x540a1, Direction=N/A + + uint8_t Reserved143; // Byte offset 0x143, CSR Addr 0x540a1, Direction=N/A + + uint8_t Reserved144; // Byte offset 0x144, CSR Addr 0x540a2, Direction=N/A + + uint8_t Reserved145; // Byte offset 0x145, CSR Addr 0x540a2, Direction=N/A + + uint8_t Reserved146; // Byte offset 0x146, CSR Addr 0x540a3, Direction=N/A + + uint8_t Reserved147; // Byte offset 0x147, CSR Addr 0x540a3, Direction=N/A + + uint8_t Reserved148; // Byte offset 0x148, CSR Addr 0x540a4, Direction=N/A + + uint8_t Reserved149; // Byte offset 0x149, CSR Addr 0x540a4, Direction=N/A + + uint8_t Reserved14A; // Byte offset 0x14a, CSR Addr 0x540a5, Direction=N/A + + uint8_t Reserved14B; // Byte offset 0x14b, CSR Addr 0x540a5, Direction=N/A + + uint8_t Reserved14C; // Byte offset 0x14c, CSR Addr 0x540a6, Direction=N/A + + uint8_t Reserved14D; // Byte offset 0x14d, CSR Addr 0x540a6, Direction=N/A + + uint8_t Reserved14E; // Byte offset 0x14e, CSR Addr 0x540a7, Direction=N/A + + uint8_t Reserved14F; // Byte offset 0x14f, CSR Addr 0x540a7, Direction=N/A + + uint8_t Reserved150; // Byte offset 0x150, CSR Addr 0x540a8, Direction=N/A + + uint8_t Reserved151; // Byte offset 0x151, CSR Addr 0x540a8, Direction=N/A + + uint8_t Reserved152; // Byte offset 0x152, CSR Addr 0x540a9, Direction=N/A + + uint8_t Reserved153; // Byte offset 0x153, CSR Addr 0x540a9, Direction=N/A + + uint8_t Reserved154; // Byte offset 0x154, CSR Addr 0x540aa, Direction=N/A + + uint8_t Reserved155; // Byte offset 0x155, CSR Addr 0x540aa, Direction=N/A + + uint8_t Reserved156; // Byte offset 0x156, CSR Addr 0x540ab, Direction=N/A + + uint8_t Reserved157; // Byte offset 0x157, CSR Addr 0x540ab, Direction=N/A + + uint8_t Reserved158; // Byte offset 0x158, CSR Addr 0x540ac, Direction=N/A + + uint8_t Reserved159; // Byte offset 0x159, CSR Addr 0x540ac, Direction=N/A + + uint8_t Reserved15A; // Byte offset 0x15a, CSR Addr 0x540ad, Direction=N/A + + uint8_t Reserved15B; // Byte offset 0x15b, CSR Addr 0x540ad, Direction=N/A + + uint8_t Reserved15C; // Byte offset 0x15c, CSR Addr 0x540ae, Direction=N/A + + uint8_t Reserved15D; // Byte offset 0x15d, CSR Addr 0x540ae, Direction=N/A + + uint8_t Reserved15E; // Byte offset 0x15e, CSR Addr 0x540af, Direction=N/A + + uint8_t Reserved15F; // Byte offset 0x15f, CSR Addr 0x540af, Direction=N/A + + uint8_t Reserved160; // Byte offset 0x160, CSR Addr 0x540b0, Direction=N/A + + uint8_t Reserved161; // Byte offset 0x161, CSR Addr 0x540b0, Direction=N/A + + uint8_t Reserved162; // Byte offset 0x162, CSR Addr 0x540b1, Direction=N/A + + uint8_t Reserved163; // Byte offset 0x163, CSR Addr 0x540b1, Direction=N/A + + uint8_t Reserved164; // Byte offset 0x164, CSR Addr 0x540b2, Direction=N/A + + uint8_t Reserved165; // Byte offset 0x165, CSR Addr 0x540b2, Direction=N/A + + uint8_t Reserved166; // Byte offset 0x166, CSR Addr 0x540b3, Direction=N/A + + uint8_t Reserved167; // Byte offset 0x167, CSR Addr 0x540b3, Direction=N/A + + uint8_t Reserved168; // Byte offset 0x168, CSR Addr 0x540b4, Direction=N/A + + uint8_t Reserved169; // Byte offset 0x169, CSR Addr 0x540b4, Direction=N/A + + uint8_t Reserved16A; // Byte offset 0x16a, CSR Addr 0x540b5, Direction=N/A + + uint8_t Reserved16B; // Byte offset 0x16b, CSR Addr 0x540b5, Direction=N/A + + uint8_t Reserved16C; // Byte offset 0x16c, CSR Addr 0x540b6, Direction=N/A + + uint8_t Reserved16D; // Byte offset 0x16d, CSR Addr 0x540b6, Direction=N/A + + uint8_t Reserved16E; // Byte offset 0x16e, CSR Addr 0x540b7, Direction=N/A + + uint8_t Reserved16F; // Byte offset 0x16f, CSR Addr 0x540b7, Direction=N/A + + uint8_t Reserved170; // Byte offset 0x170, CSR Addr 0x540b8, Direction=N/A + + uint8_t Reserved171; // Byte offset 0x171, CSR Addr 0x540b8, Direction=N/A + + uint8_t Reserved172; // Byte offset 0x172, CSR Addr 0x540b9, Direction=N/A + + uint8_t Reserved173; // Byte offset 0x173, CSR Addr 0x540b9, Direction=N/A + + uint8_t Reserved174; // Byte offset 0x174, CSR Addr 0x540ba, Direction=N/A + + uint8_t Reserved175; // Byte offset 0x175, CSR Addr 0x540ba, Direction=N/A + + uint8_t Reserved176; // Byte offset 0x176, CSR Addr 0x540bb, Direction=N/A + + uint8_t Reserved177; // Byte offset 0x177, CSR Addr 0x540bb, Direction=N/A + + uint8_t Reserved178; // Byte offset 0x178, CSR Addr 0x540bc, Direction=N/A + + uint8_t Reserved179; // Byte offset 0x179, CSR Addr 0x540bc, Direction=N/A + + uint8_t Reserved17A; // Byte offset 0x17a, CSR Addr 0x540bd, Direction=N/A + + uint8_t Reserved17B; // Byte offset 0x17b, CSR Addr 0x540bd, Direction=N/A + + uint8_t Reserved17C; // Byte offset 0x17c, CSR Addr 0x540be, Direction=N/A + + uint8_t Reserved17D; // Byte offset 0x17d, CSR Addr 0x540be, Direction=N/A + + uint8_t Reserved17E; // Byte offset 0x17e, CSR Addr 0x540bf, Direction=N/A + + uint8_t Reserved17F; // Byte offset 0x17f, CSR Addr 0x540bf, Direction=N/A + + uint8_t Reserved180; // Byte offset 0x180, CSR Addr 0x540c0, Direction=N/A + + uint8_t Reserved181; // Byte offset 0x181, CSR Addr 0x540c0, Direction=N/A + + uint8_t Reserved182; // Byte offset 0x182, CSR Addr 0x540c1, Direction=N/A + + uint8_t Reserved183; // Byte offset 0x183, CSR Addr 0x540c1, Direction=N/A + + uint8_t Reserved184; // Byte offset 0x184, CSR Addr 0x540c2, Direction=N/A + + uint8_t Reserved185; // Byte offset 0x185, CSR Addr 0x540c2, Direction=N/A + + uint8_t Reserved186; // Byte offset 0x186, CSR Addr 0x540c3, Direction=N/A + + uint8_t Reserved187; // Byte offset 0x187, CSR Addr 0x540c3, Direction=N/A + + uint8_t Reserved188; // Byte offset 0x188, CSR Addr 0x540c4, Direction=N/A + + uint8_t Reserved189; // Byte offset 0x189, CSR Addr 0x540c4, Direction=N/A + + uint8_t Reserved18A; // Byte offset 0x18a, CSR Addr 0x540c5, Direction=N/A + + uint8_t Reserved18B; // Byte offset 0x18b, CSR Addr 0x540c5, Direction=N/A + + uint8_t Reserved18C; // Byte offset 0x18c, CSR Addr 0x540c6, Direction=N/A + + uint8_t Reserved18D; // Byte offset 0x18d, CSR Addr 0x540c6, Direction=N/A + + uint8_t Reserved18E; // Byte offset 0x18e, CSR Addr 0x540c7, Direction=N/A + + uint8_t Reserved18F; // Byte offset 0x18f, CSR Addr 0x540c7, Direction=N/A + + uint8_t Reserved190; // Byte offset 0x190, CSR Addr 0x540c8, Direction=N/A + + uint8_t Reserved191; // Byte offset 0x191, CSR Addr 0x540c8, Direction=N/A + + uint8_t Reserved192; // Byte offset 0x192, CSR Addr 0x540c9, Direction=N/A + + uint8_t Reserved193; // Byte offset 0x193, CSR Addr 0x540c9, Direction=N/A + + uint8_t Reserved194; // Byte offset 0x194, CSR Addr 0x540ca, Direction=N/A + + uint8_t Reserved195; // Byte offset 0x195, CSR Addr 0x540ca, Direction=N/A + + uint8_t Reserved196; // Byte offset 0x196, CSR Addr 0x540cb, Direction=N/A + + uint8_t Reserved197; // Byte offset 0x197, CSR Addr 0x540cb, Direction=N/A + + uint8_t Reserved198; // Byte offset 0x198, CSR Addr 0x540cc, Direction=N/A + + uint8_t Reserved199; // Byte offset 0x199, CSR Addr 0x540cc, Direction=N/A + + uint8_t Reserved19A; // Byte offset 0x19a, CSR Addr 0x540cd, Direction=N/A + + uint8_t Reserved19B; // Byte offset 0x19b, CSR Addr 0x540cd, Direction=N/A + + uint8_t Reserved19C; // Byte offset 0x19c, CSR Addr 0x540ce, Direction=N/A + + uint8_t Reserved19D; // Byte offset 0x19d, CSR Addr 0x540ce, Direction=N/A + + uint8_t Reserved19E; // Byte offset 0x19e, CSR Addr 0x540cf, Direction=N/A + + uint8_t Reserved19F; // Byte offset 0x19f, CSR Addr 0x540cf, Direction=N/A + + uint8_t Reserved1A0; // Byte offset 0x1a0, CSR Addr 0x540d0, Direction=N/A + + uint8_t Reserved1A1; // Byte offset 0x1a1, CSR Addr 0x540d0, Direction=N/A + + uint8_t Reserved1A2; // Byte offset 0x1a2, CSR Addr 0x540d1, Direction=N/A + + uint8_t Reserved1A3; // Byte offset 0x1a3, CSR Addr 0x540d1, Direction=N/A + + uint8_t Reserved1A4; // Byte offset 0x1a4, CSR Addr 0x540d2, Direction=N/A + + uint8_t Reserved1A5; // Byte offset 0x1a5, CSR Addr 0x540d2, Direction=N/A + + uint8_t Reserved1A6; // Byte offset 0x1a6, CSR Addr 0x540d3, Direction=N/A + + uint8_t Reserved1A7; // Byte offset 0x1a7, CSR Addr 0x540d3, Direction=N/A + + uint8_t Reserved1A8; // Byte offset 0x1a8, CSR Addr 0x540d4, Direction=N/A + + uint8_t Reserved1A9; // Byte offset 0x1a9, CSR Addr 0x540d4, Direction=N/A + + uint8_t Reserved1AA; // Byte offset 0x1aa, CSR Addr 0x540d5, Direction=N/A + + uint8_t Reserved1AB; // Byte offset 0x1ab, CSR Addr 0x540d5, Direction=N/A + + uint8_t Reserved1AC; // Byte offset 0x1ac, CSR Addr 0x540d6, Direction=N/A + + uint8_t Reserved1AD; // Byte offset 0x1ad, CSR Addr 0x540d6, Direction=N/A + + uint8_t Reserved1AE; // Byte offset 0x1ae, CSR Addr 0x540d7, Direction=N/A + + uint8_t Reserved1AF; // Byte offset 0x1af, CSR Addr 0x540d7, Direction=N/A + + uint8_t Reserved1B0; // Byte offset 0x1b0, CSR Addr 0x540d8, Direction=N/A + + uint8_t Reserved1B1; // Byte offset 0x1b1, CSR Addr 0x540d8, Direction=N/A + + uint8_t Reserved1B2; // Byte offset 0x1b2, CSR Addr 0x540d9, Direction=N/A + + uint8_t Reserved1B3; // Byte offset 0x1b3, CSR Addr 0x540d9, Direction=N/A + + uint8_t Reserved1B4; // Byte offset 0x1b4, CSR Addr 0x540da, Direction=N/A + + uint8_t Reserved1B5; // Byte offset 0x1b5, CSR Addr 0x540da, Direction=N/A + + uint8_t Reserved1B6; // Byte offset 0x1b6, CSR Addr 0x540db, Direction=N/A + + uint8_t Reserved1B7; // Byte offset 0x1b7, CSR Addr 0x540db, Direction=N/A + + uint8_t Reserved1B8; // Byte offset 0x1b8, CSR Addr 0x540dc, Direction=N/A + + uint8_t Reserved1B9; // Byte offset 0x1b9, CSR Addr 0x540dc, Direction=N/A + + uint8_t Reserved1BA; // Byte offset 0x1ba, CSR Addr 0x540dd, Direction=N/A + + uint8_t Reserved1BB; // Byte offset 0x1bb, CSR Addr 0x540dd, Direction=N/A + + uint8_t Reserved1BC; // Byte offset 0x1bc, CSR Addr 0x540de, Direction=N/A + + uint8_t Reserved1BD; // Byte offset 0x1bd, CSR Addr 0x540de, Direction=N/A + + uint8_t Reserved1BE; // Byte offset 0x1be, CSR Addr 0x540df, Direction=N/A + + uint8_t Reserved1BF; // Byte offset 0x1bf, CSR Addr 0x540df, Direction=N/A + + uint8_t Reserved1C0; // Byte offset 0x1c0, CSR Addr 0x540e0, Direction=N/A + + uint8_t Reserved1C1; // Byte offset 0x1c1, CSR Addr 0x540e0, Direction=N/A + + uint8_t Reserved1C2; // Byte offset 0x1c2, CSR Addr 0x540e1, Direction=N/A + + uint8_t Reserved1C3; // Byte offset 0x1c3, CSR Addr 0x540e1, Direction=N/A + + uint8_t Reserved1C4; // Byte offset 0x1c4, CSR Addr 0x540e2, Direction=N/A + + uint8_t Reserved1C5; // Byte offset 0x1c5, CSR Addr 0x540e2, Direction=N/A + + uint8_t Reserved1C6; // Byte offset 0x1c6, CSR Addr 0x540e3, Direction=N/A + + uint8_t Reserved1C7; // Byte offset 0x1c7, CSR Addr 0x540e3, Direction=N/A + + uint8_t Reserved1C8; // Byte offset 0x1c8, CSR Addr 0x540e4, Direction=N/A + + uint8_t Reserved1C9; // Byte offset 0x1c9, CSR Addr 0x540e4, Direction=N/A + + uint8_t Reserved1CA; // Byte offset 0x1ca, CSR Addr 0x540e5, Direction=N/A + + uint8_t Reserved1CB; // Byte offset 0x1cb, CSR Addr 0x540e5, Direction=N/A + + uint8_t Reserved1CC; // Byte offset 0x1cc, CSR Addr 0x540e6, Direction=N/A + + uint8_t Reserved1CD; // Byte offset 0x1cd, CSR Addr 0x540e6, Direction=N/A + + uint8_t Reserved1CE; // Byte offset 0x1ce, CSR Addr 0x540e7, Direction=N/A + + uint8_t Reserved1CF; // Byte offset 0x1cf, CSR Addr 0x540e7, Direction=N/A + + uint8_t Reserved1D0; // Byte offset 0x1d0, CSR Addr 0x540e8, Direction=N/A + + uint8_t Reserved1D1; // Byte offset 0x1d1, CSR Addr 0x540e8, Direction=N/A + + uint8_t Reserved1D2; // Byte offset 0x1d2, CSR Addr 0x540e9, Direction=N/A + + uint8_t Reserved1D3; // Byte offset 0x1d3, CSR Addr 0x540e9, Direction=N/A + + uint8_t Reserved1D4; // Byte offset 0x1d4, CSR Addr 0x540ea, Direction=N/A + + uint8_t Reserved1D5; // Byte offset 0x1d5, CSR Addr 0x540ea, Direction=N/A + + uint8_t Reserved1D6; // Byte offset 0x1d6, CSR Addr 0x540eb, Direction=N/A + + uint8_t Reserved1D7; // Byte offset 0x1d7, CSR Addr 0x540eb, Direction=N/A + + uint8_t Reserved1D8; // Byte offset 0x1d8, CSR Addr 0x540ec, Direction=N/A + + uint8_t Reserved1D9; // Byte offset 0x1d9, CSR Addr 0x540ec, Direction=N/A + + uint8_t Reserved1DA; // Byte offset 0x1da, CSR Addr 0x540ed, Direction=N/A + + uint8_t Reserved1DB; // Byte offset 0x1db, CSR Addr 0x540ed, Direction=N/A + + uint8_t Reserved1DC; // Byte offset 0x1dc, CSR Addr 0x540ee, Direction=N/A + + uint8_t Reserved1DD; // Byte offset 0x1dd, CSR Addr 0x540ee, Direction=N/A + + uint8_t Reserved1DE; // Byte offset 0x1de, CSR Addr 0x540ef, Direction=N/A + + uint8_t Reserved1DF; // Byte offset 0x1df, CSR Addr 0x540ef, Direction=N/A + + uint8_t Reserved1E0; // Byte offset 0x1e0, CSR Addr 0x540f0, Direction=N/A + + uint8_t Reserved1E1; // Byte offset 0x1e1, CSR Addr 0x540f0, Direction=N/A + + uint8_t Reserved1E2; // Byte offset 0x1e2, CSR Addr 0x540f1, Direction=N/A + + uint8_t Reserved1E3; // Byte offset 0x1e3, CSR Addr 0x540f1, Direction=N/A + + uint8_t Reserved1E4; // Byte offset 0x1e4, CSR Addr 0x540f2, Direction=N/A + + uint8_t Reserved1E5; // Byte offset 0x1e5, CSR Addr 0x540f2, Direction=N/A + + uint8_t Reserved1E6; // Byte offset 0x1e6, CSR Addr 0x540f3, Direction=N/A + + uint8_t Reserved1E7; // Byte offset 0x1e7, CSR Addr 0x540f3, Direction=N/A + + uint8_t Reserved1E8; // Byte offset 0x1e8, CSR Addr 0x540f4, Direction=N/A + + uint8_t Reserved1E9; // Byte offset 0x1e9, CSR Addr 0x540f4, Direction=N/A + + uint8_t Reserved1EA; // Byte offset 0x1ea, CSR Addr 0x540f5, Direction=N/A + + uint8_t Reserved1EB; // Byte offset 0x1eb, CSR Addr 0x540f5, Direction=N/A + + uint8_t Reserved1EC; // Byte offset 0x1ec, CSR Addr 0x540f6, Direction=N/A + + uint8_t Reserved1ED; // Byte offset 0x1ed, CSR Addr 0x540f6, Direction=N/A + + uint8_t Reserved1EE; // Byte offset 0x1ee, CSR Addr 0x540f7, Direction=N/A + + uint8_t Reserved1EF; // Byte offset 0x1ef, CSR Addr 0x540f7, Direction=N/A + + uint8_t Reserved1F0; // Byte offset 0x1f0, CSR Addr 0x540f8, Direction=N/A + + uint8_t Reserved1F1; // Byte offset 0x1f1, CSR Addr 0x540f8, Direction=N/A + + uint8_t Reserved1F2; // Byte offset 0x1f2, CSR Addr 0x540f9, Direction=N/A + + uint8_t Reserved1F3; // Byte offset 0x1f3, CSR Addr 0x540f9, Direction=N/A + + uint8_t Reserved1F4; // Byte offset 0x1f4, CSR Addr 0x540fa, Direction=N/A + + uint8_t Reserved1F5; // Byte offset 0x1f5, CSR Addr 0x540fa, Direction=N/A + + uint8_t Reserved1F6; // Byte offset 0x1f6, CSR Addr 0x540fb, Direction=N/A + + uint8_t Reserved1F7; // Byte offset 0x1f7, CSR Addr 0x540fb, Direction=N/A + + uint8_t Reserved1F8; // Byte offset 0x1f8, CSR Addr 0x540fc, Direction=N/A + + uint8_t Reserved1F9; // Byte offset 0x1f9, CSR Addr 0x540fc, Direction=N/A + + uint8_t Reserved1FA; // Byte offset 0x1fa, CSR Addr 0x540fd, Direction=N/A + + uint8_t Reserved1FB; // Byte offset 0x1fb, CSR Addr 0x540fd, Direction=N/A + + uint8_t Reserved1FC; // Byte offset 0x1fc, CSR Addr 0x540fe, Direction=N/A + + uint8_t Reserved1FD; // Byte offset 0x1fd, CSR Addr 0x540fe, Direction=N/A + + uint8_t Reserved1FE; // Byte offset 0x1fe, CSR Addr 0x540ff, Direction=N/A + + uint8_t Reserved1FF; // Byte offset 0x1ff, CSR Addr 0x540ff, Direction=N/A + + uint8_t Reserved200; // Byte offset 0x200, CSR Addr 0x54100, Direction=N/A + + uint8_t Reserved201; // Byte offset 0x201, CSR Addr 0x54100, Direction=N/A + + uint8_t Reserved202; // Byte offset 0x202, CSR Addr 0x54101, Direction=N/A + + uint8_t Reserved203; // Byte offset 0x203, CSR Addr 0x54101, Direction=N/A + + uint8_t Reserved204; // Byte offset 0x204, CSR Addr 0x54102, Direction=N/A + + uint8_t Reserved205; // Byte offset 0x205, CSR Addr 0x54102, Direction=N/A + + uint8_t Reserved206; // Byte offset 0x206, CSR Addr 0x54103, Direction=N/A + + uint8_t Reserved207; // Byte offset 0x207, CSR Addr 0x54103, Direction=N/A + + uint8_t Reserved208; // Byte offset 0x208, CSR Addr 0x54104, Direction=N/A + + uint8_t Reserved209; // Byte offset 0x209, CSR Addr 0x54104, Direction=N/A + + uint8_t Reserved20A; // Byte offset 0x20a, CSR Addr 0x54105, Direction=N/A + + uint8_t Reserved20B; // Byte offset 0x20b, CSR Addr 0x54105, Direction=N/A + + uint8_t Reserved20C; // Byte offset 0x20c, CSR Addr 0x54106, Direction=N/A + + uint8_t Reserved20D; // Byte offset 0x20d, CSR Addr 0x54106, Direction=N/A + + uint8_t Reserved20E; // Byte offset 0x20e, CSR Addr 0x54107, Direction=N/A + + uint8_t Reserved20F; // Byte offset 0x20f, CSR Addr 0x54107, Direction=N/A + + uint8_t Reserved210; // Byte offset 0x210, CSR Addr 0x54108, Direction=N/A + + uint8_t Reserved211; // Byte offset 0x211, CSR Addr 0x54108, Direction=N/A + + uint8_t Reserved212; // Byte offset 0x212, CSR Addr 0x54109, Direction=N/A + + uint8_t Reserved213; // Byte offset 0x213, CSR Addr 0x54109, Direction=N/A + + uint8_t Reserved214; // Byte offset 0x214, CSR Addr 0x5410a, Direction=N/A + + uint8_t Reserved215; // Byte offset 0x215, CSR Addr 0x5410a, Direction=N/A + + uint8_t Reserved216; // Byte offset 0x216, CSR Addr 0x5410b, Direction=N/A + + uint8_t Reserved217; // Byte offset 0x217, CSR Addr 0x5410b, Direction=N/A + + uint8_t Reserved218; // Byte offset 0x218, CSR Addr 0x5410c, Direction=N/A + + uint8_t Reserved219; // Byte offset 0x219, CSR Addr 0x5410c, Direction=N/A + + uint8_t Reserved21A; // Byte offset 0x21a, CSR Addr 0x5410d, Direction=N/A + + uint8_t Reserved21B; // Byte offset 0x21b, CSR Addr 0x5410d, Direction=N/A + + uint8_t Reserved21C; // Byte offset 0x21c, CSR Addr 0x5410e, Direction=N/A + + uint8_t Reserved21D; // Byte offset 0x21d, CSR Addr 0x5410e, Direction=N/A + + uint8_t Reserved21E; // Byte offset 0x21e, CSR Addr 0x5410f, Direction=N/A + + uint8_t Reserved21F; // Byte offset 0x21f, CSR Addr 0x5410f, Direction=N/A + + uint8_t Reserved220; // Byte offset 0x220, CSR Addr 0x54110, Direction=N/A + + uint8_t Reserved221; // Byte offset 0x221, CSR Addr 0x54110, Direction=N/A + + uint8_t Reserved222; // Byte offset 0x222, CSR Addr 0x54111, Direction=N/A + + uint8_t Reserved223; // Byte offset 0x223, CSR Addr 0x54111, Direction=N/A + + uint8_t Reserved224; // Byte offset 0x224, CSR Addr 0x54112, Direction=N/A + + uint8_t Reserved225; // Byte offset 0x225, CSR Addr 0x54112, Direction=N/A + + uint8_t Reserved226; // Byte offset 0x226, CSR Addr 0x54113, Direction=N/A + + uint8_t Reserved227; // Byte offset 0x227, CSR Addr 0x54113, Direction=N/A + + uint8_t Reserved228; // Byte offset 0x228, CSR Addr 0x54114, Direction=N/A + + uint8_t Reserved229; // Byte offset 0x229, CSR Addr 0x54114, Direction=N/A + + uint8_t Reserved22A; // Byte offset 0x22a, CSR Addr 0x54115, Direction=N/A + + uint8_t Reserved22B; // Byte offset 0x22b, CSR Addr 0x54115, Direction=N/A + + uint8_t Reserved22C; // Byte offset 0x22c, CSR Addr 0x54116, Direction=N/A + + uint8_t Reserved22D; // Byte offset 0x22d, CSR Addr 0x54116, Direction=N/A + + uint8_t Reserved22E; // Byte offset 0x22e, CSR Addr 0x54117, Direction=N/A + + uint8_t Reserved22F; // Byte offset 0x22f, CSR Addr 0x54117, Direction=N/A + + uint8_t Reserved230; // Byte offset 0x230, CSR Addr 0x54118, Direction=N/A + + uint8_t Reserved231; // Byte offset 0x231, CSR Addr 0x54118, Direction=N/A + + uint8_t Reserved232; // Byte offset 0x232, CSR Addr 0x54119, Direction=N/A + + uint8_t Reserved233; // Byte offset 0x233, CSR Addr 0x54119, Direction=N/A + + uint8_t Reserved234; // Byte offset 0x234, CSR Addr 0x5411a, Direction=N/A + + uint8_t Reserved235; // Byte offset 0x235, CSR Addr 0x5411a, Direction=N/A + + uint8_t Reserved236; // Byte offset 0x236, CSR Addr 0x5411b, Direction=N/A + + uint8_t Reserved237; // Byte offset 0x237, CSR Addr 0x5411b, Direction=N/A + + uint8_t Reserved238; // Byte offset 0x238, CSR Addr 0x5411c, Direction=N/A + + uint8_t Reserved239; // Byte offset 0x239, CSR Addr 0x5411c, Direction=N/A + + uint8_t Reserved23A; // Byte offset 0x23a, CSR Addr 0x5411d, Direction=N/A + + uint8_t Reserved23B; // Byte offset 0x23b, CSR Addr 0x5411d, Direction=N/A + + uint8_t Reserved23C; // Byte offset 0x23c, CSR Addr 0x5411e, Direction=N/A + + uint8_t Reserved23D; // Byte offset 0x23d, CSR Addr 0x5411e, Direction=N/A + + uint8_t Reserved23E; // Byte offset 0x23e, CSR Addr 0x5411f, Direction=N/A + + uint8_t Reserved23F; // Byte offset 0x23f, CSR Addr 0x5411f, Direction=N/A + + uint8_t Reserved240; // Byte offset 0x240, CSR Addr 0x54120, Direction=N/A + + uint8_t Reserved241; // Byte offset 0x241, CSR Addr 0x54120, Direction=N/A + + uint8_t Reserved242; // Byte offset 0x242, CSR Addr 0x54121, Direction=N/A + + uint8_t Reserved243; // Byte offset 0x243, CSR Addr 0x54121, Direction=N/A + + uint8_t Reserved244; // Byte offset 0x244, CSR Addr 0x54122, Direction=N/A + + uint8_t Reserved245; // Byte offset 0x245, CSR Addr 0x54122, Direction=N/A + + uint8_t Reserved246; // Byte offset 0x246, CSR Addr 0x54123, Direction=N/A + + uint8_t Reserved247; // Byte offset 0x247, CSR Addr 0x54123, Direction=N/A + + uint8_t Reserved248; // Byte offset 0x248, CSR Addr 0x54124, Direction=N/A + + uint8_t Reserved249; // Byte offset 0x249, CSR Addr 0x54124, Direction=N/A + + uint8_t Reserved24A; // Byte offset 0x24a, CSR Addr 0x54125, Direction=N/A + + uint8_t Reserved24B; // Byte offset 0x24b, CSR Addr 0x54125, Direction=N/A + + uint8_t Reserved24C; // Byte offset 0x24c, CSR Addr 0x54126, Direction=N/A + + uint8_t Reserved24D; // Byte offset 0x24d, CSR Addr 0x54126, Direction=N/A + + uint8_t Reserved24E; // Byte offset 0x24e, CSR Addr 0x54127, Direction=N/A + + uint8_t Reserved24F; // Byte offset 0x24f, CSR Addr 0x54127, Direction=N/A + + uint8_t Reserved250; // Byte offset 0x250, CSR Addr 0x54128, Direction=N/A + + uint8_t Reserved251; // Byte offset 0x251, CSR Addr 0x54128, Direction=N/A + + uint8_t Reserved252; // Byte offset 0x252, CSR Addr 0x54129, Direction=N/A + + uint8_t Reserved253; // Byte offset 0x253, CSR Addr 0x54129, Direction=N/A + + uint8_t Reserved254; // Byte offset 0x254, CSR Addr 0x5412a, Direction=N/A + + uint8_t Reserved255; // Byte offset 0x255, CSR Addr 0x5412a, Direction=N/A + + uint8_t Reserved256; // Byte offset 0x256, CSR Addr 0x5412b, Direction=N/A + + uint8_t Reserved257; // Byte offset 0x257, CSR Addr 0x5412b, Direction=N/A + + uint8_t Reserved258; // Byte offset 0x258, CSR Addr 0x5412c, Direction=N/A + + uint8_t Reserved259; // Byte offset 0x259, CSR Addr 0x5412c, Direction=N/A + + uint8_t Reserved25A; // Byte offset 0x25a, CSR Addr 0x5412d, Direction=N/A + + uint8_t Reserved25B; // Byte offset 0x25b, CSR Addr 0x5412d, Direction=N/A + + uint8_t Reserved25C; // Byte offset 0x25c, CSR Addr 0x5412e, Direction=N/A + + uint8_t Reserved25D; // Byte offset 0x25d, CSR Addr 0x5412e, Direction=N/A + + uint8_t Reserved25E; // Byte offset 0x25e, CSR Addr 0x5412f, Direction=N/A + + uint8_t Reserved25F; // Byte offset 0x25f, CSR Addr 0x5412f, Direction=N/A + + uint8_t Reserved260; // Byte offset 0x260, CSR Addr 0x54130, Direction=N/A + + uint8_t Reserved261; // Byte offset 0x261, CSR Addr 0x54130, Direction=N/A + + uint8_t Reserved262; // Byte offset 0x262, CSR Addr 0x54131, Direction=N/A + + uint8_t Reserved263; // Byte offset 0x263, CSR Addr 0x54131, Direction=N/A + + uint8_t Reserved264; // Byte offset 0x264, CSR Addr 0x54132, Direction=N/A + + uint8_t Reserved265; // Byte offset 0x265, CSR Addr 0x54132, Direction=N/A + + uint8_t Reserved266; // Byte offset 0x266, CSR Addr 0x54133, Direction=N/A + + uint8_t Reserved267; // Byte offset 0x267, CSR Addr 0x54133, Direction=N/A + + uint8_t Reserved268; // Byte offset 0x268, CSR Addr 0x54134, Direction=N/A + + uint8_t Reserved269; // Byte offset 0x269, CSR Addr 0x54134, Direction=N/A + + uint8_t Reserved26A; // Byte offset 0x26a, CSR Addr 0x54135, Direction=N/A + + uint8_t Reserved26B; // Byte offset 0x26b, CSR Addr 0x54135, Direction=N/A + + uint8_t Reserved26C; // Byte offset 0x26c, CSR Addr 0x54136, Direction=N/A + + uint8_t Reserved26D; // Byte offset 0x26d, CSR Addr 0x54136, Direction=N/A + + uint8_t Reserved26E; // Byte offset 0x26e, CSR Addr 0x54137, Direction=N/A + + uint8_t Reserved26F; // Byte offset 0x26f, CSR Addr 0x54137, Direction=N/A + + uint8_t Reserved270; // Byte offset 0x270, CSR Addr 0x54138, Direction=N/A + + uint8_t Reserved271; // Byte offset 0x271, CSR Addr 0x54138, Direction=N/A + + uint8_t Reserved272; // Byte offset 0x272, CSR Addr 0x54139, Direction=N/A + + uint8_t Reserved273; // Byte offset 0x273, CSR Addr 0x54139, Direction=N/A + + uint8_t Reserved274; // Byte offset 0x274, CSR Addr 0x5413a, Direction=N/A + + uint8_t Reserved275; // Byte offset 0x275, CSR Addr 0x5413a, Direction=N/A + + uint8_t Reserved276; // Byte offset 0x276, CSR Addr 0x5413b, Direction=N/A + + uint8_t Reserved277; // Byte offset 0x277, CSR Addr 0x5413b, Direction=N/A + + uint8_t Reserved278; // Byte offset 0x278, CSR Addr 0x5413c, Direction=N/A + + uint8_t Reserved279; // Byte offset 0x279, CSR Addr 0x5413c, Direction=N/A + + uint8_t Reserved27A; // Byte offset 0x27a, CSR Addr 0x5413d, Direction=N/A + + uint8_t Reserved27B; // Byte offset 0x27b, CSR Addr 0x5413d, Direction=N/A + + uint8_t Reserved27C; // Byte offset 0x27c, CSR Addr 0x5413e, Direction=N/A + + uint8_t Reserved27D; // Byte offset 0x27d, CSR Addr 0x5413e, Direction=N/A + + uint8_t Reserved27E; // Byte offset 0x27e, CSR Addr 0x5413f, Direction=N/A + + uint8_t Reserved27F; // Byte offset 0x27f, CSR Addr 0x5413f, Direction=N/A + + uint8_t Reserved280; // Byte offset 0x280, CSR Addr 0x54140, Direction=N/A + + uint8_t Reserved281; // Byte offset 0x281, CSR Addr 0x54140, Direction=N/A + + uint8_t Reserved282; // Byte offset 0x282, CSR Addr 0x54141, Direction=N/A + + uint8_t Reserved283; // Byte offset 0x283, CSR Addr 0x54141, Direction=N/A + + uint8_t Reserved284; // Byte offset 0x284, CSR Addr 0x54142, Direction=N/A + + uint8_t Reserved285; // Byte offset 0x285, CSR Addr 0x54142, Direction=N/A + + uint8_t Reserved286; // Byte offset 0x286, CSR Addr 0x54143, Direction=N/A + + uint8_t Reserved287; // Byte offset 0x287, CSR Addr 0x54143, Direction=N/A + + uint8_t Reserved288; // Byte offset 0x288, CSR Addr 0x54144, Direction=N/A + + uint8_t Reserved289; // Byte offset 0x289, CSR Addr 0x54144, Direction=N/A + + uint8_t Reserved28A; // Byte offset 0x28a, CSR Addr 0x54145, Direction=N/A + + uint8_t Reserved28B; // Byte offset 0x28b, CSR Addr 0x54145, Direction=N/A + + uint8_t Reserved28C; // Byte offset 0x28c, CSR Addr 0x54146, Direction=N/A + + uint8_t Reserved28D; // Byte offset 0x28d, CSR Addr 0x54146, Direction=N/A + + uint8_t Reserved28E; // Byte offset 0x28e, CSR Addr 0x54147, Direction=N/A + + uint8_t Reserved28F; // Byte offset 0x28f, CSR Addr 0x54147, Direction=N/A + + uint8_t Reserved290; // Byte offset 0x290, CSR Addr 0x54148, Direction=N/A + + uint8_t Reserved291; // Byte offset 0x291, CSR Addr 0x54148, Direction=N/A + + uint8_t Reserved292; // Byte offset 0x292, CSR Addr 0x54149, Direction=N/A + + uint8_t Reserved293; // Byte offset 0x293, CSR Addr 0x54149, Direction=N/A + + uint8_t Reserved294; // Byte offset 0x294, CSR Addr 0x5414a, Direction=N/A + + uint8_t Reserved295; // Byte offset 0x295, CSR Addr 0x5414a, Direction=N/A + + uint8_t Reserved296; // Byte offset 0x296, CSR Addr 0x5414b, Direction=N/A + + uint8_t Reserved297; // Byte offset 0x297, CSR Addr 0x5414b, Direction=N/A + + uint8_t Reserved298; // Byte offset 0x298, CSR Addr 0x5414c, Direction=N/A + + uint8_t Reserved299; // Byte offset 0x299, CSR Addr 0x5414c, Direction=N/A + + uint8_t Reserved29A; // Byte offset 0x29a, CSR Addr 0x5414d, Direction=N/A + + uint8_t Reserved29B; // Byte offset 0x29b, CSR Addr 0x5414d, Direction=N/A + + uint8_t Reserved29C; // Byte offset 0x29c, CSR Addr 0x5414e, Direction=N/A + + uint8_t Reserved29D; // Byte offset 0x29d, CSR Addr 0x5414e, Direction=N/A + + uint8_t Reserved29E; // Byte offset 0x29e, CSR Addr 0x5414f, Direction=N/A + + uint8_t Reserved29F; // Byte offset 0x29f, CSR Addr 0x5414f, Direction=N/A + + uint8_t Reserved2A0; // Byte offset 0x2a0, CSR Addr 0x54150, Direction=N/A + + uint8_t Reserved2A1; // Byte offset 0x2a1, CSR Addr 0x54150, Direction=N/A + + uint8_t Reserved2A2; // Byte offset 0x2a2, CSR Addr 0x54151, Direction=N/A + + uint8_t Reserved2A3; // Byte offset 0x2a3, CSR Addr 0x54151, Direction=N/A + + uint8_t Reserved2A4; // Byte offset 0x2a4, CSR Addr 0x54152, Direction=N/A + + uint8_t Reserved2A5; // Byte offset 0x2a5, CSR Addr 0x54152, Direction=N/A + + uint8_t Reserved2A6; // Byte offset 0x2a6, CSR Addr 0x54153, Direction=N/A + + uint8_t Reserved2A7; // Byte offset 0x2a7, CSR Addr 0x54153, Direction=N/A + + uint8_t Reserved2A8; // Byte offset 0x2a8, CSR Addr 0x54154, Direction=N/A + + uint8_t Reserved2A9; // Byte offset 0x2a9, CSR Addr 0x54154, Direction=N/A + + uint8_t Reserved2AA; // Byte offset 0x2aa, CSR Addr 0x54155, Direction=N/A + + uint8_t Reserved2AB; // Byte offset 0x2ab, CSR Addr 0x54155, Direction=N/A + + uint8_t Reserved2AC; // Byte offset 0x2ac, CSR Addr 0x54156, Direction=N/A + + uint8_t Reserved2AD; // Byte offset 0x2ad, CSR Addr 0x54156, Direction=N/A + + uint8_t Reserved2AE; // Byte offset 0x2ae, CSR Addr 0x54157, Direction=N/A + + uint8_t Reserved2AF; // Byte offset 0x2af, CSR Addr 0x54157, Direction=N/A + + uint8_t Reserved2B0; // Byte offset 0x2b0, CSR Addr 0x54158, Direction=N/A + + uint8_t Reserved2B1; // Byte offset 0x2b1, CSR Addr 0x54158, Direction=N/A + + uint8_t Reserved2B2; // Byte offset 0x2b2, CSR Addr 0x54159, Direction=N/A + + uint8_t Reserved2B3; // Byte offset 0x2b3, CSR Addr 0x54159, Direction=N/A + + uint8_t Reserved2B4; // Byte offset 0x2b4, CSR Addr 0x5415a, Direction=N/A + + uint8_t Reserved2B5; // Byte offset 0x2b5, CSR Addr 0x5415a, Direction=N/A + + uint8_t Reserved2B6; // Byte offset 0x2b6, CSR Addr 0x5415b, Direction=N/A + + uint8_t Reserved2B7; // Byte offset 0x2b7, CSR Addr 0x5415b, Direction=N/A + + uint8_t Reserved2B8; // Byte offset 0x2b8, CSR Addr 0x5415c, Direction=N/A + + uint8_t Reserved2B9; // Byte offset 0x2b9, CSR Addr 0x5415c, Direction=N/A + + uint8_t Reserved2BA; // Byte offset 0x2ba, CSR Addr 0x5415d, Direction=N/A + + uint8_t Reserved2BB; // Byte offset 0x2bb, CSR Addr 0x5415d, Direction=N/A + + uint8_t Reserved2BC; // Byte offset 0x2bc, CSR Addr 0x5415e, Direction=N/A + + uint8_t Reserved2BD; // Byte offset 0x2bd, CSR Addr 0x5415e, Direction=N/A + + uint8_t Reserved2BE; // Byte offset 0x2be, CSR Addr 0x5415f, Direction=N/A + + uint8_t Reserved2BF; // Byte offset 0x2bf, CSR Addr 0x5415f, Direction=N/A + + uint8_t Reserved2C0; // Byte offset 0x2c0, CSR Addr 0x54160, Direction=N/A + + uint8_t Reserved2C1; // Byte offset 0x2c1, CSR Addr 0x54160, Direction=N/A + + uint8_t Reserved2C2; // Byte offset 0x2c2, CSR Addr 0x54161, Direction=N/A + + uint8_t Reserved2C3; // Byte offset 0x2c3, CSR Addr 0x54161, Direction=N/A + + uint8_t Reserved2C4; // Byte offset 0x2c4, CSR Addr 0x54162, Direction=N/A + + uint8_t Reserved2C5; // Byte offset 0x2c5, CSR Addr 0x54162, Direction=N/A + + uint8_t Reserved2C6; // Byte offset 0x2c6, CSR Addr 0x54163, Direction=N/A + + uint8_t Reserved2C7; // Byte offset 0x2c7, CSR Addr 0x54163, Direction=N/A + + uint8_t Reserved2C8; // Byte offset 0x2c8, CSR Addr 0x54164, Direction=N/A + + uint8_t Reserved2C9; // Byte offset 0x2c9, CSR Addr 0x54164, Direction=N/A + + uint8_t Reserved2CA; // Byte offset 0x2ca, CSR Addr 0x54165, Direction=N/A + + uint8_t Reserved2CB; // Byte offset 0x2cb, CSR Addr 0x54165, Direction=N/A + + uint8_t Reserved2CC; // Byte offset 0x2cc, CSR Addr 0x54166, Direction=N/A + + uint8_t Reserved2CD; // Byte offset 0x2cd, CSR Addr 0x54166, Direction=N/A + + uint8_t Reserved2CE; // Byte offset 0x2ce, CSR Addr 0x54167, Direction=N/A + + uint8_t Reserved2CF; // Byte offset 0x2cf, CSR Addr 0x54167, Direction=N/A + + uint8_t Reserved2D0; // Byte offset 0x2d0, CSR Addr 0x54168, Direction=N/A + + uint8_t Reserved2D1; // Byte offset 0x2d1, CSR Addr 0x54168, Direction=N/A + + uint8_t Reserved2D2; // Byte offset 0x2d2, CSR Addr 0x54169, Direction=N/A + + uint8_t Reserved2D3; // Byte offset 0x2d3, CSR Addr 0x54169, Direction=N/A + + uint8_t Reserved2D4; // Byte offset 0x2d4, CSR Addr 0x5416a, Direction=N/A + + uint8_t Reserved2D5; // Byte offset 0x2d5, CSR Addr 0x5416a, Direction=N/A + + uint8_t Reserved2D6; // Byte offset 0x2d6, CSR Addr 0x5416b, Direction=N/A + + uint8_t Reserved2D7; // Byte offset 0x2d7, CSR Addr 0x5416b, Direction=N/A + + uint8_t Reserved2D8; // Byte offset 0x2d8, CSR Addr 0x5416c, Direction=N/A + + uint8_t Reserved2D9; // Byte offset 0x2d9, CSR Addr 0x5416c, Direction=N/A + + uint8_t Reserved2DA; // Byte offset 0x2da, CSR Addr 0x5416d, Direction=N/A + + uint8_t Reserved2DB; // Byte offset 0x2db, CSR Addr 0x5416d, Direction=N/A + + uint8_t Reserved2DC; // Byte offset 0x2dc, CSR Addr 0x5416e, Direction=N/A + + uint8_t Reserved2DD; // Byte offset 0x2dd, CSR Addr 0x5416e, Direction=N/A + + uint8_t Reserved2DE; // Byte offset 0x2de, CSR Addr 0x5416f, Direction=N/A + + uint8_t Reserved2DF; // Byte offset 0x2df, CSR Addr 0x5416f, Direction=N/A + + uint8_t Reserved2E0; // Byte offset 0x2e0, CSR Addr 0x54170, Direction=N/A + + uint8_t Reserved2E1; // Byte offset 0x2e1, CSR Addr 0x54170, Direction=N/A + + uint8_t Reserved2E2; // Byte offset 0x2e2, CSR Addr 0x54171, Direction=N/A + + uint8_t Reserved2E3; // Byte offset 0x2e3, CSR Addr 0x54171, Direction=N/A + + uint8_t Reserved2E4; // Byte offset 0x2e4, CSR Addr 0x54172, Direction=N/A + + uint8_t Reserved2E5; // Byte offset 0x2e5, CSR Addr 0x54172, Direction=N/A + + uint8_t Reserved2E6; // Byte offset 0x2e6, CSR Addr 0x54173, Direction=N/A + + uint8_t Reserved2E7; // Byte offset 0x2e7, CSR Addr 0x54173, Direction=N/A + + uint8_t Reserved2E8; // Byte offset 0x2e8, CSR Addr 0x54174, Direction=N/A + + uint8_t Reserved2E9; // Byte offset 0x2e9, CSR Addr 0x54174, Direction=N/A + + uint8_t Reserved2EA; // Byte offset 0x2ea, CSR Addr 0x54175, Direction=N/A + + uint8_t Reserved2EB; // Byte offset 0x2eb, CSR Addr 0x54175, Direction=N/A + + uint8_t Reserved2EC; // Byte offset 0x2ec, CSR Addr 0x54176, Direction=N/A + + uint8_t Reserved2ED; // Byte offset 0x2ed, CSR Addr 0x54176, Direction=N/A + + uint8_t Reserved2EE; // Byte offset 0x2ee, CSR Addr 0x54177, Direction=N/A + + uint8_t Reserved2EF; // Byte offset 0x2ef, CSR Addr 0x54177, Direction=N/A + + uint8_t Reserved2F0; // Byte offset 0x2f0, CSR Addr 0x54178, Direction=N/A + + uint8_t Reserved2F1; // Byte offset 0x2f1, CSR Addr 0x54178, Direction=N/A + + uint8_t Reserved2F2; // Byte offset 0x2f2, CSR Addr 0x54179, Direction=N/A + + uint8_t Reserved2F3; // Byte offset 0x2f3, CSR Addr 0x54179, Direction=N/A + + uint8_t Reserved2F4; // Byte offset 0x2f4, CSR Addr 0x5417a, Direction=N/A + + uint8_t Reserved2F5; // Byte offset 0x2f5, CSR Addr 0x5417a, Direction=N/A + + uint8_t Reserved2F6; // Byte offset 0x2f6, CSR Addr 0x5417b, Direction=N/A + + uint8_t Reserved2F7; // Byte offset 0x2f7, CSR Addr 0x5417b, Direction=N/A + + uint8_t Reserved2F8; // Byte offset 0x2f8, CSR Addr 0x5417c, Direction=N/A + + uint8_t Reserved2F9; // Byte offset 0x2f9, CSR Addr 0x5417c, Direction=N/A + + uint8_t Reserved2FA; // Byte offset 0x2fa, CSR Addr 0x5417d, Direction=N/A + + uint8_t Reserved2FB; // Byte offset 0x2fb, CSR Addr 0x5417d, Direction=N/A + + uint8_t Reserved2FC; // Byte offset 0x2fc, CSR Addr 0x5417e, Direction=N/A + + uint8_t Reserved2FD; // Byte offset 0x2fd, CSR Addr 0x5417e, Direction=N/A + + uint8_t Reserved2FE; // Byte offset 0x2fe, CSR Addr 0x5417f, Direction=N/A + + uint8_t Reserved2FF; // Byte offset 0x2ff, CSR Addr 0x5417f, Direction=N/A + + uint8_t Reserved300; // Byte offset 0x300, CSR Addr 0x54180, Direction=N/A + + uint8_t Reserved301; // Byte offset 0x301, CSR Addr 0x54180, Direction=N/A + + uint8_t Reserved302; // Byte offset 0x302, CSR Addr 0x54181, Direction=N/A + + uint8_t Reserved303; // Byte offset 0x303, CSR Addr 0x54181, Direction=N/A + + uint8_t Reserved304; // Byte offset 0x304, CSR Addr 0x54182, Direction=N/A + + uint8_t Reserved305; // Byte offset 0x305, CSR Addr 0x54182, Direction=N/A + + uint8_t Reserved306; // Byte offset 0x306, CSR Addr 0x54183, Direction=N/A + + uint8_t Reserved307; // Byte offset 0x307, CSR Addr 0x54183, Direction=N/A + + uint8_t Reserved308; // Byte offset 0x308, CSR Addr 0x54184, Direction=N/A + + uint8_t Reserved309; // Byte offset 0x309, CSR Addr 0x54184, Direction=N/A + + uint8_t Reserved30A; // Byte offset 0x30a, CSR Addr 0x54185, Direction=N/A + + uint8_t Reserved30B; // Byte offset 0x30b, CSR Addr 0x54185, Direction=N/A + + uint8_t Reserved30C; // Byte offset 0x30c, CSR Addr 0x54186, Direction=N/A + + uint8_t Reserved30D; // Byte offset 0x30d, CSR Addr 0x54186, Direction=N/A + + uint8_t Reserved30E; // Byte offset 0x30e, CSR Addr 0x54187, Direction=N/A + + uint8_t Reserved30F; // Byte offset 0x30f, CSR Addr 0x54187, Direction=N/A + + uint8_t Reserved310; // Byte offset 0x310, CSR Addr 0x54188, Direction=N/A + + uint8_t Reserved311; // Byte offset 0x311, CSR Addr 0x54188, Direction=N/A + + uint8_t Reserved312; // Byte offset 0x312, CSR Addr 0x54189, Direction=N/A + + uint8_t Reserved313; // Byte offset 0x313, CSR Addr 0x54189, Direction=N/A + + uint8_t Reserved314; // Byte offset 0x314, CSR Addr 0x5418a, Direction=N/A + + uint8_t Reserved315; // Byte offset 0x315, CSR Addr 0x5418a, Direction=N/A + + uint8_t Reserved316; // Byte offset 0x316, CSR Addr 0x5418b, Direction=N/A + + uint8_t Reserved317; // Byte offset 0x317, CSR Addr 0x5418b, Direction=N/A + + uint8_t Reserved318; // Byte offset 0x318, CSR Addr 0x5418c, Direction=N/A + + uint8_t Reserved319; // Byte offset 0x319, CSR Addr 0x5418c, Direction=N/A + + uint8_t Reserved31A; // Byte offset 0x31a, CSR Addr 0x5418d, Direction=N/A + + uint8_t Reserved31B; // Byte offset 0x31b, CSR Addr 0x5418d, Direction=N/A + + uint8_t Reserved31C; // Byte offset 0x31c, CSR Addr 0x5418e, Direction=N/A + + uint8_t Reserved31D; // Byte offset 0x31d, CSR Addr 0x5418e, Direction=N/A + + uint8_t Reserved31E; // Byte offset 0x31e, CSR Addr 0x5418f, Direction=N/A + + uint8_t Reserved31F; // Byte offset 0x31f, CSR Addr 0x5418f, Direction=N/A + + uint8_t Reserved320; // Byte offset 0x320, CSR Addr 0x54190, Direction=N/A + + uint8_t Reserved321; // Byte offset 0x321, CSR Addr 0x54190, Direction=N/A + + uint8_t Reserved322; // Byte offset 0x322, CSR Addr 0x54191, Direction=N/A + + uint8_t Reserved323; // Byte offset 0x323, CSR Addr 0x54191, Direction=N/A + + uint8_t Reserved324; // Byte offset 0x324, CSR Addr 0x54192, Direction=N/A + + uint8_t Reserved325; // Byte offset 0x325, CSR Addr 0x54192, Direction=N/A + + uint8_t Reserved326; // Byte offset 0x326, CSR Addr 0x54193, Direction=N/A + + uint8_t Reserved327; // Byte offset 0x327, CSR Addr 0x54193, Direction=N/A + + uint8_t Reserved328; // Byte offset 0x328, CSR Addr 0x54194, Direction=N/A + + uint8_t Reserved329; // Byte offset 0x329, CSR Addr 0x54194, Direction=N/A + + uint8_t Reserved32A; // Byte offset 0x32a, CSR Addr 0x54195, Direction=N/A + + uint8_t Reserved32B; // Byte offset 0x32b, CSR Addr 0x54195, Direction=N/A + + uint8_t Reserved32C; // Byte offset 0x32c, CSR Addr 0x54196, Direction=N/A + + uint8_t Reserved32D; // Byte offset 0x32d, CSR Addr 0x54196, Direction=N/A + + uint8_t Reserved32E; // Byte offset 0x32e, CSR Addr 0x54197, Direction=N/A + + uint8_t Reserved32F; // Byte offset 0x32f, CSR Addr 0x54197, Direction=N/A + + uint8_t Reserved330; // Byte offset 0x330, CSR Addr 0x54198, Direction=N/A + + uint8_t Reserved331; // Byte offset 0x331, CSR Addr 0x54198, Direction=N/A + + uint8_t Reserved332; // Byte offset 0x332, CSR Addr 0x54199, Direction=N/A + + uint8_t Reserved333; // Byte offset 0x333, CSR Addr 0x54199, Direction=N/A + + uint8_t Reserved334; // Byte offset 0x334, CSR Addr 0x5419a, Direction=N/A + + uint8_t Reserved335; // Byte offset 0x335, CSR Addr 0x5419a, Direction=N/A + + uint8_t Reserved336; // Byte offset 0x336, CSR Addr 0x5419b, Direction=N/A + + uint8_t Reserved337; // Byte offset 0x337, CSR Addr 0x5419b, Direction=N/A + + uint8_t Reserved338; // Byte offset 0x338, CSR Addr 0x5419c, Direction=N/A + + uint8_t Reserved339; // Byte offset 0x339, CSR Addr 0x5419c, Direction=N/A + + uint8_t Reserved33A; // Byte offset 0x33a, CSR Addr 0x5419d, Direction=N/A + + uint8_t Reserved33B; // Byte offset 0x33b, CSR Addr 0x5419d, Direction=N/A + + uint8_t Reserved33C; // Byte offset 0x33c, CSR Addr 0x5419e, Direction=N/A + + uint8_t Reserved33D; // Byte offset 0x33d, CSR Addr 0x5419e, Direction=N/A + + uint8_t Reserved33E; // Byte offset 0x33e, CSR Addr 0x5419f, Direction=N/A + + uint8_t Reserved33F; // Byte offset 0x33f, CSR Addr 0x5419f, Direction=N/A + + uint8_t Reserved340; // Byte offset 0x340, CSR Addr 0x541a0, Direction=N/A + + uint8_t Reserved341; // Byte offset 0x341, CSR Addr 0x541a0, Direction=N/A + + uint8_t Reserved342; // Byte offset 0x342, CSR Addr 0x541a1, Direction=N/A + + uint8_t Reserved343; // Byte offset 0x343, CSR Addr 0x541a1, Direction=N/A + + uint8_t Reserved344; // Byte offset 0x344, CSR Addr 0x541a2, Direction=N/A + + uint8_t Reserved345; // Byte offset 0x345, CSR Addr 0x541a2, Direction=N/A + + uint8_t Reserved346; // Byte offset 0x346, CSR Addr 0x541a3, Direction=N/A + + uint8_t Reserved347; // Byte offset 0x347, CSR Addr 0x541a3, Direction=N/A + + uint8_t Reserved348; // Byte offset 0x348, CSR Addr 0x541a4, Direction=N/A + + uint8_t Reserved349; // Byte offset 0x349, CSR Addr 0x541a4, Direction=N/A + + uint8_t Reserved34A; // Byte offset 0x34a, CSR Addr 0x541a5, Direction=N/A + + uint8_t Reserved34B; // Byte offset 0x34b, CSR Addr 0x541a5, Direction=N/A + + uint8_t Reserved34C; // Byte offset 0x34c, CSR Addr 0x541a6, Direction=N/A + + uint8_t Reserved34D; // Byte offset 0x34d, CSR Addr 0x541a6, Direction=N/A + + uint8_t Reserved34E; // Byte offset 0x34e, CSR Addr 0x541a7, Direction=N/A + + uint8_t Reserved34F; // Byte offset 0x34f, CSR Addr 0x541a7, Direction=N/A + + uint8_t Reserved350; // Byte offset 0x350, CSR Addr 0x541a8, Direction=N/A + + uint8_t Reserved351; // Byte offset 0x351, CSR Addr 0x541a8, Direction=N/A + + uint8_t Reserved352; // Byte offset 0x352, CSR Addr 0x541a9, Direction=N/A + + uint8_t Reserved353; // Byte offset 0x353, CSR Addr 0x541a9, Direction=N/A + + uint8_t Reserved354; // Byte offset 0x354, CSR Addr 0x541aa, Direction=N/A + + uint8_t Reserved355; // Byte offset 0x355, CSR Addr 0x541aa, Direction=N/A + + uint8_t Reserved356; // Byte offset 0x356, CSR Addr 0x541ab, Direction=N/A + + uint8_t Reserved357; // Byte offset 0x357, CSR Addr 0x541ab, Direction=N/A + + uint8_t Reserved358; // Byte offset 0x358, CSR Addr 0x541ac, Direction=N/A + + uint8_t Reserved359; // Byte offset 0x359, CSR Addr 0x541ac, Direction=N/A + + uint8_t Reserved35A; // Byte offset 0x35a, CSR Addr 0x541ad, Direction=N/A + + uint8_t Reserved35B; // Byte offset 0x35b, CSR Addr 0x541ad, Direction=N/A + + uint8_t Reserved35C; // Byte offset 0x35c, CSR Addr 0x541ae, Direction=N/A + + uint8_t Reserved35D; // Byte offset 0x35d, CSR Addr 0x541ae, Direction=N/A + + uint8_t Reserved35E; // Byte offset 0x35e, CSR Addr 0x541af, Direction=N/A + + uint8_t Reserved35F; // Byte offset 0x35f, CSR Addr 0x541af, Direction=N/A + + uint8_t Reserved360; // Byte offset 0x360, CSR Addr 0x541b0, Direction=N/A + + uint8_t Reserved361; // Byte offset 0x361, CSR Addr 0x541b0, Direction=N/A + + uint8_t Reserved362; // Byte offset 0x362, CSR Addr 0x541b1, Direction=N/A + + uint8_t Reserved363; // Byte offset 0x363, CSR Addr 0x541b1, Direction=N/A + + uint8_t Reserved364; // Byte offset 0x364, CSR Addr 0x541b2, Direction=N/A + + uint8_t Reserved365; // Byte offset 0x365, CSR Addr 0x541b2, Direction=N/A + + uint8_t Reserved366; // Byte offset 0x366, CSR Addr 0x541b3, Direction=N/A + + uint8_t Reserved367; // Byte offset 0x367, CSR Addr 0x541b3, Direction=N/A + + uint8_t Reserved368; // Byte offset 0x368, CSR Addr 0x541b4, Direction=N/A + + uint8_t Reserved369; // Byte offset 0x369, CSR Addr 0x541b4, Direction=N/A + + uint8_t Reserved36A; // Byte offset 0x36a, CSR Addr 0x541b5, Direction=N/A + + uint8_t Reserved36B; // Byte offset 0x36b, CSR Addr 0x541b5, Direction=N/A + + uint8_t Reserved36C; // Byte offset 0x36c, CSR Addr 0x541b6, Direction=N/A + + uint8_t Reserved36D; // Byte offset 0x36d, CSR Addr 0x541b6, Direction=N/A + + uint8_t Reserved36E; // Byte offset 0x36e, CSR Addr 0x541b7, Direction=N/A + + uint8_t Reserved36F; // Byte offset 0x36f, CSR Addr 0x541b7, Direction=N/A + + uint8_t Reserved370; // Byte offset 0x370, CSR Addr 0x541b8, Direction=N/A + + uint8_t Reserved371; // Byte offset 0x371, CSR Addr 0x541b8, Direction=N/A + + uint8_t Reserved372; // Byte offset 0x372, CSR Addr 0x541b9, Direction=N/A + + uint8_t Reserved373; // Byte offset 0x373, CSR Addr 0x541b9, Direction=N/A + + uint8_t Reserved374; // Byte offset 0x374, CSR Addr 0x541ba, Direction=N/A + + uint8_t Reserved375; // Byte offset 0x375, CSR Addr 0x541ba, Direction=N/A + + uint8_t Reserved376; // Byte offset 0x376, CSR Addr 0x541bb, Direction=N/A + + uint8_t Reserved377; // Byte offset 0x377, CSR Addr 0x541bb, Direction=N/A + + uint8_t Reserved378; // Byte offset 0x378, CSR Addr 0x541bc, Direction=N/A + + uint8_t Reserved379; // Byte offset 0x379, CSR Addr 0x541bc, Direction=N/A + + uint8_t Reserved37A; // Byte offset 0x37a, CSR Addr 0x541bd, Direction=N/A + + uint8_t Reserved37B; // Byte offset 0x37b, CSR Addr 0x541bd, Direction=N/A + + uint8_t Reserved37C; // Byte offset 0x37c, CSR Addr 0x541be, Direction=N/A + + uint8_t Reserved37D; // Byte offset 0x37d, CSR Addr 0x541be, Direction=N/A + + uint8_t Reserved37E; // Byte offset 0x37e, CSR Addr 0x541bf, Direction=N/A + + uint8_t Reserved37F; // Byte offset 0x37f, CSR Addr 0x541bf, Direction=N/A + + uint8_t Reserved380; // Byte offset 0x380, CSR Addr 0x541c0, Direction=N/A + + uint8_t Reserved381; // Byte offset 0x381, CSR Addr 0x541c0, Direction=N/A + + uint8_t Reserved382; // Byte offset 0x382, CSR Addr 0x541c1, Direction=N/A + + uint8_t Reserved383; // Byte offset 0x383, CSR Addr 0x541c1, Direction=N/A + + uint8_t Reserved384; // Byte offset 0x384, CSR Addr 0x541c2, Direction=N/A + + uint8_t Reserved385; // Byte offset 0x385, CSR Addr 0x541c2, Direction=N/A + + uint8_t Reserved386; // Byte offset 0x386, CSR Addr 0x541c3, Direction=N/A + + uint8_t Reserved387; // Byte offset 0x387, CSR Addr 0x541c3, Direction=N/A + + uint8_t Reserved388; // Byte offset 0x388, CSR Addr 0x541c4, Direction=N/A + + uint8_t Reserved389; // Byte offset 0x389, CSR Addr 0x541c4, Direction=N/A + + uint8_t Reserved38A; // Byte offset 0x38a, CSR Addr 0x541c5, Direction=N/A + + uint8_t Reserved38B; // Byte offset 0x38b, CSR Addr 0x541c5, Direction=N/A + + uint8_t Reserved38C; // Byte offset 0x38c, CSR Addr 0x541c6, Direction=N/A + + uint8_t Reserved38D; // Byte offset 0x38d, CSR Addr 0x541c6, Direction=N/A + + uint8_t Reserved38E; // Byte offset 0x38e, CSR Addr 0x541c7, Direction=N/A + + uint8_t Reserved38F; // Byte offset 0x38f, CSR Addr 0x541c7, Direction=N/A + + uint8_t Reserved390; // Byte offset 0x390, CSR Addr 0x541c8, Direction=N/A + + uint8_t Reserved391; // Byte offset 0x391, CSR Addr 0x541c8, Direction=N/A + + uint8_t Reserved392; // Byte offset 0x392, CSR Addr 0x541c9, Direction=N/A + + uint8_t Reserved393; // Byte offset 0x393, CSR Addr 0x541c9, Direction=N/A + + uint8_t Reserved394; // Byte offset 0x394, CSR Addr 0x541ca, Direction=N/A + + uint8_t Reserved395; // Byte offset 0x395, CSR Addr 0x541ca, Direction=N/A + + uint8_t Reserved396; // Byte offset 0x396, CSR Addr 0x541cb, Direction=N/A + + uint8_t Reserved397; // Byte offset 0x397, CSR Addr 0x541cb, Direction=N/A + + uint8_t Reserved398; // Byte offset 0x398, CSR Addr 0x541cc, Direction=N/A + + uint8_t Reserved399; // Byte offset 0x399, CSR Addr 0x541cc, Direction=N/A + + uint8_t Reserved39A; // Byte offset 0x39a, CSR Addr 0x541cd, Direction=N/A + + uint8_t Reserved39B; // Byte offset 0x39b, CSR Addr 0x541cd, Direction=N/A + + uint8_t Reserved39C; // Byte offset 0x39c, CSR Addr 0x541ce, Direction=N/A + + uint8_t Reserved39D; // Byte offset 0x39d, CSR Addr 0x541ce, Direction=N/A + + uint8_t Reserved39E; // Byte offset 0x39e, CSR Addr 0x541cf, Direction=N/A + + uint8_t Reserved39F; // Byte offset 0x39f, CSR Addr 0x541cf, Direction=N/A + + uint8_t Reserved3A0; // Byte offset 0x3a0, CSR Addr 0x541d0, Direction=N/A + + uint8_t Reserved3A1; // Byte offset 0x3a1, CSR Addr 0x541d0, Direction=N/A + + uint8_t Reserved3A2; // Byte offset 0x3a2, CSR Addr 0x541d1, Direction=N/A + + uint8_t Reserved3A3; // Byte offset 0x3a3, CSR Addr 0x541d1, Direction=N/A + + uint8_t Reserved3A4; // Byte offset 0x3a4, CSR Addr 0x541d2, Direction=N/A + + uint8_t Reserved3A5; // Byte offset 0x3a5, CSR Addr 0x541d2, Direction=N/A + + uint8_t Reserved3A6; // Byte offset 0x3a6, CSR Addr 0x541d3, Direction=N/A + + uint8_t Reserved3A7; // Byte offset 0x3a7, CSR Addr 0x541d3, Direction=N/A + + uint8_t Reserved3A8; // Byte offset 0x3a8, CSR Addr 0x541d4, Direction=N/A + + uint8_t Reserved3A9; // Byte offset 0x3a9, CSR Addr 0x541d4, Direction=N/A + + uint8_t Reserved3AA; // Byte offset 0x3aa, CSR Addr 0x541d5, Direction=N/A + + uint8_t Reserved3AB; // Byte offset 0x3ab, CSR Addr 0x541d5, Direction=N/A + + uint8_t Reserved3AC; // Byte offset 0x3ac, CSR Addr 0x541d6, Direction=N/A + + uint8_t Reserved3AD; // Byte offset 0x3ad, CSR Addr 0x541d6, Direction=N/A + + uint8_t Reserved3AE; // Byte offset 0x3ae, CSR Addr 0x541d7, Direction=N/A + + uint8_t Reserved3AF; // Byte offset 0x3af, CSR Addr 0x541d7, Direction=N/A + + uint8_t Reserved3B0; // Byte offset 0x3b0, CSR Addr 0x541d8, Direction=N/A + + uint8_t Reserved3B1; // Byte offset 0x3b1, CSR Addr 0x541d8, Direction=N/A + + uint8_t Reserved3B2; // Byte offset 0x3b2, CSR Addr 0x541d9, Direction=N/A + + uint8_t Reserved3B3; // Byte offset 0x3b3, CSR Addr 0x541d9, Direction=N/A + + uint8_t Reserved3B4; // Byte offset 0x3b4, CSR Addr 0x541da, Direction=N/A + + uint8_t Reserved3B5; // Byte offset 0x3b5, CSR Addr 0x541da, Direction=N/A + + uint8_t Reserved3B6; // Byte offset 0x3b6, CSR Addr 0x541db, Direction=N/A + + uint8_t Reserved3B7; // Byte offset 0x3b7, CSR Addr 0x541db, Direction=N/A + + uint8_t Reserved3B8; // Byte offset 0x3b8, CSR Addr 0x541dc, Direction=N/A + + uint8_t Reserved3B9; // Byte offset 0x3b9, CSR Addr 0x541dc, Direction=N/A + + uint8_t Reserved3BA; // Byte offset 0x3ba, CSR Addr 0x541dd, Direction=N/A + + uint8_t Reserved3BB; // Byte offset 0x3bb, CSR Addr 0x541dd, Direction=N/A + + uint8_t Reserved3BC; // Byte offset 0x3bc, CSR Addr 0x541de, Direction=N/A + + uint8_t Reserved3BD; // Byte offset 0x3bd, CSR Addr 0x541de, Direction=N/A + + uint8_t Reserved3BE; // Byte offset 0x3be, CSR Addr 0x541df, Direction=N/A + + uint8_t Reserved3BF; // Byte offset 0x3bf, CSR Addr 0x541df, Direction=N/A + + uint8_t Reserved3C0; // Byte offset 0x3c0, CSR Addr 0x541e0, Direction=N/A + + uint8_t Reserved3C1; // Byte offset 0x3c1, CSR Addr 0x541e0, Direction=N/A + + uint8_t Reserved3C2; // Byte offset 0x3c2, CSR Addr 0x541e1, Direction=N/A + + uint8_t Reserved3C3; // Byte offset 0x3c3, CSR Addr 0x541e1, Direction=N/A + + uint8_t Reserved3C4; // Byte offset 0x3c4, CSR Addr 0x541e2, Direction=N/A + + uint8_t Reserved3C5; // Byte offset 0x3c5, CSR Addr 0x541e2, Direction=N/A + + uint8_t Reserved3C6; // Byte offset 0x3c6, CSR Addr 0x541e3, Direction=N/A + + uint8_t Reserved3C7; // Byte offset 0x3c7, CSR Addr 0x541e3, Direction=N/A + + uint8_t Reserved3C8; // Byte offset 0x3c8, CSR Addr 0x541e4, Direction=N/A + + uint8_t Reserved3C9; // Byte offset 0x3c9, CSR Addr 0x541e4, Direction=N/A + + uint8_t Reserved3CA; // Byte offset 0x3ca, CSR Addr 0x541e5, Direction=N/A + + uint8_t Reserved3CB; // Byte offset 0x3cb, CSR Addr 0x541e5, Direction=N/A + + uint8_t Reserved3CC; // Byte offset 0x3cc, CSR Addr 0x541e6, Direction=N/A + + uint8_t Reserved3CD; // Byte offset 0x3cd, CSR Addr 0x541e6, Direction=N/A + + uint8_t Reserved3CE; // Byte offset 0x3ce, CSR Addr 0x541e7, Direction=N/A + + uint8_t Reserved3CF; // Byte offset 0x3cf, CSR Addr 0x541e7, Direction=N/A + + uint8_t Reserved3D0; // Byte offset 0x3d0, CSR Addr 0x541e8, Direction=N/A + + uint8_t Reserved3D1; // Byte offset 0x3d1, CSR Addr 0x541e8, Direction=N/A + + uint8_t Reserved3D2; // Byte offset 0x3d2, CSR Addr 0x541e9, Direction=N/A + + uint8_t Reserved3D3; // Byte offset 0x3d3, CSR Addr 0x541e9, Direction=N/A + + uint8_t Reserved3D4; // Byte offset 0x3d4, CSR Addr 0x541ea, Direction=N/A + + uint8_t Reserved3D5; // Byte offset 0x3d5, CSR Addr 0x541ea, Direction=N/A + + uint8_t Reserved3D6; // Byte offset 0x3d6, CSR Addr 0x541eb, Direction=N/A + + uint8_t Reserved3D7; // Byte offset 0x3d7, CSR Addr 0x541eb, Direction=N/A + + uint8_t Reserved3D8; // Byte offset 0x3d8, CSR Addr 0x541ec, Direction=N/A + + uint8_t Reserved3D9; // Byte offset 0x3d9, CSR Addr 0x541ec, Direction=N/A + + uint8_t Reserved3DA; // Byte offset 0x3da, CSR Addr 0x541ed, Direction=N/A + + uint8_t Reserved3DB; // Byte offset 0x3db, CSR Addr 0x541ed, Direction=N/A + + uint8_t Reserved3DC; // Byte offset 0x3dc, CSR Addr 0x541ee, Direction=N/A + + uint8_t Reserved3DD; // Byte offset 0x3dd, CSR Addr 0x541ee, Direction=N/A + + uint8_t Reserved3DE; // Byte offset 0x3de, CSR Addr 0x541ef, Direction=N/A + + uint8_t Reserved3DF; // Byte offset 0x3df, CSR Addr 0x541ef, Direction=N/A + + uint8_t Reserved3E0; // Byte offset 0x3e0, CSR Addr 0x541f0, Direction=N/A + + uint8_t Reserved3E1; // Byte offset 0x3e1, CSR Addr 0x541f0, Direction=N/A + + uint8_t Reserved3E2; // Byte offset 0x3e2, CSR Addr 0x541f1, Direction=N/A + + uint8_t Reserved3E3; // Byte offset 0x3e3, CSR Addr 0x541f1, Direction=N/A + + uint8_t Reserved3E4; // Byte offset 0x3e4, CSR Addr 0x541f2, Direction=N/A + + uint8_t Reserved3E5; // Byte offset 0x3e5, CSR Addr 0x541f2, Direction=N/A + + uint8_t Reserved3E6; // Byte offset 0x3e6, CSR Addr 0x541f3, Direction=N/A + + uint8_t Reserved3E7; // Byte offset 0x3e7, CSR Addr 0x541f3, Direction=N/A + + uint8_t Reserved3E8; // Byte offset 0x3e8, CSR Addr 0x541f4, Direction=N/A + + uint8_t Reserved3E9; // Byte offset 0x3e9, CSR Addr 0x541f4, Direction=N/A + + uint8_t Reserved3EA; // Byte offset 0x3ea, CSR Addr 0x541f5, Direction=N/A + + uint8_t Reserved3EB; // Byte offset 0x3eb, CSR Addr 0x541f5, Direction=N/A + + uint8_t Reserved3EC; // Byte offset 0x3ec, CSR Addr 0x541f6, Direction=N/A + + uint8_t Reserved3ED; // Byte offset 0x3ed, CSR Addr 0x541f6, Direction=N/A + + uint8_t Reserved3EE; // Byte offset 0x3ee, CSR Addr 0x541f7, Direction=N/A + + uint8_t Reserved3EF; // Byte offset 0x3ef, CSR Addr 0x541f7, Direction=N/A + + uint8_t Reserved3F0; // Byte offset 0x3f0, CSR Addr 0x541f8, Direction=N/A + + uint8_t Reserved3F1; // Byte offset 0x3f1, CSR Addr 0x541f8, Direction=N/A + + uint8_t Reserved3F2; // Byte offset 0x3f2, CSR Addr 0x541f9, Direction=N/A + + uint8_t Reserved3F3; // Byte offset 0x3f3, CSR Addr 0x541f9, Direction=N/A + + uint8_t Reserved3F4; // Byte offset 0x3f4, CSR Addr 0x541fa, Direction=N/A + + uint8_t Reserved3F5; // Byte offset 0x3f5, CSR Addr 0x541fa, Direction=N/A + + uint16_t ALT_CAS_L; // Byte offset 0x3f6, CSR Addr 0x541fb, Direction=in + // This field must be populated if RdDBI is enabled (applicable when MR5[A12] == 1). + // RdDBI is dynamically disabled in certain training steps, + // and so the [RdDBI disabled] CAS Latency must be provided in this field. + // The required encoding is as follows: + // ALT_CAS_L[0] == 0: use value in MR0 + // ALT_CAS_L[0] == 1: use value in ALT_CAS_L, i.e., MR0{A[12],A[6],A[5],A[4],A[2]} = ALT_CAS_L[12,6,5,4,2] + // Other bits are ignored + uint8_t ALT_WCAS_L; // Byte offset 0x3f8, CSR Addr 0x541fc, Direction=In + // This field must be populated if 2tCK write preambles are enabled (applicable when MR4[A12] == 1). + // 2tCK write prambles are dynamically disabled in certain training steps, + // and so the [1tCK write preamble] WCAS Latency must be provided in this field. + // The required encoding is as follows: + // ALT_WCAS_L[0] == 0: use value in MR2 + // ALT_WCAS_L[0] == 1: use value in ALT_WCAS_L, i.e., MR2{A[5],A[4],A[3]} = ALT_WCAS_L[5,4,3] + // Other bits are ignored + uint8_t D4Misc; // Byte offset 0x3f9, CSR Addr 0x541fc, Direction=In + // Contains various options for training DDR4 Devices. + // + // Bit fields: + // + // D4Misc[7:1] RFU, must be zero + // + // D4Misc[0] = protect memory reset + // 0x1 = dfi_reset_n cannot control BP_MEMRESERT_L to devices after training. + // 0x0 = dfi_resert_n can control BP_MEMRESERT_L to devices after training +} __attribute__ ((packed)) PMU_SMB_DDR4U_1D_t;
diff --git a/arch/arm/include/asm/arch-a1/mnPmuSramMsgBlock_ddr4_2d.h b/arch/arm/include/asm/arch-a1/mnPmuSramMsgBlock_ddr4_2d.h new file mode 100644 index 0000000..35b1e23 --- /dev/null +++ b/arch/arm/include/asm/arch-a1/mnPmuSramMsgBlock_ddr4_2d.h
@@ -0,0 +1,2282 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +/** \brief DDR4U_2D training firmware message block structure + * + * Please refer to the Training Firmware App Note for futher information about + * the usage for Message Block. + */ +typedef struct _PMU_SMB_DDR4U_2D_t { + uint8_t Reserved00; // Byte offset 0x00, CSR Addr 0x54000, Direction=In + // Reserved00[0:4] RFU, must be zero + // + // Reserved00[5] = Train vrefDAC0 During Read Deskew + // 0x1 = Read Deskew will begin by enabling and roughly training the phy’s per-lane reference voltages. Training the vrefDACs CSRs will increase the maximum 1D training time by around half a millisecond, but will improve 1D training accuracy on systems with significant voltage-offsets between lane read eyes. + // 0X0 = Read Deskew will assume the messageblock’s phyVref setting will work for all lanes. + // + // Reserved00[6] = Enable High Effort WrDQ1D + // 0x1 = WrDQ1D will conditionally retry training at several extra RxClkDly Timings. This will increase the maximum 1D training time by up to 4 extra iterations of WrDQ1D. This is only required in systems that suffer from very large, asymmetric eye-collapse when receiving PRBS patterns. + // 0x0 = WrDQ1D assume rxClkDly values found by SI Friendly RdDqs1D will work for receiving PRBS patterns + // + // Reserved00[7] = Optimize for the special hard macros in TSMC28. + // 0x1 = set if the phy being trained was manufactured in any TSMC28 process node. + // 0x0 = otherwise, when not training a TSMC28 phy, leave this field as 0. + uint8_t MsgMisc; // Byte offset 0x01, CSR Addr 0x54000, Direction=In + // Contains various global options for training. + // + // Bit fields: + // + // MsgMisc[0] = MTESTEnable + // 0x1 = Pulse primary digital test output bump at the end of each major training stage. This enables observation of training stage completion by observing the digital test output. + // 0x0 = Do not pulse primary digital test output bump + // + // MsgMisc[1] = SimulationOnlyReset + // 0x1 = Verilog only simulation option to shorten duration of DRAM reset pulse length to 1ns. + // Must never be set to 1 in silicon. + // 0x0 = Use reset pulse length specifed by JEDEC standard + // + // MsgMisc[2] = SimulationOnlyTraining + // 0x1 = Verilog only simulation option to shorten the duration of the training steps by performing fewer iterations. + // Must never be set to 1 in silicon. + // 0x0 = Use standard training duration. + // + // MsgMisc[3] = UseDdr4PerDeviceVrefDq (DDR4 UDIMM and RDIMM only, otherwise RFU, must be zero) + // 0x1 = Program user characterized Vref DQ values per DDR4 DRAM device. The message block VrefDqR*Nib* fields must be populated with the desired per device Vref DQs when using this option. Note: this option is not applicable in 2D training because these values are explicitly trained in 2D. + // 0x0 = Program Vref DQ for all DDR4 devices with the single value provided in MR6 message block field + // + // MsgMisc[4] = Suppress streaming messages, including assertions, regardless of HdtCtrl setting. + // Stage Completion messages, as well as training completion and error messages are + // Still sent depending on HdtCtrl setting. + // + // MsgMisc[5] = PerByteMaxRdLat + // 0x1 = Each DBYTE will return dfi_rddata_valid at the lowest possible latency. This may result in unaligned data between bytes to be returned to the DFI. + // 0x0 = Every DBYTE will return dfi_rddata_valid simultaneously. This will ensure that data bytes will return aligned accesses to the DFI. + // + // MsgMisc[6] = PartialRank (DDR3 UDIMM and DDR4 UDIMM only, otherwise RFU, must be zero) + // 0x1 = Support rank populated with a subset of byte, but where even-odd pair of rank support all the byte + // 0x0 = All rank populated with all the byte (tyical configuration) + // + // MsgMisc[7] RFU, must be zero + // + // Notes: + // + // - SimulationOnlyReset and SimulationOnlyTraining can be used to speed up simulation run times, and must never be used in real silicon. Some VIPs may have checks on DRAM reset parameters that may need to be disabled when using SimulationOnlyReset. + uint16_t PmuRevision; // Byte offset 0x02, CSR Addr 0x54001, Direction=Out + // PMU firmware revision ID + // After training is run, this address will contain the revision ID of the firmware. + // Please reference this revision ID when filing support cases with Synopsys. + uint8_t Pstate; // Byte offset 0x04, CSR Addr 0x54002, Direction=In + // Must be set to the target Pstate to be trained + // 0x0 = Pstate 0 + // 0x1 = Pstate 1 + // 0x2 = Pstate 2 + // 0x3 = Pstate 3 + // All other encodings are reserved + uint8_t PllBypassEn; // Byte offset 0x05, CSR Addr 0x54002, Direction=In + // Set according to whether target Pstate uses PHY PLL bypass + // 0x0 = PHY PLL is enabled for target Pstate + // 0x1 = PHY PLL is bypassed for target Pstate + uint16_t DRAMFreq; // Byte offset 0x06, CSR Addr 0x54003, Direction=In + // DDR data rate for the target Pstate in units of MT/s. + // For example enter 0x0640 for DDR1600. + uint8_t DfiFreqRatio; // Byte offset 0x08, CSR Addr 0x54004, Direction=In + // Frequency ratio betwen DfiCtlClk and SDRAM memclk. + // 0x1 = 1:1 + // 0x2 = 1:2 + // 0x4 = 1:4 + uint8_t BPZNResVal ; // Byte offset 0x09, CSR Addr 0x54004, Direction=In + // Must be programmed to match the precision resistor connected to Phy BP_ZN + // 0x00 = Do not program. Use current CSR value. + // 0xf0 = 240 Ohm (recommended value) + // 0x78 = 120 Ohm + // 0x28 = 40 Ohm + // All other values are reserved. + // + uint8_t PhyOdtImpedance; // Byte offset 0x0a, CSR Addr 0x54005, Direction=In + // Must be programmed to the termination impedance in ohms used by PHY during reads. + // + // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start) + // + // See PHY databook for legal termination impedance values. + // + // For digital simulation, any legal value can be used. For silicon, the users must determine the correct value through SI simulation or other methods. + uint8_t PhyDrvImpedance; // Byte offset 0x0b, CSR Addr 0x54005, Direction=In + // Must be programmed to the driver impedance in ohms used by PHY during writes for all DBYTE drivers (DQ/DM/DBI/DQS). + // + // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start) + // + // See PHY databook for legal R_on driver impedance values. + // + // For digital simulation, any value can be used that is not Hi-Z. For silicon, the users must determine the correct value through SI simulation or other methods. + uint8_t PhyVref; // Byte offset 0x0c, CSR Addr 0x54006, Direction=In + // Must be programmed with the Vref level to be used by the PHY during reads + // + // The units of this field are a percentage of VDDQ according to the following equation: + // + // Receiver Vref = VDDQ*PhyVref[6:0]/128 + // + // For example to set Vref at 0.75*VDDQ, set this field to 0x60. + // + // For digital simulation, any legal value can be used. For silicon, the users must calculate the analytical Vref by using the impedances, terminations, and series resistance present in the system. + uint8_t DramType; // Byte offset 0x0d, CSR Addr 0x54006, Direction=In + // Module Type: + // 0x01 = Reserved + // 0x02 = DDR4 unbuffered + // 0x03 = Reserved + // 0x04 = Reserved + // 0x05 = Reserved + // + uint8_t DisabledDbyte; // Byte offset 0x0e, CSR Addr 0x54007, Direction=In + // Bitmap to indicate which Dbyte are not connected (for DByte 0 to 7): + // Set DisabledDbyte[i] to 1 only to specify that DByte i not need to be trained (DByte 8 can be disabled via EnabledDQs setting) + uint8_t EnabledDQs; // Byte offset 0x0f, CSR Addr 0x54007, Direction=In + // Total number of DQ bits enabled in PHY + uint8_t CsPresent; // Byte offset 0x10, CSR Addr 0x54008, Direction=In + // Indicates presence of DRAM at each chip select for PHY. Each bit corresponds to a logical CS. + // + // If the bit is set to 1, the CS is connected to DRAM. + // If the bit is set to 0, the CS is not connected to DRAM. + // + // CsPresent[0] = CS0 is populated with DRAM + // CsPresent[1] = CS1 is populated with DRAM + // CsPresent[2] = CS2 is populated with DRAM + // CsPresent[3] = CS3 is populated with DRAM + // CsPresent[7:4] = Reserved (must be programmed to 0) + // + // + uint8_t CsPresentD0; // Byte offset 0x11, CSR Addr 0x54008, Direction=In + // The CS signals from field CsPresent that are routed to DIMM connector 0 + uint8_t CsPresentD1; // Byte offset 0x12, CSR Addr 0x54009, Direction=In + // The CS signals from field CsPresent that are routed to DIMM connector 1 + uint8_t AddrMirror; // Byte offset 0x13, CSR Addr 0x54009, Direction=In + // Corresponds to CS[3:0] + // 1 = Address Mirror. + // 0 = No Address Mirror. + uint8_t CsTestFail; // Byte offset 0x14, CSR Addr 0x5400a, Direction=Out + // This field will be set if training fails on any rank. + // 0x0 = No failures + // non-zero = one or more ranks failed training + uint8_t PhyCfg; // Byte offset 0x15, CSR Addr 0x5400a, Direction=In + // Additional mode bits. + // + // Bit fields: + // [0] SlowAccessMode : + // 1 = 2T Address Timing. + // 0 = 1T Address Timing. + // [7-1] RFU, must be zero + uint16_t SequenceCtrl; // Byte offset 0x16, CSR Addr 0x5400b, Direction=In + // Controls the training steps to be run. Each bit corresponds to a training step. + // + // If the bit is set to 1, the training step will run. + // If the bit is set to 0, the training step will be skipped. + // + // Training step to bit mapping: + // SequenceCtrl[0] = Run DevInit - Device/phy initialization. Should always be set. + // SequenceCtrl[1] = RFU, must be zero + // SequenceCtrl[2] = RFU, must be zero + // SequenceCtrl[3] = RFU, must be zero + // SequenceCtrl[4] = RFU, must be zero + // SequenceCtrl[5] = Run rd2D - 2d read dqs training + // SequenceCtrl[6] = Run wr2D - 2d write dq training + // SequenceCtrl[7] = RFU, must be zero + // SequenceCtrl[8] = RFU, must be zero + // SequenceCtrl[9] = RFU, must be zero + // SequenceCtrl[10] = RFU, must be zero + // SequenceCtrl[11] = RFU, must be zero + // SequenceCtrl[12] = RFU, must be zero + // SequenceCtrl[13] = RFU, must be zero + // SequenceCtrl[15-14] = RFU, must be zero + uint8_t HdtCtrl; // Byte offset 0x18, CSR Addr 0x5400c, Direction=In + // To control the total number of debug messages, a verbosity subfield (HdtCtrl, Hardware Debug Trace Control) exists in the message block. Every message has a verbosity level associated with it, and as the HdtCtrl value is increased, less important s messages stop being sent through the mailboxes. The meanings of several major HdtCtrl thresholds are explained below: + // + // 0x05 = Detailed debug messages (e.g. Eye delays) + // 0x0A = Coarse debug messages (e.g. rank information) + // 0xC8 = Stage completion + // 0xC9 = Assertion messages + // 0xFF = Firmware completion messages only + // + // See Training App Note for more detailed information on what messages are included for each threshold. + // + uint8_t RX2D_TrainOpt; // Byte offset 0x19, CSR Addr 0x5400c, Direction=In + // Bit fields, if 2D read training enabled, then use these additional options: + // [0] DFE + // 1 = Run rx2D with DFE + // 0 = Run rx2D with DFE off + // [1-2] Voltage Step Size (2^n) + // 3 = 8 DAC settings between checked values + // 2 = 4 DAC settings between checked values + // 1 = 2 DAC settings between checked values + // 0 = 1 DAC settings between checked values + // [3-4] Delay Step Size (2^n) + // 3 = 8 LCDL delays between checked values + // 2 = 4 LCDL delays between checked values + // 1 = 2 LCDL delays between checked values + // 0 = 1 LCDL delays between checked values + // [5-7] RFU, must be zero + // + uint8_t TX2D_TrainOpt; // Byte offset 0x1a, CSR Addr 0x5400d, Direction=In + // Bit fields, if 2D write training is enabled, then use these additional options: + // [0] FFE + // 1 = Train tx2D with FFE + // 0 = Train tx2D with FFE off + // [1-2] Voltage Step Size (2^n) + // 3 = 8 DAC settings between checked values + // 2 = 4 DAC settings between checked values + // 1 = 2 DAC settings between checked values + // 0 = 1 DAC settings between checked values + // [3-4] Delay Step Size (2^n) + // 3 = 8 LCDL delays between checked values + // 2 = 4 LCDL delays between checked values + // 1 = 2 LCDL delays between checked values + // 0 = 1 LCDL delays between checked values + // [5] FFE Decision Algorithm Control + // 1 = FFE chooses the drive strength that maximizes the average eye-area across the entire phy. + // 0 = FFE chooses the drive strength that maximizes the smallest eye across the entire phy. + // [6-7] RFU, must be zero + // + uint8_t Share2DVrefResult; // Byte offset 0x1b, CSR Addr 0x5400d, Direction=In + // Bitmap that designates the phy's vref source for every pstate + // If Share2DVrefResult[x] = 0, then after 2D training, pstate x will continue using the phyVref provided in pstate x’s 1D messageblock. + // If Share2DVrefResult[x] = 1, then after 2D training, pstate x will use the per-lane VrefDAC0/1 CSRs trained by 2d training. + uint8_t Delay_Weight2D; // Byte offset 0x1c, CSR Addr 0x5400e, Direction=In + // During 2D training, the ideal eye center changes depending on how valuable delay margin is compared to voltage margin. delay_weight2D sets the value, or weight, of one step of delay margin. The ratio of voltage_weight2D to delay_weight2D will be used by 2D training to choose your preferred center point. There are 32 delay steps in a perfect eye. + uint8_t Voltage_Weight2D; // Byte offset 0x1d, CSR Addr 0x5400e, Direction=In + // During 2D training, the ideal eye center changes depending on how valuable voltage margin is compared to delay margin. voltage_weight2D sets the value, or weight, of one step of voltage margin. The ratio of voltage_weight2D to delay_weight2D will be used by 2D training to choose your preferred center point. There are 128 voltage steps in a perfect eye. + uint8_t Reserved1E; // Byte offset 0x1e, CSR Addr 0x5400f, Direction=In + // Input for constraining the range of vref(DQ) values training will collect data for, usually reducing training time. However, too large of a voltage range may cause longer 2D training times while too small of a voltage range may truncate passing regions. When in doubt, leave this field set to 0. + // Used by 2D training in: Rd2D, Wr2D + // + // Reserved1E[0-3]: Rd2D Voltage Range + // 0 = Training will search all phy vref(DQ) settings + // 1 = limit to +/-2 %VDDQ from phyVref + // 2 = limit to +/-4 %VDDQ from phyVref + // … + // 15 = limit to +/-30% VDDQ from phyVref + // + // Reserved1E[4-7]: Wr2D Voltage Range + // 0 = Training will search all dram vref(DQ) settings + // 1 = limit to +/-2 %VDDQ from MR6 + // 2 = limit to +/-4 %VDDQ from MR6 + // … + // 15 = limit to +/-30% VDDQ from MR6 + uint8_t Reserved1F; // Byte offset 0x1f, CSR Addr 0x5400f, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved20; // Byte offset 0x20, CSR Addr 0x54010, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved21; // Byte offset 0x21, CSR Addr 0x54010, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint16_t PhyConfigOverride; // Byte offset 0x22, CSR Addr 0x54011, Direction=In + // Override PhyConfig csr. + // 0x0: Use hardware csr value for PhyConfing (recommended) + // Other values: Use value for PhyConfig instead of Hardware value. + // + uint8_t DFIMRLMargin; // Byte offset 0x24, CSR Addr 0x54012, Direction=In + // Margin added to smallest passing trained DFI Max Read Latency value, in units of DFI clocks. Recommended to be >= 1. See the Training App Note for more details on the training process and the use of this value. + uint8_t R0_RxClkDly_Margin; // Byte offset 0x25, CSR Addr 0x54012, Direction=Out + // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group. + uint8_t R0_VrefDac_Margin; // Byte offset 0x26, CSR Addr 0x54013, Direction=Out + // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group. + uint8_t R0_TxDqDly_Margin; // Byte offset 0x27, CSR Addr 0x54013, Direction=Out + // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group. + uint8_t R0_DeviceVref_Margin; // Byte offset 0x28, CSR Addr 0x54014, Direction=Out + // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group. + uint8_t Reserved29; // Byte offset 0x29, CSR Addr 0x54014, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved2A; // Byte offset 0x2a, CSR Addr 0x54015, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved2B; // Byte offset 0x2b, CSR Addr 0x54015, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved2C; // Byte offset 0x2c, CSR Addr 0x54016, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved2D; // Byte offset 0x2d, CSR Addr 0x54016, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved2E; // Byte offset 0x2e, CSR Addr 0x54017, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved2F; // Byte offset 0x2f, CSR Addr 0x54017, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved30; // Byte offset 0x30, CSR Addr 0x54018, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved31; // Byte offset 0x31, CSR Addr 0x54018, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved32; // Byte offset 0x32, CSR Addr 0x54019, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t R1_RxClkDly_Margin; // Byte offset 0x33, CSR Addr 0x54019, Direction=Out + // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group. + uint8_t R1_VrefDac_Margin; // Byte offset 0x34, CSR Addr 0x5401a, Direction=Out + // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group. + uint8_t R1_TxDqDly_Margin; // Byte offset 0x35, CSR Addr 0x5401a, Direction=Out + // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group. + uint8_t R1_DeviceVref_Margin; // Byte offset 0x36, CSR Addr 0x5401b, Direction=Out + // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group. + uint8_t Reserved37; // Byte offset 0x37, CSR Addr 0x5401b, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved38; // Byte offset 0x38, CSR Addr 0x5401c, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved39; // Byte offset 0x39, CSR Addr 0x5401c, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved3A; // Byte offset 0x3a, CSR Addr 0x5401d, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved3B; // Byte offset 0x3b, CSR Addr 0x5401d, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved3C; // Byte offset 0x3c, CSR Addr 0x5401e, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved3D; // Byte offset 0x3d, CSR Addr 0x5401e, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved3E; // Byte offset 0x3e, CSR Addr 0x5401f, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved3F; // Byte offset 0x3f, CSR Addr 0x5401f, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved40; // Byte offset 0x40, CSR Addr 0x54020, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t R2_RxClkDly_Margin; // Byte offset 0x41, CSR Addr 0x54020, Direction=Out + // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group. + uint8_t R2_VrefDac_Margin; // Byte offset 0x42, CSR Addr 0x54021, Direction=Out + // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group. + uint8_t R2_TxDqDly_Margin; // Byte offset 0x43, CSR Addr 0x54021, Direction=Out + // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group. + uint8_t R2_DeviceVref_Margin; // Byte offset 0x44, CSR Addr 0x54022, Direction=Out + // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group. + uint8_t Reserved45; // Byte offset 0x45, CSR Addr 0x54022, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved46; // Byte offset 0x46, CSR Addr 0x54023, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved47; // Byte offset 0x47, CSR Addr 0x54023, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved48; // Byte offset 0x48, CSR Addr 0x54024, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved49; // Byte offset 0x49, CSR Addr 0x54024, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved4A; // Byte offset 0x4a, CSR Addr 0x54025, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved4B; // Byte offset 0x4b, CSR Addr 0x54025, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved4C; // Byte offset 0x4c, CSR Addr 0x54026, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved4D; // Byte offset 0x4d, CSR Addr 0x54026, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved4E; // Byte offset 0x4e, CSR Addr 0x54027, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t R3_RxClkDly_Margin; // Byte offset 0x4f, CSR Addr 0x54027, Direction=Out + // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group. + uint8_t R3_VrefDac_Margin; // Byte offset 0x50, CSR Addr 0x54028, Direction=Out + // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group. + uint8_t R3_TxDqDly_Margin; // Byte offset 0x51, CSR Addr 0x54028, Direction=Out + // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group. + uint8_t R3_DeviceVref_Margin; // Byte offset 0x52, CSR Addr 0x54029, Direction=Out + // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group. + uint8_t Reserved53; // Byte offset 0x53, CSR Addr 0x54029, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved54; // Byte offset 0x54, CSR Addr 0x5402a, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved55; // Byte offset 0x55, CSR Addr 0x5402a, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved56; // Byte offset 0x56, CSR Addr 0x5402b, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved57; // Byte offset 0x57, CSR Addr 0x5402b, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved58; // Byte offset 0x58, CSR Addr 0x5402c, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved59; // Byte offset 0x59, CSR Addr 0x5402c, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved5A; // Byte offset 0x5a, CSR Addr 0x5402d, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved5B; // Byte offset 0x5b, CSR Addr 0x5402d, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved5C; // Byte offset 0x5c, CSR Addr 0x5402e, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved5D; // Byte offset 0x5d, CSR Addr 0x5402e, Direction=In + // Bit Field for enabling optional 2D training features that impact both Rx2D and Tx2D. + // + // Reserved5D[0-3]: bitTimeControl + // Input for increasing the number of data-comparisons 2D runs per (delay,voltage) point. Every time this input increases by 1, the number of 2D data comparisons is doubled. The 2D run time will increase proportionally to the number of bit times requested per point. + // 0 = 1 kilobit per point (legacy behavior) + // 1 = 2 kilobits per point + // 2 = 4 kilobits per point + // … + // 15 = 32 megabits per point + // + // Reserved5D[4]: Exhaustive2D + // 0 = 2D’s optimization assumes the optimal trained point is near the 1D trained point (legacy behavior) + // 1 = 2D’s optimization searches the entire passing region at the cost of run time. Recommended for optimal results any time the optimal trained point is expected to be near the edges of the eyes instead of near the 1D trained point. + // + // Reserved5D[5:7]: RFU, must be 0 + uint16_t MR0; // Byte offset 0x5e, CSR Addr 0x5402f, Direction=In + // Value of DDR mode register MR0 for all ranks for current pstate + uint16_t MR1; // Byte offset 0x60, CSR Addr 0x54030, Direction=In + // Value of DDR mode register MR1 for all ranks for current pstate + uint16_t MR2; // Byte offset 0x62, CSR Addr 0x54031, Direction=In + // Value of DDR mode register MR2 for all ranks for current pstate + uint16_t MR3; // Byte offset 0x64, CSR Addr 0x54032, Direction=In + // Value of DDR mode register MR3 for all ranks for current pstate + uint16_t MR4; // Byte offset 0x66, CSR Addr 0x54033, Direction=In + // Value of DDR mode register MR4 for all ranks for current pstate + uint16_t MR5; // Byte offset 0x68, CSR Addr 0x54034, Direction=In + // Value of DDR mode register MR5 for all ranks for current pstate + uint16_t MR6; // Byte offset 0x6a, CSR Addr 0x54035, Direction=In + // Value of DDR mode register MR6 for all ranks for current pstate. Note: The initial VrefDq value and range must be set in A6:A0. + uint8_t X16Present; // Byte offset 0x6c, CSR Addr 0x54036, Direction=In + // X16 device map. Corresponds to CS[3:0]. + // X16Present[0] = CS0 is populated with X16 devices + // X16Present[1] = CS1 is populated with X16 devices + // X16Present[2] = CS2 is populated with X16 devices + // X16Present[3] = CS3 is populated with X16 devices + // X16Present[7:4] = Reserved (must be programmed to 0) + // + // Ranks may not contain mixed device types. + uint8_t CsSetupGDDec; // Byte offset 0x6d, CSR Addr 0x54036, Direction=In + // controls timing of chip select signals when DDR4 gear-down mode is active + // 0 - Leave delay of chip select timing group signal the same both before and after gear-down sync occurs + // 1 - Add 1UI of delay to chip select timing group signals when geardown-mode is active. This allows CS signals to have equal setup and hold time in gear-down mode + uint16_t RTT_NOM_WR_PARK0; // Byte offset 0x6e, CSR Addr 0x54037, Direction=In + // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 0 DRAM: + // RTT_NOM_WR_PARK0[0] = 1: Option is enable (otherwise, remaining bit fields are don't care) + // RTT_NOM_WR_PARK0[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 0 + // RTT_NOM_WR_PARK0[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 0 + // RTT_NOM_WR_PARK0[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 0 + uint16_t RTT_NOM_WR_PARK1; // Byte offset 0x70, CSR Addr 0x54038, Direction=In + // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 1 DRAM: + // RTT_NOM_WR_PARK1[0] = 1: Option is enable (otherwise, remaining bit fields are don't care) + // RTT_NOM_WR_PARK1[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 1 + // RTT_NOM_WR_PARK1[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 1 + // RTT_NOM_WR_PARK1[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 1 + uint16_t RTT_NOM_WR_PARK2; // Byte offset 0x72, CSR Addr 0x54039, Direction=In + // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 2 DRAM: + // RTT_NOM_WR_PARK2[0] = 1: Option is enable (otherwise, remaining bit fields are don't care) + // RTT_NOM_WR_PARK2[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 2 + // RTT_NOM_WR_PARK2[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 2 + // RTT_NOM_WR_PARK2[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 2 + uint16_t RTT_NOM_WR_PARK3; // Byte offset 0x74, CSR Addr 0x5403a, Direction=In + // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 3 DRAM: + // RTT_NOM_WR_PARK3[0] = 1: Option is enable (otherwise, remaining bit fields are don't care) + // RTT_NOM_WR_PARK3[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 3 + // RTT_NOM_WR_PARK3[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 3 + // RTT_NOM_WR_PARK3[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 3 + uint16_t RTT_NOM_WR_PARK4; // Byte offset 0x76, CSR Addr 0x5403b, Direction=In + // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 4 DRAM: + // RTT_NOM_WR_PARK4[0] = 1: Option is enable (otherwise, remaining bit fields are don't care) + // RTT_NOM_WR_PARK4[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 4 + // RTT_NOM_WR_PARK4[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 4 + // RTT_NOM_WR_PARK4[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 4 + uint16_t RTT_NOM_WR_PARK5; // Byte offset 0x78, CSR Addr 0x5403c, Direction=In + // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 5 DRAM: + // RTT_NOM_WR_PARK5[0] = 1: Option is enable (otherwise, remaining bit fields are don't care) + // RTT_NOM_WR_PARK5[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 5 + // RTT_NOM_WR_PARK5[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 5 + // RTT_NOM_WR_PARK5[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 5 + uint16_t RTT_NOM_WR_PARK6; // Byte offset 0x7a, CSR Addr 0x5403d, Direction=In + // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 6 DRAM: + // RTT_NOM_WR_PARK6[0] = 1: Option is enable (otherwise, remaining bit fields are don't care) + // RTT_NOM_WR_PARK6[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 6 + // RTT_NOM_WR_PARK6[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 6 + // RTT_NOM_WR_PARK6[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 6 + uint16_t RTT_NOM_WR_PARK7; // Byte offset 0x7c, CSR Addr 0x5403e, Direction=In + // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 7 DRAM: + // RTT_NOM_WR_PARK7[0] = 1: Option is enable (otherwise, remaining bit fields are don't care) + // RTT_NOM_WR_PARK7[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 7 + // RTT_NOM_WR_PARK7[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 7 + // RTT_NOM_WR_PARK7[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 7 + uint8_t AcsmOdtCtrl0; // Byte offset 0x7e, CSR Addr 0x5403f, Direction=In + // Odt pattern for accesses targeting rank 0. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl1; // Byte offset 0x7f, CSR Addr 0x5403f, Direction=In + // Odt pattern for accesses targeting rank 1. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl2; // Byte offset 0x80, CSR Addr 0x54040, Direction=In + // Odt pattern for accesses targeting rank 2. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl3; // Byte offset 0x81, CSR Addr 0x54040, Direction=In + // Odt pattern for accesses targeting rank 3. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl4; // Byte offset 0x82, CSR Addr 0x54041, Direction=In + // Odt pattern for accesses targeting rank 4. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl5; // Byte offset 0x83, CSR Addr 0x54041, Direction=In + // Odt pattern for accesses targeting rank 5. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl6; // Byte offset 0x84, CSR Addr 0x54042, Direction=In + // Odt pattern for accesses targeting rank 6. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl7; // Byte offset 0x85, CSR Addr 0x54042, Direction=In + // Odt pattern for accesses targeting rank 7. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t VrefDqR0Nib0; // Byte offset 0x86, CSR Addr 0x54043, Direction=InOut + // VrefDq for rank 0 nibble 0. Specifies MR6[6:0] + uint8_t VrefDqR0Nib1; // Byte offset 0x87, CSR Addr 0x54043, Direction=InOut + // VrefDq for rank 0 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR0Nib0 for x8 or x16 devices. + uint8_t VrefDqR0Nib2; // Byte offset 0x88, CSR Addr 0x54044, Direction=InOut + // VrefDq for rank 0 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR0Nib0 for x16 devices. + uint8_t VrefDqR0Nib3; // Byte offset 0x89, CSR Addr 0x54044, Direction=InOut + // VrefDq for rank 0 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR0Nib0 for x16 devices, or VrefDqR0Nib2 for x8 devices. + uint8_t VrefDqR0Nib4; // Byte offset 0x8a, CSR Addr 0x54045, Direction=InOut + // VrefDq for rank 0 nibble 4. Specifies MR6[6:0] + uint8_t VrefDqR0Nib5; // Byte offset 0x8b, CSR Addr 0x54045, Direction=InOut + // VrefDq for rank 0 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR0Nib4 for x8 or x16 devices. + uint8_t VrefDqR0Nib6; // Byte offset 0x8c, CSR Addr 0x54046, Direction=InOut + // VrefDq for rank 0 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR0Nib4 for x16 devices. + uint8_t VrefDqR0Nib7; // Byte offset 0x8d, CSR Addr 0x54046, Direction=InOut + // VrefDq for rank 0 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR0Nib4 for x16 devices, or VrefDqR0Nib6 for x8 devices. + uint8_t VrefDqR0Nib8; // Byte offset 0x8e, CSR Addr 0x54047, Direction=InOut + // VrefDq for rank 0 nibble 8. Specifies MR6[6:0] + uint8_t VrefDqR0Nib9; // Byte offset 0x8f, CSR Addr 0x54047, Direction=InOut + // VrefDq for rank 0 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR0Nib8 for x8 or x16 devices. + uint8_t VrefDqR0Nib10; // Byte offset 0x90, CSR Addr 0x54048, Direction=InOut + // VrefDq for rank 0 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR0Nib8 for x16 devices. + uint8_t VrefDqR0Nib11; // Byte offset 0x91, CSR Addr 0x54048, Direction=InOut + // VrefDq for rank 0 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR0Nib8 for x16 devices, or VrefDqR0Nib10 for x8 devices. + uint8_t VrefDqR0Nib12; // Byte offset 0x92, CSR Addr 0x54049, Direction=InOut + // VrefDq for rank 0 nibble 12. Specifies MR6[6:0] + uint8_t VrefDqR0Nib13; // Byte offset 0x93, CSR Addr 0x54049, Direction=InOut + // VrefDq for rank 0 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR0Nib12 for x8 or x16 devices. + uint8_t VrefDqR0Nib14; // Byte offset 0x94, CSR Addr 0x5404a, Direction=InOut + // VrefDq for rank 0 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR0Nib12 for x16 devices. + uint8_t VrefDqR0Nib15; // Byte offset 0x95, CSR Addr 0x5404a, Direction=InOut + // VrefDq for rank 0 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR0Nib12 for x16 devices, or VrefDqR0Nib14 for x8 devices. + uint8_t VrefDqR0Nib16; // Byte offset 0x96, CSR Addr 0x5404b, Direction=InOut + // VrefDq for rank 0 nibble 16. Specifies MR6[6:0] + uint8_t VrefDqR0Nib17; // Byte offset 0x97, CSR Addr 0x5404b, Direction=InOut + // VrefDq for rank 0 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR0Nib16 for x8 or x16 devices. + uint8_t VrefDqR0Nib18; // Byte offset 0x98, CSR Addr 0x5404c, Direction=InOut + // VrefDq for rank 0 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR0Nib16 for x16 devices. + uint8_t VrefDqR0Nib19; // Byte offset 0x99, CSR Addr 0x5404c, Direction=InOut + // VrefDq for rank 0 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR0Nib16 for x16 devices, or VrefDqR0Nib18 for x8 devices. + uint8_t VrefDqR1Nib0; // Byte offset 0x9a, CSR Addr 0x5404d, Direction=InOut + // VrefDq for rank 1 nibble 0. Specifies MR6[6:0] + uint8_t VrefDqR1Nib1; // Byte offset 0x9b, CSR Addr 0x5404d, Direction=InOut + // VrefDq for rank 1 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR1Nib0 for x8 or x16 devices. + uint8_t VrefDqR1Nib2; // Byte offset 0x9c, CSR Addr 0x5404e, Direction=InOut + // VrefDq for rank 1 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR1Nib0 for x16 devices. + uint8_t VrefDqR1Nib3; // Byte offset 0x9d, CSR Addr 0x5404e, Direction=InOut + // VrefDq for rank 1 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR1Nib0 for x16 devices, or VrefDqR1Nib2 for x8 devices. + uint8_t VrefDqR1Nib4; // Byte offset 0x9e, CSR Addr 0x5404f, Direction=InOut + // VrefDq for rank 1 nibble 4. Specifies MR6[6:0] + uint8_t VrefDqR1Nib5; // Byte offset 0x9f, CSR Addr 0x5404f, Direction=InOut + // VrefDq for rank 1 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR1Nib4 for x8 or x16 devices. + uint8_t VrefDqR1Nib6; // Byte offset 0xa0, CSR Addr 0x54050, Direction=InOut + // VrefDq for rank 1 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR1Nib4 for x16 devices. + uint8_t VrefDqR1Nib7; // Byte offset 0xa1, CSR Addr 0x54050, Direction=InOut + // VrefDq for rank 1 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR1Nib4 for x16 devices, or VrefDqR1Nib6 for x8 devices. + uint8_t VrefDqR1Nib8; // Byte offset 0xa2, CSR Addr 0x54051, Direction=InOut + // VrefDq for rank 1 nibble 8. Specifies MR6[6:0] + uint8_t VrefDqR1Nib9; // Byte offset 0xa3, CSR Addr 0x54051, Direction=InOut + // VrefDq for rank 1 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR1Nib8 for x8 or x16 devices. + uint8_t VrefDqR1Nib10; // Byte offset 0xa4, CSR Addr 0x54052, Direction=InOut + // VrefDq for rank 1 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR1Nib8 for x16 devices. + uint8_t VrefDqR1Nib11; // Byte offset 0xa5, CSR Addr 0x54052, Direction=InOut + // VrefDq for rank 1 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR1Nib8 for x16 devices, or VrefDqR1Nib10 for x8 devices. + uint8_t VrefDqR1Nib12; // Byte offset 0xa6, CSR Addr 0x54053, Direction=InOut + // VrefDq for rank 1 nibble 12. Specifies MR6[6:0] + uint8_t VrefDqR1Nib13; // Byte offset 0xa7, CSR Addr 0x54053, Direction=InOut + // VrefDq for rank 1 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR1Nib12 for x8 or x16 devices. + uint8_t VrefDqR1Nib14; // Byte offset 0xa8, CSR Addr 0x54054, Direction=InOut + // VrefDq for rank 1 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR1Nib12 for x16 devices. + uint8_t VrefDqR1Nib15; // Byte offset 0xa9, CSR Addr 0x54054, Direction=InOut + // VrefDq for rank 1 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR1Nib12 for x16 devices, or VrefDqR1Nib14 for x8 devices. + uint8_t VrefDqR1Nib16; // Byte offset 0xaa, CSR Addr 0x54055, Direction=InOut + // VrefDq for rank 1 nibble 16. Specifies MR6[6:0] + uint8_t VrefDqR1Nib17; // Byte offset 0xab, CSR Addr 0x54055, Direction=InOut + // VrefDq for rank 1 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR1Nib16 for x8 or x16 devices. + uint8_t VrefDqR1Nib18; // Byte offset 0xac, CSR Addr 0x54056, Direction=InOut + // VrefDq for rank 1 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR1Nib16 for x16 devices. + uint8_t VrefDqR1Nib19; // Byte offset 0xad, CSR Addr 0x54056, Direction=InOut + // VrefDq for rank 1 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR1Nib16 for x16 devices, or VrefDqR1Nib18 for x8 devices. + uint8_t VrefDqR2Nib0; // Byte offset 0xae, CSR Addr 0x54057, Direction=InOut + // VrefDq for rank 2 nibble 0. Specifies MR6[6:0] + uint8_t VrefDqR2Nib1; // Byte offset 0xaf, CSR Addr 0x54057, Direction=InOut + // VrefDq for rank 2 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR2Nib0 for x8 or x16 devices. + uint8_t VrefDqR2Nib2; // Byte offset 0xb0, CSR Addr 0x54058, Direction=InOut + // VrefDq for rank 2 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR2Nib0 for x16 devices. + uint8_t VrefDqR2Nib3; // Byte offset 0xb1, CSR Addr 0x54058, Direction=InOut + // VrefDq for rank 2 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR2Nib0 for x16 devices, or VrefDqR2Nib2 for x8 devices. + uint8_t VrefDqR2Nib4; // Byte offset 0xb2, CSR Addr 0x54059, Direction=InOut + // VrefDq for rank 2 nibble 4. Specifies MR6[6:0] + uint8_t VrefDqR2Nib5; // Byte offset 0xb3, CSR Addr 0x54059, Direction=InOut + // VrefDq for rank 2 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR2Nib4 for x8 or x16 devices. + uint8_t VrefDqR2Nib6; // Byte offset 0xb4, CSR Addr 0x5405a, Direction=InOut + // VrefDq for rank 2 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR2Nib4 for x16 devices. + uint8_t VrefDqR2Nib7; // Byte offset 0xb5, CSR Addr 0x5405a, Direction=InOut + // VrefDq for rank 2 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR2Nib4 for x16 devices, or VrefDqR2Nib6 for x8 devices. + uint8_t VrefDqR2Nib8; // Byte offset 0xb6, CSR Addr 0x5405b, Direction=InOut + // VrefDq for rank 2 nibble 8. Specifies MR6[6:0] + uint8_t VrefDqR2Nib9; // Byte offset 0xb7, CSR Addr 0x5405b, Direction=InOut + // VrefDq for rank 2 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR2Nib8 for x8 or x16 devices. + uint8_t VrefDqR2Nib10; // Byte offset 0xb8, CSR Addr 0x5405c, Direction=InOut + // VrefDq for rank 2 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR2Nib8 for x16 devices. + uint8_t VrefDqR2Nib11; // Byte offset 0xb9, CSR Addr 0x5405c, Direction=InOut + // VrefDq for rank 2 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR2Nib8 for x16 devices, or VrefDqR2Nib10 for x8 devices. + uint8_t VrefDqR2Nib12; // Byte offset 0xba, CSR Addr 0x5405d, Direction=InOut + // VrefDq for rank 2 nibble 12. Specifies MR6[6:0] + uint8_t VrefDqR2Nib13; // Byte offset 0xbb, CSR Addr 0x5405d, Direction=InOut + // VrefDq for rank 2 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR2Nib12 for x8 or x16 devices. + uint8_t VrefDqR2Nib14; // Byte offset 0xbc, CSR Addr 0x5405e, Direction=InOut + // VrefDq for rank 2 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR2Nib12 for x16 devices. + uint8_t VrefDqR2Nib15; // Byte offset 0xbd, CSR Addr 0x5405e, Direction=InOut + // VrefDq for rank 2 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR2Nib12 for x16 devices, or VrefDqR2Nib14 for x8 devices. + uint8_t VrefDqR2Nib16; // Byte offset 0xbe, CSR Addr 0x5405f, Direction=InOut + // VrefDq for rank 2 nibble 16. Specifies MR6[6:0] + uint8_t VrefDqR2Nib17; // Byte offset 0xbf, CSR Addr 0x5405f, Direction=InOut + // VrefDq for rank 2 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR2Nib16 for x8 or x16 devices. + uint8_t VrefDqR2Nib18; // Byte offset 0xc0, CSR Addr 0x54060, Direction=InOut + // VrefDq for rank 2 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR2Nib16 for x16 devices. + uint8_t VrefDqR2Nib19; // Byte offset 0xc1, CSR Addr 0x54060, Direction=InOut + // VrefDq for rank 2 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR2Nib16 for x16 devices, or VrefDqR2Nib18 for x8 devices. + uint8_t VrefDqR3Nib0; // Byte offset 0xc2, CSR Addr 0x54061, Direction=InOut + // VrefDq for rank 3 nibble 0. Specifies MR6[6:0] + uint8_t VrefDqR3Nib1; // Byte offset 0xc3, CSR Addr 0x54061, Direction=InOut + // VrefDq for rank 3 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR3Nib0 for x8 or x16 devices. + uint8_t VrefDqR3Nib2; // Byte offset 0xc4, CSR Addr 0x54062, Direction=InOut + // VrefDq for rank 3 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR3Nib0 for x16 devices. + uint8_t VrefDqR3Nib3; // Byte offset 0xc5, CSR Addr 0x54062, Direction=InOut + // VrefDq for rank 3 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR3Nib0 for x16 devices, or VrefDqR3Nib2 for x8 devices. + uint8_t VrefDqR3Nib4; // Byte offset 0xc6, CSR Addr 0x54063, Direction=InOut + // VrefDq for rank 3 nibble 4. Specifies MR6[6:0] + uint8_t VrefDqR3Nib5; // Byte offset 0xc7, CSR Addr 0x54063, Direction=InOut + // VrefDq for rank 3 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR3Nib4 for x8 or x16 devices. + uint8_t VrefDqR3Nib6; // Byte offset 0xc8, CSR Addr 0x54064, Direction=InOut + // VrefDq for rank 3 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR3Nib4 for x16 devices. + uint8_t VrefDqR3Nib7; // Byte offset 0xc9, CSR Addr 0x54064, Direction=InOut + // VrefDq for rank 3 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR3Nib4 for x16 devices, or VrefDqR3Nib6 for x8 devices. + uint8_t VrefDqR3Nib8; // Byte offset 0xca, CSR Addr 0x54065, Direction=InOut + // VrefDq for rank 3 nibble 8. Specifies MR6[6:0] + uint8_t VrefDqR3Nib9; // Byte offset 0xcb, CSR Addr 0x54065, Direction=InOut + // VrefDq for rank 3 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR3Nib8 for x8 or x16 devices. + uint8_t VrefDqR3Nib10; // Byte offset 0xcc, CSR Addr 0x54066, Direction=InOut + // VrefDq for rank 3 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR3Nib8 for x16 devices. + uint8_t VrefDqR3Nib11; // Byte offset 0xcd, CSR Addr 0x54066, Direction=InOut + // VrefDq for rank 3 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR3Nib8 for x16 devices, or VrefDqR3Nib10 for x8 devices. + uint8_t VrefDqR3Nib12; // Byte offset 0xce, CSR Addr 0x54067, Direction=InOut + // VrefDq for rank 3 nibble 12. Specifies MR6[6:0] + uint8_t VrefDqR3Nib13; // Byte offset 0xcf, CSR Addr 0x54067, Direction=InOut + // VrefDq for rank 3 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR3Nib12 for x8 or x16 devices. + uint8_t VrefDqR3Nib14; // Byte offset 0xd0, CSR Addr 0x54068, Direction=InOut + // VrefDq for rank 3 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR3Nib12 for x16 devices. + uint8_t VrefDqR3Nib15; // Byte offset 0xd1, CSR Addr 0x54068, Direction=InOut + // VrefDq for rank 3 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR3Nib12 for x16 devices, or VrefDqR3Nib14 for x8 devices. + uint8_t VrefDqR3Nib16; // Byte offset 0xd2, CSR Addr 0x54069, Direction=InOut + // VrefDq for rank 3 nibble 16. Specifies MR6[6:0] + uint8_t VrefDqR3Nib17; // Byte offset 0xd3, CSR Addr 0x54069, Direction=InOut + // VrefDq for rank 3 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR3Nib16 for x8 or x16 devices. + uint8_t VrefDqR3Nib18; // Byte offset 0xd4, CSR Addr 0x5406a, Direction=InOut + // VrefDq for rank 3 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR3Nib16 for x16 devices. + uint8_t VrefDqR3Nib19; // Byte offset 0xd5, CSR Addr 0x5406a, Direction=InOut + // VrefDq for rank 3 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR3Nib16 for x16 devices, or VrefDqR3Nib18 for x8 devices. + uint8_t ReservedD6; // Byte offset 0xd6, CSR Addr 0x5406b, Direction=N/A + + uint8_t ReservedD7; // Byte offset 0xd7, CSR Addr 0x5406b, Direction=N/A + + uint8_t ReservedD8; // Byte offset 0xd8, CSR Addr 0x5406c, Direction=N/A + + uint8_t ReservedD9; // Byte offset 0xd9, CSR Addr 0x5406c, Direction=N/A + + uint8_t ReservedDA; // Byte offset 0xda, CSR Addr 0x5406d, Direction=N/A + + uint8_t ReservedDB; // Byte offset 0xdb, CSR Addr 0x5406d, Direction=N/A + + uint8_t ReservedDC; // Byte offset 0xdc, CSR Addr 0x5406e, Direction=N/A + + uint8_t ReservedDD; // Byte offset 0xdd, CSR Addr 0x5406e, Direction=N/A + + uint8_t ReservedDE; // Byte offset 0xde, CSR Addr 0x5406f, Direction=N/A + + uint8_t ReservedDF; // Byte offset 0xdf, CSR Addr 0x5406f, Direction=N/A + + uint8_t ReservedE0; // Byte offset 0xe0, CSR Addr 0x54070, Direction=N/A + + uint8_t ReservedE1; // Byte offset 0xe1, CSR Addr 0x54070, Direction=N/A + + uint8_t ReservedE2; // Byte offset 0xe2, CSR Addr 0x54071, Direction=N/A + + uint8_t ReservedE3; // Byte offset 0xe3, CSR Addr 0x54071, Direction=N/A + + uint8_t ReservedE4; // Byte offset 0xe4, CSR Addr 0x54072, Direction=N/A + + uint8_t ReservedE5; // Byte offset 0xe5, CSR Addr 0x54072, Direction=N/A + + uint8_t ReservedE6; // Byte offset 0xe6, CSR Addr 0x54073, Direction=N/A + + uint8_t ReservedE7; // Byte offset 0xe7, CSR Addr 0x54073, Direction=N/A + + uint8_t ReservedE8; // Byte offset 0xe8, CSR Addr 0x54074, Direction=N/A + + uint8_t ReservedE9; // Byte offset 0xe9, CSR Addr 0x54074, Direction=N/A + + uint8_t ReservedEA; // Byte offset 0xea, CSR Addr 0x54075, Direction=N/A + + uint8_t ReservedEB; // Byte offset 0xeb, CSR Addr 0x54075, Direction=N/A + + uint8_t ReservedEC; // Byte offset 0xec, CSR Addr 0x54076, Direction=N/A + + uint8_t ReservedED; // Byte offset 0xed, CSR Addr 0x54076, Direction=N/A + + uint8_t ReservedEE; // Byte offset 0xee, CSR Addr 0x54077, Direction=N/A + + uint8_t ReservedEF; // Byte offset 0xef, CSR Addr 0x54077, Direction=N/A + + uint8_t ReservedF0; // Byte offset 0xf0, CSR Addr 0x54078, Direction=N/A + + uint8_t ReservedF1; // Byte offset 0xf1, CSR Addr 0x54078, Direction=N/A + + uint8_t ReservedF2; // Byte offset 0xf2, CSR Addr 0x54079, Direction=N/A + + uint8_t ReservedF3; // Byte offset 0xf3, CSR Addr 0x54079, Direction=N/A + + uint8_t ReservedF4; // Byte offset 0xf4, CSR Addr 0x5407a, Direction=N/A + + uint8_t ReservedF5; // Byte offset 0xf5, CSR Addr 0x5407a, Direction=N/A + + uint8_t ReservedF6; // Byte offset 0xf6, CSR Addr 0x5407b, Direction=N/A + + uint8_t ReservedF7; // Byte offset 0xf7, CSR Addr 0x5407b, Direction=N/A + + uint8_t ReservedF8; // Byte offset 0xf8, CSR Addr 0x5407c, Direction=N/A + + uint8_t ReservedF9; // Byte offset 0xf9, CSR Addr 0x5407c, Direction=N/A + + uint8_t ReservedFA; // Byte offset 0xfa, CSR Addr 0x5407d, Direction=N/A + + uint8_t ReservedFB; // Byte offset 0xfb, CSR Addr 0x5407d, Direction=N/A + + uint8_t ReservedFC; // Byte offset 0xfc, CSR Addr 0x5407e, Direction=N/A + + uint8_t ReservedFD; // Byte offset 0xfd, CSR Addr 0x5407e, Direction=N/A + + uint8_t ReservedFE; // Byte offset 0xfe, CSR Addr 0x5407f, Direction=N/A + + uint8_t ReservedFF; // Byte offset 0xff, CSR Addr 0x5407f, Direction=N/A + + uint8_t Reserved100; // Byte offset 0x100, CSR Addr 0x54080, Direction=N/A + + uint8_t Reserved101; // Byte offset 0x101, CSR Addr 0x54080, Direction=N/A + + uint8_t Reserved102; // Byte offset 0x102, CSR Addr 0x54081, Direction=N/A + + uint8_t Reserved103; // Byte offset 0x103, CSR Addr 0x54081, Direction=N/A + + uint8_t Reserved104; // Byte offset 0x104, CSR Addr 0x54082, Direction=N/A + + uint8_t Reserved105; // Byte offset 0x105, CSR Addr 0x54082, Direction=N/A + + uint8_t Reserved106; // Byte offset 0x106, CSR Addr 0x54083, Direction=N/A + + uint8_t Reserved107; // Byte offset 0x107, CSR Addr 0x54083, Direction=N/A + + uint8_t Reserved108; // Byte offset 0x108, CSR Addr 0x54084, Direction=N/A + + uint8_t Reserved109; // Byte offset 0x109, CSR Addr 0x54084, Direction=N/A + + uint8_t Reserved10A; // Byte offset 0x10a, CSR Addr 0x54085, Direction=N/A + + uint8_t Reserved10B; // Byte offset 0x10b, CSR Addr 0x54085, Direction=N/A + + uint8_t Reserved10C; // Byte offset 0x10c, CSR Addr 0x54086, Direction=N/A + + uint8_t Reserved10D; // Byte offset 0x10d, CSR Addr 0x54086, Direction=N/A + + uint8_t Reserved10E; // Byte offset 0x10e, CSR Addr 0x54087, Direction=N/A + + uint8_t Reserved10F; // Byte offset 0x10f, CSR Addr 0x54087, Direction=N/A + + uint8_t Reserved110; // Byte offset 0x110, CSR Addr 0x54088, Direction=N/A + + uint8_t Reserved111; // Byte offset 0x111, CSR Addr 0x54088, Direction=N/A + + uint8_t Reserved112; // Byte offset 0x112, CSR Addr 0x54089, Direction=N/A + + uint8_t Reserved113; // Byte offset 0x113, CSR Addr 0x54089, Direction=N/A + + uint8_t Reserved114; // Byte offset 0x114, CSR Addr 0x5408a, Direction=N/A + + uint8_t Reserved115; // Byte offset 0x115, CSR Addr 0x5408a, Direction=N/A + + uint8_t Reserved116; // Byte offset 0x116, CSR Addr 0x5408b, Direction=N/A + + uint8_t Reserved117; // Byte offset 0x117, CSR Addr 0x5408b, Direction=N/A + + uint8_t Reserved118; // Byte offset 0x118, CSR Addr 0x5408c, Direction=N/A + + uint8_t Reserved119; // Byte offset 0x119, CSR Addr 0x5408c, Direction=N/A + + uint8_t Reserved11A; // Byte offset 0x11a, CSR Addr 0x5408d, Direction=N/A + + uint8_t Reserved11B; // Byte offset 0x11b, CSR Addr 0x5408d, Direction=N/A + + uint8_t Reserved11C; // Byte offset 0x11c, CSR Addr 0x5408e, Direction=N/A + + uint8_t Reserved11D; // Byte offset 0x11d, CSR Addr 0x5408e, Direction=N/A + + uint8_t Reserved11E; // Byte offset 0x11e, CSR Addr 0x5408f, Direction=N/A + + uint8_t Reserved11F; // Byte offset 0x11f, CSR Addr 0x5408f, Direction=N/A + + uint8_t Reserved120; // Byte offset 0x120, CSR Addr 0x54090, Direction=N/A + + uint8_t Reserved121; // Byte offset 0x121, CSR Addr 0x54090, Direction=N/A + + uint8_t Reserved122; // Byte offset 0x122, CSR Addr 0x54091, Direction=N/A + + uint8_t Reserved123; // Byte offset 0x123, CSR Addr 0x54091, Direction=N/A + + uint8_t Reserved124; // Byte offset 0x124, CSR Addr 0x54092, Direction=N/A + + uint8_t Reserved125; // Byte offset 0x125, CSR Addr 0x54092, Direction=N/A + + uint8_t Reserved126; // Byte offset 0x126, CSR Addr 0x54093, Direction=N/A + + uint8_t Reserved127; // Byte offset 0x127, CSR Addr 0x54093, Direction=N/A + + uint8_t Reserved128; // Byte offset 0x128, CSR Addr 0x54094, Direction=N/A + + uint8_t Reserved129; // Byte offset 0x129, CSR Addr 0x54094, Direction=N/A + + uint8_t Reserved12A; // Byte offset 0x12a, CSR Addr 0x54095, Direction=N/A + + uint8_t Reserved12B; // Byte offset 0x12b, CSR Addr 0x54095, Direction=N/A + + uint8_t Reserved12C; // Byte offset 0x12c, CSR Addr 0x54096, Direction=N/A + + uint8_t Reserved12D; // Byte offset 0x12d, CSR Addr 0x54096, Direction=N/A + + uint8_t Reserved12E; // Byte offset 0x12e, CSR Addr 0x54097, Direction=N/A + + uint8_t Reserved12F; // Byte offset 0x12f, CSR Addr 0x54097, Direction=N/A + + uint8_t Reserved130; // Byte offset 0x130, CSR Addr 0x54098, Direction=N/A + + uint8_t Reserved131; // Byte offset 0x131, CSR Addr 0x54098, Direction=N/A + + uint8_t Reserved132; // Byte offset 0x132, CSR Addr 0x54099, Direction=N/A + + uint8_t Reserved133; // Byte offset 0x133, CSR Addr 0x54099, Direction=N/A + + uint8_t Reserved134; // Byte offset 0x134, CSR Addr 0x5409a, Direction=N/A + + uint8_t Reserved135; // Byte offset 0x135, CSR Addr 0x5409a, Direction=N/A + + uint8_t Reserved136; // Byte offset 0x136, CSR Addr 0x5409b, Direction=N/A + + uint8_t Reserved137; // Byte offset 0x137, CSR Addr 0x5409b, Direction=N/A + + uint8_t Reserved138; // Byte offset 0x138, CSR Addr 0x5409c, Direction=N/A + + uint8_t Reserved139; // Byte offset 0x139, CSR Addr 0x5409c, Direction=N/A + + uint8_t Reserved13A; // Byte offset 0x13a, CSR Addr 0x5409d, Direction=N/A + + uint8_t Reserved13B; // Byte offset 0x13b, CSR Addr 0x5409d, Direction=N/A + + uint8_t Reserved13C; // Byte offset 0x13c, CSR Addr 0x5409e, Direction=N/A + + uint8_t Reserved13D; // Byte offset 0x13d, CSR Addr 0x5409e, Direction=N/A + + uint8_t Reserved13E; // Byte offset 0x13e, CSR Addr 0x5409f, Direction=N/A + + uint8_t Reserved13F; // Byte offset 0x13f, CSR Addr 0x5409f, Direction=N/A + + uint8_t Reserved140; // Byte offset 0x140, CSR Addr 0x540a0, Direction=N/A + + uint8_t Reserved141; // Byte offset 0x141, CSR Addr 0x540a0, Direction=N/A + + uint8_t Reserved142; // Byte offset 0x142, CSR Addr 0x540a1, Direction=N/A + + uint8_t Reserved143; // Byte offset 0x143, CSR Addr 0x540a1, Direction=N/A + + uint8_t Reserved144; // Byte offset 0x144, CSR Addr 0x540a2, Direction=N/A + + uint8_t Reserved145; // Byte offset 0x145, CSR Addr 0x540a2, Direction=N/A + + uint8_t Reserved146; // Byte offset 0x146, CSR Addr 0x540a3, Direction=N/A + + uint8_t Reserved147; // Byte offset 0x147, CSR Addr 0x540a3, Direction=N/A + + uint8_t Reserved148; // Byte offset 0x148, CSR Addr 0x540a4, Direction=N/A + + uint8_t Reserved149; // Byte offset 0x149, CSR Addr 0x540a4, Direction=N/A + + uint8_t Reserved14A; // Byte offset 0x14a, CSR Addr 0x540a5, Direction=N/A + + uint8_t Reserved14B; // Byte offset 0x14b, CSR Addr 0x540a5, Direction=N/A + + uint8_t Reserved14C; // Byte offset 0x14c, CSR Addr 0x540a6, Direction=N/A + + uint8_t Reserved14D; // Byte offset 0x14d, CSR Addr 0x540a6, Direction=N/A + + uint8_t Reserved14E; // Byte offset 0x14e, CSR Addr 0x540a7, Direction=N/A + + uint8_t Reserved14F; // Byte offset 0x14f, CSR Addr 0x540a7, Direction=N/A + + uint8_t Reserved150; // Byte offset 0x150, CSR Addr 0x540a8, Direction=N/A + + uint8_t Reserved151; // Byte offset 0x151, CSR Addr 0x540a8, Direction=N/A + + uint8_t Reserved152; // Byte offset 0x152, CSR Addr 0x540a9, Direction=N/A + + uint8_t Reserved153; // Byte offset 0x153, CSR Addr 0x540a9, Direction=N/A + + uint8_t Reserved154; // Byte offset 0x154, CSR Addr 0x540aa, Direction=N/A + + uint8_t Reserved155; // Byte offset 0x155, CSR Addr 0x540aa, Direction=N/A + + uint8_t Reserved156; // Byte offset 0x156, CSR Addr 0x540ab, Direction=N/A + + uint8_t Reserved157; // Byte offset 0x157, CSR Addr 0x540ab, Direction=N/A + + uint8_t Reserved158; // Byte offset 0x158, CSR Addr 0x540ac, Direction=N/A + + uint8_t Reserved159; // Byte offset 0x159, CSR Addr 0x540ac, Direction=N/A + + uint8_t Reserved15A; // Byte offset 0x15a, CSR Addr 0x540ad, Direction=N/A + + uint8_t Reserved15B; // Byte offset 0x15b, CSR Addr 0x540ad, Direction=N/A + + uint8_t Reserved15C; // Byte offset 0x15c, CSR Addr 0x540ae, Direction=N/A + + uint8_t Reserved15D; // Byte offset 0x15d, CSR Addr 0x540ae, Direction=N/A + + uint8_t Reserved15E; // Byte offset 0x15e, CSR Addr 0x540af, Direction=N/A + + uint8_t Reserved15F; // Byte offset 0x15f, CSR Addr 0x540af, Direction=N/A + + uint8_t Reserved160; // Byte offset 0x160, CSR Addr 0x540b0, Direction=N/A + + uint8_t Reserved161; // Byte offset 0x161, CSR Addr 0x540b0, Direction=N/A + + uint8_t Reserved162; // Byte offset 0x162, CSR Addr 0x540b1, Direction=N/A + + uint8_t Reserved163; // Byte offset 0x163, CSR Addr 0x540b1, Direction=N/A + + uint8_t Reserved164; // Byte offset 0x164, CSR Addr 0x540b2, Direction=N/A + + uint8_t Reserved165; // Byte offset 0x165, CSR Addr 0x540b2, Direction=N/A + + uint8_t Reserved166; // Byte offset 0x166, CSR Addr 0x540b3, Direction=N/A + + uint8_t Reserved167; // Byte offset 0x167, CSR Addr 0x540b3, Direction=N/A + + uint8_t Reserved168; // Byte offset 0x168, CSR Addr 0x540b4, Direction=N/A + + uint8_t Reserved169; // Byte offset 0x169, CSR Addr 0x540b4, Direction=N/A + + uint8_t Reserved16A; // Byte offset 0x16a, CSR Addr 0x540b5, Direction=N/A + + uint8_t Reserved16B; // Byte offset 0x16b, CSR Addr 0x540b5, Direction=N/A + + uint8_t Reserved16C; // Byte offset 0x16c, CSR Addr 0x540b6, Direction=N/A + + uint8_t Reserved16D; // Byte offset 0x16d, CSR Addr 0x540b6, Direction=N/A + + uint8_t Reserved16E; // Byte offset 0x16e, CSR Addr 0x540b7, Direction=N/A + + uint8_t Reserved16F; // Byte offset 0x16f, CSR Addr 0x540b7, Direction=N/A + + uint8_t Reserved170; // Byte offset 0x170, CSR Addr 0x540b8, Direction=N/A + + uint8_t Reserved171; // Byte offset 0x171, CSR Addr 0x540b8, Direction=N/A + + uint8_t Reserved172; // Byte offset 0x172, CSR Addr 0x540b9, Direction=N/A + + uint8_t Reserved173; // Byte offset 0x173, CSR Addr 0x540b9, Direction=N/A + + uint8_t Reserved174; // Byte offset 0x174, CSR Addr 0x540ba, Direction=N/A + + uint8_t Reserved175; // Byte offset 0x175, CSR Addr 0x540ba, Direction=N/A + + uint8_t Reserved176; // Byte offset 0x176, CSR Addr 0x540bb, Direction=N/A + + uint8_t Reserved177; // Byte offset 0x177, CSR Addr 0x540bb, Direction=N/A + + uint8_t Reserved178; // Byte offset 0x178, CSR Addr 0x540bc, Direction=N/A + + uint8_t Reserved179; // Byte offset 0x179, CSR Addr 0x540bc, Direction=N/A + + uint8_t Reserved17A; // Byte offset 0x17a, CSR Addr 0x540bd, Direction=N/A + + uint8_t Reserved17B; // Byte offset 0x17b, CSR Addr 0x540bd, Direction=N/A + + uint8_t Reserved17C; // Byte offset 0x17c, CSR Addr 0x540be, Direction=N/A + + uint8_t Reserved17D; // Byte offset 0x17d, CSR Addr 0x540be, Direction=N/A + + uint8_t Reserved17E; // Byte offset 0x17e, CSR Addr 0x540bf, Direction=N/A + + uint8_t Reserved17F; // Byte offset 0x17f, CSR Addr 0x540bf, Direction=N/A + + uint8_t Reserved180; // Byte offset 0x180, CSR Addr 0x540c0, Direction=N/A + + uint8_t Reserved181; // Byte offset 0x181, CSR Addr 0x540c0, Direction=N/A + + uint8_t Reserved182; // Byte offset 0x182, CSR Addr 0x540c1, Direction=N/A + + uint8_t Reserved183; // Byte offset 0x183, CSR Addr 0x540c1, Direction=N/A + + uint8_t Reserved184; // Byte offset 0x184, CSR Addr 0x540c2, Direction=N/A + + uint8_t Reserved185; // Byte offset 0x185, CSR Addr 0x540c2, Direction=N/A + + uint8_t Reserved186; // Byte offset 0x186, CSR Addr 0x540c3, Direction=N/A + + uint8_t Reserved187; // Byte offset 0x187, CSR Addr 0x540c3, Direction=N/A + + uint8_t Reserved188; // Byte offset 0x188, CSR Addr 0x540c4, Direction=N/A + + uint8_t Reserved189; // Byte offset 0x189, CSR Addr 0x540c4, Direction=N/A + + uint8_t Reserved18A; // Byte offset 0x18a, CSR Addr 0x540c5, Direction=N/A + + uint8_t Reserved18B; // Byte offset 0x18b, CSR Addr 0x540c5, Direction=N/A + + uint8_t Reserved18C; // Byte offset 0x18c, CSR Addr 0x540c6, Direction=N/A + + uint8_t Reserved18D; // Byte offset 0x18d, CSR Addr 0x540c6, Direction=N/A + + uint8_t Reserved18E; // Byte offset 0x18e, CSR Addr 0x540c7, Direction=N/A + + uint8_t Reserved18F; // Byte offset 0x18f, CSR Addr 0x540c7, Direction=N/A + + uint8_t Reserved190; // Byte offset 0x190, CSR Addr 0x540c8, Direction=N/A + + uint8_t Reserved191; // Byte offset 0x191, CSR Addr 0x540c8, Direction=N/A + + uint8_t Reserved192; // Byte offset 0x192, CSR Addr 0x540c9, Direction=N/A + + uint8_t Reserved193; // Byte offset 0x193, CSR Addr 0x540c9, Direction=N/A + + uint8_t Reserved194; // Byte offset 0x194, CSR Addr 0x540ca, Direction=N/A + + uint8_t Reserved195; // Byte offset 0x195, CSR Addr 0x540ca, Direction=N/A + + uint8_t Reserved196; // Byte offset 0x196, CSR Addr 0x540cb, Direction=N/A + + uint8_t Reserved197; // Byte offset 0x197, CSR Addr 0x540cb, Direction=N/A + + uint8_t Reserved198; // Byte offset 0x198, CSR Addr 0x540cc, Direction=N/A + + uint8_t Reserved199; // Byte offset 0x199, CSR Addr 0x540cc, Direction=N/A + + uint8_t Reserved19A; // Byte offset 0x19a, CSR Addr 0x540cd, Direction=N/A + + uint8_t Reserved19B; // Byte offset 0x19b, CSR Addr 0x540cd, Direction=N/A + + uint8_t Reserved19C; // Byte offset 0x19c, CSR Addr 0x540ce, Direction=N/A + + uint8_t Reserved19D; // Byte offset 0x19d, CSR Addr 0x540ce, Direction=N/A + + uint8_t Reserved19E; // Byte offset 0x19e, CSR Addr 0x540cf, Direction=N/A + + uint8_t Reserved19F; // Byte offset 0x19f, CSR Addr 0x540cf, Direction=N/A + + uint8_t Reserved1A0; // Byte offset 0x1a0, CSR Addr 0x540d0, Direction=N/A + + uint8_t Reserved1A1; // Byte offset 0x1a1, CSR Addr 0x540d0, Direction=N/A + + uint8_t Reserved1A2; // Byte offset 0x1a2, CSR Addr 0x540d1, Direction=N/A + + uint8_t Reserved1A3; // Byte offset 0x1a3, CSR Addr 0x540d1, Direction=N/A + + uint8_t Reserved1A4; // Byte offset 0x1a4, CSR Addr 0x540d2, Direction=N/A + + uint8_t Reserved1A5; // Byte offset 0x1a5, CSR Addr 0x540d2, Direction=N/A + + uint8_t Reserved1A6; // Byte offset 0x1a6, CSR Addr 0x540d3, Direction=N/A + + uint8_t Reserved1A7; // Byte offset 0x1a7, CSR Addr 0x540d3, Direction=N/A + + uint8_t Reserved1A8; // Byte offset 0x1a8, CSR Addr 0x540d4, Direction=N/A + + uint8_t Reserved1A9; // Byte offset 0x1a9, CSR Addr 0x540d4, Direction=N/A + + uint8_t Reserved1AA; // Byte offset 0x1aa, CSR Addr 0x540d5, Direction=N/A + + uint8_t Reserved1AB; // Byte offset 0x1ab, CSR Addr 0x540d5, Direction=N/A + + uint8_t Reserved1AC; // Byte offset 0x1ac, CSR Addr 0x540d6, Direction=N/A + + uint8_t Reserved1AD; // Byte offset 0x1ad, CSR Addr 0x540d6, Direction=N/A + + uint8_t Reserved1AE; // Byte offset 0x1ae, CSR Addr 0x540d7, Direction=N/A + + uint8_t Reserved1AF; // Byte offset 0x1af, CSR Addr 0x540d7, Direction=N/A + + uint8_t Reserved1B0; // Byte offset 0x1b0, CSR Addr 0x540d8, Direction=N/A + + uint8_t Reserved1B1; // Byte offset 0x1b1, CSR Addr 0x540d8, Direction=N/A + + uint8_t Reserved1B2; // Byte offset 0x1b2, CSR Addr 0x540d9, Direction=N/A + + uint8_t Reserved1B3; // Byte offset 0x1b3, CSR Addr 0x540d9, Direction=N/A + + uint8_t Reserved1B4; // Byte offset 0x1b4, CSR Addr 0x540da, Direction=N/A + + uint8_t Reserved1B5; // Byte offset 0x1b5, CSR Addr 0x540da, Direction=N/A + + uint8_t Reserved1B6; // Byte offset 0x1b6, CSR Addr 0x540db, Direction=N/A + + uint8_t Reserved1B7; // Byte offset 0x1b7, CSR Addr 0x540db, Direction=N/A + + uint8_t Reserved1B8; // Byte offset 0x1b8, CSR Addr 0x540dc, Direction=N/A + + uint8_t Reserved1B9; // Byte offset 0x1b9, CSR Addr 0x540dc, Direction=N/A + + uint8_t Reserved1BA; // Byte offset 0x1ba, CSR Addr 0x540dd, Direction=N/A + + uint8_t Reserved1BB; // Byte offset 0x1bb, CSR Addr 0x540dd, Direction=N/A + + uint8_t Reserved1BC; // Byte offset 0x1bc, CSR Addr 0x540de, Direction=N/A + + uint8_t Reserved1BD; // Byte offset 0x1bd, CSR Addr 0x540de, Direction=N/A + + uint8_t Reserved1BE; // Byte offset 0x1be, CSR Addr 0x540df, Direction=N/A + + uint8_t Reserved1BF; // Byte offset 0x1bf, CSR Addr 0x540df, Direction=N/A + + uint8_t Reserved1C0; // Byte offset 0x1c0, CSR Addr 0x540e0, Direction=N/A + + uint8_t Reserved1C1; // Byte offset 0x1c1, CSR Addr 0x540e0, Direction=N/A + + uint8_t Reserved1C2; // Byte offset 0x1c2, CSR Addr 0x540e1, Direction=N/A + + uint8_t Reserved1C3; // Byte offset 0x1c3, CSR Addr 0x540e1, Direction=N/A + + uint8_t Reserved1C4; // Byte offset 0x1c4, CSR Addr 0x540e2, Direction=N/A + + uint8_t Reserved1C5; // Byte offset 0x1c5, CSR Addr 0x540e2, Direction=N/A + + uint8_t Reserved1C6; // Byte offset 0x1c6, CSR Addr 0x540e3, Direction=N/A + + uint8_t Reserved1C7; // Byte offset 0x1c7, CSR Addr 0x540e3, Direction=N/A + + uint8_t Reserved1C8; // Byte offset 0x1c8, CSR Addr 0x540e4, Direction=N/A + + uint8_t Reserved1C9; // Byte offset 0x1c9, CSR Addr 0x540e4, Direction=N/A + + uint8_t Reserved1CA; // Byte offset 0x1ca, CSR Addr 0x540e5, Direction=N/A + + uint8_t Reserved1CB; // Byte offset 0x1cb, CSR Addr 0x540e5, Direction=N/A + + uint8_t Reserved1CC; // Byte offset 0x1cc, CSR Addr 0x540e6, Direction=N/A + + uint8_t Reserved1CD; // Byte offset 0x1cd, CSR Addr 0x540e6, Direction=N/A + + uint8_t Reserved1CE; // Byte offset 0x1ce, CSR Addr 0x540e7, Direction=N/A + + uint8_t Reserved1CF; // Byte offset 0x1cf, CSR Addr 0x540e7, Direction=N/A + + uint8_t Reserved1D0; // Byte offset 0x1d0, CSR Addr 0x540e8, Direction=N/A + + uint8_t Reserved1D1; // Byte offset 0x1d1, CSR Addr 0x540e8, Direction=N/A + + uint8_t Reserved1D2; // Byte offset 0x1d2, CSR Addr 0x540e9, Direction=N/A + + uint8_t Reserved1D3; // Byte offset 0x1d3, CSR Addr 0x540e9, Direction=N/A + + uint8_t Reserved1D4; // Byte offset 0x1d4, CSR Addr 0x540ea, Direction=N/A + + uint8_t Reserved1D5; // Byte offset 0x1d5, CSR Addr 0x540ea, Direction=N/A + + uint8_t Reserved1D6; // Byte offset 0x1d6, CSR Addr 0x540eb, Direction=N/A + + uint8_t Reserved1D7; // Byte offset 0x1d7, CSR Addr 0x540eb, Direction=N/A + + uint8_t Reserved1D8; // Byte offset 0x1d8, CSR Addr 0x540ec, Direction=N/A + + uint8_t Reserved1D9; // Byte offset 0x1d9, CSR Addr 0x540ec, Direction=N/A + + uint8_t Reserved1DA; // Byte offset 0x1da, CSR Addr 0x540ed, Direction=N/A + + uint8_t Reserved1DB; // Byte offset 0x1db, CSR Addr 0x540ed, Direction=N/A + + uint8_t Reserved1DC; // Byte offset 0x1dc, CSR Addr 0x540ee, Direction=N/A + + uint8_t Reserved1DD; // Byte offset 0x1dd, CSR Addr 0x540ee, Direction=N/A + + uint8_t Reserved1DE; // Byte offset 0x1de, CSR Addr 0x540ef, Direction=N/A + + uint8_t Reserved1DF; // Byte offset 0x1df, CSR Addr 0x540ef, Direction=N/A + + uint8_t Reserved1E0; // Byte offset 0x1e0, CSR Addr 0x540f0, Direction=N/A + + uint8_t Reserved1E1; // Byte offset 0x1e1, CSR Addr 0x540f0, Direction=N/A + + uint8_t Reserved1E2; // Byte offset 0x1e2, CSR Addr 0x540f1, Direction=N/A + + uint8_t Reserved1E3; // Byte offset 0x1e3, CSR Addr 0x540f1, Direction=N/A + + uint8_t Reserved1E4; // Byte offset 0x1e4, CSR Addr 0x540f2, Direction=N/A + + uint8_t Reserved1E5; // Byte offset 0x1e5, CSR Addr 0x540f2, Direction=N/A + + uint8_t Reserved1E6; // Byte offset 0x1e6, CSR Addr 0x540f3, Direction=N/A + + uint8_t Reserved1E7; // Byte offset 0x1e7, CSR Addr 0x540f3, Direction=N/A + + uint8_t Reserved1E8; // Byte offset 0x1e8, CSR Addr 0x540f4, Direction=N/A + + uint8_t Reserved1E9; // Byte offset 0x1e9, CSR Addr 0x540f4, Direction=N/A + + uint8_t Reserved1EA; // Byte offset 0x1ea, CSR Addr 0x540f5, Direction=N/A + + uint8_t Reserved1EB; // Byte offset 0x1eb, CSR Addr 0x540f5, Direction=N/A + + uint8_t Reserved1EC; // Byte offset 0x1ec, CSR Addr 0x540f6, Direction=N/A + + uint8_t Reserved1ED; // Byte offset 0x1ed, CSR Addr 0x540f6, Direction=N/A + + uint8_t Reserved1EE; // Byte offset 0x1ee, CSR Addr 0x540f7, Direction=N/A + + uint8_t Reserved1EF; // Byte offset 0x1ef, CSR Addr 0x540f7, Direction=N/A + + uint8_t Reserved1F0; // Byte offset 0x1f0, CSR Addr 0x540f8, Direction=N/A + + uint8_t Reserved1F1; // Byte offset 0x1f1, CSR Addr 0x540f8, Direction=N/A + + uint8_t Reserved1F2; // Byte offset 0x1f2, CSR Addr 0x540f9, Direction=N/A + + uint8_t Reserved1F3; // Byte offset 0x1f3, CSR Addr 0x540f9, Direction=N/A + + uint8_t Reserved1F4; // Byte offset 0x1f4, CSR Addr 0x540fa, Direction=N/A + + uint8_t Reserved1F5; // Byte offset 0x1f5, CSR Addr 0x540fa, Direction=N/A + + uint8_t Reserved1F6; // Byte offset 0x1f6, CSR Addr 0x540fb, Direction=N/A + + uint8_t Reserved1F7; // Byte offset 0x1f7, CSR Addr 0x540fb, Direction=N/A + + uint8_t Reserved1F8; // Byte offset 0x1f8, CSR Addr 0x540fc, Direction=N/A + + uint8_t Reserved1F9; // Byte offset 0x1f9, CSR Addr 0x540fc, Direction=N/A + + uint8_t Reserved1FA; // Byte offset 0x1fa, CSR Addr 0x540fd, Direction=N/A + + uint8_t Reserved1FB; // Byte offset 0x1fb, CSR Addr 0x540fd, Direction=N/A + + uint8_t Reserved1FC; // Byte offset 0x1fc, CSR Addr 0x540fe, Direction=N/A + + uint8_t Reserved1FD; // Byte offset 0x1fd, CSR Addr 0x540fe, Direction=N/A + + uint8_t Reserved1FE; // Byte offset 0x1fe, CSR Addr 0x540ff, Direction=N/A + + uint8_t Reserved1FF; // Byte offset 0x1ff, CSR Addr 0x540ff, Direction=N/A + + uint8_t Reserved200; // Byte offset 0x200, CSR Addr 0x54100, Direction=N/A + + uint8_t Reserved201; // Byte offset 0x201, CSR Addr 0x54100, Direction=N/A + + uint8_t Reserved202; // Byte offset 0x202, CSR Addr 0x54101, Direction=N/A + + uint8_t Reserved203; // Byte offset 0x203, CSR Addr 0x54101, Direction=N/A + + uint8_t Reserved204; // Byte offset 0x204, CSR Addr 0x54102, Direction=N/A + + uint8_t Reserved205; // Byte offset 0x205, CSR Addr 0x54102, Direction=N/A + + uint8_t Reserved206; // Byte offset 0x206, CSR Addr 0x54103, Direction=N/A + + uint8_t Reserved207; // Byte offset 0x207, CSR Addr 0x54103, Direction=N/A + + uint8_t Reserved208; // Byte offset 0x208, CSR Addr 0x54104, Direction=N/A + + uint8_t Reserved209; // Byte offset 0x209, CSR Addr 0x54104, Direction=N/A + + uint8_t Reserved20A; // Byte offset 0x20a, CSR Addr 0x54105, Direction=N/A + + uint8_t Reserved20B; // Byte offset 0x20b, CSR Addr 0x54105, Direction=N/A + + uint8_t Reserved20C; // Byte offset 0x20c, CSR Addr 0x54106, Direction=N/A + + uint8_t Reserved20D; // Byte offset 0x20d, CSR Addr 0x54106, Direction=N/A + + uint8_t Reserved20E; // Byte offset 0x20e, CSR Addr 0x54107, Direction=N/A + + uint8_t Reserved20F; // Byte offset 0x20f, CSR Addr 0x54107, Direction=N/A + + uint8_t Reserved210; // Byte offset 0x210, CSR Addr 0x54108, Direction=N/A + + uint8_t Reserved211; // Byte offset 0x211, CSR Addr 0x54108, Direction=N/A + + uint8_t Reserved212; // Byte offset 0x212, CSR Addr 0x54109, Direction=N/A + + uint8_t Reserved213; // Byte offset 0x213, CSR Addr 0x54109, Direction=N/A + + uint8_t Reserved214; // Byte offset 0x214, CSR Addr 0x5410a, Direction=N/A + + uint8_t Reserved215; // Byte offset 0x215, CSR Addr 0x5410a, Direction=N/A + + uint8_t Reserved216; // Byte offset 0x216, CSR Addr 0x5410b, Direction=N/A + + uint8_t Reserved217; // Byte offset 0x217, CSR Addr 0x5410b, Direction=N/A + + uint8_t Reserved218; // Byte offset 0x218, CSR Addr 0x5410c, Direction=N/A + + uint8_t Reserved219; // Byte offset 0x219, CSR Addr 0x5410c, Direction=N/A + + uint8_t Reserved21A; // Byte offset 0x21a, CSR Addr 0x5410d, Direction=N/A + + uint8_t Reserved21B; // Byte offset 0x21b, CSR Addr 0x5410d, Direction=N/A + + uint8_t Reserved21C; // Byte offset 0x21c, CSR Addr 0x5410e, Direction=N/A + + uint8_t Reserved21D; // Byte offset 0x21d, CSR Addr 0x5410e, Direction=N/A + + uint8_t Reserved21E; // Byte offset 0x21e, CSR Addr 0x5410f, Direction=N/A + + uint8_t Reserved21F; // Byte offset 0x21f, CSR Addr 0x5410f, Direction=N/A + + uint8_t Reserved220; // Byte offset 0x220, CSR Addr 0x54110, Direction=N/A + + uint8_t Reserved221; // Byte offset 0x221, CSR Addr 0x54110, Direction=N/A + + uint8_t Reserved222; // Byte offset 0x222, CSR Addr 0x54111, Direction=N/A + + uint8_t Reserved223; // Byte offset 0x223, CSR Addr 0x54111, Direction=N/A + + uint8_t Reserved224; // Byte offset 0x224, CSR Addr 0x54112, Direction=N/A + + uint8_t Reserved225; // Byte offset 0x225, CSR Addr 0x54112, Direction=N/A + + uint8_t Reserved226; // Byte offset 0x226, CSR Addr 0x54113, Direction=N/A + + uint8_t Reserved227; // Byte offset 0x227, CSR Addr 0x54113, Direction=N/A + + uint8_t Reserved228; // Byte offset 0x228, CSR Addr 0x54114, Direction=N/A + + uint8_t Reserved229; // Byte offset 0x229, CSR Addr 0x54114, Direction=N/A + + uint8_t Reserved22A; // Byte offset 0x22a, CSR Addr 0x54115, Direction=N/A + + uint8_t Reserved22B; // Byte offset 0x22b, CSR Addr 0x54115, Direction=N/A + + uint8_t Reserved22C; // Byte offset 0x22c, CSR Addr 0x54116, Direction=N/A + + uint8_t Reserved22D; // Byte offset 0x22d, CSR Addr 0x54116, Direction=N/A + + uint8_t Reserved22E; // Byte offset 0x22e, CSR Addr 0x54117, Direction=N/A + + uint8_t Reserved22F; // Byte offset 0x22f, CSR Addr 0x54117, Direction=N/A + + uint8_t Reserved230; // Byte offset 0x230, CSR Addr 0x54118, Direction=N/A + + uint8_t Reserved231; // Byte offset 0x231, CSR Addr 0x54118, Direction=N/A + + uint8_t Reserved232; // Byte offset 0x232, CSR Addr 0x54119, Direction=N/A + + uint8_t Reserved233; // Byte offset 0x233, CSR Addr 0x54119, Direction=N/A + + uint8_t Reserved234; // Byte offset 0x234, CSR Addr 0x5411a, Direction=N/A + + uint8_t Reserved235; // Byte offset 0x235, CSR Addr 0x5411a, Direction=N/A + + uint8_t Reserved236; // Byte offset 0x236, CSR Addr 0x5411b, Direction=N/A + + uint8_t Reserved237; // Byte offset 0x237, CSR Addr 0x5411b, Direction=N/A + + uint8_t Reserved238; // Byte offset 0x238, CSR Addr 0x5411c, Direction=N/A + + uint8_t Reserved239; // Byte offset 0x239, CSR Addr 0x5411c, Direction=N/A + + uint8_t Reserved23A; // Byte offset 0x23a, CSR Addr 0x5411d, Direction=N/A + + uint8_t Reserved23B; // Byte offset 0x23b, CSR Addr 0x5411d, Direction=N/A + + uint8_t Reserved23C; // Byte offset 0x23c, CSR Addr 0x5411e, Direction=N/A + + uint8_t Reserved23D; // Byte offset 0x23d, CSR Addr 0x5411e, Direction=N/A + + uint8_t Reserved23E; // Byte offset 0x23e, CSR Addr 0x5411f, Direction=N/A + + uint8_t Reserved23F; // Byte offset 0x23f, CSR Addr 0x5411f, Direction=N/A + + uint8_t Reserved240; // Byte offset 0x240, CSR Addr 0x54120, Direction=N/A + + uint8_t Reserved241; // Byte offset 0x241, CSR Addr 0x54120, Direction=N/A + + uint8_t Reserved242; // Byte offset 0x242, CSR Addr 0x54121, Direction=N/A + + uint8_t Reserved243; // Byte offset 0x243, CSR Addr 0x54121, Direction=N/A + + uint8_t Reserved244; // Byte offset 0x244, CSR Addr 0x54122, Direction=N/A + + uint8_t Reserved245; // Byte offset 0x245, CSR Addr 0x54122, Direction=N/A + + uint8_t Reserved246; // Byte offset 0x246, CSR Addr 0x54123, Direction=N/A + + uint8_t Reserved247; // Byte offset 0x247, CSR Addr 0x54123, Direction=N/A + + uint8_t Reserved248; // Byte offset 0x248, CSR Addr 0x54124, Direction=N/A + + uint8_t Reserved249; // Byte offset 0x249, CSR Addr 0x54124, Direction=N/A + + uint8_t Reserved24A; // Byte offset 0x24a, CSR Addr 0x54125, Direction=N/A + + uint8_t Reserved24B; // Byte offset 0x24b, CSR Addr 0x54125, Direction=N/A + + uint8_t Reserved24C; // Byte offset 0x24c, CSR Addr 0x54126, Direction=N/A + + uint8_t Reserved24D; // Byte offset 0x24d, CSR Addr 0x54126, Direction=N/A + + uint8_t Reserved24E; // Byte offset 0x24e, CSR Addr 0x54127, Direction=N/A + + uint8_t Reserved24F; // Byte offset 0x24f, CSR Addr 0x54127, Direction=N/A + + uint8_t Reserved250; // Byte offset 0x250, CSR Addr 0x54128, Direction=N/A + + uint8_t Reserved251; // Byte offset 0x251, CSR Addr 0x54128, Direction=N/A + + uint8_t Reserved252; // Byte offset 0x252, CSR Addr 0x54129, Direction=N/A + + uint8_t Reserved253; // Byte offset 0x253, CSR Addr 0x54129, Direction=N/A + + uint8_t Reserved254; // Byte offset 0x254, CSR Addr 0x5412a, Direction=N/A + + uint8_t Reserved255; // Byte offset 0x255, CSR Addr 0x5412a, Direction=N/A + + uint8_t Reserved256; // Byte offset 0x256, CSR Addr 0x5412b, Direction=N/A + + uint8_t Reserved257; // Byte offset 0x257, CSR Addr 0x5412b, Direction=N/A + + uint8_t Reserved258; // Byte offset 0x258, CSR Addr 0x5412c, Direction=N/A + + uint8_t Reserved259; // Byte offset 0x259, CSR Addr 0x5412c, Direction=N/A + + uint8_t Reserved25A; // Byte offset 0x25a, CSR Addr 0x5412d, Direction=N/A + + uint8_t Reserved25B; // Byte offset 0x25b, CSR Addr 0x5412d, Direction=N/A + + uint8_t Reserved25C; // Byte offset 0x25c, CSR Addr 0x5412e, Direction=N/A + + uint8_t Reserved25D; // Byte offset 0x25d, CSR Addr 0x5412e, Direction=N/A + + uint8_t Reserved25E; // Byte offset 0x25e, CSR Addr 0x5412f, Direction=N/A + + uint8_t Reserved25F; // Byte offset 0x25f, CSR Addr 0x5412f, Direction=N/A + + uint8_t Reserved260; // Byte offset 0x260, CSR Addr 0x54130, Direction=N/A + + uint8_t Reserved261; // Byte offset 0x261, CSR Addr 0x54130, Direction=N/A + + uint8_t Reserved262; // Byte offset 0x262, CSR Addr 0x54131, Direction=N/A + + uint8_t Reserved263; // Byte offset 0x263, CSR Addr 0x54131, Direction=N/A + + uint8_t Reserved264; // Byte offset 0x264, CSR Addr 0x54132, Direction=N/A + + uint8_t Reserved265; // Byte offset 0x265, CSR Addr 0x54132, Direction=N/A + + uint8_t Reserved266; // Byte offset 0x266, CSR Addr 0x54133, Direction=N/A + + uint8_t Reserved267; // Byte offset 0x267, CSR Addr 0x54133, Direction=N/A + + uint8_t Reserved268; // Byte offset 0x268, CSR Addr 0x54134, Direction=N/A + + uint8_t Reserved269; // Byte offset 0x269, CSR Addr 0x54134, Direction=N/A + + uint8_t Reserved26A; // Byte offset 0x26a, CSR Addr 0x54135, Direction=N/A + + uint8_t Reserved26B; // Byte offset 0x26b, CSR Addr 0x54135, Direction=N/A + + uint8_t Reserved26C; // Byte offset 0x26c, CSR Addr 0x54136, Direction=N/A + + uint8_t Reserved26D; // Byte offset 0x26d, CSR Addr 0x54136, Direction=N/A + + uint8_t Reserved26E; // Byte offset 0x26e, CSR Addr 0x54137, Direction=N/A + + uint8_t Reserved26F; // Byte offset 0x26f, CSR Addr 0x54137, Direction=N/A + + uint8_t Reserved270; // Byte offset 0x270, CSR Addr 0x54138, Direction=N/A + + uint8_t Reserved271; // Byte offset 0x271, CSR Addr 0x54138, Direction=N/A + + uint8_t Reserved272; // Byte offset 0x272, CSR Addr 0x54139, Direction=N/A + + uint8_t Reserved273; // Byte offset 0x273, CSR Addr 0x54139, Direction=N/A + + uint8_t Reserved274; // Byte offset 0x274, CSR Addr 0x5413a, Direction=N/A + + uint8_t Reserved275; // Byte offset 0x275, CSR Addr 0x5413a, Direction=N/A + + uint8_t Reserved276; // Byte offset 0x276, CSR Addr 0x5413b, Direction=N/A + + uint8_t Reserved277; // Byte offset 0x277, CSR Addr 0x5413b, Direction=N/A + + uint8_t Reserved278; // Byte offset 0x278, CSR Addr 0x5413c, Direction=N/A + + uint8_t Reserved279; // Byte offset 0x279, CSR Addr 0x5413c, Direction=N/A + + uint8_t Reserved27A; // Byte offset 0x27a, CSR Addr 0x5413d, Direction=N/A + + uint8_t Reserved27B; // Byte offset 0x27b, CSR Addr 0x5413d, Direction=N/A + + uint8_t Reserved27C; // Byte offset 0x27c, CSR Addr 0x5413e, Direction=N/A + + uint8_t Reserved27D; // Byte offset 0x27d, CSR Addr 0x5413e, Direction=N/A + + uint8_t Reserved27E; // Byte offset 0x27e, CSR Addr 0x5413f, Direction=N/A + + uint8_t Reserved27F; // Byte offset 0x27f, CSR Addr 0x5413f, Direction=N/A + + uint8_t Reserved280; // Byte offset 0x280, CSR Addr 0x54140, Direction=N/A + + uint8_t Reserved281; // Byte offset 0x281, CSR Addr 0x54140, Direction=N/A + + uint8_t Reserved282; // Byte offset 0x282, CSR Addr 0x54141, Direction=N/A + + uint8_t Reserved283; // Byte offset 0x283, CSR Addr 0x54141, Direction=N/A + + uint8_t Reserved284; // Byte offset 0x284, CSR Addr 0x54142, Direction=N/A + + uint8_t Reserved285; // Byte offset 0x285, CSR Addr 0x54142, Direction=N/A + + uint8_t Reserved286; // Byte offset 0x286, CSR Addr 0x54143, Direction=N/A + + uint8_t Reserved287; // Byte offset 0x287, CSR Addr 0x54143, Direction=N/A + + uint8_t Reserved288; // Byte offset 0x288, CSR Addr 0x54144, Direction=N/A + + uint8_t Reserved289; // Byte offset 0x289, CSR Addr 0x54144, Direction=N/A + + uint8_t Reserved28A; // Byte offset 0x28a, CSR Addr 0x54145, Direction=N/A + + uint8_t Reserved28B; // Byte offset 0x28b, CSR Addr 0x54145, Direction=N/A + + uint8_t Reserved28C; // Byte offset 0x28c, CSR Addr 0x54146, Direction=N/A + + uint8_t Reserved28D; // Byte offset 0x28d, CSR Addr 0x54146, Direction=N/A + + uint8_t Reserved28E; // Byte offset 0x28e, CSR Addr 0x54147, Direction=N/A + + uint8_t Reserved28F; // Byte offset 0x28f, CSR Addr 0x54147, Direction=N/A + + uint8_t Reserved290; // Byte offset 0x290, CSR Addr 0x54148, Direction=N/A + + uint8_t Reserved291; // Byte offset 0x291, CSR Addr 0x54148, Direction=N/A + + uint8_t Reserved292; // Byte offset 0x292, CSR Addr 0x54149, Direction=N/A + + uint8_t Reserved293; // Byte offset 0x293, CSR Addr 0x54149, Direction=N/A + + uint8_t Reserved294; // Byte offset 0x294, CSR Addr 0x5414a, Direction=N/A + + uint8_t Reserved295; // Byte offset 0x295, CSR Addr 0x5414a, Direction=N/A + + uint8_t Reserved296; // Byte offset 0x296, CSR Addr 0x5414b, Direction=N/A + + uint8_t Reserved297; // Byte offset 0x297, CSR Addr 0x5414b, Direction=N/A + + uint8_t Reserved298; // Byte offset 0x298, CSR Addr 0x5414c, Direction=N/A + + uint8_t Reserved299; // Byte offset 0x299, CSR Addr 0x5414c, Direction=N/A + + uint8_t Reserved29A; // Byte offset 0x29a, CSR Addr 0x5414d, Direction=N/A + + uint8_t Reserved29B; // Byte offset 0x29b, CSR Addr 0x5414d, Direction=N/A + + uint8_t Reserved29C; // Byte offset 0x29c, CSR Addr 0x5414e, Direction=N/A + + uint8_t Reserved29D; // Byte offset 0x29d, CSR Addr 0x5414e, Direction=N/A + + uint8_t Reserved29E; // Byte offset 0x29e, CSR Addr 0x5414f, Direction=N/A + + uint8_t Reserved29F; // Byte offset 0x29f, CSR Addr 0x5414f, Direction=N/A + + uint8_t Reserved2A0; // Byte offset 0x2a0, CSR Addr 0x54150, Direction=N/A + + uint8_t Reserved2A1; // Byte offset 0x2a1, CSR Addr 0x54150, Direction=N/A + + uint8_t Reserved2A2; // Byte offset 0x2a2, CSR Addr 0x54151, Direction=N/A + + uint8_t Reserved2A3; // Byte offset 0x2a3, CSR Addr 0x54151, Direction=N/A + + uint8_t Reserved2A4; // Byte offset 0x2a4, CSR Addr 0x54152, Direction=N/A + + uint8_t Reserved2A5; // Byte offset 0x2a5, CSR Addr 0x54152, Direction=N/A + + uint8_t Reserved2A6; // Byte offset 0x2a6, CSR Addr 0x54153, Direction=N/A + + uint8_t Reserved2A7; // Byte offset 0x2a7, CSR Addr 0x54153, Direction=N/A + + uint8_t Reserved2A8; // Byte offset 0x2a8, CSR Addr 0x54154, Direction=N/A + + uint8_t Reserved2A9; // Byte offset 0x2a9, CSR Addr 0x54154, Direction=N/A + + uint8_t Reserved2AA; // Byte offset 0x2aa, CSR Addr 0x54155, Direction=N/A + + uint8_t Reserved2AB; // Byte offset 0x2ab, CSR Addr 0x54155, Direction=N/A + + uint8_t Reserved2AC; // Byte offset 0x2ac, CSR Addr 0x54156, Direction=N/A + + uint8_t Reserved2AD; // Byte offset 0x2ad, CSR Addr 0x54156, Direction=N/A + + uint8_t Reserved2AE; // Byte offset 0x2ae, CSR Addr 0x54157, Direction=N/A + + uint8_t Reserved2AF; // Byte offset 0x2af, CSR Addr 0x54157, Direction=N/A + + uint8_t Reserved2B0; // Byte offset 0x2b0, CSR Addr 0x54158, Direction=N/A + + uint8_t Reserved2B1; // Byte offset 0x2b1, CSR Addr 0x54158, Direction=N/A + + uint8_t Reserved2B2; // Byte offset 0x2b2, CSR Addr 0x54159, Direction=N/A + + uint8_t Reserved2B3; // Byte offset 0x2b3, CSR Addr 0x54159, Direction=N/A + + uint8_t Reserved2B4; // Byte offset 0x2b4, CSR Addr 0x5415a, Direction=N/A + + uint8_t Reserved2B5; // Byte offset 0x2b5, CSR Addr 0x5415a, Direction=N/A + + uint8_t Reserved2B6; // Byte offset 0x2b6, CSR Addr 0x5415b, Direction=N/A + + uint8_t Reserved2B7; // Byte offset 0x2b7, CSR Addr 0x5415b, Direction=N/A + + uint8_t Reserved2B8; // Byte offset 0x2b8, CSR Addr 0x5415c, Direction=N/A + + uint8_t Reserved2B9; // Byte offset 0x2b9, CSR Addr 0x5415c, Direction=N/A + + uint8_t Reserved2BA; // Byte offset 0x2ba, CSR Addr 0x5415d, Direction=N/A + + uint8_t Reserved2BB; // Byte offset 0x2bb, CSR Addr 0x5415d, Direction=N/A + + uint8_t Reserved2BC; // Byte offset 0x2bc, CSR Addr 0x5415e, Direction=N/A + + uint8_t Reserved2BD; // Byte offset 0x2bd, CSR Addr 0x5415e, Direction=N/A + + uint8_t Reserved2BE; // Byte offset 0x2be, CSR Addr 0x5415f, Direction=N/A + + uint8_t Reserved2BF; // Byte offset 0x2bf, CSR Addr 0x5415f, Direction=N/A + + uint8_t Reserved2C0; // Byte offset 0x2c0, CSR Addr 0x54160, Direction=N/A + + uint8_t Reserved2C1; // Byte offset 0x2c1, CSR Addr 0x54160, Direction=N/A + + uint8_t Reserved2C2; // Byte offset 0x2c2, CSR Addr 0x54161, Direction=N/A + + uint8_t Reserved2C3; // Byte offset 0x2c3, CSR Addr 0x54161, Direction=N/A + + uint8_t Reserved2C4; // Byte offset 0x2c4, CSR Addr 0x54162, Direction=N/A + + uint8_t Reserved2C5; // Byte offset 0x2c5, CSR Addr 0x54162, Direction=N/A + + uint8_t Reserved2C6; // Byte offset 0x2c6, CSR Addr 0x54163, Direction=N/A + + uint8_t Reserved2C7; // Byte offset 0x2c7, CSR Addr 0x54163, Direction=N/A + + uint8_t Reserved2C8; // Byte offset 0x2c8, CSR Addr 0x54164, Direction=N/A + + uint8_t Reserved2C9; // Byte offset 0x2c9, CSR Addr 0x54164, Direction=N/A + + uint8_t Reserved2CA; // Byte offset 0x2ca, CSR Addr 0x54165, Direction=N/A + + uint8_t Reserved2CB; // Byte offset 0x2cb, CSR Addr 0x54165, Direction=N/A + + uint8_t Reserved2CC; // Byte offset 0x2cc, CSR Addr 0x54166, Direction=N/A + + uint8_t Reserved2CD; // Byte offset 0x2cd, CSR Addr 0x54166, Direction=N/A + + uint8_t Reserved2CE; // Byte offset 0x2ce, CSR Addr 0x54167, Direction=N/A + + uint8_t Reserved2CF; // Byte offset 0x2cf, CSR Addr 0x54167, Direction=N/A + + uint8_t Reserved2D0; // Byte offset 0x2d0, CSR Addr 0x54168, Direction=N/A + + uint8_t Reserved2D1; // Byte offset 0x2d1, CSR Addr 0x54168, Direction=N/A + + uint8_t Reserved2D2; // Byte offset 0x2d2, CSR Addr 0x54169, Direction=N/A + + uint8_t Reserved2D3; // Byte offset 0x2d3, CSR Addr 0x54169, Direction=N/A + + uint8_t Reserved2D4; // Byte offset 0x2d4, CSR Addr 0x5416a, Direction=N/A + + uint8_t Reserved2D5; // Byte offset 0x2d5, CSR Addr 0x5416a, Direction=N/A + + uint8_t Reserved2D6; // Byte offset 0x2d6, CSR Addr 0x5416b, Direction=N/A + + uint8_t Reserved2D7; // Byte offset 0x2d7, CSR Addr 0x5416b, Direction=N/A + + uint8_t Reserved2D8; // Byte offset 0x2d8, CSR Addr 0x5416c, Direction=N/A + + uint8_t Reserved2D9; // Byte offset 0x2d9, CSR Addr 0x5416c, Direction=N/A + + uint8_t Reserved2DA; // Byte offset 0x2da, CSR Addr 0x5416d, Direction=N/A + + uint8_t Reserved2DB; // Byte offset 0x2db, CSR Addr 0x5416d, Direction=N/A + + uint8_t Reserved2DC; // Byte offset 0x2dc, CSR Addr 0x5416e, Direction=N/A + + uint8_t Reserved2DD; // Byte offset 0x2dd, CSR Addr 0x5416e, Direction=N/A + + uint8_t Reserved2DE; // Byte offset 0x2de, CSR Addr 0x5416f, Direction=N/A + + uint8_t Reserved2DF; // Byte offset 0x2df, CSR Addr 0x5416f, Direction=N/A + + uint8_t Reserved2E0; // Byte offset 0x2e0, CSR Addr 0x54170, Direction=N/A + + uint8_t Reserved2E1; // Byte offset 0x2e1, CSR Addr 0x54170, Direction=N/A + + uint8_t Reserved2E2; // Byte offset 0x2e2, CSR Addr 0x54171, Direction=N/A + + uint8_t Reserved2E3; // Byte offset 0x2e3, CSR Addr 0x54171, Direction=N/A + + uint8_t Reserved2E4; // Byte offset 0x2e4, CSR Addr 0x54172, Direction=N/A + + uint8_t Reserved2E5; // Byte offset 0x2e5, CSR Addr 0x54172, Direction=N/A + + uint8_t Reserved2E6; // Byte offset 0x2e6, CSR Addr 0x54173, Direction=N/A + + uint8_t Reserved2E7; // Byte offset 0x2e7, CSR Addr 0x54173, Direction=N/A + + uint8_t Reserved2E8; // Byte offset 0x2e8, CSR Addr 0x54174, Direction=N/A + + uint8_t Reserved2E9; // Byte offset 0x2e9, CSR Addr 0x54174, Direction=N/A + + uint8_t Reserved2EA; // Byte offset 0x2ea, CSR Addr 0x54175, Direction=N/A + + uint8_t Reserved2EB; // Byte offset 0x2eb, CSR Addr 0x54175, Direction=N/A + + uint8_t Reserved2EC; // Byte offset 0x2ec, CSR Addr 0x54176, Direction=N/A + + uint8_t Reserved2ED; // Byte offset 0x2ed, CSR Addr 0x54176, Direction=N/A + + uint8_t Reserved2EE; // Byte offset 0x2ee, CSR Addr 0x54177, Direction=N/A + + uint8_t Reserved2EF; // Byte offset 0x2ef, CSR Addr 0x54177, Direction=N/A + + uint8_t Reserved2F0; // Byte offset 0x2f0, CSR Addr 0x54178, Direction=N/A + + uint8_t Reserved2F1; // Byte offset 0x2f1, CSR Addr 0x54178, Direction=N/A + + uint8_t Reserved2F2; // Byte offset 0x2f2, CSR Addr 0x54179, Direction=N/A + + uint8_t Reserved2F3; // Byte offset 0x2f3, CSR Addr 0x54179, Direction=N/A + + uint8_t Reserved2F4; // Byte offset 0x2f4, CSR Addr 0x5417a, Direction=N/A + + uint8_t Reserved2F5; // Byte offset 0x2f5, CSR Addr 0x5417a, Direction=N/A + + uint8_t Reserved2F6; // Byte offset 0x2f6, CSR Addr 0x5417b, Direction=N/A + + uint8_t Reserved2F7; // Byte offset 0x2f7, CSR Addr 0x5417b, Direction=N/A + + uint8_t Reserved2F8; // Byte offset 0x2f8, CSR Addr 0x5417c, Direction=N/A + + uint8_t Reserved2F9; // Byte offset 0x2f9, CSR Addr 0x5417c, Direction=N/A + + uint8_t Reserved2FA; // Byte offset 0x2fa, CSR Addr 0x5417d, Direction=N/A + + uint8_t Reserved2FB; // Byte offset 0x2fb, CSR Addr 0x5417d, Direction=N/A + + uint8_t Reserved2FC; // Byte offset 0x2fc, CSR Addr 0x5417e, Direction=N/A + + uint8_t Reserved2FD; // Byte offset 0x2fd, CSR Addr 0x5417e, Direction=N/A + + uint8_t Reserved2FE; // Byte offset 0x2fe, CSR Addr 0x5417f, Direction=N/A + + uint8_t Reserved2FF; // Byte offset 0x2ff, CSR Addr 0x5417f, Direction=N/A + + uint8_t Reserved300; // Byte offset 0x300, CSR Addr 0x54180, Direction=N/A + + uint8_t Reserved301; // Byte offset 0x301, CSR Addr 0x54180, Direction=N/A + + uint8_t Reserved302; // Byte offset 0x302, CSR Addr 0x54181, Direction=N/A + + uint8_t Reserved303; // Byte offset 0x303, CSR Addr 0x54181, Direction=N/A + + uint8_t Reserved304; // Byte offset 0x304, CSR Addr 0x54182, Direction=N/A + + uint8_t Reserved305; // Byte offset 0x305, CSR Addr 0x54182, Direction=N/A + + uint8_t Reserved306; // Byte offset 0x306, CSR Addr 0x54183, Direction=N/A + + uint8_t Reserved307; // Byte offset 0x307, CSR Addr 0x54183, Direction=N/A + + uint8_t Reserved308; // Byte offset 0x308, CSR Addr 0x54184, Direction=N/A + + uint8_t Reserved309; // Byte offset 0x309, CSR Addr 0x54184, Direction=N/A + + uint8_t Reserved30A; // Byte offset 0x30a, CSR Addr 0x54185, Direction=N/A + + uint8_t Reserved30B; // Byte offset 0x30b, CSR Addr 0x54185, Direction=N/A + + uint8_t Reserved30C; // Byte offset 0x30c, CSR Addr 0x54186, Direction=N/A + + uint8_t Reserved30D; // Byte offset 0x30d, CSR Addr 0x54186, Direction=N/A + + uint8_t Reserved30E; // Byte offset 0x30e, CSR Addr 0x54187, Direction=N/A + + uint8_t Reserved30F; // Byte offset 0x30f, CSR Addr 0x54187, Direction=N/A + + uint8_t Reserved310; // Byte offset 0x310, CSR Addr 0x54188, Direction=N/A + + uint8_t Reserved311; // Byte offset 0x311, CSR Addr 0x54188, Direction=N/A + + uint8_t Reserved312; // Byte offset 0x312, CSR Addr 0x54189, Direction=N/A + + uint8_t Reserved313; // Byte offset 0x313, CSR Addr 0x54189, Direction=N/A + + uint8_t Reserved314; // Byte offset 0x314, CSR Addr 0x5418a, Direction=N/A + + uint8_t Reserved315; // Byte offset 0x315, CSR Addr 0x5418a, Direction=N/A + + uint8_t Reserved316; // Byte offset 0x316, CSR Addr 0x5418b, Direction=N/A + + uint8_t Reserved317; // Byte offset 0x317, CSR Addr 0x5418b, Direction=N/A + + uint8_t Reserved318; // Byte offset 0x318, CSR Addr 0x5418c, Direction=N/A + + uint8_t Reserved319; // Byte offset 0x319, CSR Addr 0x5418c, Direction=N/A + + uint8_t Reserved31A; // Byte offset 0x31a, CSR Addr 0x5418d, Direction=N/A + + uint8_t Reserved31B; // Byte offset 0x31b, CSR Addr 0x5418d, Direction=N/A + + uint8_t Reserved31C; // Byte offset 0x31c, CSR Addr 0x5418e, Direction=N/A + + uint8_t Reserved31D; // Byte offset 0x31d, CSR Addr 0x5418e, Direction=N/A + + uint8_t Reserved31E; // Byte offset 0x31e, CSR Addr 0x5418f, Direction=N/A + + uint8_t Reserved31F; // Byte offset 0x31f, CSR Addr 0x5418f, Direction=N/A + + uint8_t Reserved320; // Byte offset 0x320, CSR Addr 0x54190, Direction=N/A + + uint8_t Reserved321; // Byte offset 0x321, CSR Addr 0x54190, Direction=N/A + + uint8_t Reserved322; // Byte offset 0x322, CSR Addr 0x54191, Direction=N/A + + uint8_t Reserved323; // Byte offset 0x323, CSR Addr 0x54191, Direction=N/A + + uint8_t Reserved324; // Byte offset 0x324, CSR Addr 0x54192, Direction=N/A + + uint8_t Reserved325; // Byte offset 0x325, CSR Addr 0x54192, Direction=N/A + + uint8_t Reserved326; // Byte offset 0x326, CSR Addr 0x54193, Direction=N/A + + uint8_t Reserved327; // Byte offset 0x327, CSR Addr 0x54193, Direction=N/A + + uint8_t Reserved328; // Byte offset 0x328, CSR Addr 0x54194, Direction=N/A + + uint8_t Reserved329; // Byte offset 0x329, CSR Addr 0x54194, Direction=N/A + + uint8_t Reserved32A; // Byte offset 0x32a, CSR Addr 0x54195, Direction=N/A + + uint8_t Reserved32B; // Byte offset 0x32b, CSR Addr 0x54195, Direction=N/A + + uint8_t Reserved32C; // Byte offset 0x32c, CSR Addr 0x54196, Direction=N/A + + uint8_t Reserved32D; // Byte offset 0x32d, CSR Addr 0x54196, Direction=N/A + + uint8_t Reserved32E; // Byte offset 0x32e, CSR Addr 0x54197, Direction=N/A + + uint8_t Reserved32F; // Byte offset 0x32f, CSR Addr 0x54197, Direction=N/A + + uint8_t Reserved330; // Byte offset 0x330, CSR Addr 0x54198, Direction=N/A + + uint8_t Reserved331; // Byte offset 0x331, CSR Addr 0x54198, Direction=N/A + + uint8_t Reserved332; // Byte offset 0x332, CSR Addr 0x54199, Direction=N/A + + uint8_t Reserved333; // Byte offset 0x333, CSR Addr 0x54199, Direction=N/A + + uint8_t Reserved334; // Byte offset 0x334, CSR Addr 0x5419a, Direction=N/A + + uint8_t Reserved335; // Byte offset 0x335, CSR Addr 0x5419a, Direction=N/A + + uint8_t Reserved336; // Byte offset 0x336, CSR Addr 0x5419b, Direction=N/A + + uint8_t Reserved337; // Byte offset 0x337, CSR Addr 0x5419b, Direction=N/A + + uint8_t Reserved338; // Byte offset 0x338, CSR Addr 0x5419c, Direction=N/A + + uint8_t Reserved339; // Byte offset 0x339, CSR Addr 0x5419c, Direction=N/A + + uint8_t Reserved33A; // Byte offset 0x33a, CSR Addr 0x5419d, Direction=N/A + + uint8_t Reserved33B; // Byte offset 0x33b, CSR Addr 0x5419d, Direction=N/A + + uint8_t Reserved33C; // Byte offset 0x33c, CSR Addr 0x5419e, Direction=N/A + + uint8_t Reserved33D; // Byte offset 0x33d, CSR Addr 0x5419e, Direction=N/A + + uint8_t Reserved33E; // Byte offset 0x33e, CSR Addr 0x5419f, Direction=N/A + + uint8_t Reserved33F; // Byte offset 0x33f, CSR Addr 0x5419f, Direction=N/A + + uint8_t Reserved340; // Byte offset 0x340, CSR Addr 0x541a0, Direction=N/A + + uint8_t Reserved341; // Byte offset 0x341, CSR Addr 0x541a0, Direction=N/A + + uint8_t Reserved342; // Byte offset 0x342, CSR Addr 0x541a1, Direction=N/A + + uint8_t Reserved343; // Byte offset 0x343, CSR Addr 0x541a1, Direction=N/A + + uint8_t Reserved344; // Byte offset 0x344, CSR Addr 0x541a2, Direction=N/A + + uint8_t Reserved345; // Byte offset 0x345, CSR Addr 0x541a2, Direction=N/A + + uint8_t Reserved346; // Byte offset 0x346, CSR Addr 0x541a3, Direction=N/A + + uint8_t Reserved347; // Byte offset 0x347, CSR Addr 0x541a3, Direction=N/A + + uint8_t Reserved348; // Byte offset 0x348, CSR Addr 0x541a4, Direction=N/A + + uint8_t Reserved349; // Byte offset 0x349, CSR Addr 0x541a4, Direction=N/A + + uint8_t Reserved34A; // Byte offset 0x34a, CSR Addr 0x541a5, Direction=N/A + + uint8_t Reserved34B; // Byte offset 0x34b, CSR Addr 0x541a5, Direction=N/A + + uint8_t Reserved34C; // Byte offset 0x34c, CSR Addr 0x541a6, Direction=N/A + + uint8_t Reserved34D; // Byte offset 0x34d, CSR Addr 0x541a6, Direction=N/A + + uint8_t Reserved34E; // Byte offset 0x34e, CSR Addr 0x541a7, Direction=N/A + + uint8_t Reserved34F; // Byte offset 0x34f, CSR Addr 0x541a7, Direction=N/A + + uint8_t Reserved350; // Byte offset 0x350, CSR Addr 0x541a8, Direction=N/A + + uint8_t Reserved351; // Byte offset 0x351, CSR Addr 0x541a8, Direction=N/A + + uint8_t Reserved352; // Byte offset 0x352, CSR Addr 0x541a9, Direction=N/A + + uint8_t Reserved353; // Byte offset 0x353, CSR Addr 0x541a9, Direction=N/A + + uint8_t Reserved354; // Byte offset 0x354, CSR Addr 0x541aa, Direction=N/A + + uint8_t Reserved355; // Byte offset 0x355, CSR Addr 0x541aa, Direction=N/A + + uint8_t Reserved356; // Byte offset 0x356, CSR Addr 0x541ab, Direction=N/A + + uint8_t Reserved357; // Byte offset 0x357, CSR Addr 0x541ab, Direction=N/A + + uint8_t Reserved358; // Byte offset 0x358, CSR Addr 0x541ac, Direction=N/A + + uint8_t Reserved359; // Byte offset 0x359, CSR Addr 0x541ac, Direction=N/A + + uint8_t Reserved35A; // Byte offset 0x35a, CSR Addr 0x541ad, Direction=N/A + + uint8_t Reserved35B; // Byte offset 0x35b, CSR Addr 0x541ad, Direction=N/A + + uint8_t Reserved35C; // Byte offset 0x35c, CSR Addr 0x541ae, Direction=N/A + + uint8_t Reserved35D; // Byte offset 0x35d, CSR Addr 0x541ae, Direction=N/A + + uint8_t Reserved35E; // Byte offset 0x35e, CSR Addr 0x541af, Direction=N/A + + uint8_t Reserved35F; // Byte offset 0x35f, CSR Addr 0x541af, Direction=N/A + + uint8_t Reserved360; // Byte offset 0x360, CSR Addr 0x541b0, Direction=N/A + + uint8_t Reserved361; // Byte offset 0x361, CSR Addr 0x541b0, Direction=N/A + + uint8_t Reserved362; // Byte offset 0x362, CSR Addr 0x541b1, Direction=N/A + + uint8_t Reserved363; // Byte offset 0x363, CSR Addr 0x541b1, Direction=N/A + + uint8_t Reserved364; // Byte offset 0x364, CSR Addr 0x541b2, Direction=N/A + + uint8_t Reserved365; // Byte offset 0x365, CSR Addr 0x541b2, Direction=N/A + + uint8_t Reserved366; // Byte offset 0x366, CSR Addr 0x541b3, Direction=N/A + + uint8_t Reserved367; // Byte offset 0x367, CSR Addr 0x541b3, Direction=N/A + + uint8_t Reserved368; // Byte offset 0x368, CSR Addr 0x541b4, Direction=N/A + + uint8_t Reserved369; // Byte offset 0x369, CSR Addr 0x541b4, Direction=N/A + + uint8_t Reserved36A; // Byte offset 0x36a, CSR Addr 0x541b5, Direction=N/A + + uint8_t Reserved36B; // Byte offset 0x36b, CSR Addr 0x541b5, Direction=N/A + + uint8_t Reserved36C; // Byte offset 0x36c, CSR Addr 0x541b6, Direction=N/A + + uint8_t Reserved36D; // Byte offset 0x36d, CSR Addr 0x541b6, Direction=N/A + + uint8_t Reserved36E; // Byte offset 0x36e, CSR Addr 0x541b7, Direction=N/A + + uint8_t Reserved36F; // Byte offset 0x36f, CSR Addr 0x541b7, Direction=N/A + + uint8_t Reserved370; // Byte offset 0x370, CSR Addr 0x541b8, Direction=N/A + + uint8_t Reserved371; // Byte offset 0x371, CSR Addr 0x541b8, Direction=N/A + + uint8_t Reserved372; // Byte offset 0x372, CSR Addr 0x541b9, Direction=N/A + + uint8_t Reserved373; // Byte offset 0x373, CSR Addr 0x541b9, Direction=N/A + + uint8_t Reserved374; // Byte offset 0x374, CSR Addr 0x541ba, Direction=N/A + + uint8_t Reserved375; // Byte offset 0x375, CSR Addr 0x541ba, Direction=N/A + + uint8_t Reserved376; // Byte offset 0x376, CSR Addr 0x541bb, Direction=N/A + + uint8_t Reserved377; // Byte offset 0x377, CSR Addr 0x541bb, Direction=N/A + + uint8_t Reserved378; // Byte offset 0x378, CSR Addr 0x541bc, Direction=N/A + + uint8_t Reserved379; // Byte offset 0x379, CSR Addr 0x541bc, Direction=N/A + + uint8_t Reserved37A; // Byte offset 0x37a, CSR Addr 0x541bd, Direction=N/A + + uint8_t Reserved37B; // Byte offset 0x37b, CSR Addr 0x541bd, Direction=N/A + + uint8_t Reserved37C; // Byte offset 0x37c, CSR Addr 0x541be, Direction=N/A + + uint8_t Reserved37D; // Byte offset 0x37d, CSR Addr 0x541be, Direction=N/A + + uint8_t Reserved37E; // Byte offset 0x37e, CSR Addr 0x541bf, Direction=N/A + + uint8_t Reserved37F; // Byte offset 0x37f, CSR Addr 0x541bf, Direction=N/A + + uint8_t Reserved380; // Byte offset 0x380, CSR Addr 0x541c0, Direction=N/A + + uint8_t Reserved381; // Byte offset 0x381, CSR Addr 0x541c0, Direction=N/A + + uint8_t Reserved382; // Byte offset 0x382, CSR Addr 0x541c1, Direction=N/A + + uint8_t Reserved383; // Byte offset 0x383, CSR Addr 0x541c1, Direction=N/A + + uint8_t Reserved384; // Byte offset 0x384, CSR Addr 0x541c2, Direction=N/A + + uint8_t Reserved385; // Byte offset 0x385, CSR Addr 0x541c2, Direction=N/A + + uint8_t Reserved386; // Byte offset 0x386, CSR Addr 0x541c3, Direction=N/A + + uint8_t Reserved387; // Byte offset 0x387, CSR Addr 0x541c3, Direction=N/A + + uint8_t Reserved388; // Byte offset 0x388, CSR Addr 0x541c4, Direction=N/A + + uint8_t Reserved389; // Byte offset 0x389, CSR Addr 0x541c4, Direction=N/A + + uint8_t Reserved38A; // Byte offset 0x38a, CSR Addr 0x541c5, Direction=N/A + + uint8_t Reserved38B; // Byte offset 0x38b, CSR Addr 0x541c5, Direction=N/A + + uint8_t Reserved38C; // Byte offset 0x38c, CSR Addr 0x541c6, Direction=N/A + + uint8_t Reserved38D; // Byte offset 0x38d, CSR Addr 0x541c6, Direction=N/A + + uint8_t Reserved38E; // Byte offset 0x38e, CSR Addr 0x541c7, Direction=N/A + + uint8_t Reserved38F; // Byte offset 0x38f, CSR Addr 0x541c7, Direction=N/A + + uint8_t Reserved390; // Byte offset 0x390, CSR Addr 0x541c8, Direction=N/A + + uint8_t Reserved391; // Byte offset 0x391, CSR Addr 0x541c8, Direction=N/A + + uint8_t Reserved392; // Byte offset 0x392, CSR Addr 0x541c9, Direction=N/A + + uint8_t Reserved393; // Byte offset 0x393, CSR Addr 0x541c9, Direction=N/A + + uint8_t Reserved394; // Byte offset 0x394, CSR Addr 0x541ca, Direction=N/A + + uint8_t Reserved395; // Byte offset 0x395, CSR Addr 0x541ca, Direction=N/A + + uint8_t Reserved396; // Byte offset 0x396, CSR Addr 0x541cb, Direction=N/A + + uint8_t Reserved397; // Byte offset 0x397, CSR Addr 0x541cb, Direction=N/A + + uint8_t Reserved398; // Byte offset 0x398, CSR Addr 0x541cc, Direction=N/A + + uint8_t Reserved399; // Byte offset 0x399, CSR Addr 0x541cc, Direction=N/A + + uint8_t Reserved39A; // Byte offset 0x39a, CSR Addr 0x541cd, Direction=N/A + + uint8_t Reserved39B; // Byte offset 0x39b, CSR Addr 0x541cd, Direction=N/A + + uint8_t Reserved39C; // Byte offset 0x39c, CSR Addr 0x541ce, Direction=N/A + + uint8_t Reserved39D; // Byte offset 0x39d, CSR Addr 0x541ce, Direction=N/A + + uint8_t Reserved39E; // Byte offset 0x39e, CSR Addr 0x541cf, Direction=N/A + + uint8_t Reserved39F; // Byte offset 0x39f, CSR Addr 0x541cf, Direction=N/A + + uint8_t Reserved3A0; // Byte offset 0x3a0, CSR Addr 0x541d0, Direction=N/A + + uint8_t Reserved3A1; // Byte offset 0x3a1, CSR Addr 0x541d0, Direction=N/A + + uint8_t Reserved3A2; // Byte offset 0x3a2, CSR Addr 0x541d1, Direction=N/A + + uint8_t Reserved3A3; // Byte offset 0x3a3, CSR Addr 0x541d1, Direction=N/A + + uint8_t Reserved3A4; // Byte offset 0x3a4, CSR Addr 0x541d2, Direction=N/A + + uint8_t Reserved3A5; // Byte offset 0x3a5, CSR Addr 0x541d2, Direction=N/A + + uint8_t Reserved3A6; // Byte offset 0x3a6, CSR Addr 0x541d3, Direction=N/A + + uint8_t Reserved3A7; // Byte offset 0x3a7, CSR Addr 0x541d3, Direction=N/A + + uint8_t Reserved3A8; // Byte offset 0x3a8, CSR Addr 0x541d4, Direction=N/A + + uint8_t Reserved3A9; // Byte offset 0x3a9, CSR Addr 0x541d4, Direction=N/A + + uint8_t Reserved3AA; // Byte offset 0x3aa, CSR Addr 0x541d5, Direction=N/A + + uint8_t Reserved3AB; // Byte offset 0x3ab, CSR Addr 0x541d5, Direction=N/A + + uint8_t Reserved3AC; // Byte offset 0x3ac, CSR Addr 0x541d6, Direction=N/A + + uint8_t Reserved3AD; // Byte offset 0x3ad, CSR Addr 0x541d6, Direction=N/A + + uint8_t Reserved3AE; // Byte offset 0x3ae, CSR Addr 0x541d7, Direction=N/A + + uint8_t Reserved3AF; // Byte offset 0x3af, CSR Addr 0x541d7, Direction=N/A + + uint8_t Reserved3B0; // Byte offset 0x3b0, CSR Addr 0x541d8, Direction=N/A + + uint8_t Reserved3B1; // Byte offset 0x3b1, CSR Addr 0x541d8, Direction=N/A + + uint8_t Reserved3B2; // Byte offset 0x3b2, CSR Addr 0x541d9, Direction=N/A + + uint8_t Reserved3B3; // Byte offset 0x3b3, CSR Addr 0x541d9, Direction=N/A + + uint8_t Reserved3B4; // Byte offset 0x3b4, CSR Addr 0x541da, Direction=N/A + + uint8_t Reserved3B5; // Byte offset 0x3b5, CSR Addr 0x541da, Direction=N/A + + uint8_t Reserved3B6; // Byte offset 0x3b6, CSR Addr 0x541db, Direction=N/A + + uint8_t Reserved3B7; // Byte offset 0x3b7, CSR Addr 0x541db, Direction=N/A + + uint8_t Reserved3B8; // Byte offset 0x3b8, CSR Addr 0x541dc, Direction=N/A + + uint8_t Reserved3B9; // Byte offset 0x3b9, CSR Addr 0x541dc, Direction=N/A + + uint8_t Reserved3BA; // Byte offset 0x3ba, CSR Addr 0x541dd, Direction=N/A + + uint8_t Reserved3BB; // Byte offset 0x3bb, CSR Addr 0x541dd, Direction=N/A + + uint8_t Reserved3BC; // Byte offset 0x3bc, CSR Addr 0x541de, Direction=N/A + + uint8_t Reserved3BD; // Byte offset 0x3bd, CSR Addr 0x541de, Direction=N/A + + uint8_t Reserved3BE; // Byte offset 0x3be, CSR Addr 0x541df, Direction=N/A + + uint8_t Reserved3BF; // Byte offset 0x3bf, CSR Addr 0x541df, Direction=N/A + + uint8_t Reserved3C0; // Byte offset 0x3c0, CSR Addr 0x541e0, Direction=N/A + + uint8_t Reserved3C1; // Byte offset 0x3c1, CSR Addr 0x541e0, Direction=N/A + + uint8_t Reserved3C2; // Byte offset 0x3c2, CSR Addr 0x541e1, Direction=N/A + + uint8_t Reserved3C3; // Byte offset 0x3c3, CSR Addr 0x541e1, Direction=N/A + + uint8_t Reserved3C4; // Byte offset 0x3c4, CSR Addr 0x541e2, Direction=N/A + + uint8_t Reserved3C5; // Byte offset 0x3c5, CSR Addr 0x541e2, Direction=N/A + + uint8_t Reserved3C6; // Byte offset 0x3c6, CSR Addr 0x541e3, Direction=N/A + + uint8_t Reserved3C7; // Byte offset 0x3c7, CSR Addr 0x541e3, Direction=N/A + + uint8_t Reserved3C8; // Byte offset 0x3c8, CSR Addr 0x541e4, Direction=N/A + + uint8_t Reserved3C9; // Byte offset 0x3c9, CSR Addr 0x541e4, Direction=N/A + + uint8_t Reserved3CA; // Byte offset 0x3ca, CSR Addr 0x541e5, Direction=N/A + + uint8_t Reserved3CB; // Byte offset 0x3cb, CSR Addr 0x541e5, Direction=N/A + + uint8_t Reserved3CC; // Byte offset 0x3cc, CSR Addr 0x541e6, Direction=N/A + + uint8_t Reserved3CD; // Byte offset 0x3cd, CSR Addr 0x541e6, Direction=N/A + + uint8_t Reserved3CE; // Byte offset 0x3ce, CSR Addr 0x541e7, Direction=N/A + + uint8_t Reserved3CF; // Byte offset 0x3cf, CSR Addr 0x541e7, Direction=N/A + + uint8_t Reserved3D0; // Byte offset 0x3d0, CSR Addr 0x541e8, Direction=N/A + + uint8_t Reserved3D1; // Byte offset 0x3d1, CSR Addr 0x541e8, Direction=N/A + + uint8_t Reserved3D2; // Byte offset 0x3d2, CSR Addr 0x541e9, Direction=N/A + + uint8_t Reserved3D3; // Byte offset 0x3d3, CSR Addr 0x541e9, Direction=N/A + + uint8_t Reserved3D4; // Byte offset 0x3d4, CSR Addr 0x541ea, Direction=N/A + + uint8_t Reserved3D5; // Byte offset 0x3d5, CSR Addr 0x541ea, Direction=N/A + + uint8_t Reserved3D6; // Byte offset 0x3d6, CSR Addr 0x541eb, Direction=N/A + + uint8_t Reserved3D7; // Byte offset 0x3d7, CSR Addr 0x541eb, Direction=N/A + + uint8_t Reserved3D8; // Byte offset 0x3d8, CSR Addr 0x541ec, Direction=N/A + + uint8_t Reserved3D9; // Byte offset 0x3d9, CSR Addr 0x541ec, Direction=N/A + + uint8_t Reserved3DA; // Byte offset 0x3da, CSR Addr 0x541ed, Direction=N/A + + uint8_t Reserved3DB; // Byte offset 0x3db, CSR Addr 0x541ed, Direction=N/A + + uint8_t Reserved3DC; // Byte offset 0x3dc, CSR Addr 0x541ee, Direction=N/A + + uint8_t Reserved3DD; // Byte offset 0x3dd, CSR Addr 0x541ee, Direction=N/A + + uint8_t Reserved3DE; // Byte offset 0x3de, CSR Addr 0x541ef, Direction=N/A + + uint8_t Reserved3DF; // Byte offset 0x3df, CSR Addr 0x541ef, Direction=N/A + + uint8_t Reserved3E0; // Byte offset 0x3e0, CSR Addr 0x541f0, Direction=N/A + + uint8_t Reserved3E1; // Byte offset 0x3e1, CSR Addr 0x541f0, Direction=N/A + + uint8_t Reserved3E2; // Byte offset 0x3e2, CSR Addr 0x541f1, Direction=N/A + + uint8_t Reserved3E3; // Byte offset 0x3e3, CSR Addr 0x541f1, Direction=N/A + + uint8_t Reserved3E4; // Byte offset 0x3e4, CSR Addr 0x541f2, Direction=N/A + + uint8_t Reserved3E5; // Byte offset 0x3e5, CSR Addr 0x541f2, Direction=N/A + + uint8_t Reserved3E6; // Byte offset 0x3e6, CSR Addr 0x541f3, Direction=N/A + + uint8_t Reserved3E7; // Byte offset 0x3e7, CSR Addr 0x541f3, Direction=N/A + + uint8_t Reserved3E8; // Byte offset 0x3e8, CSR Addr 0x541f4, Direction=N/A + + uint8_t Reserved3E9; // Byte offset 0x3e9, CSR Addr 0x541f4, Direction=N/A + + uint8_t Reserved3EA; // Byte offset 0x3ea, CSR Addr 0x541f5, Direction=N/A + + uint8_t Reserved3EB; // Byte offset 0x3eb, CSR Addr 0x541f5, Direction=N/A + + uint8_t Reserved3EC; // Byte offset 0x3ec, CSR Addr 0x541f6, Direction=N/A + + uint8_t Reserved3ED; // Byte offset 0x3ed, CSR Addr 0x541f6, Direction=N/A + + uint8_t Reserved3EE; // Byte offset 0x3ee, CSR Addr 0x541f7, Direction=N/A + + uint8_t Reserved3EF; // Byte offset 0x3ef, CSR Addr 0x541f7, Direction=N/A + + uint8_t Reserved3F0; // Byte offset 0x3f0, CSR Addr 0x541f8, Direction=N/A + + uint8_t Reserved3F1; // Byte offset 0x3f1, CSR Addr 0x541f8, Direction=N/A + + uint8_t Reserved3F2; // Byte offset 0x3f2, CSR Addr 0x541f9, Direction=N/A + + uint8_t Reserved3F3; // Byte offset 0x3f3, CSR Addr 0x541f9, Direction=N/A + + uint8_t Reserved3F4; // Byte offset 0x3f4, CSR Addr 0x541fa, Direction=N/A + + uint8_t Reserved3F5; // Byte offset 0x3f5, CSR Addr 0x541fa, Direction=N/A + + uint16_t ALT_CAS_L; // Byte offset 0x3f6, CSR Addr 0x541fb, Direction=in + // This field must be populated if RdDBI is enabled (applicable when MR5[A12] == 1). + // RdDBI is dynamically disabled in certain training steps, + // and so the [RdDBI disabled] CAS Latency must be provided in this field. + // The required encoding is as follows: + // ALT_CAS_L[0] == 0: use value in MR0 + // ALT_CAS_L[0] == 1: use value in ALT_CAS_L, i.e., MR0{A[12],A[6],A[5],A[4],A[2]} = ALT_CAS_L[12,6,5,4,2] + // Other bits are ignored + uint8_t ALT_WCAS_L; // Byte offset 0x3f8, CSR Addr 0x541fc, Direction=In + // This field must be populated if 2tCK write preambles are enabled (applicable when MR4[A12] == 1). + // 2tCK write prambles are dynamically disabled in certain training steps, + // and so the [1tCK write preamble] WCAS Latency must be provided in this field. + // The required encoding is as follows: + // ALT_WCAS_L[0] == 0: use value in MR2 + // ALT_WCAS_L[0] == 1: use value in ALT_WCAS_L, i.e., MR2{A[5],A[4],A[3]} = ALT_WCAS_L[5,4,3] + // Other bits are ignored + uint8_t D4Misc; // Byte offset 0x3f9, CSR Addr 0x541fc, Direction=In + // Contains various options for training DDR4 Devices. + // + // Bit fields: + // + // D4Misc[7:1] RFU, must be zero + // + // D4Misc[0] = protect memory reset + // 0x1 = dfi_reset_n cannot control BP_MEMRESERT_L to devices after training. + // 0x0 = dfi_resert_n can control BP_MEMRESERT_L to devices after training +} __attribute__ ((packed)) PMU_SMB_DDR4U_2D_t;
diff --git a/arch/arm/include/asm/arch-a1/mnPmuSramMsgBlock_lpddr3.h b/arch/arm/include/asm/arch-a1/mnPmuSramMsgBlock_lpddr3.h new file mode 100644 index 0000000..6850d06 --- /dev/null +++ b/arch/arm/include/asm/arch-a1/mnPmuSramMsgBlock_lpddr3.h
@@ -0,0 +1,434 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +/** \brief LPDDR3_1D training firmware message block structure + * + * Please refer to the Training Firmware App Note for futher information about + * the usage for Message Block. + */ +typedef struct _PMU_SMB_LPDDR3_1D_t { + uint8_t Reserved00; // Byte offset 0x00, CSR Addr 0x54000, Direction=In + // Reserved00[0:5] RFU, must be zero + // + // Reserved00[6] = Enable High Effort WrDQ1D + // 0x1 = WrDQ1D will conditionally retry training at several extra RxClkDly Timings. This will increase the maximum 1D training time by up to 4 extra iterations of WrDQ1D. This is only required in systems that suffer from very large, asymmetric eye-collapse when receiving PRBS patterns. + // 0x0 = WrDQ1D assume rxClkDly values found by SI Friendly RdDqs1D will work for receiving PRBS patterns + // + // Reserved00[7] = Optimize for the special hard macros in TSMC28. + // 0x1 = set if the phy being trained was manufactured in any TSMC28 process node. + // 0x0 = otherwise, when not training a TSMC28 phy, leave this field as 0. + uint8_t MsgMisc; // Byte offset 0x01, CSR Addr 0x54000, Direction=In + // Contains various global options for training. + // + // Bit fields: + // + // MsgMisc[0] MTESTEnable + // 0x1 = Pulse primary digital test output bump at the end of each major training stage. This enables observation of training stage completion by observing the digital test output. + // 0x0 = Do not pulse primary digital test output bump + // + // MsgMisc[1] SimulationOnlyReset + // 0x1 = Verilog only simulation option to shorten duration of DRAM reset pulse length to 1ns. + // Must never be set to 1 in silicon. + // 0x0 = Use reset pulse length specifed by JEDEC standard + // + // MsgMisc[2] SimulationOnlyTraining + // 0x1 = Verilog only simulation option to shorten the duration of the training steps by performing fewer iterations. + // Must never be set to 1 in silicon. + // 0x0 = Use standard training duration. + // + // MsgMisc[3] RFU, must be zero + // + // MsgMisc[4] Suppress streaming messages, including assertions, regardless of HdtCtrl setting. + // Stage Completion messages, as well as training completion and error messages are + // Still sent depending on HdtCtrl setting. + // + // MsgMisc[5] PerByteMaxRdLat + // 0x1 = Each DBYTE will return dfi_rddata_valid at the lowest possible latency. This may result in unaligned data between bytes to be returned to the DFI. + // 0x0 = Every DBYTE will return dfi_rddata_valid simultaneously. This will ensure that data bytes will return aligned accesses to the DFI. + // + // MsgMisc[7-6] RFU, must be zero + // + // Notes: + // + // - SimulationOnlyReset and SimulationOnlyTraining can be used to speed up simulation run times, and must never be used in real silicon. Some VIPs may have checks on DRAM reset parameters that may need to be disabled when using SimulationOnlyReset. + uint16_t PmuRevision; // Byte offset 0x02, CSR Addr 0x54001, Direction=Out + // PMU firmware revision ID + // After training is run, this address will contain the revision ID of the firmware + uint8_t Pstate; // Byte offset 0x04, CSR Addr 0x54002, Direction=In + // Must be set to the target Pstate to be trained + // 0x0 = Pstate 0 + // 0x1 = Pstate 1 + // 0x2 = Pstate 2 + // 0x3 = Pstate 3 + // All other encodings are reserved + uint8_t PllBypassEn; // Byte offset 0x05, CSR Addr 0x54002, Direction=In + // Set according to whether target Pstate uses PHY PLL bypass + // 0x0 = PHY PLL is enabled for target Pstate + // 0x1 = PHY PLL is bypassed for target Pstate + uint16_t DRAMFreq; // Byte offset 0x06, CSR Addr 0x54003, Direction=In + // DDR data rate for the target Pstate in units of MT/s. + // For example enter 0x0640 for DDR1600. + uint8_t DfiFreqRatio; // Byte offset 0x08, CSR Addr 0x54004, Direction=In + // Frequency ratio betwen DfiCtlClk and SDRAM memclk. + // 0x1 = 1:1 + // 0x2 = 1:2 + // 0x4 = 1:4 + uint8_t BPZNResVal ; // Byte offset 0x09, CSR Addr 0x54004, Direction=In + // Must be programmed to match the precision resistor connected to Phy BP_ZN + // 0x00 = Do not program. Use current CSR value. + // 0xf0 = 240 Ohm (recommended value) + // 0x78 = 120 Ohm + // 0x28 = 40 Ohm + // All other values are reserved. + // + uint8_t PhyOdtImpedance; // Byte offset 0x0a, CSR Addr 0x54005, Direction=In + // Must be programmed to the termination impedance in ohms used by PHY during reads. + // + // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start) + // + // See PHY databook for legal termination impedance values. + // + // For digital simulation, any legal value can be used. For silicon, the users must determine the correct value through SI simulation or other methods. + uint8_t PhyDrvImpedance; // Byte offset 0x0b, CSR Addr 0x54005, Direction=In + // Must be programmed to the driver impedance in ohms used by PHY during writes for all DBYTE drivers (DQ/DM/DBI/DQS). + // + // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start) + // + // See PHY databook for legal R_on driver impedance values. + // + // For digital simulation, any value can be used that is not Hi-Z. For silicon, the users must determine the correct value through SI simulation or other methods. + uint8_t PhyVref; // Byte offset 0x0c, CSR Addr 0x54006, Direction=In + // Must be programmed with the Vref level to be used by the PHY during reads + // + // The units of this field are a percentage of VDDQ according to the following equation: + // + // Receiver Vref = VDDQ*PhyVref[6:0]/128 + // + // For example to set Vref at 0.75*VDDQ, set this field to 0x60. + // + // For digital simulation, any legal value can be used. For silicon, the users must calculate the analytical Vref by using the impedances, terminations, and series resistance present in the system. + uint8_t Reserved0D; // Byte offset 0x0d, CSR Addr 0x54006, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved0E; // Byte offset 0x0e, CSR Addr 0x54007, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t CsTestFail; // Byte offset 0x0f, CSR Addr 0x54007, Direction=Out + // This field will be set if training fails on any rank. + // 0x0 = No failures + // non-zero = one or more ranks failed training + uint16_t SequenceCtrl; // Byte offset 0x10, CSR Addr 0x54008, Direction=In + // Controls the training steps to be run. Each bit corresponds to a training step. + // + // If the bit is set to 1, the training step will run. + // If the bit is set to 0, the training step will be skipped. + // + // Training step to bit mapping: + // SequenceCtrl[0] = Run DevInit - Device/phy initialization. Should always be set. + // SequenceCtrl[1] = Run WrLvl - Write leveling + // SequenceCtrl[2] = Run RxEn - Read gate training + // SequenceCtrl[3] = Run RdDQS1D - 1d read dqs training + // SequenceCtrl[4] = RunWrDQ1D - 1d write dq training + // SequenceCtrl[5] = RFU, must be zero + // SequenceCtrl[6] = RFU, must be zero + // SequenceCtrl[7] = RFU, must be zero + // SequenceCtrl[8] = Run RdDeskew - Per lane read dq deskew training + // SequenceCtrl[9] = Run MxRdLat - Max read latency training + // SequenceCtrl[10] = RFU, must be zero + // SequenceCtrl[11] = RFU, must be zero + // SequenceCtrl[12] = Run LPCA - CA Training + // SequenceCtrl[13] = RFU, must be zero + // SequenceCtrl[14] = RFU, must be zero + // SequenceCtrl[15] = RFU, must be zero + // + uint8_t HdtCtrl; // Byte offset 0x12, CSR Addr 0x54009, Direction=In + // To control the total number of debug messages, a verbosity subfield (HdtCtrl, Hardware Debug Trace Control) exists in the message block. Every message has a verbosity level associated with it, and as the HdtCtrl value is increased, less important s messages stop being sent through the mailboxes. The meanings of several major HdtCtrl thresholds are explained below: + // + // 0x05 = Detailed debug messages (e.g. Eye delays) + // 0x0A = Coarse debug messages (e.g. rank information) + // 0xC8 = Stage completion + // 0xC9 = Assertion messages + // 0xFF = Firmware completion messages only + // + // See Training App Note for more detailed information on what messages are included for each threshold. + // + uint8_t Reserved13; // Byte offset 0x13, CSR Addr 0x54009, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t DFIMRLMargin; // Byte offset 0x14, CSR Addr 0x5400a, Direction=In + // Margin added to smallest passing trained DFI Max Read Latency value, in units of DFI clocks. Recommended to be >= 1. See the Training App Note for more details on the training process and the use of this value. + // + // This margin must include the maximum positive drift expected in tDQSCK over the target temperature and voltage range of the users system. + uint8_t Reserved15; // Byte offset 0x15, CSR Addr 0x5400a, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t UseBroadcastMR; // Byte offset 0x16, CSR Addr 0x5400b, Direction=In + // Training firmware can optionally set per rank mode register values for DRAM partial array self-refresh features if desired. + // + // 0x0 = Use MR<0:17>_A0 for rank 0 channel A + // Use MR<0:17>_B0 for rank 0 channel B + // Use MR<0:17>_A1 for rank 1 channel A + // Use MR<0:17>_B1 for rank 1 channel B + // + // 0x1 = Use MR<0:17>_A0 setting for all channels/ranks + // + // This should be set to 1 for all systems. + // + // Note: If setting this to 0, only mode register settings related to DRAM partial array self-refresh may be different between the ranks and channels. All other mode register settings must be the same for all ranks and channels. + uint8_t Reserved17; // Byte offset 0x17, CSR Addr 0x5400b, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t LogToPhyByteMap0; // Byte offset 0x18, CSR Addr 0x5400c, Direction=In + // Physical Byte associated with Channel A logical Byte 0, depending on LogToPhyByteMap0[7] value: + // LogToPhyByteMap0[7]==0: Logical Byte 0 map on Physical Byte 0 + // LogToPhyByteMap0[7]==1: Logical Byte 0 map on Physical Byte LogToPhyByteMap0[6:0] + uint8_t LogToPhyByteMap1; // Byte offset 0x19, CSR Addr 0x5400c, Direction=In + // Physical Byte associated with Channel A logical Byte 1, depending on LogToPhyByteMap1[7] value: + // LogToPhyByteMap1[7]==0: Logical Byte 1 map on Physical Byte 1 + // LogToPhyByteMap1[7]==1: Logical Byte 1 map on Physical Byte LogToPhyByteMap1[6:0] + uint8_t LogToPhyByteMap2; // Byte offset 0x1a, CSR Addr 0x5400d, Direction=In + // Physical Byte associated with Channel A logical Byte 2, depending on LogToPhyByteMap2[7] value: + // LogToPhyByteMap2[7]==0: Logical Byte 2 map on Physical Byte 2 + // LogToPhyByteMap2[7]==1: Logical Byte 2 map on Physical Byte LogToPhyByteMap2[6:0] + uint8_t LogToPhyByteMap3; // Byte offset 0x1b, CSR Addr 0x5400d, Direction=In + // Physical Byte associated with Channel A logical Byte 3, depending on LogToPhyByteMap3[7] value: + // LogToPhyByteMap3[7]==0: Logical Byte 3 map on Physical Byte 3 + // LogToPhyByteMap3[7]==1: Logical Byte 3 map on Physical Byte LogToPhyByteMap3[6:0] + uint8_t LogToPhyByteMap4; // Byte offset 0x1c, CSR Addr 0x5400e, Direction=In + // Physical Byte associated with Channel B logical Byte 0, depending on LogToPhyByteMap4[7] value: + // LogToPhyByteMap4[7]==0: Logical Byte 0 map on Physical Byte 4 + // LogToPhyByteMap4[7]==1: Logical Byte 0 map on Physical Byte LogToPhyByteMap4[6:0] + uint8_t LogToPhyByteMap5; // Byte offset 0x1d, CSR Addr 0x5400e, Direction=In + // Physical Byte associated with Channel B logical Byte 1, depending on LogToPhyByteMap5[7] value: + // LogToPhyByteMap5[7]==0: Logical Byte 1 map on Physical Byte 5 + // LogToPhyByteMap5[7]==1: Logical Byte 1 map on Physical Byte LogToPhyByteMap5[6:0] + uint8_t LogToPhyByteMap6; // Byte offset 0x1e, CSR Addr 0x5400f, Direction=In + // Physical Byte associated with Channel B logical Byte 2, depending on LogToPhyByteMap6[7] value: + // LogToPhyByteMap6[7]==0: Logical Byte 2 map on Physical Byte 6 + // LogToPhyByteMap6[7]==1: Logical Byte 2 map on Physical Byte LogToPhyByteMap6[6:0] + uint8_t LogToPhyByteMap7; // Byte offset 0x1f, CSR Addr 0x5400f, Direction=In + // Physical Byte associated with Channel B logical Byte 3, depending on LogToPhyByteMap7[7] value: + // LogToPhyByteMap7[7]==0: Logical Byte 3 map on Physical Byte 7 + // LogToPhyByteMap7[7]==1: Logical Byte 3 map on Physical Byte LogToPhyByteMap7[6:0] + uint8_t LogToPhyByteMap8; // Byte offset 0x20, CSR Addr 0x54010, Direction=In + // This field is reserved and must be programmed to 0x00. + uint8_t LogToPhyByteMap9; // Byte offset 0x21, CSR Addr 0x54010, Direction=In + // This field is reserved and must be programmed to 0x00. + uint8_t EnabledDQsChA; // Byte offset 0x22, CSR Addr 0x54011, Direction=In + // Total number of DQ bits enabled in PHY Channel A + uint8_t CsPresentChA; // Byte offset 0x23, CSR Addr 0x54011, Direction=In + // Indicates presence of DRAM at each chip select for PHY channel A. + // + // 0x1 = CS0 is populated with DRAM + // 0x3 = CS0 and CS1 are populated with DRAM + // + // All other encodings are illegal + // + int8_t CDD_ChA_RR_1_0; // Byte offset 0x24, CSR Addr 0x54012, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 1 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_RR_0_1; // Byte offset 0x25, CSR Addr 0x54012, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 0 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_RW_1_1; // Byte offset 0x26, CSR Addr 0x54013, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_RW_1_0; // Byte offset 0x27, CSR Addr 0x54013, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_RW_0_1; // Byte offset 0x28, CSR Addr 0x54014, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 0 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_RW_0_0; // Byte offset 0x29, CSR Addr 0x54014, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs0 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WR_1_1; // Byte offset 0x2a, CSR Addr 0x54015, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WR_1_0; // Byte offset 0x2b, CSR Addr 0x54015, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WR_0_1; // Byte offset 0x2c, CSR Addr 0x54016, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WR_0_0; // Byte offset 0x2d, CSR Addr 0x54016, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WW_1_0; // Byte offset 0x2e, CSR Addr 0x54017, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 1 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WW_0_1; // Byte offset 0x2f, CSR Addr 0x54017, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 0 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + uint8_t Reserved30; // Byte offset 0x30, CSR Addr 0x54018, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t MR1_A0; // Byte offset 0x31, CSR Addr 0x54018, Direction=In + // Value to be programmed in DRAM Mode Register 1 {Channel A, Rank 0} + uint8_t MR2_A0; // Byte offset 0x32, CSR Addr 0x54019, Direction=In + // Value to be programmed in DRAM Mode Register 2 {Channel A, Rank 0} + uint8_t MR3_A0; // Byte offset 0x33, CSR Addr 0x54019, Direction=In + // Value to be programmed in DRAM Mode Register 3 {Channel A, Rank 0} + uint8_t Reserved34; // Byte offset 0x34, CSR Addr 0x5401a, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t MR11_A0; // Byte offset 0x35, CSR Addr 0x5401a, Direction=In + // Value to be programmed in DRAM Mode Register 11 {Channel A, Rank 0} + uint8_t MR16_A0; // Byte offset 0x36, CSR Addr 0x5401b, Direction=In + // Value to be programmed in DRAM Mode Register 16 {Channel A, Rank 0} + uint8_t MR17_A0; // Byte offset 0x37, CSR Addr 0x5401b, Direction=In + // Value to be programmed in DRAM Mode Register 17 {Channel A, Rank 0} + uint8_t Reserved38; // Byte offset 0x38, CSR Addr 0x5401c, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t MR1_A1; // Byte offset 0x39, CSR Addr 0x5401c, Direction=In + // Must be programmed the same as MR1_A0 + uint8_t MR2_A1; // Byte offset 0x3a, CSR Addr 0x5401d, Direction=In + // Must be programmed the same as MR2_A0 + uint8_t MR3_A1; // Byte offset 0x3b, CSR Addr 0x5401d, Direction=In + // Must be programmed the same as MR3_A0 + uint8_t Reserved3C; // Byte offset 0x3c, CSR Addr 0x5401e, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t MR11_A1; // Byte offset 0x3d, CSR Addr 0x5401e, Direction=In + // Must be programmed the same as MR11_A0 + uint8_t MR16_A1; // Byte offset 0x3e, CSR Addr 0x5401f, Direction=In + // Value to be programmed in DRAM Mode Register 16 {Channel A, Rank 1} + uint8_t MR17_A1; // Byte offset 0x3f, CSR Addr 0x5401f, Direction=In + // Value to be programmed in DRAM Mode Register 17 {Channel A, Rank 1} + uint8_t Reserved40; // Byte offset 0x40, CSR Addr 0x54020, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved41; // Byte offset 0x41, CSR Addr 0x54020, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved42; // Byte offset 0x42, CSR Addr 0x54021, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved43; // Byte offset 0x43, CSR Addr 0x54021, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved44; // Byte offset 0x44, CSR Addr 0x54022, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved45; // Byte offset 0x45, CSR Addr 0x54022, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved46; // Byte offset 0x46, CSR Addr 0x54023, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved47; // Byte offset 0x47, CSR Addr 0x54023, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t EnabledDQsChB; // Byte offset 0x48, CSR Addr 0x54024, Direction=In + // Total number of DQ bits enabled in PHY Channel B + uint8_t CsPresentChB; // Byte offset 0x49, CSR Addr 0x54024, Direction=In + // Indicates presence of DRAM at each chip select for PHY channel B. + // + // 0x0 = No chip selects are populated with DRAM + // 0x1 = CS0 is populated with DRAM + // 0x3 = CS0 and CS1 are populated with DRAM + // + // All other encodings are illegal + // + int8_t CDD_ChB_RR_1_0; // Byte offset 0x4a, CSR Addr 0x54025, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 1 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_RR_0_1; // Byte offset 0x4b, CSR Addr 0x54025, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 0 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_RW_1_1; // Byte offset 0x4c, CSR Addr 0x54026, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_RW_1_0; // Byte offset 0x4d, CSR Addr 0x54026, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_RW_0_1; // Byte offset 0x4e, CSR Addr 0x54027, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 0 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_RW_0_0; // Byte offset 0x4f, CSR Addr 0x54027, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs01 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WR_1_1; // Byte offset 0x50, CSR Addr 0x54028, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WR_1_0; // Byte offset 0x51, CSR Addr 0x54028, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WR_0_1; // Byte offset 0x52, CSR Addr 0x54029, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WR_0_0; // Byte offset 0x53, CSR Addr 0x54029, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WW_1_0; // Byte offset 0x54, CSR Addr 0x5402a, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 1 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WW_0_1; // Byte offset 0x55, CSR Addr 0x5402a, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 0 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + uint8_t Reserved56; // Byte offset 0x56, CSR Addr 0x5402b, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t MR1_B0; // Byte offset 0x57, CSR Addr 0x5402b, Direction=In + // Must be programmed the same as MR1_A0 + uint8_t MR2_B0; // Byte offset 0x58, CSR Addr 0x5402c, Direction=In + // Must be programmed the same as MR2_A0 + uint8_t MR3_B0; // Byte offset 0x59, CSR Addr 0x5402c, Direction=In + // Must be programmed the same as MR3_A0 + uint8_t Reserved5A; // Byte offset 0x5a, CSR Addr 0x5402d, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t MR11_B0; // Byte offset 0x5b, CSR Addr 0x5402d, Direction=In + // Must be programmed the same as MR11_A0 + uint8_t MR16_B0; // Byte offset 0x5c, CSR Addr 0x5402e, Direction=In + // Value to be programmed in DRAM Mode Register 16 {Channel B, Rank 0} + uint8_t MR17_B0; // Byte offset 0x5d, CSR Addr 0x5402e, Direction=In + // Value to be programmed in DRAM Mode Register 17 {Channel B, Rank 0} + uint8_t Reserved5E; // Byte offset 0x5e, CSR Addr 0x5402f, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t MR1_B1; // Byte offset 0x5f, CSR Addr 0x5402f, Direction=In + // Must be programmed the same as MR1_A0 + uint8_t MR2_B1; // Byte offset 0x60, CSR Addr 0x54030, Direction=In + // Must be programmed the same as MR2_A0 + uint8_t MR3_B1; // Byte offset 0x61, CSR Addr 0x54030, Direction=In + // Must be programmed the same as MR3_A0 + uint8_t Reserved62; // Byte offset 0x62, CSR Addr 0x54031, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t MR11_B1; // Byte offset 0x63, CSR Addr 0x54031, Direction=In + // Must be programmed the same as MR11_A0 + uint8_t MR16_B1; // Byte offset 0x64, CSR Addr 0x54032, Direction=In + // Value to be programmed in DRAM Mode Register 16 {Channel B, Rank 1} + uint8_t MR17_B1; // Byte offset 0x65, CSR Addr 0x54032, Direction=In + // Value to be programmed in DRAM Mode Register 17 {Channel B, Rank 1} + uint8_t Reserved66; // Byte offset 0x66, CSR Addr 0x54033, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved67; // Byte offset 0x67, CSR Addr 0x54033, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved68; // Byte offset 0x68, CSR Addr 0x54034, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved69; // Byte offset 0x69, CSR Addr 0x54034, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved6A; // Byte offset 0x6a, CSR Addr 0x54035, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved6B; // Byte offset 0x6b, CSR Addr 0x54035, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved6C; // Byte offset 0x6c, CSR Addr 0x54036, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved6D; // Byte offset 0x6d, CSR Addr 0x54036, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint16_t PhyConfigOverride; // Byte offset 0x6e, CSR Addr 0x54037, Direction=In + // Override PhyConfig csr. + // 0x0: Use hardware csr value for PhyConfing (recommended) + // Other values: Use value for PhyConfig instead of Hardware value. + // + uint8_t Reserved70; // Byte offset 0x70, CSR Addr 0x54038, Direction=N/A + // This field is reserved and must be programmed to 0x00. +} __attribute__ ((packed)) PMU_SMB_LPDDR3_1D_t;
diff --git a/arch/arm/include/asm/arch-a1/mnPmuSramMsgBlock_lpddr4.h b/arch/arm/include/asm/arch-a1/mnPmuSramMsgBlock_lpddr4.h new file mode 100644 index 0000000..d194621 --- /dev/null +++ b/arch/arm/include/asm/arch-a1/mnPmuSramMsgBlock_lpddr4.h
@@ -0,0 +1,557 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +/** \brief LPDDR4_1D training firmware message block structure + * + * Please refer to the Training Firmware App Note for futher information about + * the usage for Message Block. + */ +typedef struct _PMU_SMB_LPDDR4_1D_t { + uint8_t Reserved00; // Byte offset 0x00, CSR Addr 0x54000, Direction=In + // Reserved00[0:4] RFU, must be zero + // + // Reserved00[5] = Quick Rd2D during 1D Training + // 0x1 = Read Deskew will begin by enabling and quickly training the phy’s per-lane reference voltages. Training the vrefDACs CSRs will increase the maximum 1D training time by around half a millisecond, but will improve 1D training accuracy on systems with significant voltage-offsets between lane read eyes. + // 0X0 = Read Deskew will assume the messageblock’s phyVref setting is optimal for all lanes. + // + // Reserved00[6] = Enable High Effort WrDQ1D + // 0x1 = WrDQ1D will conditionally retry training at several extra RxClkDly Timings. This will increase the maximum 1D training time by up to 4 extra iterations of WrDQ1D. This is only required in systems that suffer from very large, asymmetric eye-collapse when receiving PRBS patterns. + // 0x0 = WrDQ1D assume rxClkDly values found by SI Friendly RdDqs1D will work for receiving PRBS patterns + // + // Reserved00[7] = Optimize for the special hard macros in TSMC28. + // 0x1 = set if the phy being trained was manufactured in any TSMC28 process node. + // 0x0 = otherwise, when not training a TSMC28 phy, leave this field as 0. + uint8_t MsgMisc; // Byte offset 0x01, CSR Addr 0x54000, Direction=In + // Contains various global options for training. + // + // Bit fields: + // + // MsgMisc[0] MTESTEnable + // 0x1 = Pulse primary digital test output bump at the end of each major training stage. This enables observation of training stage completion by observing the digital test output. + // 0x0 = Do not pulse primary digital test output bump + // + // MsgMisc[1] SimulationOnlyReset + // 0x1 = Verilog only simulation option to shorten duration of DRAM reset pulse length to 1ns. + // Must never be set to 1 in silicon. + // 0x0 = Use reset pulse length specifed by JEDEC standard + // + // MsgMisc[2] SimulationOnlyTraining + // 0x1 = Verilog only simulation option to shorten the duration of the training steps by performing fewer iterations. + // Must never be set to 1 in silicon. + // 0x0 = Use standard training duration. + // + // MsgMisc[3] Disable Boot Clock + // 0x1 = Disable boot frequency clock when initializing DRAM. (not recommended) + // 0x0 = Use Boot Frequency Clock + // + // MsgMisc[4] Suppress streaming messages, including assertions, regardless of HdtCtrl setting. + // Stage Completion messages, as well as training completion and error messages are + // Still sent depending on HdtCtrl setting. + // + // MsgMisc[5] PerByteMaxRdLat + // 0x1 = Each DBYTE will return dfi_rddata_valid at the lowest possible latency. This may result in unaligned data between bytes to be returned to the DFI. + // 0x0 = Every DBYTE will return dfi_rddata_valid simultaneously. This will ensure that data bytes will return aligned accesses to the DFI. + // + // MsgMisc[7-6] RFU, must be zero + // + // Notes: + // + // - SimulationOnlyReset and SimulationOnlyTraining can be used to speed up simulation run times, and must never be used in real silicon. Some VIPs may have checks on DRAM reset parameters that may need to be disabled when using SimulationOnlyReset. + uint16_t PmuRevision; // Byte offset 0x02, CSR Addr 0x54001, Direction=Out + // PMU firmware revision ID + // After training is run, this address will contain the revision ID of the firmware + uint8_t Pstate; // Byte offset 0x04, CSR Addr 0x54002, Direction=In + // Must be set to the target Pstate to be trained + // 0x0 = Pstate 0 + // 0x1 = Pstate 1 + // 0x2 = Pstate 2 + // 0x3 = Pstate 3 + // All other encodings are reserved + uint8_t PllBypassEn; // Byte offset 0x05, CSR Addr 0x54002, Direction=In + // Set according to whether target Pstate uses PHY PLL bypass + // 0x0 = PHY PLL is enabled for target Pstate + // 0x1 = PHY PLL is bypassed for target Pstate + uint16_t DRAMFreq; // Byte offset 0x06, CSR Addr 0x54003, Direction=In + // DDR data rate for the target Pstate in units of MT/s. + // For example enter 0x0640 for DDR1600. + uint8_t DfiFreqRatio; // Byte offset 0x08, CSR Addr 0x54004, Direction=In + // Frequency ratio betwen DfiCtlClk and SDRAM memclk. + // 0x1 = 1:1 + // 0x2 = 1:2 + // 0x4 = 1:4 + uint8_t BPZNResVal ; // Byte offset 0x09, CSR Addr 0x54004, Direction=In + // Must be programmed to match the precision resistor connected to Phy BP_ZN + // 0x00 = Do not program. Use current CSR value. + // 0xf0 = 240 Ohm (recommended value) + // 0x78 = 120 Ohm + // 0x28 = 40 Ohm + // All other values are reserved. + // + uint8_t PhyOdtImpedance; // Byte offset 0x0a, CSR Addr 0x54005, Direction=In + // Must be programmed to the termination impedance in ohms used by PHY during reads. + // + // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start) + // + // See PHY databook for legal termination impedance values. + // + // For digital simulation, any legal value can be used. For silicon, the users must determine the correct value through SI simulation or other methods. + uint8_t PhyDrvImpedance; // Byte offset 0x0b, CSR Addr 0x54005, Direction=In + // Must be programmed to the driver impedance in ohms used by PHY during writes for all DBYTE drivers (DQ/DM/DBI/DQS). + // + // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start) + // + // See PHY databook for legal R_on driver impedance values. + // + // For digital simulation, any value can be used that is not Hi-Z. For silicon, the users must determine the correct value through SI simulation or other methods. + uint8_t PhyVref; // Byte offset 0x0c, CSR Addr 0x54006, Direction=In + // Must be programmed with the Vref level to be used by the PHY during reads + // + // The units of this field are a percentage of VDDQ according to the following equation: + // + // Receiver Vref = VDDQ*PhyVref[6:0]/128 + // + // For example to set Vref at 0.25*VDDQ, set this field to 0x20. + // + // For digital simulation, any legal value can be used. For silicon, the users must calculate the analytical Vref by using the impedances, terminations, and series resistance present in the system. + uint8_t Lp4Misc; // Byte offset 0x0d, CSR Addr 0x54006, Direction=In + // Lp4 specific options for training. + // + // Bit fields: + // + // Lp4Misc[0] Enable dfi_reset_n + // + // 0x0 = (Recommended) PHY internal registers control memreset during training, and also after training. + // dfi_reset_n cannot control the PHY BP_MEMRESET_L pin. + // + // 0x1 = Enables dfi_reset_n to control memreset after training. + // PHY Internal registers control memreset during training only. + // To ensure that no glitches occur on BP_MEMRESET at the end of training, + // The MC must drive dfi_reset_n=1'b1 _prior to starting training_ + // + // Lp4Misc[7-1] RFU, must be zero + uint8_t Reserved0E; // Byte offset 0x0e, CSR Addr 0x54007, Direction=In + // Bit Field for enabling optional 2D training features that impact both Rx2D and Tx2D. + // + // Reserved0E[0:3]: bitTimeControl + // Input for increasing the number of data-comparisons 2D runs per (delay,voltage) point. Every time this input increases by 1, the number of 2D data comparisons is doubled. The 2D run time will increase proportionally to the number of bit times requested per point. + // 0 = 288 bits per point (legacy behavior) + // 1 = 576 bits per point + // 2 = 1.125 kilobits per point + // … + // 15 = 9 megabits per point + // + // Reserved0E[4]: Exhaustive2D + // 0 = 2D’s optimization assumes the optimal trained point is near the 1D trained point (legacy behavior) + // 1 = 2D’s optimization searches the entire passing region at the cost of run time. Recommended for optimal results any time the optimal trained point is expected to be near the edges of the eyes instead of near the 1D trained point. + // + // Reserved0E[5:7]: RFU, must be 0 + uint8_t CsTestFail; // Byte offset 0x0f, CSR Addr 0x54007, Direction=Out + // This field will be set if training fails on any rank. + // 0x0 = No failures + // non-zero = one or more ranks failed training + uint16_t SequenceCtrl; // Byte offset 0x10, CSR Addr 0x54008, Direction=In + // Controls the training steps to be run. Each bit corresponds to a training step. + // + // If the bit is set to 1, the training step will run. + // If the bit is set to 0, the training step will be skipped. + // + // Training step to bit mapping: + // SequenceCtrl[0] = Run DevInit - Device/phy initialization. Should always be set. + // SequenceCtrl[1] = Run WrLvl - Write leveling + // SequenceCtrl[2] = Run RxEn - Read gate training + // SequenceCtrl[3] = Run RdDQS1D - 1d read dqs training + // SequenceCtrl[4] = Run WrDQ1D - 1d write dq training + // SequenceCtrl[5] = RFU, must be zero + // SequenceCtrl[6] = RFU, must be zero + // SequenceCtrl[7] = RFU, must be zero + // SequenceCtrl[8] = Run RdDeskew - Per lane read dq deskew training + // SequenceCtrl[9] = Run MxRdLat - Max read latency training + // SequenceCtrl[11-10] = RFU, must be zero + // SequenceCtrl[12] = Run LPCA - CA Training + // SequenceCtrl[15-13] = RFU, must be zero + uint8_t HdtCtrl; // Byte offset 0x12, CSR Addr 0x54009, Direction=In + // To control the total number of debug messages, a verbosity subfield (HdtCtrl, Hardware Debug Trace Control) exists in the message block. Every message has a verbosity level associated with it, and as the HdtCtrl value is increased, less important s messages stop being sent through the mailboxes. The meanings of several major HdtCtrl thresholds are explained below: + // + // 0x05 = Detailed debug messages (e.g. Eye delays) + // 0x0A = Coarse debug messages (e.g. rank information) + // 0xC8 = Stage completion + // 0xC9 = Assertion messages + // 0xFF = Firmware completion messages only + // + // See Training App Note for more detailed information on what messages are included for each threshold. + // + uint8_t Reserved13; // Byte offset 0x13, CSR Addr 0x54009, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved14; // Byte offset 0x14, CSR Addr 0x5400a, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved15; // Byte offset 0x15, CSR Addr 0x5400a, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t DFIMRLMargin; // Byte offset 0x16, CSR Addr 0x5400b, Direction=In + // Margin added to smallest passing trained DFI Max Read Latency value, in units of DFI clocks. Recommended to be >= 1. See the Training App Note for more details on the training process and the use of this value. + // + // This margin must include the maximum positive drift expected in tDQSCK over the target temperature and voltage range of the users system. + uint8_t Reserved17; // Byte offset 0x17, CSR Addr 0x5400b, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t UseBroadcastMR; // Byte offset 0x18, CSR Addr 0x5400c, Direction=In + // Training firmware can optionally set per rank mode register values for DRAM partial array self-refresh features if desired. + // + // 0x0 = Use MR<0:17>_A0 for rank 0 channel A + // Use MR<0:17>_B0 for rank 0 channel B + // Use MR<0:17>_A1 for rank 1 channel A + // Use MR<0:17>_B1 for rank 1 channel B + // + // 0x1 = Use MR<0:17>_A0 setting for all channels/ranks + // + // It is recommended in most LPDDR4 system configurations to set this to 1. + // + // Note: When set to 0, only mode registers associated with Vref CA, Vref DQ, and DRAM partial array self-refresh may differ between ranks and channels. + // + uint8_t Lp4Quickboot; // Byte offset 0x19, CSR Addr 0x5400c, Direction=In + // Enable Quickboot. + uint8_t Reserved1A; // Byte offset 0x1a, CSR Addr 0x5400d, Direction=In + // Input for constraining the range of vref(DQ) values training will collect data for, usually reducing training time. However, too large of a voltage range may cause longer 2D training times while too small of a voltage range may truncate passing regions. When in doubt, leave this field set to 0. + // Used by 2D stages: Rd2D, Wr2D + // + // Reserved1A[0-3]: Rd2D Voltage Range + // 0 = Training will search all phy vref(DQ) settings + // 1 = limit to +/-2 %VDDQ from phyVref + // 2 = limit to +/-4 %VDDQ from phyVref + // … + // 15 = limit to +/-30% VDDQ from phyVref + // + // Reserved1A[4-7]: Wr2D Voltage Range + // 0 = Training will search all dram vref(DQ) settings + // 1 = limit to +/-2 %VDDQ from MR14 + // 2 = limit to +/-4 %VDDQ from MR14 + // … + // 15 = limit to +/-30% VDDQ from MR14 + uint8_t CATrainOpt; // Byte offset 0x1b, CSR Addr 0x5400d, Direction=In + // CA training option bit field + // [0] CA VREF Training + // 1 = Enable CA VREF Training + // 0 = Disable CA VREF Training + // [1-7] RFU must be zero + uint8_t X8Mode; // Byte offset 0x1c, CSR Addr 0x5400e, Direction=In + // X8 mode configuration: + // 0x0 = x16 configuration for all devices + // 0xF = x8 configuration for all devices + // All other values are RFU + uint8_t Reserved1D; // Byte offset 0x1d, CSR Addr 0x5400e, Direction=N/A + + + + + + + + + + + + + + + + + uint8_t Reserved1E; // Byte offset 0x1e, CSR Addr 0x5400f, Direction=N/A + + + + + + + + + + + + + + + + + uint8_t Reserved1F; // Byte offset 0x1f, CSR Addr 0x5400f, Direction=N/A + + + + uint8_t Reserved20; // Byte offset 0x20, CSR Addr 0x54010, Direction=N/A + + uint8_t Reserved21; // Byte offset 0x21, CSR Addr 0x54010, Direction=N/A + + uint16_t PhyConfigOverride; // Byte offset 0x22, CSR Addr 0x54011, Direction=In + // Override PhyConfig csr. + // 0x0: Use hardware csr value for PhyConfing (recommended) + // Other values: Use value for PhyConfig instead of Hardware value. + // + uint8_t EnabledDQsChA; // Byte offset 0x24, CSR Addr 0x54012, Direction=In + // Total number of DQ bits enabled in PHY Channel A + uint8_t CsPresentChA; // Byte offset 0x25, CSR Addr 0x54012, Direction=In + // Indicates presence of DRAM at each chip select for PHY channel A. + // + // 0x1 = CS0 is populated with DRAM + // 0x3 = CS0 and CS1 are populated with DRAM + // + // All other encodings are illegal + // + int8_t CDD_ChA_RR_1_0; // Byte offset 0x26, CSR Addr 0x54013, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 1 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_RR_0_1; // Byte offset 0x27, CSR Addr 0x54013, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 0 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_RW_1_1; // Byte offset 0x28, CSR Addr 0x54014, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_RW_1_0; // Byte offset 0x29, CSR Addr 0x54014, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_RW_0_1; // Byte offset 0x2a, CSR Addr 0x54015, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 0 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_RW_0_0; // Byte offset 0x2b, CSR Addr 0x54015, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs0 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WR_1_1; // Byte offset 0x2c, CSR Addr 0x54016, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WR_1_0; // Byte offset 0x2d, CSR Addr 0x54016, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WR_0_1; // Byte offset 0x2e, CSR Addr 0x54017, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WR_0_0; // Byte offset 0x2f, CSR Addr 0x54017, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WW_1_0; // Byte offset 0x30, CSR Addr 0x54018, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 1 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WW_0_1; // Byte offset 0x31, CSR Addr 0x54018, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 0 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + uint8_t MR1_A0; // Byte offset 0x32, CSR Addr 0x54019, Direction=In + // Value to be programmed in DRAM Mode Register 1 {Channel A, Rank 0} + uint8_t MR2_A0; // Byte offset 0x33, CSR Addr 0x54019, Direction=In + // Value to be programmed in DRAM Mode Register 2 {Channel A, Rank 0} + uint8_t MR3_A0; // Byte offset 0x34, CSR Addr 0x5401a, Direction=In + // Value to be programmed in DRAM Mode Register 3 {Channel A, Rank 0} + uint8_t MR4_A0; // Byte offset 0x35, CSR Addr 0x5401a, Direction=In + // Value to be programmed in DRAM Mode Register 4 {Channel A, Rank 0} + uint8_t MR11_A0; // Byte offset 0x36, CSR Addr 0x5401b, Direction=In + // Value to be programmed in DRAM Mode Register 11 {Channel A, Rank 0} + uint8_t MR12_A0; // Byte offset 0x37, CSR Addr 0x5401b, Direction=In + // Value to be programmed in DRAM Mode Register 12 {Channel A, Rank 0} + uint8_t MR13_A0; // Byte offset 0x38, CSR Addr 0x5401c, Direction=In + // Value to be programmed in DRAM Mode Register 13 {Channel A, Rank 0} + uint8_t MR14_A0; // Byte offset 0x39, CSR Addr 0x5401c, Direction=In + // Value to be programmed in DRAM Mode Register 14 {Channel A, Rank 0} + uint8_t MR16_A0; // Byte offset 0x3a, CSR Addr 0x5401d, Direction=In + // Value to be programmed in DRAM Mode Register 16 {Channel A, Rank 0} + uint8_t MR17_A0; // Byte offset 0x3b, CSR Addr 0x5401d, Direction=In + // Value to be programmed in DRAM Mode Register 17 {Channel A, Rank 0} + uint8_t MR22_A0; // Byte offset 0x3c, CSR Addr 0x5401e, Direction=In + // Value to be programmed in DRAM Mode Register 22 {Channel A, Rank 0} + uint8_t MR24_A0; // Byte offset 0x3d, CSR Addr 0x5401e, Direction=In + // Value to be programmed in DRAM Mode Register 24 {Channel A, Rank 0} + uint8_t MR1_A1; // Byte offset 0x3e, CSR Addr 0x5401f, Direction=In + // Value to be programmed in DRAM Mode Register 1 {Channel A, Rank 1} + uint8_t MR2_A1; // Byte offset 0x3f, CSR Addr 0x5401f, Direction=In + // Value to be programmed in DRAM Mode Register 2 {Channel A, Rank 1} + uint8_t MR3_A1; // Byte offset 0x40, CSR Addr 0x54020, Direction=In + // Value to be programmed in DRAM Mode Register 3 {Channel A, Rank 1} + uint8_t MR4_A1; // Byte offset 0x41, CSR Addr 0x54020, Direction=In + // Value to be programmed in DRAM Mode Register 4 {Channel A, Rank 1} + uint8_t MR11_A1; // Byte offset 0x42, CSR Addr 0x54021, Direction=In + // Value to be programmed in DRAM Mode Register 11 {Channel A, Rank 1} + uint8_t MR12_A1; // Byte offset 0x43, CSR Addr 0x54021, Direction=In + // Value to be programmed in DRAM Mode Register 12 {Channel A, Rank 1} + uint8_t MR13_A1; // Byte offset 0x44, CSR Addr 0x54022, Direction=In + // Value to be programmed in DRAM Mode Register 13 {Channel A, Rank 1} + uint8_t MR14_A1; // Byte offset 0x45, CSR Addr 0x54022, Direction=In + // Value to be programmed in DRAM Mode Register 14 {Channel A, Rank 1} + uint8_t MR16_A1; // Byte offset 0x46, CSR Addr 0x54023, Direction=In + // Value to be programmed in DRAM Mode Register 16 {Channel A, Rank 1} + uint8_t MR17_A1; // Byte offset 0x47, CSR Addr 0x54023, Direction=In + // Value to be programmed in DRAM Mode Register 17 {Channel A, Rank 1} + uint8_t MR22_A1; // Byte offset 0x48, CSR Addr 0x54024, Direction=In + // Value to be programmed in DRAM Mode Register 22 {Channel A, Rank 1} + uint8_t MR24_A1; // Byte offset 0x49, CSR Addr 0x54024, Direction=In + // Value to be programmed in DRAM Mode Register 24 {Channel A, Rank 1} + uint8_t CATerminatingRankChA; // Byte offset 0x4a, CSR Addr 0x54025, Direction=In + // Terminating Rank for CA bus on Channel A + // 0x0 = Rank 0 is terminating rank + // 0x1 = Rank 1 is terminating rank + uint8_t Reserved4B; // Byte offset 0x4b, CSR Addr 0x54025, Direction=N/A + + uint8_t Reserved4C; // Byte offset 0x4c, CSR Addr 0x54026, Direction=N/A + + uint8_t Reserved4D; // Byte offset 0x4d, CSR Addr 0x54026, Direction=N/A + + uint8_t Reserved4E; // Byte offset 0x4e, CSR Addr 0x54027, Direction=N/A + + uint8_t Reserved4F; // Byte offset 0x4f, CSR Addr 0x54027, Direction=N/A + + uint8_t Reserved50; // Byte offset 0x50, CSR Addr 0x54028, Direction=N/A + + uint8_t Reserved51; // Byte offset 0x51, CSR Addr 0x54028, Direction=N/A + + uint8_t Reserved52; // Byte offset 0x52, CSR Addr 0x54029, Direction=N/A + + uint8_t Reserved53; // Byte offset 0x53, CSR Addr 0x54029, Direction=N/A + + uint8_t Reserved54; // Byte offset 0x54, CSR Addr 0x5402a, Direction=N/A + + uint8_t Reserved55; // Byte offset 0x55, CSR Addr 0x5402a, Direction=N/A + + uint8_t Reserved56; // Byte offset 0x56, CSR Addr 0x5402b, Direction=N/A + + uint8_t EnabledDQsChB; // Byte offset 0x57, CSR Addr 0x5402b, Direction=In + // Total number of DQ bits enabled in PHY Channel B + uint8_t CsPresentChB; // Byte offset 0x58, CSR Addr 0x5402c, Direction=In + // Indicates presence of DRAM at each chip select for PHY channel B. + // + // 0x0 = No chip selects are populated with DRAM + // 0x1 = CS0 is populated with DRAM + // 0x3 = CS0 and CS1 are populated with DRAM + // + // All other encodings are illegal + // + int8_t CDD_ChB_RR_1_0; // Byte offset 0x59, CSR Addr 0x5402c, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 1 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_RR_0_1; // Byte offset 0x5a, CSR Addr 0x5402d, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 0 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_RW_1_1; // Byte offset 0x5b, CSR Addr 0x5402d, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_RW_1_0; // Byte offset 0x5c, CSR Addr 0x5402e, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_RW_0_1; // Byte offset 0x5d, CSR Addr 0x5402e, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 0 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_RW_0_0; // Byte offset 0x5e, CSR Addr 0x5402f, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs01 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WR_1_1; // Byte offset 0x5f, CSR Addr 0x5402f, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WR_1_0; // Byte offset 0x60, CSR Addr 0x54030, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WR_0_1; // Byte offset 0x61, CSR Addr 0x54030, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WR_0_0; // Byte offset 0x62, CSR Addr 0x54031, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WW_1_0; // Byte offset 0x63, CSR Addr 0x54031, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 1 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WW_0_1; // Byte offset 0x64, CSR Addr 0x54032, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 0 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + uint8_t MR1_B0; // Byte offset 0x65, CSR Addr 0x54032, Direction=In + // Value to be programmed in DRAM Mode Register 1 {Channel B, Rank 0} + uint8_t MR2_B0; // Byte offset 0x66, CSR Addr 0x54033, Direction=In + // Value to be programmed in DRAM Mode Register 2 {Channel B, Rank 0} + uint8_t MR3_B0; // Byte offset 0x67, CSR Addr 0x54033, Direction=In + // Value to be programmed in DRAM Mode Register 3 {Channel B, Rank 0} + uint8_t MR4_B0; // Byte offset 0x68, CSR Addr 0x54034, Direction=In + // Value to be programmed in DRAM Mode Register 4 {Channel B, Rank 0} + uint8_t MR11_B0; // Byte offset 0x69, CSR Addr 0x54034, Direction=In + // Value to be programmed in DRAM Mode Register 11 {Channel B, Rank 0} + uint8_t MR12_B0; // Byte offset 0x6a, CSR Addr 0x54035, Direction=In + // Value to be programmed in DRAM Mode Register 12 {Channel B, Rank 0} + uint8_t MR13_B0; // Byte offset 0x6b, CSR Addr 0x54035, Direction=In + // Value to be programmed in DRAM Mode Register 13 {Channel B, Rank 0} + uint8_t MR14_B0; // Byte offset 0x6c, CSR Addr 0x54036, Direction=In + // Value to be programmed in DRAM Mode Register 14 {Channel B, Rank 0} + uint8_t MR16_B0; // Byte offset 0x6d, CSR Addr 0x54036, Direction=In + // Value to be programmed in DRAM Mode Register 16 {Channel B, Rank 0} + uint8_t MR17_B0; // Byte offset 0x6e, CSR Addr 0x54037, Direction=In + // Value to be programmed in DRAM Mode Register 17 {Channel B, Rank 0} + uint8_t MR22_B0; // Byte offset 0x6f, CSR Addr 0x54037, Direction=In + // Value to be programmed in DRAM Mode Register 22 {Channel B, Rank 0} + uint8_t MR24_B0; // Byte offset 0x70, CSR Addr 0x54038, Direction=In + // Value to be programmed in DRAM Mode Register 24 {Channel B, Rank 0} + uint8_t MR1_B1; // Byte offset 0x71, CSR Addr 0x54038, Direction=In + // Value to be programmed in DRAM Mode Register 1 {Channel B, Rank 1} + uint8_t MR2_B1; // Byte offset 0x72, CSR Addr 0x54039, Direction=In + // Value to be programmed in DRAM Mode Register 2 {Channel B, Rank 1} + uint8_t MR3_B1; // Byte offset 0x73, CSR Addr 0x54039, Direction=In + // Value to be programmed in DRAM Mode Register 3 {Channel B, Rank 1} + uint8_t MR4_B1; // Byte offset 0x74, CSR Addr 0x5403a, Direction=In + // Value to be programmed in DRAM Mode Register 4 {Channel B, Rank 1} + uint8_t MR11_B1; // Byte offset 0x75, CSR Addr 0x5403a, Direction=In + // Value to be programmed in DRAM Mode Register 11 {Channel B, Rank 1} + uint8_t MR12_B1; // Byte offset 0x76, CSR Addr 0x5403b, Direction=In + // Value to be programmed in DRAM Mode Register 12 {Channel B, Rank 1} + uint8_t MR13_B1; // Byte offset 0x77, CSR Addr 0x5403b, Direction=In + // Value to be programmed in DRAM Mode Register 13 {Channel B, Rank 1} + uint8_t MR14_B1; // Byte offset 0x78, CSR Addr 0x5403c, Direction=In + // Value to be programmed in DRAM Mode Register 14 {Channel B, Rank 1} + uint8_t MR16_B1; // Byte offset 0x79, CSR Addr 0x5403c, Direction=In + // Value to be programmed in DRAM Mode Register 16 {Channel B, Rank 1} + uint8_t MR17_B1; // Byte offset 0x7a, CSR Addr 0x5403d, Direction=In + // Value to be programmed in DRAM Mode Register 17 {Channel B, Rank 1} + uint8_t MR22_B1; // Byte offset 0x7b, CSR Addr 0x5403d, Direction=In + // Value to be programmed in DRAM Mode Register 22 {Channel B, Rank 1} + uint8_t MR24_B1; // Byte offset 0x7c, CSR Addr 0x5403e, Direction=In + // Value to be programmed in DRAM Mode Register 24 {Channel B, Rank 1} + uint8_t CATerminatingRankChB; // Byte offset 0x7d, CSR Addr 0x5403e, Direction=In + // Terminating Rank for CA bus on Channel B + // 0x0 = Rank 0 is terminating rank + // 0x1 = Rank 1 is terminating rank + uint8_t Reserved7E; // Byte offset 0x7e, CSR Addr 0x5403f, Direction=N/A + + uint8_t Reserved7F; // Byte offset 0x7f, CSR Addr 0x5403f, Direction=N/A + + uint8_t Reserved80; // Byte offset 0x80, CSR Addr 0x54040, Direction=N/A + + uint8_t Reserved81; // Byte offset 0x81, CSR Addr 0x54040, Direction=N/A + + uint8_t Reserved82; // Byte offset 0x82, CSR Addr 0x54041, Direction=N/A + + uint8_t Reserved83; // Byte offset 0x83, CSR Addr 0x54041, Direction=N/A + + uint8_t Reserved84; // Byte offset 0x84, CSR Addr 0x54042, Direction=N/A + + uint8_t Reserved85; // Byte offset 0x85, CSR Addr 0x54042, Direction=N/A + + uint8_t Reserved86; // Byte offset 0x86, CSR Addr 0x54043, Direction=N/A + + uint8_t Reserved87; // Byte offset 0x87, CSR Addr 0x54043, Direction=N/A + + uint8_t Reserved88; // Byte offset 0x88, CSR Addr 0x54044, Direction=N/A + + uint8_t Reserved89; // Byte offset 0x89, CSR Addr 0x54044, Direction=N/A + +} __attribute__ ((packed)) PMU_SMB_LPDDR4_1D_t;
diff --git a/arch/arm/include/asm/arch-a1/mnPmuSramMsgBlock_lpddr4_2d.h b/arch/arm/include/asm/arch-a1/mnPmuSramMsgBlock_lpddr4_2d.h new file mode 100644 index 0000000..c6ab3d3 --- /dev/null +++ b/arch/arm/include/asm/arch-a1/mnPmuSramMsgBlock_lpddr4_2d.h
@@ -0,0 +1,557 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +/** \brief LPDDR4_2D training firmware message block structure + * + * Please refer to the Training Firmware App Note for futher information about + * the usage for Message Block. + */ +typedef struct _PMU_SMB_LPDDR4_2D_t { + uint8_t Reserved00; // Byte offset 0x00, CSR Addr 0x54000, Direction=In + // Reserved00[0:4] RFU, must be zero + // + // Reserved00[5] = Quick Rd2D during 1D Training + // 0x1 = Read Deskew will begin by enabling and quickly training the phy’s per-lane reference voltages. Training the vrefDACs CSRs will increase the maximum 1D training time by around half a millisecond, but will improve 1D training accuracy on systems with significant voltage-offsets between lane read eyes. + // 0X0 = Read Deskew will assume the messageblock’s phyVref setting is optimal for all lanes. + // + // Reserved00[6] = Enable High Effort WrDQ1D + // 0x1 = WrDQ1D will conditionally retry training at several extra RxClkDly Timings. This will increase the maximum 1D training time by up to 4 extra iterations of WrDQ1D. This is only required in systems that suffer from very large, asymmetric eye-collapse when receiving PRBS patterns. + // 0x0 = WrDQ1D assume rxClkDly values found by SI Friendly RdDqs1D will work for receiving PRBS patterns + // + // Reserved00[7] = Optimize for the special hard macros in TSMC28. + // 0x1 = set if the phy being trained was manufactured in any TSMC28 process node. + // 0x0 = otherwise, when not training a TSMC28 phy, leave this field as 0. + uint8_t MsgMisc; // Byte offset 0x01, CSR Addr 0x54000, Direction=In + // Contains various global options for training. + // + // Bit fields: + // + // MsgMisc[0] MTESTEnable + // 0x1 = Pulse primary digital test output bump at the end of each major training stage. This enables observation of training stage completion by observing the digital test output. + // 0x0 = Do not pulse primary digital test output bump + // + // MsgMisc[1] SimulationOnlyReset + // 0x1 = Verilog only simulation option to shorten duration of DRAM reset pulse length to 1ns. + // Must never be set to 1 in silicon. + // 0x0 = Use reset pulse length specifed by JEDEC standard + // + // MsgMisc[2] SimulationOnlyTraining + // 0x1 = Verilog only simulation option to shorten the duration of the training steps by performing fewer iterations. + // Must never be set to 1 in silicon. + // 0x0 = Use standard training duration. + // + // MsgMisc[3] Disable Boot Clock + // 0x1 = Disable boot frequency clock when initializing DRAM. (not recommended) + // 0x0 = Use Boot Frequency Clock + // + // MsgMisc[4] Suppress streaming messages, including assertions, regardless of HdtCtrl setting. + // Stage Completion messages, as well as training completion and error messages are + // Still sent depending on HdtCtrl setting. + // + // MsgMisc[5] PerByteMaxRdLat + // 0x1 = Each DBYTE will return dfi_rddata_valid at the lowest possible latency. This may result in unaligned data between bytes to be returned to the DFI. + // 0x0 = Every DBYTE will return dfi_rddata_valid simultaneously. This will ensure that data bytes will return aligned accesses to the DFI. + // + // MsgMisc[7-6] RFU, must be zero + // + // Notes: + // + // - SimulationOnlyReset and SimulationOnlyTraining can be used to speed up simulation run times, and must never be used in real silicon. Some VIPs may have checks on DRAM reset parameters that may need to be disabled when using SimulationOnlyReset. + uint16_t PmuRevision; // Byte offset 0x02, CSR Addr 0x54001, Direction=Out + // PMU firmware revision ID + // After training is run, this address will contain the revision ID of the firmware + uint8_t Pstate; // Byte offset 0x04, CSR Addr 0x54002, Direction=In + // Must be set to the target Pstate to be trained + // 0x0 = Pstate 0 + // 0x1 = Pstate 1 + // 0x2 = Pstate 2 + // 0x3 = Pstate 3 + // All other encodings are reserved + uint8_t PllBypassEn; // Byte offset 0x05, CSR Addr 0x54002, Direction=In + // Set according to whether target Pstate uses PHY PLL bypass + // 0x0 = PHY PLL is enabled for target Pstate + // 0x1 = PHY PLL is bypassed for target Pstate + uint16_t DRAMFreq; // Byte offset 0x06, CSR Addr 0x54003, Direction=In + // DDR data rate for the target Pstate in units of MT/s. + // For example enter 0x0640 for DDR1600. + uint8_t DfiFreqRatio; // Byte offset 0x08, CSR Addr 0x54004, Direction=In + // Frequency ratio betwen DfiCtlClk and SDRAM memclk. + // 0x1 = 1:1 + // 0x2 = 1:2 + // 0x4 = 1:4 + uint8_t BPZNResVal ; // Byte offset 0x09, CSR Addr 0x54004, Direction=In + // Must be programmed to match the precision resistor connected to Phy BP_ZN + // 0x00 = Do not program. Use current CSR value. + // 0xf0 = 240 Ohm (recommended value) + // 0x78 = 120 Ohm + // 0x28 = 40 Ohm + // All other values are reserved. + // + uint8_t PhyOdtImpedance; // Byte offset 0x0a, CSR Addr 0x54005, Direction=In + // Must be programmed to the termination impedance in ohms used by PHY during reads. + // + // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start) + // + // See PHY databook for legal termination impedance values. + // + // For digital simulation, any legal value can be used. For silicon, the users must determine the correct value through SI simulation or other methods. + uint8_t PhyDrvImpedance; // Byte offset 0x0b, CSR Addr 0x54005, Direction=In + // Must be programmed to the driver impedance in ohms used by PHY during writes for all DBYTE drivers (DQ/DM/DBI/DQS). + // + // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start) + // + // See PHY databook for legal R_on driver impedance values. + // + // For digital simulation, any value can be used that is not Hi-Z. For silicon, the users must determine the correct value through SI simulation or other methods. + uint8_t PhyVref; // Byte offset 0x0c, CSR Addr 0x54006, Direction=In + // Must be programmed with the Vref level to be used by the PHY during reads + // + // The units of this field are a percentage of VDDQ according to the following equation: + // + // Receiver Vref = VDDQ*PhyVref[6:0]/128 + // + // For example to set Vref at 0.25*VDDQ, set this field to 0x20. + // + // For digital simulation, any legal value can be used. For silicon, the users must calculate the analytical Vref by using the impedances, terminations, and series resistance present in the system. + uint8_t Lp4Misc; // Byte offset 0x0d, CSR Addr 0x54006, Direction=In + // Lp4 specific options for training. + // + // Bit fields: + // + // Lp4Misc[0] Enable dfi_reset_n + // + // 0x0 = (Recommended) PHY internal registers control memreset during training, and also after training. + // dfi_reset_n cannot control the PHY BP_MEMRESET_L pin. + // + // 0x1 = Enables dfi_reset_n to control memreset after training. + // PHY Internal registers control memreset during training only. + // To ensure that no glitches occur on BP_MEMRESET at the end of training, + // The MC must drive dfi_reset_n=1'b1 _prior to starting training_ + // + // Lp4Misc[7-1] RFU, must be zero + uint8_t Reserved0E; // Byte offset 0x0e, CSR Addr 0x54007, Direction=In + // Bit Field for enabling optional 2D training features that impact both Rx2D and Tx2D. + // + // Reserved0E[0:3]: bitTimeControl + // Input for increasing the number of data-comparisons 2D runs per (delay,voltage) point. Every time this input increases by 1, the number of 2D data comparisons is doubled. The 2D run time will increase proportionally to the number of bit times requested per point. + // 0 = 288 bits per point (legacy behavior) + // 1 = 576 bits per point + // 2 = 1.125 kilobits per point + // … + // 15 = 9 megabits per point + // + // Reserved0E[4]: Exhaustive2D + // 0 = 2D’s optimization assumes the optimal trained point is near the 1D trained point (legacy behavior) + // 1 = 2D’s optimization searches the entire passing region at the cost of run time. Recommended for optimal results any time the optimal trained point is expected to be near the edges of the eyes instead of near the 1D trained point. + // + // Reserved0E[5:7]: RFU, must be 0 + uint8_t CsTestFail; // Byte offset 0x0f, CSR Addr 0x54007, Direction=Out + // This field will be set if training fails on any rank. + // 0x0 = No failures + // non-zero = one or more ranks failed training + uint16_t SequenceCtrl; // Byte offset 0x10, CSR Addr 0x54008, Direction=In + // Controls the training steps to be run. Each bit corresponds to a training step. + // + // If the bit is set to 1, the training step will run. + // If the bit is set to 0, the training step will be skipped. + // + // Training step to bit mapping: + // SequenceCtrl[0] = Run DevInit - Device/phy initialization. Should always be set. + // SequenceCtrl[1] = RFU, must be zero + // SequenceCtrl[2] = RFU, must be zero + // SequenceCtrl[3] = RFU, must be zero + // SequenceCtrl[4] = RFU, must be zero + // SequenceCtrl[5] = Run rd2D - 2d read dqs training + // SequenceCtrl[6] = Run wr2D - 2d write dq training + // SequenceCtrl[7] = RFU, must be zero + // SequenceCtrl[8] = RFU, must be zero + // SequenceCtrl[9] = RFU, must be zero + // SequenceCtrl[11-10] = RFU, must be zero + // SequenceCtrl[12] = RFU, must be zero + // SequenceCtrl[15-13] = RFU, must be zero + uint8_t HdtCtrl; // Byte offset 0x12, CSR Addr 0x54009, Direction=In + // To control the total number of debug messages, a verbosity subfield (HdtCtrl, Hardware Debug Trace Control) exists in the message block. Every message has a verbosity level associated with it, and as the HdtCtrl value is increased, less important s messages stop being sent through the mailboxes. The meanings of several major HdtCtrl thresholds are explained below: + // + // 0x05 = Detailed debug messages (e.g. Eye delays) + // 0x0A = Coarse debug messages (e.g. rank information) + // 0xC8 = Stage completion + // 0xC9 = Assertion messages + // 0xFF = Firmware completion messages only + // + // See Training App Note for more detailed information on what messages are included for each threshold. + // + uint8_t Reserved13; // Byte offset 0x13, CSR Addr 0x54009, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved14; // Byte offset 0x14, CSR Addr 0x5400a, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved15; // Byte offset 0x15, CSR Addr 0x5400a, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t DFIMRLMargin; // Byte offset 0x16, CSR Addr 0x5400b, Direction=In + // Margin added to smallest passing trained DFI Max Read Latency value, in units of DFI clocks. Recommended to be >= 1. See the Training App Note for more details on the training process and the use of this value. + // + // This margin must include the maximum positive drift expected in tDQSCK over the target temperature and voltage range of the users system. + uint8_t Reserved17; // Byte offset 0x17, CSR Addr 0x5400b, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t UseBroadcastMR; // Byte offset 0x18, CSR Addr 0x5400c, Direction=In + // Training firmware can optionally set per rank mode register values for DRAM partial array self-refresh features if desired. + // + // 0x0 = Use MR<0:17>_A0 for rank 0 channel A + // Use MR<0:17>_B0 for rank 0 channel B + // Use MR<0:17>_A1 for rank 1 channel A + // Use MR<0:17>_B1 for rank 1 channel B + // + // 0x1 = Use MR<0:17>_A0 setting for all channels/ranks + // + // It is recommended in most LPDDR4 system configurations to set this to 1. + // + // Note: When set to 0, only mode registers associated with Vref CA, Vref DQ, and DRAM partial array self-refresh may differ between ranks and channels. + // + uint8_t Reserved19; // Byte offset 0x19, CSR Addr 0x5400c, Direction=N/A + + uint8_t Reserved1A; // Byte offset 0x1a, CSR Addr 0x5400d, Direction=In + // Input for constraining the range of vref(DQ) values training will collect data for, usually reducing training time. However, too large of a voltage range may cause longer 2D training times while too small of a voltage range may truncate passing regions. When in doubt, leave this field set to 0. + // Used by 2D stages: Rd2D, Wr2D + // + // Reserved1A[0-3]: Rd2D Voltage Range + // 0 = Training will search all phy vref(DQ) settings + // 1 = limit to +/-2 %VDDQ from phyVref + // 2 = limit to +/-4 %VDDQ from phyVref + // … + // 15 = limit to +/-30% VDDQ from phyVref + // + // Reserved1A[4-7]: Wr2D Voltage Range + // 0 = Training will search all dram vref(DQ) settings + // 1 = limit to +/-2 %VDDQ from MR14 + // 2 = limit to +/-4 %VDDQ from MR14 + // … + // 15 = limit to +/-30% VDDQ from MR14 + uint8_t CATrainOpt; // Byte offset 0x1b, CSR Addr 0x5400d, Direction=In + // CA training option bit field + // [0] CA VREF Setting + // 1 = Set MR12 from internal register + // 0 = Set MR12 from message block + // [1-7] RFU must be zero + uint8_t X8Mode; // Byte offset 0x1c, CSR Addr 0x5400e, Direction=In + // X8 mode configuration: + // 0x0 = x16 configuration for all devices + // 0xF = x8 configuration for all devices + // All other values are RFU + uint8_t RX2D_TrainOpt; // Byte offset 0x1d, CSR Addr 0x5400e, Direction=In + // Bit fields, if 2D read training enabled, then use these additional options: + // [0] DFE + // 1 = Run rx2D with DFE + // 0 = Run rx2D with DFE off + // [1-2] Voltage Step Size (2^n) + // 3 = 8 DAC settings between checked values + // 2 = 4 DAC settings between checked values + // 1 = 2 DAC settings between checked values + // 0 = 1 DAC settings between checked values + // [3-4] Delay Step Size (2^n) + // 3 = 8 LCDL delays between checked values + // 2 = 4 LCDL delays between checked values + // 1 = 2 LCDL delays between checked values + // 0 = 1 LCDL delays between checked values + // [5-7] RFU, must be zero + // + uint8_t TX2D_TrainOpt; // Byte offset 0x1e, CSR Addr 0x5400f, Direction=In + // Bit fields, if 2D write training is enabled, then use these additional options: + // [0] FFE + // 1 = Train tx2D with FFE + // 0 = Train tx2D with FFE off + // [1-2] Voltage Step Size (2^n) + // 3 = 8 DAC settings between checked values + // 2 = 4 DAC settings between checked values + // 1 = 2 DAC settings between checked values + // 0 = 1 DAC settings between checked values + // [3-4] Delay Step Size (2^n) + // 3 = 8 LCDL delays between checked values + // 2 = 4 LCDL delays between checked values + // 1 = 2 LCDL delays between checked values + // 0 = 1 LCDL delays between checked values + // [5-7] RFU, must be zero + // + uint8_t Share2DVrefResult; // Byte offset 0x1f, CSR Addr 0x5400f, Direction=In + // Bitmap that designates the phy's vref source for every pstate + // If Share2DVrefResult[x] = 0, then after 2D training, pstate x will continue using the phyVref provided in pstate x’s 1D messageblock. + // If Share2DVrefResult[x] = 1, then after 2D training, pstate x will use the per-lane VrefDAC0/1 CSRs trained by 2d training. + uint8_t Delay_Weight2D; // Byte offset 0x20, CSR Addr 0x54010, Direction=In + // During 2D training, the ideal eye center changes depending on how valuable delay margin is compared to voltage margin. delay_weight2D sets the value, or weight, of one step of delay margin. The ratio of voltage_weight2D to delay_weight2D will be used by 2D training to choose your preferred center point. There are 32 delay steps in a perfect eye. + uint8_t Voltage_Weight2D; // Byte offset 0x21, CSR Addr 0x54010, Direction=In + // During 2D training, the ideal eye center changes depending on how valuable voltage margin is compared to delay margin. voltage_weight2D sets the value, or weight, of one step of voltage margin. The ratio of voltage_weight2D to delay_weight2D will be used by 2D training to choose your preferred center point. There are 128 voltage steps in a perfect eye. + uint16_t PhyConfigOverride; // Byte offset 0x22, CSR Addr 0x54011, Direction=In + // Override PhyConfig csr. + // 0x0: Use hardware csr value for PhyConfing (recommended) + // Other values: Use value for PhyConfig instead of Hardware value. + // + uint8_t EnabledDQsChA; // Byte offset 0x24, CSR Addr 0x54012, Direction=In + // Total number of DQ bits enabled in PHY Channel A + uint8_t CsPresentChA; // Byte offset 0x25, CSR Addr 0x54012, Direction=In + // Indicates presence of DRAM at each chip select for PHY channel A. + // + // 0x1 = CS0 is populated with DRAM + // 0x3 = CS0 and CS1 are populated with DRAM + // + // All other encodings are illegal + // + int8_t CDD_ChA_RR_1_0; // Byte offset 0x26, CSR Addr 0x54013, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 1 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_RR_0_1; // Byte offset 0x27, CSR Addr 0x54013, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 0 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_RW_1_1; // Byte offset 0x28, CSR Addr 0x54014, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_RW_1_0; // Byte offset 0x29, CSR Addr 0x54014, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_RW_0_1; // Byte offset 0x2a, CSR Addr 0x54015, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 0 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_RW_0_0; // Byte offset 0x2b, CSR Addr 0x54015, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs0 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WR_1_1; // Byte offset 0x2c, CSR Addr 0x54016, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WR_1_0; // Byte offset 0x2d, CSR Addr 0x54016, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WR_0_1; // Byte offset 0x2e, CSR Addr 0x54017, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WR_0_0; // Byte offset 0x2f, CSR Addr 0x54017, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WW_1_0; // Byte offset 0x30, CSR Addr 0x54018, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 1 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WW_0_1; // Byte offset 0x31, CSR Addr 0x54018, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 0 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + uint8_t MR1_A0; // Byte offset 0x32, CSR Addr 0x54019, Direction=In + // Value to be programmed in DRAM Mode Register 1 {Channel A, Rank 0} + uint8_t MR2_A0; // Byte offset 0x33, CSR Addr 0x54019, Direction=In + // Value to be programmed in DRAM Mode Register 2 {Channel A, Rank 0} + uint8_t MR3_A0; // Byte offset 0x34, CSR Addr 0x5401a, Direction=In + // Value to be programmed in DRAM Mode Register 3 {Channel A, Rank 0} + uint8_t MR4_A0; // Byte offset 0x35, CSR Addr 0x5401a, Direction=In + // Value to be programmed in DRAM Mode Register 4 {Channel A, Rank 0} + uint8_t MR11_A0; // Byte offset 0x36, CSR Addr 0x5401b, Direction=In + // Value to be programmed in DRAM Mode Register 11 {Channel A, Rank 0} + uint8_t MR12_A0; // Byte offset 0x37, CSR Addr 0x5401b, Direction=In + // Value to be programmed in DRAM Mode Register 12 {Channel A, Rank 0} + uint8_t MR13_A0; // Byte offset 0x38, CSR Addr 0x5401c, Direction=In + // Value to be programmed in DRAM Mode Register 13 {Channel A, Rank 0} + uint8_t MR14_A0; // Byte offset 0x39, CSR Addr 0x5401c, Direction=In + // Value to be programmed in DRAM Mode Register 14 {Channel A, Rank 0} + uint8_t MR16_A0; // Byte offset 0x3a, CSR Addr 0x5401d, Direction=In + // Value to be programmed in DRAM Mode Register 16 {Channel A, Rank 0} + uint8_t MR17_A0; // Byte offset 0x3b, CSR Addr 0x5401d, Direction=In + // Value to be programmed in DRAM Mode Register 17 {Channel A, Rank 0} + uint8_t MR22_A0; // Byte offset 0x3c, CSR Addr 0x5401e, Direction=In + // Value to be programmed in DRAM Mode Register 22 {Channel A, Rank 0} + uint8_t MR24_A0; // Byte offset 0x3d, CSR Addr 0x5401e, Direction=In + // Value to be programmed in DRAM Mode Register 24 {Channel A, Rank 0} + uint8_t MR1_A1; // Byte offset 0x3e, CSR Addr 0x5401f, Direction=In + // Value to be programmed in DRAM Mode Register 1 {Channel A, Rank 1} + uint8_t MR2_A1; // Byte offset 0x3f, CSR Addr 0x5401f, Direction=In + // Value to be programmed in DRAM Mode Register 2 {Channel A, Rank 1} + uint8_t MR3_A1; // Byte offset 0x40, CSR Addr 0x54020, Direction=In + // Value to be programmed in DRAM Mode Register 3 {Channel A, Rank 1} + uint8_t MR4_A1; // Byte offset 0x41, CSR Addr 0x54020, Direction=In + // Value to be programmed in DRAM Mode Register 4 {Channel A, Rank 1} + uint8_t MR11_A1; // Byte offset 0x42, CSR Addr 0x54021, Direction=In + // Value to be programmed in DRAM Mode Register 11 {Channel A, Rank 1} + uint8_t MR12_A1; // Byte offset 0x43, CSR Addr 0x54021, Direction=In + // Value to be programmed in DRAM Mode Register 12 {Channel A, Rank 1} + uint8_t MR13_A1; // Byte offset 0x44, CSR Addr 0x54022, Direction=In + // Value to be programmed in DRAM Mode Register 13 {Channel A, Rank 1} + uint8_t MR14_A1; // Byte offset 0x45, CSR Addr 0x54022, Direction=In + // Value to be programmed in DRAM Mode Register 14 {Channel A, Rank 1} + uint8_t MR16_A1; // Byte offset 0x46, CSR Addr 0x54023, Direction=In + // Value to be programmed in DRAM Mode Register 16 {Channel A, Rank 1} + uint8_t MR17_A1; // Byte offset 0x47, CSR Addr 0x54023, Direction=In + // Value to be programmed in DRAM Mode Register 17 {Channel A, Rank 1} + uint8_t MR22_A1; // Byte offset 0x48, CSR Addr 0x54024, Direction=In + // Value to be programmed in DRAM Mode Register 22 {Channel A, Rank 1} + uint8_t MR24_A1; // Byte offset 0x49, CSR Addr 0x54024, Direction=In + // Value to be programmed in DRAM Mode Register 24 {Channel A, Rank 1} + uint8_t CATerminatingRankChA; // Byte offset 0x4a, CSR Addr 0x54025, Direction=In + // Terminating Rank for CA bus on Channel A + // 0x0 = Rank 0 is terminating rank + // 0x1 = Rank 1 is terminating rank + uint8_t Reserved4B; // Byte offset 0x4b, CSR Addr 0x54025, Direction=N/A + + uint8_t Reserved4C; // Byte offset 0x4c, CSR Addr 0x54026, Direction=N/A + + uint8_t TrainedVREFDQ_A0; // Byte offset 0x4d, CSR Addr 0x54026, Direction=Out + // Trained DQ Vref setting for Ch A Rank 0 + uint8_t TrainedVREFDQ_A1; // Byte offset 0x4e, CSR Addr 0x54027, Direction=Out + // Trained DQ Vref setting for Ch A Rank 1 + uint8_t RxClkDly_Margin_A0; // Byte offset 0x4f, CSR Addr 0x54027, Direction=Out + // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group. + uint8_t VrefDac_Margin_A0; // Byte offset 0x50, CSR Addr 0x54028, Direction=Out + // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group. + uint8_t TxDqDly_Margin_A0; // Byte offset 0x51, CSR Addr 0x54028, Direction=Out + // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group. + uint8_t DeviceVref_Margin_A0; // Byte offset 0x52, CSR Addr 0x54029, Direction=Out + // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group. + uint8_t RxClkDly_Margin_A1; // Byte offset 0x53, CSR Addr 0x54029, Direction=Out + // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group. + uint8_t VrefDac_Margin_A1; // Byte offset 0x54, CSR Addr 0x5402a, Direction=Out + // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group. + uint8_t TxDqDly_Margin_A1; // Byte offset 0x55, CSR Addr 0x5402a, Direction=Out + // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group. + uint8_t DeviceVref_Margin_A1; // Byte offset 0x56, CSR Addr 0x5402b, Direction=Out + // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group. + uint8_t EnabledDQsChB; // Byte offset 0x57, CSR Addr 0x5402b, Direction=In + // Total number of DQ bits enabled in PHY Channel B + uint8_t CsPresentChB; // Byte offset 0x58, CSR Addr 0x5402c, Direction=In + // Indicates presence of DRAM at each chip select for PHY channel B. + // + // 0x0 = No chip selects are populated with DRAM + // 0x1 = CS0 is populated with DRAM + // 0x3 = CS0 and CS1 are populated with DRAM + // + // All other encodings are illegal + // + int8_t CDD_ChB_RR_1_0; // Byte offset 0x59, CSR Addr 0x5402c, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 1 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_RR_0_1; // Byte offset 0x5a, CSR Addr 0x5402d, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 0 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_RW_1_1; // Byte offset 0x5b, CSR Addr 0x5402d, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_RW_1_0; // Byte offset 0x5c, CSR Addr 0x5402e, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_RW_0_1; // Byte offset 0x5d, CSR Addr 0x5402e, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 0 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_RW_0_0; // Byte offset 0x5e, CSR Addr 0x5402f, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs01 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WR_1_1; // Byte offset 0x5f, CSR Addr 0x5402f, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WR_1_0; // Byte offset 0x60, CSR Addr 0x54030, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WR_0_1; // Byte offset 0x61, CSR Addr 0x54030, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WR_0_0; // Byte offset 0x62, CSR Addr 0x54031, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WW_1_0; // Byte offset 0x63, CSR Addr 0x54031, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 1 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WW_0_1; // Byte offset 0x64, CSR Addr 0x54032, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 0 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + uint8_t MR1_B0; // Byte offset 0x65, CSR Addr 0x54032, Direction=In + // Value to be programmed in DRAM Mode Register 1 {Channel B, Rank 0} + uint8_t MR2_B0; // Byte offset 0x66, CSR Addr 0x54033, Direction=In + // Value to be programmed in DRAM Mode Register 2 {Channel B, Rank 0} + uint8_t MR3_B0; // Byte offset 0x67, CSR Addr 0x54033, Direction=In + // Value to be programmed in DRAM Mode Register 3 {Channel B, Rank 0} + uint8_t MR4_B0; // Byte offset 0x68, CSR Addr 0x54034, Direction=In + // Value to be programmed in DRAM Mode Register 4 {Channel B, Rank 0} + uint8_t MR11_B0; // Byte offset 0x69, CSR Addr 0x54034, Direction=In + // Value to be programmed in DRAM Mode Register 11 {Channel B, Rank 0} + uint8_t MR12_B0; // Byte offset 0x6a, CSR Addr 0x54035, Direction=In + // Value to be programmed in DRAM Mode Register 12 {Channel B, Rank 0} + uint8_t MR13_B0; // Byte offset 0x6b, CSR Addr 0x54035, Direction=In + // Value to be programmed in DRAM Mode Register 13 {Channel B, Rank 0} + uint8_t MR14_B0; // Byte offset 0x6c, CSR Addr 0x54036, Direction=In + // Value to be programmed in DRAM Mode Register 14 {Channel B, Rank 0} + uint8_t MR16_B0; // Byte offset 0x6d, CSR Addr 0x54036, Direction=In + // Value to be programmed in DRAM Mode Register 16 {Channel B, Rank 0} + uint8_t MR17_B0; // Byte offset 0x6e, CSR Addr 0x54037, Direction=In + // Value to be programmed in DRAM Mode Register 17 {Channel B, Rank 0} + uint8_t MR22_B0; // Byte offset 0x6f, CSR Addr 0x54037, Direction=In + // Value to be programmed in DRAM Mode Register 22 {Channel B, Rank 0} + uint8_t MR24_B0; // Byte offset 0x70, CSR Addr 0x54038, Direction=In + // Value to be programmed in DRAM Mode Register 24 {Channel B, Rank 0} + uint8_t MR1_B1; // Byte offset 0x71, CSR Addr 0x54038, Direction=In + // Value to be programmed in DRAM Mode Register 1 {Channel B, Rank 1} + uint8_t MR2_B1; // Byte offset 0x72, CSR Addr 0x54039, Direction=In + // Value to be programmed in DRAM Mode Register 2 {Channel B, Rank 1} + uint8_t MR3_B1; // Byte offset 0x73, CSR Addr 0x54039, Direction=In + // Value to be programmed in DRAM Mode Register 3 {Channel B, Rank 1} + uint8_t MR4_B1; // Byte offset 0x74, CSR Addr 0x5403a, Direction=In + // Value to be programmed in DRAM Mode Register 4 {Channel B, Rank 1} + uint8_t MR11_B1; // Byte offset 0x75, CSR Addr 0x5403a, Direction=In + // Value to be programmed in DRAM Mode Register 11 {Channel B, Rank 1} + uint8_t MR12_B1; // Byte offset 0x76, CSR Addr 0x5403b, Direction=In + // Value to be programmed in DRAM Mode Register 12 {Channel B, Rank 1} + uint8_t MR13_B1; // Byte offset 0x77, CSR Addr 0x5403b, Direction=In + // Value to be programmed in DRAM Mode Register 13 {Channel B, Rank 1} + uint8_t MR14_B1; // Byte offset 0x78, CSR Addr 0x5403c, Direction=In + // Value to be programmed in DRAM Mode Register 14 {Channel B, Rank 1} + uint8_t MR16_B1; // Byte offset 0x79, CSR Addr 0x5403c, Direction=In + // Value to be programmed in DRAM Mode Register 16 {Channel B, Rank 1} + uint8_t MR17_B1; // Byte offset 0x7a, CSR Addr 0x5403d, Direction=In + // Value to be programmed in DRAM Mode Register 17 {Channel B, Rank 1} + uint8_t MR22_B1; // Byte offset 0x7b, CSR Addr 0x5403d, Direction=In + // Value to be programmed in DRAM Mode Register 22 {Channel B, Rank 1} + uint8_t MR24_B1; // Byte offset 0x7c, CSR Addr 0x5403e, Direction=In + // Value to be programmed in DRAM Mode Register 24 {Channel B, Rank 1} + uint8_t CATerminatingRankChB; // Byte offset 0x7d, CSR Addr 0x5403e, Direction=In + // Terminating Rank for CA bus on Channel B + // 0x0 = Rank 0 is terminating rank + // 0x1 = Rank 1 is terminating rank + uint8_t Reserved7E; // Byte offset 0x7e, CSR Addr 0x5403f, Direction=N/A + + uint8_t Reserved7F; // Byte offset 0x7f, CSR Addr 0x5403f, Direction=N/A + + uint8_t TrainedVREFDQ_B0; // Byte offset 0x80, CSR Addr 0x54040, Direction=Out + // Trained DQ Vref setting for Ch B Rank 0 + uint8_t TrainedVREFDQ_B1; // Byte offset 0x81, CSR Addr 0x54040, Direction=Out + // Trained DQ Vref setting for Ch B Rank 1 + uint8_t RxClkDly_Margin_B0; // Byte offset 0x82, CSR Addr 0x54041, Direction=Out + // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group. + uint8_t VrefDac_Margin_B0; // Byte offset 0x83, CSR Addr 0x54041, Direction=Out + // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group. + uint8_t TxDqDly_Margin_B0; // Byte offset 0x84, CSR Addr 0x54042, Direction=Out + // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group. + uint8_t DeviceVref_Margin_B0; // Byte offset 0x85, CSR Addr 0x54042, Direction=Out + // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group. + uint8_t RxClkDly_Margin_B1; // Byte offset 0x86, CSR Addr 0x54043, Direction=Out + // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group. + uint8_t VrefDac_Margin_B1; // Byte offset 0x87, CSR Addr 0x54043, Direction=Out + // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group. + uint8_t TxDqDly_Margin_B1; // Byte offset 0x88, CSR Addr 0x54044, Direction=Out + // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group. + uint8_t DeviceVref_Margin_B1; // Byte offset 0x89, CSR Addr 0x54044, Direction=Out + // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group. +} __attribute__ ((packed)) PMU_SMB_LPDDR4_2D_t;
diff --git a/arch/arm/include/asm/arch-a1/nand.h b/arch/arm/include/asm/arch-a1/nand.h new file mode 100644 index 0000000..d0a873a --- /dev/null +++ b/arch/arm/include/asm/arch-a1/nand.h
@@ -0,0 +1,136 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __NAND_H__ +#define __NAND_H__ +#include <asm/arch/cpu_config.h> + +#ifndef SD_EMMC_BASE_C +#define SD_EMMC_BASE_C 0xd0074000 +#endif + +#define P_NAND_BASE (SD_EMMC_BASE_C | (1<<11)) +#define P_CLK_CNTL (volatile uint32_t *)(SD_EMMC_BASE_C) +#define P_NAND_CMD (volatile uint32_t *)(P_NAND_BASE + 0x00) +#define P_NAND_CFG (volatile uint32_t *)(P_NAND_BASE + 0x04) +#define P_NAND_DADR (volatile uint32_t *)(P_NAND_BASE + 0x08) +#define P_NAND_IADR (volatile uint32_t *)(P_NAND_BASE + 0x0c) +#define P_NAND_BUF (volatile uint32_t *)(P_NAND_BASE + 0x10) +#define P_NAND_INFO (volatile uint32_t *)(P_NAND_BASE + 0x14) +#define P_NAND_DC (volatile uint32_t *)(P_NAND_BASE + 0x18) +#define P_NAND_ADR (volatile uint32_t *)(P_NAND_BASE + 0x1c) +#define P_NAND_DL (volatile uint32_t *)(P_NAND_BASE + 0x20) +#define P_NAND_DH (volatile uint32_t *)(P_NAND_BASE + 0x24) +#define P_NAND_CADR (volatile uint32_t *)(P_NAND_BASE + 0x28) +#define P_NAND_SADR (volatile uint32_t *)(P_NAND_BASE + 0x2c) + +#define CEF (0xf<<10) +#define CE0 (0xe<<10) +#define CE1 (0xd<<10) +#define CE2 (0xb<<10) +#define CE3 (0x7<<10) + +#define IO4 ((0xe<<10)|(1<<18)) +#define IO5 ((0xd<<10)|(1<<18)) +#define IO6 ((0xb<<10)|(1<<18)) + +#define CLE (0x5<<14) +#define ALE (0x6<<14) +#define DWR (0x4<<14) +#define DRD (0x8<<14) +#define IDLE (0xc<<14) +#define RB (1<<20) + +#define M2N ((0<<17) | (2<<20) | (1<<19)) +#define N2M ((1<<17) | (2<<20) | (1<<19)) +#define STS ((3<<17) | (2<<20)) +#define ADL ((0<<16) | (3<<20)) +#define ADH ((1<<16) | (3<<20)) +#define AIL ((2<<16) | (3<<20)) +#define AIH ((3<<16) | (3<<20)) +#define ASL ((4<<16) | (3<<20)) +#define ASH ((5<<16) | (3<<20)) +#define SEED ((8<<16) | (3<<20)) + +// NAND Flash Manufacturer ID Codes +#define NAND_MFR_TOSHIBA 0x98 +#define NAND_MFR_SAMSUNG 0xec +#define NAND_MFR_FUJITSU 0x04 +#define NAND_MFR_NATIONAL 0x8f +#define NAND_MFR_RENESAS 0x07 +#define NAND_MFR_STMICRO 0x20 +#define NAND_MFR_HYNIX 0xad +#define NAND_MFR_MICRON 0x2c +#define NAND_MFR_AMD 0x01 +#define NAND_MFR_INTEL 0x89 +#define NAND_MFR_SANDISK 0x45 +#define NAND_MFR_USER 0x100 +#define NAND_MFR_EFUSE 0x101 +#define NAND_MFR_ZETTA 0xba + +typedef struct nand_setup { + union { + uint32_t d32; + struct { + unsigned cmd:22; + unsigned large_page:1; // 22 + unsigned no_rb:1; // 23 from efuse + unsigned a2:1; // 24 + unsigned reserved25:1; // 25 + unsigned page_list:1; // 26 + unsigned sync_mode:2; // 27 from efuse + unsigned size:2; // 29 from efuse + unsigned active:1; // 31 + } b; + } cfg; + uint16_t id; + uint16_t max; // id:0x100 user, max:0 disable. +} nand_setup_t; + +typedef struct _nand_cmd{ + unsigned char type; + unsigned char val; +} nand_cmd_t; + +typedef struct _ext_info{ + uint32_t read_info; //nand_read_info; + uint32_t new_type; //new_nand_type; + uint32_t page_per_blk; //pages_in_block; + uint32_t xlc; //slc=1, mlc=2, tlc=3. + uint32_t rsv1[5]; +} ext_info_t; + +typedef struct _nand_page0 { + nand_setup_t nand_setup; //8 + unsigned char page_list[16]; //16 + nand_cmd_t retry_usr[32]; //64 (32 cmd max I/F) + ext_info_t ext_info; //64 +} nand_page0_t; //384 bytes max. + +//#define NAND_PAGE0_BUF BL1_NAND_BUFF +#define NAND_PAGE0_BUF (0x1800000) +#define NAND_PAGE_LIST (NAND_PAGE0_BUF + sizeof(nand_setup_t)) +#define NAND_RETRY_USER (NAND_PAGE_LIST + 16) +#define NAND_INFO_BUF (NAND_PAGE0_BUF + 512) +#define DEFAULT_ECC_MODE ((1<<23) |(1<<22) | (2<<20) |(1<<19) |(1<<17)|(7<<14)|(1<<13)|(48<<6)|1) +//#define DEFAULT_ECC_MODE ((1<<23) |(1<<22) | (2<<20) |(1<<19) |(1<<17)|(7<<14)|(1<<13)|(48<<6)|1) + +#define ERROR_MOD(mod,num) ((uint32_t)(((mod<<6)|num))) +#define ERROR_NAND_TIMEOUT ERROR_MOD(2,1) // +#define ERROR_NAND_ECC ERROR_MOD(2,2) // +#define ERROR_NAND_MAGIC_WORD ERROR_MOD(2,3) // +#define ERROR_NAND_INIT_READ ERROR_MOD(2,4) // +#define ERROR_NAND_BLANK_PAGE ERROR_MOD(2,5) // +#define ERROR_NAND_UNALIGN_SRC ERROR_MOD(2,6) // + +#define NAND_SECTOR_SIZE (512) +#define NAND_MAX_PAGESIZE (0x4000) //16K +#define SRC_ALIGN_SIZE (NAND_MAX_PAGESIZE) + +#define INFO_BYTE_PER_ECCPAGE (8) +uint32_t nfio_init(void); +uint32_t nf_read(uint32_t boot_device, uint32_t src, uint32_t des, uint32_t size); +#endif /* __NAND_H__ */ +
diff --git a/arch/arm/include/asm/arch-a1/oscring.h b/arch/arm/include/asm/arch-a1/oscring.h new file mode 100644 index 0000000..ffa5778 --- /dev/null +++ b/arch/arm/include/asm/arch-a1/oscring.h
@@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __OSCRING_H__ +#define __OSCRING_H__ + +#define OSCRING_CTL_REG SYSCTRL_OSC_RING_CTRL0 +#define OSCRING_CTL_DATA 0x55555555 /*0:23*/ + +#define RING_PWM_VCCK PWMAB_PWM_A + +int ring_msr(int index); +#endif
diff --git a/arch/arm/include/asm/arch-a1/p_register.h b/arch/arm/include/asm/arch-a1/p_register.h new file mode 100644 index 0000000..24b136d --- /dev/null +++ b/arch/arm/include/asm/arch-a1/p_register.h
@@ -0,0 +1,4083 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifdef P_REGISTER_H +#else +#define P_REGISTER_H + +// +// Reading file: ./REG_LIST_RTL.h +// +// synopsys translate_off +// synopsys translate_on +// +// Reading file: REG_LIST_AUDIO_RTL.h +// +//======================================================================== +// AUDIO - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe050000 +// ----------------------------------------------- +#define P_EE_AUDIO_CLK_GATE_EN0 ((volatile uint32_t *)0xfe050000) +#define P_EE_AUDIO_CLK_GATE_EN1 ((volatile uint32_t *)0xfe050004) +#define P_EE_AUDIO_MCLK_A_CTRL ((volatile uint32_t *)0xfe050008) +#define P_EE_AUDIO_MCLK_B_CTRL ((volatile uint32_t *)0xfe05000c) +#define P_EE_AUDIO_MCLK_C_CTRL ((volatile uint32_t *)0xfe050010) +#define P_EE_AUDIO_MCLK_D_CTRL ((volatile uint32_t *)0xfe050014) +#define P_EE_AUDIO_MCLK_E_CTRL ((volatile uint32_t *)0xfe050018) +#define P_EE_AUDIO_MCLK_F_CTRL ((volatile uint32_t *)0xfe05001c) +#define P_EE_AUDIO_PAD_CTRL0 ((volatile uint32_t *)0xfe050020) +#define P_EE_AUDIO_PAD_CTRL1 ((volatile uint32_t *)0xfe050024) +#define P_EE_AUDIO_SW_RESET0 ((volatile uint32_t *)0xfe050028) +#define P_EE_AUDIO_SW_RESET1 ((volatile uint32_t *)0xfe05002c) +#define P_EE_AUDIO_CLK81_CTRL ((volatile uint32_t *)0xfe050030) +#define P_EE_AUDIO_CLK81_EN ((volatile uint32_t *)0xfe050034) +#define P_EE_AUDIO_MST_A_SCLK_CTRL0 ((volatile uint32_t *)0xfe050040) +#define P_EE_AUDIO_MST_A_SCLK_CTRL1 ((volatile uint32_t *)0xfe050044) +#define P_EE_AUDIO_MST_B_SCLK_CTRL0 ((volatile uint32_t *)0xfe050048) +#define P_EE_AUDIO_MST_B_SCLK_CTRL1 ((volatile uint32_t *)0xfe05004c) +#define P_EE_AUDIO_MST_C_SCLK_CTRL0 ((volatile uint32_t *)0xfe050050) +#define P_EE_AUDIO_MST_C_SCLK_CTRL1 ((volatile uint32_t *)0xfe050054) +#define P_EE_AUDIO_MST_D_SCLK_CTRL0 ((volatile uint32_t *)0xfe050058) +#define P_EE_AUDIO_MST_D_SCLK_CTRL1 ((volatile uint32_t *)0xfe05005c) +#define P_EE_AUDIO_MST_E_SCLK_CTRL0 ((volatile uint32_t *)0xfe050060) +#define P_EE_AUDIO_MST_E_SCLK_CTRL1 ((volatile uint32_t *)0xfe050064) +#define P_EE_AUDIO_MST_F_SCLK_CTRL0 ((volatile uint32_t *)0xfe050068) +#define P_EE_AUDIO_MST_F_SCLK_CTRL1 ((volatile uint32_t *)0xfe05006c) +#define P_EE_AUDIO_MST_DLY_CTRL0 ((volatile uint32_t *)0xfe050070) +#define P_EE_AUDIO_MST_DLY_CTRL1 ((volatile uint32_t *)0xfe050074) +#define P_EE_AUDIO_CLK_TDMIN_A_CTRL ((volatile uint32_t *)0xfe050080) +#define P_EE_AUDIO_CLK_TDMIN_B_CTRL ((volatile uint32_t *)0xfe050084) +#define P_EE_AUDIO_CLK_TDMIN_C_CTRL ((volatile uint32_t *)0xfe050088) +#define P_EE_AUDIO_CLK_TDMIN_LB_CTRL ((volatile uint32_t *)0xfe05008c) +#define P_EE_AUDIO_CLK_TDMOUT_A_CTRL ((volatile uint32_t *)0xfe050090) +#define P_EE_AUDIO_CLK_TDMOUT_B_CTRL ((volatile uint32_t *)0xfe050094) +#define P_EE_AUDIO_CLK_TDMOUT_C_CTRL ((volatile uint32_t *)0xfe050098) +#define P_EE_AUDIO_CLK_SPDIFIN_CTRL ((volatile uint32_t *)0xfe05009c) +#define P_EE_AUDIO_CLK_SPDIFOUT_CTRL ((volatile uint32_t *)0xfe0500a0) +#define P_EE_AUDIO_CLK_RESAMPLEA_CTRL ((volatile uint32_t *)0xfe0500a4) +#define P_EE_AUDIO_CLK_LOCKER_CTRL ((volatile uint32_t *)0xfe0500a8) +#define P_EE_AUDIO_CLK_PDMIN_CTRL0 ((volatile uint32_t *)0xfe0500ac) +#define P_EE_AUDIO_CLK_PDMIN_CTRL1 ((volatile uint32_t *)0xfe0500b0) +#define P_EE_AUDIO_CLK_SPDIFOUT_B_CTRL ((volatile uint32_t *)0xfe0500b4) +#define P_EE_AUDIO_CLK_RESAMPLEB_CTRL ((volatile uint32_t *)0xfe0500b8) +#define P_EE_AUDIO_CLK_SPDIFIN_LB_CTRL ((volatile uint32_t *)0xfe0500bc) +#define P_EE_AUDIO_CLK_EQDRC_CTRL0 ((volatile uint32_t *)0xfe0500c0) +#define P_EE_AUDIO_VAD_CLK_CTRL ((volatile uint32_t *)0xfe0500c4) +#define P_EE_AUDIO_EARCTX_CMDC_CLK_CTRL ((volatile uint32_t *)0xfe0500c8) +#define P_EE_AUDIO_EARCTX_DMAC_CLK_CTRL ((volatile uint32_t *)0xfe0500cc) +#define P_EE_AUDIO_EARCRX_CMDC_CLK_CTRL ((volatile uint32_t *)0xfe0500d0) +#define P_EE_AUDIO_EARCRX_DMAC_CLK_CTRL ((volatile uint32_t *)0xfe0500d4) +#define P_EE_AUDIO_CLK_LOCKERB_CTRL ((volatile uint32_t *)0xfe0500d8) +#define P_EE_AUDIO_TODDR_A_CTRL0 ((volatile uint32_t *)0xfe050100) +#define P_EE_AUDIO_TODDR_A_CTRL1 ((volatile uint32_t *)0xfe050104) +#define P_EE_AUDIO_TODDR_A_START_ADDR ((volatile uint32_t *)0xfe050108) +#define P_EE_AUDIO_TODDR_A_FINISH_ADDR ((volatile uint32_t *)0xfe05010c) +#define P_EE_AUDIO_TODDR_A_INT_ADDR ((volatile uint32_t *)0xfe050110) +#define P_EE_AUDIO_TODDR_A_STATUS1 ((volatile uint32_t *)0xfe050114) +#define P_EE_AUDIO_TODDR_A_STATUS2 ((volatile uint32_t *)0xfe050118) +#define P_EE_AUDIO_TODDR_A_START_ADDRB ((volatile uint32_t *)0xfe05011c) +#define P_EE_AUDIO_TODDR_A_FINISH_ADDRB ((volatile uint32_t *)0xfe050120) +#define P_EE_AUDIO_TODDR_A_INIT_ADDR ((volatile uint32_t *)0xfe050124) +#define P_EE_AUDIO_TODDR_A_CTRL2 ((volatile uint32_t *)0xfe050128) +#define P_EE_AUDIO_TODDR_B_CTRL0 ((volatile uint32_t *)0xfe050140) +#define P_EE_AUDIO_TODDR_B_CTRL1 ((volatile uint32_t *)0xfe050144) +#define P_EE_AUDIO_TODDR_B_START_ADDR ((volatile uint32_t *)0xfe050148) +#define P_EE_AUDIO_TODDR_B_FINISH_ADDR ((volatile uint32_t *)0xfe05014c) +#define P_EE_AUDIO_TODDR_B_INT_ADDR ((volatile uint32_t *)0xfe050150) +#define P_EE_AUDIO_TODDR_B_STATUS1 ((volatile uint32_t *)0xfe050154) +#define P_EE_AUDIO_TODDR_B_STATUS2 ((volatile uint32_t *)0xfe050158) +#define P_EE_AUDIO_TODDR_B_START_ADDRB ((volatile uint32_t *)0xfe05015c) +#define P_EE_AUDIO_TODDR_B_FINISH_ADDRB ((volatile uint32_t *)0xfe050160) +#define P_EE_AUDIO_TODDR_B_INIT_ADDR ((volatile uint32_t *)0xfe050164) +#define P_EE_AUDIO_TODDR_B_CTRL2 ((volatile uint32_t *)0xfe050168) +#define P_EE_AUDIO_TODDR_C_CTRL0 ((volatile uint32_t *)0xfe050180) +#define P_EE_AUDIO_TODDR_C_CTRL1 ((volatile uint32_t *)0xfe050184) +#define P_EE_AUDIO_TODDR_C_START_ADDR ((volatile uint32_t *)0xfe050188) +#define P_EE_AUDIO_TODDR_C_FINISH_ADDR ((volatile uint32_t *)0xfe05018c) +#define P_EE_AUDIO_TODDR_C_INT_ADDR ((volatile uint32_t *)0xfe050190) +#define P_EE_AUDIO_TODDR_C_STATUS1 ((volatile uint32_t *)0xfe050194) +#define P_EE_AUDIO_TODDR_C_STATUS2 ((volatile uint32_t *)0xfe050198) +#define P_EE_AUDIO_TODDR_C_START_ADDRB ((volatile uint32_t *)0xfe05019c) +#define P_EE_AUDIO_TODDR_C_FINISH_ADDRB ((volatile uint32_t *)0xfe0501a0) +#define P_EE_AUDIO_TODDR_C_INIT_ADDR ((volatile uint32_t *)0xfe0501a4) +#define P_EE_AUDIO_TODDR_C_CTRL2 ((volatile uint32_t *)0xfe0501a8) +#define P_EE_AUDIO_FRDDR_A_CTRL0 ((volatile uint32_t *)0xfe0501c0) +#define P_EE_AUDIO_FRDDR_A_CTRL1 ((volatile uint32_t *)0xfe0501c4) +#define P_EE_AUDIO_FRDDR_A_START_ADDR ((volatile uint32_t *)0xfe0501c8) +#define P_EE_AUDIO_FRDDR_A_FINISH_ADDR ((volatile uint32_t *)0xfe0501cc) +#define P_EE_AUDIO_FRDDR_A_INT_ADDR ((volatile uint32_t *)0xfe0501d0) +#define P_EE_AUDIO_FRDDR_A_STATUS1 ((volatile uint32_t *)0xfe0501d4) +#define P_EE_AUDIO_FRDDR_A_STATUS2 ((volatile uint32_t *)0xfe0501d8) +#define P_EE_AUDIO_FRDDR_A_START_ADDRB ((volatile uint32_t *)0xfe0501dc) +#define P_EE_AUDIO_FRDDR_A_FINISH_ADDRB ((volatile uint32_t *)0xfe0501e0) +#define P_EE_AUDIO_FRDDR_A_INIT_ADDR ((volatile uint32_t *)0xfe0501e4) +#define P_EE_AUDIO_FRDDR_A_CTRL2 ((volatile uint32_t *)0xfe0501e8) +#define P_EE_AUDIO_FRDDR_B_CTRL0 ((volatile uint32_t *)0xfe050200) +#define P_EE_AUDIO_FRDDR_B_CTRL1 ((volatile uint32_t *)0xfe050204) +#define P_EE_AUDIO_FRDDR_B_START_ADDR ((volatile uint32_t *)0xfe050208) +#define P_EE_AUDIO_FRDDR_B_FINISH_ADDR ((volatile uint32_t *)0xfe05020c) +#define P_EE_AUDIO_FRDDR_B_INT_ADDR ((volatile uint32_t *)0xfe050210) +#define P_EE_AUDIO_FRDDR_B_STATUS1 ((volatile uint32_t *)0xfe050214) +#define P_EE_AUDIO_FRDDR_B_STATUS2 ((volatile uint32_t *)0xfe050218) +#define P_EE_AUDIO_FRDDR_B_START_ADDRB ((volatile uint32_t *)0xfe05021c) +#define P_EE_AUDIO_FRDDR_B_FINISH_ADDRB ((volatile uint32_t *)0xfe050220) +#define P_EE_AUDIO_FRDDR_B_INIT_ADDR ((volatile uint32_t *)0xfe050224) +#define P_EE_AUDIO_FRDDR_B_CTRL2 ((volatile uint32_t *)0xfe050228) +#define P_EE_AUDIO_FRDDR_C_CTRL0 ((volatile uint32_t *)0xfe050240) +#define P_EE_AUDIO_FRDDR_C_CTRL1 ((volatile uint32_t *)0xfe050244) +#define P_EE_AUDIO_FRDDR_C_START_ADDR ((volatile uint32_t *)0xfe050248) +#define P_EE_AUDIO_FRDDR_C_FINISH_ADDR ((volatile uint32_t *)0xfe05024c) +#define P_EE_AUDIO_FRDDR_C_INT_ADDR ((volatile uint32_t *)0xfe050250) +#define P_EE_AUDIO_FRDDR_C_STATUS1 ((volatile uint32_t *)0xfe050254) +#define P_EE_AUDIO_FRDDR_C_STATUS2 ((volatile uint32_t *)0xfe050258) +#define P_EE_AUDIO_FRDDR_C_START_ADDRB ((volatile uint32_t *)0xfe05025c) +#define P_EE_AUDIO_FRDDR_C_FINISH_ADDRB ((volatile uint32_t *)0xfe050260) +#define P_EE_AUDIO_FRDDR_C_INIT_ADDR ((volatile uint32_t *)0xfe050264) +#define P_EE_AUDIO_FRDDR_C_CTRL2 ((volatile uint32_t *)0xfe050268) +#define P_EE_AUDIO_ARB_CTRL ((volatile uint32_t *)0xfe050280) +#define P_EE_AUDIO_LB_A_CTRL0 ((volatile uint32_t *)0xfe0502c0) +#define P_EE_AUDIO_LB_A_CTRL1 ((volatile uint32_t *)0xfe0502c4) +#define P_EE_AUDIO_LB_A_CTRL2 ((volatile uint32_t *)0xfe0502c8) +#define P_EE_AUDIO_LB_A_CTRL3 ((volatile uint32_t *)0xfe0502cc) +#define P_EE_AUDIO_LB_A_DAT_CH_ID0 ((volatile uint32_t *)0xfe0502d0) +#define P_EE_AUDIO_LB_A_DAT_CH_ID1 ((volatile uint32_t *)0xfe0502d4) +#define P_EE_AUDIO_LB_A_DAT_CH_ID2 ((volatile uint32_t *)0xfe0502d8) +#define P_EE_AUDIO_LB_A_DAT_CH_ID3 ((volatile uint32_t *)0xfe0502dc) +#define P_EE_AUDIO_LB_A_LB_CH_ID0 ((volatile uint32_t *)0xfe0502e0) +#define P_EE_AUDIO_LB_A_LB_CH_ID1 ((volatile uint32_t *)0xfe0502e4) +#define P_EE_AUDIO_LB_A_LB_CH_ID2 ((volatile uint32_t *)0xfe0502e8) +#define P_EE_AUDIO_LB_A_LB_CH_ID3 ((volatile uint32_t *)0xfe0502ec) +#define P_EE_AUDIO_LB_A_STS ((volatile uint32_t *)0xfe0502f0) +#define P_EE_AUDIO_TDMIN_A_CTRL ((volatile uint32_t *)0xfe050300) +#define P_EE_AUDIO_TDMIN_A_SWAP0 ((volatile uint32_t *)0xfe050304) +#define P_EE_AUDIO_TDMIN_A_MASK0 ((volatile uint32_t *)0xfe050308) +#define P_EE_AUDIO_TDMIN_A_MASK1 ((volatile uint32_t *)0xfe05030c) +#define P_EE_AUDIO_TDMIN_A_MASK2 ((volatile uint32_t *)0xfe050310) +#define P_EE_AUDIO_TDMIN_A_MASK3 ((volatile uint32_t *)0xfe050314) +#define P_EE_AUDIO_TDMIN_A_STAT ((volatile uint32_t *)0xfe050318) +#define P_EE_AUDIO_TDMIN_A_MUTE_VAL ((volatile uint32_t *)0xfe05031c) +#define P_EE_AUDIO_TDMIN_A_MUTE0 ((volatile uint32_t *)0xfe050320) +#define P_EE_AUDIO_TDMIN_A_MUTE1 ((volatile uint32_t *)0xfe050324) +#define P_EE_AUDIO_TDMIN_A_MUTE2 ((volatile uint32_t *)0xfe050328) +#define P_EE_AUDIO_TDMIN_A_MUTE3 ((volatile uint32_t *)0xfe05032c) +#define P_EE_AUDIO_TDMIN_B_CTRL ((volatile uint32_t *)0xfe050340) +#define P_EE_AUDIO_TDMIN_B_SWAP0 ((volatile uint32_t *)0xfe050344) +#define P_EE_AUDIO_TDMIN_B_MASK0 ((volatile uint32_t *)0xfe050348) +#define P_EE_AUDIO_TDMIN_B_MASK1 ((volatile uint32_t *)0xfe05034c) +#define P_EE_AUDIO_TDMIN_B_MASK2 ((volatile uint32_t *)0xfe050350) +#define P_EE_AUDIO_TDMIN_B_MASK3 ((volatile uint32_t *)0xfe050354) +#define P_EE_AUDIO_TDMIN_B_STAT ((volatile uint32_t *)0xfe050358) +#define P_EE_AUDIO_TDMIN_B_MUTE_VAL ((volatile uint32_t *)0xfe05035c) +#define P_EE_AUDIO_TDMIN_B_MUTE0 ((volatile uint32_t *)0xfe050360) +#define P_EE_AUDIO_TDMIN_B_MUTE1 ((volatile uint32_t *)0xfe050364) +#define P_EE_AUDIO_TDMIN_B_MUTE2 ((volatile uint32_t *)0xfe050368) +#define P_EE_AUDIO_TDMIN_B_MUTE3 ((volatile uint32_t *)0xfe05036c) +#define P_EE_AUDIO_TDMIN_C_CTRL ((volatile uint32_t *)0xfe050380) +#define P_EE_AUDIO_TDMIN_C_SWAP0 ((volatile uint32_t *)0xfe050384) +#define P_EE_AUDIO_TDMIN_C_MASK0 ((volatile uint32_t *)0xfe050388) +#define P_EE_AUDIO_TDMIN_C_MASK1 ((volatile uint32_t *)0xfe05038c) +#define P_EE_AUDIO_TDMIN_C_MASK2 ((volatile uint32_t *)0xfe050390) +#define P_EE_AUDIO_TDMIN_C_MASK3 ((volatile uint32_t *)0xfe050394) +#define P_EE_AUDIO_TDMIN_C_STAT ((volatile uint32_t *)0xfe050398) +#define P_EE_AUDIO_TDMIN_C_MUTE_VAL ((volatile uint32_t *)0xfe05039c) +#define P_EE_AUDIO_TDMIN_C_MUTE0 ((volatile uint32_t *)0xfe0503a0) +#define P_EE_AUDIO_TDMIN_C_MUTE1 ((volatile uint32_t *)0xfe0503a4) +#define P_EE_AUDIO_TDMIN_C_MUTE2 ((volatile uint32_t *)0xfe0503a8) +#define P_EE_AUDIO_TDMIN_C_MUTE3 ((volatile uint32_t *)0xfe0503ac) +#define P_EE_AUDIO_TDMIN_LB_CTRL ((volatile uint32_t *)0xfe0503c0) +#define P_EE_AUDIO_TDMIN_LB_SWAP0 ((volatile uint32_t *)0xfe0503c4) +#define P_EE_AUDIO_TDMIN_LB_MASK0 ((volatile uint32_t *)0xfe0503c8) +#define P_EE_AUDIO_TDMIN_LB_MASK1 ((volatile uint32_t *)0xfe0503cc) +#define P_EE_AUDIO_TDMIN_LB_MASK2 ((volatile uint32_t *)0xfe0503d0) +#define P_EE_AUDIO_TDMIN_LB_MASK3 ((volatile uint32_t *)0xfe0503d4) +#define P_EE_AUDIO_TDMIN_LB_STAT ((volatile uint32_t *)0xfe0503d8) +#define P_EE_AUDIO_TDMIN_LB_MUTE_VAL ((volatile uint32_t *)0xfe0503dc) +#define P_EE_AUDIO_TDMIN_LB_MUTE0 ((volatile uint32_t *)0xfe0503e0) +#define P_EE_AUDIO_TDMIN_LB_MUTE1 ((volatile uint32_t *)0xfe0503e4) +#define P_EE_AUDIO_TDMIN_LB_MUTE2 ((volatile uint32_t *)0xfe0503e8) +#define P_EE_AUDIO_TDMIN_LB_MUTE3 ((volatile uint32_t *)0xfe0503ec) +#define P_EE_AUDIO_SPDIFIN_CTRL0 ((volatile uint32_t *)0xfe050400) +#define P_EE_AUDIO_SPDIFIN_CTRL1 ((volatile uint32_t *)0xfe050404) +#define P_EE_AUDIO_SPDIFIN_CTRL2 ((volatile uint32_t *)0xfe050408) +#define P_EE_AUDIO_SPDIFIN_CTRL3 ((volatile uint32_t *)0xfe05040c) +#define P_EE_AUDIO_SPDIFIN_CTRL4 ((volatile uint32_t *)0xfe050410) +#define P_EE_AUDIO_SPDIFIN_CTRL5 ((volatile uint32_t *)0xfe050414) +#define P_EE_AUDIO_SPDIFIN_CTRL6 ((volatile uint32_t *)0xfe050418) +#define P_EE_AUDIO_SPDIFIN_STAT0 ((volatile uint32_t *)0xfe05041c) +#define P_EE_AUDIO_SPDIFIN_STAT1 ((volatile uint32_t *)0xfe050420) +#define P_EE_AUDIO_SPDIFIN_STAT2 ((volatile uint32_t *)0xfe050424) +#define P_EE_AUDIO_SPDIFIN_MUTE_VAL ((volatile uint32_t *)0xfe050428) +#define P_EE_AUDIO_RESAMPLEA_CTRL0 ((volatile uint32_t *)0xfe050440) +#define P_EE_AUDIO_RESAMPLEA_CTRL1 ((volatile uint32_t *)0xfe050444) +#define P_EE_AUDIO_RESAMPLEA_CTRL2 ((volatile uint32_t *)0xfe050448) +#define P_EE_AUDIO_RESAMPLEA_CTRL3 ((volatile uint32_t *)0xfe05044c) +#define P_EE_AUDIO_RESAMPLEA_COEF0 ((volatile uint32_t *)0xfe050450) +#define P_EE_AUDIO_RESAMPLEA_COEF1 ((volatile uint32_t *)0xfe050454) +#define P_EE_AUDIO_RESAMPLEA_COEF2 ((volatile uint32_t *)0xfe050458) +#define P_EE_AUDIO_RESAMPLEA_COEF3 ((volatile uint32_t *)0xfe05045c) +#define P_EE_AUDIO_RESAMPLEA_COEF4 ((volatile uint32_t *)0xfe050460) +#define P_EE_AUDIO_RESAMPLEA_STATUS1 ((volatile uint32_t *)0xfe050464) +#define P_EE_AUDIO_SPDIFOUT_STAT ((volatile uint32_t *)0xfe050480) +#define P_EE_AUDIO_SPDIFOUT_GAIN0 ((volatile uint32_t *)0xfe050484) +#define P_EE_AUDIO_SPDIFOUT_GAIN1 ((volatile uint32_t *)0xfe050488) +#define P_EE_AUDIO_SPDIFOUT_CTRL0 ((volatile uint32_t *)0xfe05048c) +#define P_EE_AUDIO_SPDIFOUT_CTRL1 ((volatile uint32_t *)0xfe050490) +#define P_EE_AUDIO_SPDIFOUT_PREAMB ((volatile uint32_t *)0xfe050494) +#define P_EE_AUDIO_SPDIFOUT_SWAP ((volatile uint32_t *)0xfe050498) +#define P_EE_AUDIO_SPDIFOUT_CHSTS0 ((volatile uint32_t *)0xfe05049c) +#define P_EE_AUDIO_SPDIFOUT_CHSTS1 ((volatile uint32_t *)0xfe0504a0) +#define P_EE_AUDIO_SPDIFOUT_CHSTS2 ((volatile uint32_t *)0xfe0504a4) +#define P_EE_AUDIO_SPDIFOUT_CHSTS3 ((volatile uint32_t *)0xfe0504a8) +#define P_EE_AUDIO_SPDIFOUT_CHSTS4 ((volatile uint32_t *)0xfe0504ac) +#define P_EE_AUDIO_SPDIFOUT_CHSTS5 ((volatile uint32_t *)0xfe0504b0) +#define P_EE_AUDIO_SPDIFOUT_CHSTS6 ((volatile uint32_t *)0xfe0504b4) +#define P_EE_AUDIO_SPDIFOUT_CHSTS7 ((volatile uint32_t *)0xfe0504b8) +#define P_EE_AUDIO_SPDIFOUT_CHSTS8 ((volatile uint32_t *)0xfe0504bc) +#define P_EE_AUDIO_SPDIFOUT_CHSTS9 ((volatile uint32_t *)0xfe0504c0) +#define P_EE_AUDIO_SPDIFOUT_CHSTSA ((volatile uint32_t *)0xfe0504c4) +#define P_EE_AUDIO_SPDIFOUT_CHSTSB ((volatile uint32_t *)0xfe0504c8) +#define P_EE_AUDIO_SPDIFOUT_MUTE_VAL ((volatile uint32_t *)0xfe0504cc) +#define P_EE_AUDIO_TDMOUT_A_CTRL0 ((volatile uint32_t *)0xfe050500) +#define P_EE_AUDIO_TDMOUT_A_CTRL1 ((volatile uint32_t *)0xfe050504) +#define P_EE_AUDIO_TDMOUT_A_SWAP0 ((volatile uint32_t *)0xfe050508) +#define P_EE_AUDIO_TDMOUT_A_MASK0 ((volatile uint32_t *)0xfe05050c) +#define P_EE_AUDIO_TDMOUT_A_MASK1 ((volatile uint32_t *)0xfe050510) +#define P_EE_AUDIO_TDMOUT_A_MASK2 ((volatile uint32_t *)0xfe050514) +#define P_EE_AUDIO_TDMOUT_A_MASK3 ((volatile uint32_t *)0xfe050518) +#define P_EE_AUDIO_TDMOUT_A_STAT ((volatile uint32_t *)0xfe05051c) +#define P_EE_AUDIO_TDMOUT_A_GAIN0 ((volatile uint32_t *)0xfe050520) +#define P_EE_AUDIO_TDMOUT_A_GAIN1 ((volatile uint32_t *)0xfe050524) +#define P_EE_AUDIO_TDMOUT_A_MUTE_VAL ((volatile uint32_t *)0xfe050528) +#define P_EE_AUDIO_TDMOUT_A_MUTE0 ((volatile uint32_t *)0xfe05052c) +#define P_EE_AUDIO_TDMOUT_A_MUTE1 ((volatile uint32_t *)0xfe050530) +#define P_EE_AUDIO_TDMOUT_A_MUTE2 ((volatile uint32_t *)0xfe050534) +#define P_EE_AUDIO_TDMOUT_A_MUTE3 ((volatile uint32_t *)0xfe050538) +#define P_EE_AUDIO_TDMOUT_A_MASK_VAL ((volatile uint32_t *)0xfe05053c) +#define P_EE_AUDIO_TDMOUT_B_CTRL0 ((volatile uint32_t *)0xfe050540) +#define P_EE_AUDIO_TDMOUT_B_CTRL1 ((volatile uint32_t *)0xfe050544) +#define P_EE_AUDIO_TDMOUT_B_SWAP0 ((volatile uint32_t *)0xfe050548) +#define P_EE_AUDIO_TDMOUT_B_MASK0 ((volatile uint32_t *)0xfe05054c) +#define P_EE_AUDIO_TDMOUT_B_MASK1 ((volatile uint32_t *)0xfe050550) +#define P_EE_AUDIO_TDMOUT_B_MASK2 ((volatile uint32_t *)0xfe050554) +#define P_EE_AUDIO_TDMOUT_B_MASK3 ((volatile uint32_t *)0xfe050558) +#define P_EE_AUDIO_TDMOUT_B_STAT ((volatile uint32_t *)0xfe05055c) +#define P_EE_AUDIO_TDMOUT_B_GAIN0 ((volatile uint32_t *)0xfe050560) +#define P_EE_AUDIO_TDMOUT_B_GAIN1 ((volatile uint32_t *)0xfe050564) +#define P_EE_AUDIO_TDMOUT_B_MUTE_VAL ((volatile uint32_t *)0xfe050568) +#define P_EE_AUDIO_TDMOUT_B_MUTE0 ((volatile uint32_t *)0xfe05056c) +#define P_EE_AUDIO_TDMOUT_B_MUTE1 ((volatile uint32_t *)0xfe050570) +#define P_EE_AUDIO_TDMOUT_B_MUTE2 ((volatile uint32_t *)0xfe050574) +#define P_EE_AUDIO_TDMOUT_B_MUTE3 ((volatile uint32_t *)0xfe050578) +#define P_EE_AUDIO_TDMOUT_B_MASK_VAL ((volatile uint32_t *)0xfe05057c) +#define P_EE_AUDIO_TDMOUT_C_CTRL0 ((volatile uint32_t *)0xfe050580) +#define P_EE_AUDIO_TDMOUT_C_CTRL1 ((volatile uint32_t *)0xfe050584) +#define P_EE_AUDIO_TDMOUT_C_SWAP0 ((volatile uint32_t *)0xfe050588) +#define P_EE_AUDIO_TDMOUT_C_MASK0 ((volatile uint32_t *)0xfe05058c) +#define P_EE_AUDIO_TDMOUT_C_MASK1 ((volatile uint32_t *)0xfe050590) +#define P_EE_AUDIO_TDMOUT_C_MASK2 ((volatile uint32_t *)0xfe050594) +#define P_EE_AUDIO_TDMOUT_C_MASK3 ((volatile uint32_t *)0xfe050598) +#define P_EE_AUDIO_TDMOUT_C_STAT ((volatile uint32_t *)0xfe05059c) +#define P_EE_AUDIO_TDMOUT_C_GAIN0 ((volatile uint32_t *)0xfe0505a0) +#define P_EE_AUDIO_TDMOUT_C_GAIN1 ((volatile uint32_t *)0xfe0505a4) +#define P_EE_AUDIO_TDMOUT_C_MUTE_VAL ((volatile uint32_t *)0xfe0505a8) +#define P_EE_AUDIO_TDMOUT_C_MUTE0 ((volatile uint32_t *)0xfe0505ac) +#define P_EE_AUDIO_TDMOUT_C_MUTE1 ((volatile uint32_t *)0xfe0505b0) +#define P_EE_AUDIO_TDMOUT_C_MUTE2 ((volatile uint32_t *)0xfe0505b4) +#define P_EE_AUDIO_TDMOUT_C_MUTE3 ((volatile uint32_t *)0xfe0505b8) +#define P_EE_AUDIO_TDMOUT_C_MASK_VAL ((volatile uint32_t *)0xfe0505bc) +//`define EE_AUDIO_POW_DET_CTRL0 10'h180 +//`define EE_AUDIO_POW_DET_CTRL1 10'h181 +//`define EE_AUDIO_POW_DET_TH_HI 10'h182 +//`define EE_AUDIO_POW_DET_TH_LO 10'h183 +//`define EE_AUDIO_POW_DET_VALUE 10'h184 +#define P_EE_AUDIO_SECURITY_CTRL0 ((volatile uint32_t *)0xfe050640) +#define P_EE_AUDIO_SECURITY_CTRL1 ((volatile uint32_t *)0xfe050644) +#define P_EE_AUDIO_SPDIFOUT_B_STAT ((volatile uint32_t *)0xfe050680) +#define P_EE_AUDIO_SPDIFOUT_B_GAIN0 ((volatile uint32_t *)0xfe050684) +#define P_EE_AUDIO_SPDIFOUT_B_GAIN1 ((volatile uint32_t *)0xfe050688) +#define P_EE_AUDIO_SPDIFOUT_B_CTRL0 ((volatile uint32_t *)0xfe05068c) +#define P_EE_AUDIO_SPDIFOUT_B_CTRL1 ((volatile uint32_t *)0xfe050690) +#define P_EE_AUDIO_SPDIFOUT_B_PREAMB ((volatile uint32_t *)0xfe050694) +#define P_EE_AUDIO_SPDIFOUT_B_SWAP ((volatile uint32_t *)0xfe050698) +#define P_EE_AUDIO_SPDIFOUT_B_CHSTS0 ((volatile uint32_t *)0xfe05069c) +#define P_EE_AUDIO_SPDIFOUT_B_CHSTS1 ((volatile uint32_t *)0xfe0506a0) +#define P_EE_AUDIO_SPDIFOUT_B_CHSTS2 ((volatile uint32_t *)0xfe0506a4) +#define P_EE_AUDIO_SPDIFOUT_B_CHSTS3 ((volatile uint32_t *)0xfe0506a8) +#define P_EE_AUDIO_SPDIFOUT_B_CHSTS4 ((volatile uint32_t *)0xfe0506ac) +#define P_EE_AUDIO_SPDIFOUT_B_CHSTS5 ((volatile uint32_t *)0xfe0506b0) +#define P_EE_AUDIO_SPDIFOUT_B_CHSTS6 ((volatile uint32_t *)0xfe0506b4) +#define P_EE_AUDIO_SPDIFOUT_B_CHSTS7 ((volatile uint32_t *)0xfe0506b8) +#define P_EE_AUDIO_SPDIFOUT_B_CHSTS8 ((volatile uint32_t *)0xfe0506bc) +#define P_EE_AUDIO_SPDIFOUT_B_CHSTS9 ((volatile uint32_t *)0xfe0506c0) +#define P_EE_AUDIO_SPDIFOUT_B_CHSTSA ((volatile uint32_t *)0xfe0506c4) +#define P_EE_AUDIO_SPDIFOUT_B_CHSTSB ((volatile uint32_t *)0xfe0506c8) +#define P_EE_AUDIO_SPDIFOUT_B_MUTE_VAL ((volatile uint32_t *)0xfe0506cc) +#define P_EE_AUDIO_TORAM_CTRL0 ((volatile uint32_t *)0xfe050700) +#define P_EE_AUDIO_TORAM_CTRL1 ((volatile uint32_t *)0xfe050704) +#define P_EE_AUDIO_TORAM_START_ADDR ((volatile uint32_t *)0xfe050708) +#define P_EE_AUDIO_TORAM_FINISH_ADDR ((volatile uint32_t *)0xfe05070c) +#define P_EE_AUDIO_TORAM_INT_ADDR ((volatile uint32_t *)0xfe050710) +#define P_EE_AUDIO_TORAM_STATUS1 ((volatile uint32_t *)0xfe050714) +#define P_EE_AUDIO_TORAM_STATUS2 ((volatile uint32_t *)0xfe050718) +#define P_EE_AUDIO_TORAM_INIT_ADDR ((volatile uint32_t *)0xfe05071c) +#define P_EE_AUDIO_TOACODEC_CTRL0 ((volatile uint32_t *)0xfe050740) +#define P_EE_AUDIO_TOHDMITX_CTRL0 ((volatile uint32_t *)0xfe050744) +#define P_EE_AUDIO_TOVAD_CTRL0 ((volatile uint32_t *)0xfe050748) +#define P_EE_AUDIO_FRATV_CTRL0 ((volatile uint32_t *)0xfe05074c) +#define P_EE_AUDIO_RESAMPLEB_CTRL0 ((volatile uint32_t *)0xfe050780) +#define P_EE_AUDIO_RESAMPLEB_CTRL1 ((volatile uint32_t *)0xfe050784) +#define P_EE_AUDIO_RESAMPLEB_CTRL2 ((volatile uint32_t *)0xfe050788) +#define P_EE_AUDIO_RESAMPLEB_CTRL3 ((volatile uint32_t *)0xfe05078c) +#define P_EE_AUDIO_RESAMPLEB_COEF0 ((volatile uint32_t *)0xfe050790) +#define P_EE_AUDIO_RESAMPLEB_COEF1 ((volatile uint32_t *)0xfe050794) +#define P_EE_AUDIO_RESAMPLEB_COEF2 ((volatile uint32_t *)0xfe050798) +#define P_EE_AUDIO_RESAMPLEB_COEF3 ((volatile uint32_t *)0xfe05079c) +#define P_EE_AUDIO_RESAMPLEB_COEF4 ((volatile uint32_t *)0xfe0507a0) +#define P_EE_AUDIO_RESAMPLEB_STATUS1 ((volatile uint32_t *)0xfe0507a4) +#define P_EE_AUDIO_SPDIFIN_LB_CTRL0 ((volatile uint32_t *)0xfe0507c0) +#define P_EE_AUDIO_SPDIFIN_LB_CTRL1 ((volatile uint32_t *)0xfe0507c4) +#define P_EE_AUDIO_SPDIFIN_LB_CTRL6 ((volatile uint32_t *)0xfe0507d8) +#define P_EE_AUDIO_SPDIFIN_LB_STAT0 ((volatile uint32_t *)0xfe0507dc) +#define P_EE_AUDIO_SPDIFIN_LB_STAT1 ((volatile uint32_t *)0xfe0507e0) +#define P_EE_AUDIO_SPDIFIN_LB_MUTE_VAL ((volatile uint32_t *)0xfe0507e8) +#define P_EE_AUDIO_FRHDMIRX_CTRL0 ((volatile uint32_t *)0xfe050800) +#define P_EE_AUDIO_FRHDMIRX_CTRL1 ((volatile uint32_t *)0xfe050804) +#define P_EE_AUDIO_FRHDMIRX_CTRL2 ((volatile uint32_t *)0xfe050808) +#define P_EE_AUDIO_FRHDMIRX_CTRL3 ((volatile uint32_t *)0xfe05080c) +#define P_EE_AUDIO_FRHDMIRX_CTRL4 ((volatile uint32_t *)0xfe050810) +#define P_EE_AUDIO_FRHDMIRX_CTRL5 ((volatile uint32_t *)0xfe050814) +#define P_EE_AUDIO_FRHDMIRX_STAT0 ((volatile uint32_t *)0xfe050828) +#define P_EE_AUDIO_FRHDMIRX_STAT1 ((volatile uint32_t *)0xfe05082c) +#define P_EE_AUDIO_TODDR_D_CTRL0 ((volatile uint32_t *)0xfe050840) +#define P_EE_AUDIO_TODDR_D_CTRL1 ((volatile uint32_t *)0xfe050844) +#define P_EE_AUDIO_TODDR_D_START_ADDR ((volatile uint32_t *)0xfe050848) +#define P_EE_AUDIO_TODDR_D_FINISH_ADDR ((volatile uint32_t *)0xfe05084c) +#define P_EE_AUDIO_TODDR_D_INT_ADDR ((volatile uint32_t *)0xfe050850) +#define P_EE_AUDIO_TODDR_D_STATUS1 ((volatile uint32_t *)0xfe050854) +#define P_EE_AUDIO_TODDR_D_STATUS2 ((volatile uint32_t *)0xfe050858) +#define P_EE_AUDIO_TODDR_D_START_ADDRB ((volatile uint32_t *)0xfe05085c) +#define P_EE_AUDIO_TODDR_D_FINISH_ADDRB ((volatile uint32_t *)0xfe050860) +#define P_EE_AUDIO_TODDR_D_INIT_ADDR ((volatile uint32_t *)0xfe050864) +#define P_EE_AUDIO_TODDR_D_CTRL2 ((volatile uint32_t *)0xfe050868) +#define P_EE_AUDIO_FRDDR_D_CTRL0 ((volatile uint32_t *)0xfe050880) +#define P_EE_AUDIO_FRDDR_D_CTRL1 ((volatile uint32_t *)0xfe050884) +#define P_EE_AUDIO_FRDDR_D_START_ADDR ((volatile uint32_t *)0xfe050888) +#define P_EE_AUDIO_FRDDR_D_FINISH_ADDR ((volatile uint32_t *)0xfe05088c) +#define P_EE_AUDIO_FRDDR_D_INT_ADDR ((volatile uint32_t *)0xfe050890) +#define P_EE_AUDIO_FRDDR_D_STATUS1 ((volatile uint32_t *)0xfe050894) +#define P_EE_AUDIO_FRDDR_D_STATUS2 ((volatile uint32_t *)0xfe050898) +#define P_EE_AUDIO_FRDDR_D_START_ADDRB ((volatile uint32_t *)0xfe05089c) +#define P_EE_AUDIO_FRDDR_D_FINISH_ADDRB ((volatile uint32_t *)0xfe0508a0) +#define P_EE_AUDIO_FRDDR_D_INIT_ADDR ((volatile uint32_t *)0xfe0508a4) +#define P_EE_AUDIO_FRDDR_D_CTRL2 ((volatile uint32_t *)0xfe0508a8) +#define P_EE_AUDIO_LB_B_CTRL0 ((volatile uint32_t *)0xfe0508c0) +#define P_EE_AUDIO_LB_B_CTRL1 ((volatile uint32_t *)0xfe0508c4) +#define P_EE_AUDIO_LB_B_CTRL2 ((volatile uint32_t *)0xfe0508c8) +#define P_EE_AUDIO_LB_B_CTRL3 ((volatile uint32_t *)0xfe0508cc) +#define P_EE_AUDIO_LB_B_DAT_CH_ID0 ((volatile uint32_t *)0xfe0508d0) +#define P_EE_AUDIO_LB_B_DAT_CH_ID1 ((volatile uint32_t *)0xfe0508d4) +#define P_EE_AUDIO_LB_B_DAT_CH_ID2 ((volatile uint32_t *)0xfe0508d8) +#define P_EE_AUDIO_LB_B_DAT_CH_ID3 ((volatile uint32_t *)0xfe0508dc) +#define P_EE_AUDIO_LB_B_LB_CH_ID0 ((volatile uint32_t *)0xfe0508e0) +#define P_EE_AUDIO_LB_B_LB_CH_ID1 ((volatile uint32_t *)0xfe0508e4) +#define P_EE_AUDIO_LB_B_LB_CH_ID2 ((volatile uint32_t *)0xfe0508e8) +#define P_EE_AUDIO_LB_B_LB_CH_ID3 ((volatile uint32_t *)0xfe0508ec) +#define P_EE_AUDIO_LB_B_STS ((volatile uint32_t *)0xfe0508f0) +#define P_EE_AUDIO_TODDR_E_CTRL0 ((volatile uint32_t *)0xfe050900) +#define P_EE_AUDIO_TODDR_E_CTRL1 ((volatile uint32_t *)0xfe050904) +#define P_EE_AUDIO_TODDR_E_START_ADDR ((volatile uint32_t *)0xfe050908) +#define P_EE_AUDIO_TODDR_E_FINISH_ADDR ((volatile uint32_t *)0xfe05090c) +#define P_EE_AUDIO_TODDR_E_INT_ADDR ((volatile uint32_t *)0xfe050910) +#define P_EE_AUDIO_TODDR_E_STATUS1 ((volatile uint32_t *)0xfe050914) +#define P_EE_AUDIO_TODDR_E_STATUS2 ((volatile uint32_t *)0xfe050918) +#define P_EE_AUDIO_TODDR_E_START_ADDRB ((volatile uint32_t *)0xfe05091c) +#define P_EE_AUDIO_TODDR_E_FINISH_ADDRB ((volatile uint32_t *)0xfe050920) +#define P_EE_AUDIO_TODDR_E_INIT_ADDR ((volatile uint32_t *)0xfe050924) +#define P_EE_AUDIO_TODDR_E_CTRL2 ((volatile uint32_t *)0xfe050928) +#define P_EE_AUDIO_FRDDR_E_CTRL0 ((volatile uint32_t *)0xfe050940) +#define P_EE_AUDIO_FRDDR_E_CTRL1 ((volatile uint32_t *)0xfe050944) +#define P_EE_AUDIO_FRDDR_E_START_ADDR ((volatile uint32_t *)0xfe050948) +#define P_EE_AUDIO_FRDDR_E_FINISH_ADDR ((volatile uint32_t *)0xfe05094c) +#define P_EE_AUDIO_FRDDR_E_INT_ADDR ((volatile uint32_t *)0xfe050950) +#define P_EE_AUDIO_FRDDR_E_STATUS1 ((volatile uint32_t *)0xfe050954) +#define P_EE_AUDIO_FRDDR_E_STATUS2 ((volatile uint32_t *)0xfe050958) +#define P_EE_AUDIO_FRDDR_E_START_ADDRB ((volatile uint32_t *)0xfe05095c) +#define P_EE_AUDIO_FRDDR_E_FINISH_ADDRB ((volatile uint32_t *)0xfe050960) +#define P_EE_AUDIO_FRDDR_E_INIT_ADDR ((volatile uint32_t *)0xfe050964) +#define P_EE_AUDIO_FRDDR_E_CTRL2 ((volatile uint32_t *)0xfe050968) +#define P_EE_AUDIO_TDMIN_A_SWAP1 ((volatile uint32_t *)0xfe050980) +#define P_EE_AUDIO_TDMIN_A_MASK4 ((volatile uint32_t *)0xfe050984) +#define P_EE_AUDIO_TDMIN_A_MASK5 ((volatile uint32_t *)0xfe050988) +#define P_EE_AUDIO_TDMIN_A_MASK6 ((volatile uint32_t *)0xfe05098c) +#define P_EE_AUDIO_TDMIN_A_MASK7 ((volatile uint32_t *)0xfe050990) +#define P_EE_AUDIO_TDMIN_A_MUTE4 ((volatile uint32_t *)0xfe050994) +#define P_EE_AUDIO_TDMIN_A_MUTE5 ((volatile uint32_t *)0xfe050998) +#define P_EE_AUDIO_TDMIN_A_MUTE6 ((volatile uint32_t *)0xfe05099c) +#define P_EE_AUDIO_TDMIN_A_MUTE7 ((volatile uint32_t *)0xfe0509a0) +#define P_EE_AUDIO_TDMIN_B_SWAP1 ((volatile uint32_t *)0xfe0509c0) +#define P_EE_AUDIO_TDMIN_B_MASK4 ((volatile uint32_t *)0xfe0509c4) +#define P_EE_AUDIO_TDMIN_B_MASK5 ((volatile uint32_t *)0xfe0509c8) +#define P_EE_AUDIO_TDMIN_B_MASK6 ((volatile uint32_t *)0xfe0509cc) +#define P_EE_AUDIO_TDMIN_B_MASK7 ((volatile uint32_t *)0xfe0509d0) +#define P_EE_AUDIO_TDMIN_B_MUTE4 ((volatile uint32_t *)0xfe0509d4) +#define P_EE_AUDIO_TDMIN_B_MUTE5 ((volatile uint32_t *)0xfe0509d8) +#define P_EE_AUDIO_TDMIN_B_MUTE6 ((volatile uint32_t *)0xfe0509dc) +#define P_EE_AUDIO_TDMIN_B_MUTE7 ((volatile uint32_t *)0xfe0509e0) +#define P_EE_AUDIO_TDMIN_C_SWAP1 ((volatile uint32_t *)0xfe050a00) +#define P_EE_AUDIO_TDMIN_C_MASK4 ((volatile uint32_t *)0xfe050a04) +#define P_EE_AUDIO_TDMIN_C_MASK5 ((volatile uint32_t *)0xfe050a08) +#define P_EE_AUDIO_TDMIN_C_MASK6 ((volatile uint32_t *)0xfe050a0c) +#define P_EE_AUDIO_TDMIN_C_MASK7 ((volatile uint32_t *)0xfe050a10) +#define P_EE_AUDIO_TDMIN_C_MUTE4 ((volatile uint32_t *)0xfe050a14) +#define P_EE_AUDIO_TDMIN_C_MUTE5 ((volatile uint32_t *)0xfe050a18) +#define P_EE_AUDIO_TDMIN_C_MUTE6 ((volatile uint32_t *)0xfe050a1c) +#define P_EE_AUDIO_TDMIN_C_MUTE7 ((volatile uint32_t *)0xfe050a20) +#define P_EE_AUDIO_TDMIN_LB_SWAP1 ((volatile uint32_t *)0xfe050a40) +#define P_EE_AUDIO_TDMIN_LB_MASK4 ((volatile uint32_t *)0xfe050a44) +#define P_EE_AUDIO_TDMIN_LB_MASK5 ((volatile uint32_t *)0xfe050a48) +#define P_EE_AUDIO_TDMIN_LB_MASK6 ((volatile uint32_t *)0xfe050a4c) +#define P_EE_AUDIO_TDMIN_LB_MASK7 ((volatile uint32_t *)0xfe050a50) +#define P_EE_AUDIO_TDMIN_LB_MUTE4 ((volatile uint32_t *)0xfe050a54) +#define P_EE_AUDIO_TDMIN_LB_MUTE5 ((volatile uint32_t *)0xfe050a58) +#define P_EE_AUDIO_TDMIN_LB_MUTE6 ((volatile uint32_t *)0xfe050a5c) +#define P_EE_AUDIO_TDMIN_LB_MUTE7 ((volatile uint32_t *)0xfe050a60) +#define P_EE_AUDIO_TDMOUT_A_CTRL2 ((volatile uint32_t *)0xfe050a80) +#define P_EE_AUDIO_TDMOUT_A_SWAP1 ((volatile uint32_t *)0xfe050a84) +#define P_EE_AUDIO_TDMOUT_A_GAIN2 ((volatile uint32_t *)0xfe050a88) +#define P_EE_AUDIO_TDMOUT_A_GAIN3 ((volatile uint32_t *)0xfe050a8c) +#define P_EE_AUDIO_TDMOUT_A_MASK4 ((volatile uint32_t *)0xfe050a90) +#define P_EE_AUDIO_TDMOUT_A_MASK5 ((volatile uint32_t *)0xfe050a94) +#define P_EE_AUDIO_TDMOUT_A_MASK6 ((volatile uint32_t *)0xfe050a98) +#define P_EE_AUDIO_TDMOUT_A_MASK7 ((volatile uint32_t *)0xfe050a9c) +#define P_EE_AUDIO_TDMOUT_A_MUTE4 ((volatile uint32_t *)0xfe050aa0) +#define P_EE_AUDIO_TDMOUT_A_MUTE5 ((volatile uint32_t *)0xfe050aa4) +#define P_EE_AUDIO_TDMOUT_A_MUTE6 ((volatile uint32_t *)0xfe050aa8) +#define P_EE_AUDIO_TDMOUT_A_MUTE7 ((volatile uint32_t *)0xfe050aac) +#define P_EE_AUDIO_TDMOUT_B_CTRL2 ((volatile uint32_t *)0xfe050ac0) +#define P_EE_AUDIO_TDMOUT_B_SWAP1 ((volatile uint32_t *)0xfe050ac4) +#define P_EE_AUDIO_TDMOUT_B_GAIN2 ((volatile uint32_t *)0xfe050ac8) +#define P_EE_AUDIO_TDMOUT_B_GAIN3 ((volatile uint32_t *)0xfe050acc) +#define P_EE_AUDIO_TDMOUT_B_MASK4 ((volatile uint32_t *)0xfe050ad0) +#define P_EE_AUDIO_TDMOUT_B_MASK5 ((volatile uint32_t *)0xfe050ad4) +#define P_EE_AUDIO_TDMOUT_B_MASK6 ((volatile uint32_t *)0xfe050ad8) +#define P_EE_AUDIO_TDMOUT_B_MASK7 ((volatile uint32_t *)0xfe050adc) +#define P_EE_AUDIO_TDMOUT_B_MUTE4 ((volatile uint32_t *)0xfe050ae0) +#define P_EE_AUDIO_TDMOUT_B_MUTE5 ((volatile uint32_t *)0xfe050ae4) +#define P_EE_AUDIO_TDMOUT_B_MUTE6 ((volatile uint32_t *)0xfe050ae8) +#define P_EE_AUDIO_TDMOUT_B_MUTE7 ((volatile uint32_t *)0xfe050aec) +#define P_EE_AUDIO_TDMOUT_C_CTRL2 ((volatile uint32_t *)0xfe050b00) +#define P_EE_AUDIO_TDMOUT_C_SWAP1 ((volatile uint32_t *)0xfe050b04) +#define P_EE_AUDIO_TDMOUT_C_GAIN2 ((volatile uint32_t *)0xfe050b08) +#define P_EE_AUDIO_TDMOUT_C_GAIN3 ((volatile uint32_t *)0xfe050b0c) +#define P_EE_AUDIO_TDMOUT_C_MASK4 ((volatile uint32_t *)0xfe050b10) +#define P_EE_AUDIO_TDMOUT_C_MASK5 ((volatile uint32_t *)0xfe050b14) +#define P_EE_AUDIO_TDMOUT_C_MASK6 ((volatile uint32_t *)0xfe050b18) +#define P_EE_AUDIO_TDMOUT_C_MASK7 ((volatile uint32_t *)0xfe050b1c) +#define P_EE_AUDIO_TDMOUT_C_MUTE4 ((volatile uint32_t *)0xfe050b20) +#define P_EE_AUDIO_TDMOUT_C_MUTE5 ((volatile uint32_t *)0xfe050b24) +#define P_EE_AUDIO_TDMOUT_C_MUTE6 ((volatile uint32_t *)0xfe050b28) +#define P_EE_AUDIO_TDMOUT_C_MUTE7 ((volatile uint32_t *)0xfe050b2c) +//======================================================================== +// PDM - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe051000 +// ----------------------------------------------- +#define P_PDM_CTRL ((volatile uint32_t *)0xfe051000) +//bit 31: PDM enable. +//bit 30: invert the PDM_DCLK. +//bit 29: output mode: 1: 24bits. 0: 32 bits. +//bit 28: bypass mode. 1: bypass all filter. directly output the PDM input to DDR. 0: normal mode. +//bit 27~9: not used. +//bit 16:. PDM Asynchronous FIFO soft reset. write 1 to soft reset AFIFO. +//bit 15:8 PDM channel reset. 0: to reset each PDM channel. 1: normal mode. +//bit 7:0. PDM channel enable. each bit for one channel. +#define P_PDM_HCIC_CTRL1 ((volatile uint32_t *)0xfe051004) +//bit 31 hcic filter enable. 1 use sinc filter. 0 bypass input to output. +//bit 29:24. hcic final gain shift parameter. +//bit 23:16 hcic final gain multiplier. +//bit 8:4 hcic down sample rate. +//bit 3:0 hcic stage number. must be between 3 to 9. +#define P_PDM_HCIC_CTRL2 ((volatile uint32_t *)0xfe051008) +//Not used. +#define P_PDM_F1_CTRL ((volatile uint32_t *)0xfe05100c) +//bit 31 . filter 1 enable. +//bit 16:15. f1 round mode. 2'b00 : sign bit at bit 49. 28bits output [49:22] round at bit 21. 32bits output [49:18]. 24bits output [49:26] +// 2'b01 : sign bit at bit 50. 28bits output [50:23] round at bit 22. 32bits output [49:18]. 24bits output [49:26] +// 2'b10 : sign bit at bit 51. 28bits output [51:24] round at bit 23 32bits output [49:18]. 24bits output [49:26]. +//bit 15:12. filter 1 down sample rate. +//bit 8:0. filter 1 stage number. +#define P_PDM_F2_CTRL ((volatile uint32_t *)0xfe051010) +//bit 31 . filter 2 enable. +//bit 16:15. f2 round mode. 2'b00 : round at bit 21. 2'b01 : round at bit 22. 2'b10 : round at bit 23. +//bit 15:12. filter 2 down sample rate. +//bit 8:0. filter 2 stage number. +#define P_PDM_F3_CTRL ((volatile uint32_t *)0xfe051014) +//bit 31 . filter 3 enable. +//bit 16:15. f3 round mode. 2'b00 : round at bit 21. 2'b01 : round at bit 22. 2'b10 : round at bit 23. +//bit 15:12. filter 3 down sample rate. +//bit 8:0. filter 3 stage number. +#define P_PDM_HPF_CTRL ((volatile uint32_t *)0xfe051018) +//bit 31 High pass filter enable. +//bit 20:16 high pass filter shift steps. 6~19 steps. +//bit 15:0 high pass filter output factor. +#define P_PDM_CHAN_CTRL ((volatile uint32_t *)0xfe05101c) +//bit 31:24. chan3 data sample pointer vs edge of the PDM_DCLK. +//bit 23:16 chan2 data sample pointer vs edge of the PDM_DCLK. +//bit 15:8. chan1 data sample pointer vs edge of the PDM_DCLK. +//bit 7:0 chan0 data sample pointer vs edge of the PDM_DCLK. +#define P_PDM_CHAN_CTRL1 ((volatile uint32_t *)0xfe051020) +//bit 31:24. chan7 data sample pointer vs edge of the PDM_DCLK. +//bit 23:16 chan6 data sample pointer vs edge of the PDM_DCLK. +//bit 15:8. chan5 data sample pointer vs edge of the PDM_DCLK. +//bit 7:0 chan4 data sample pointer vs edge of the PDM_DCLK. +#define P_PDM_COEFF_ADDR ((volatile uint32_t *)0xfe051024) +// address of the write/read of coeff data. +#define P_PDM_COEFF_DATA ((volatile uint32_t *)0xfe051028) +//write/read data to coeff memory. +#define P_PDM_CLKG_CTRL ((volatile uint32_t *)0xfe05102c) +// auto clock gating control. 1: disable the clock gating function. the clock will awlays enabled. 0 : use RTL auto clock gating. +//31:7 not used. +//bit 6 filt_ctrl module auto clock gating control. +//bit 5 sinc fifo module auto clock gating control. +//bit 4 filter module auto clock gating control. +//bit 3 apb module auto clock gating control. +//bit 2 coeff memory module auto clock gating control. +//bit 1 each channel module auto clock gating control. +//bit 0 cts_pdm_clk auto clock gating control. +#define P_PDM_STS ((volatile uint32_t *)0xfe051030) +//bit 1 HPF filter output overflow. means the PCLK is too slow. +//bit 0 HCIC filter output overflow. means the CTS_PDM_CLK is too slow. can't finished the filter function. +#define P_PDM_MUTE_VALUE ((volatile uint32_t *)0xfe051034) +#define P_PDM_MASK_NUM ((volatile uint32_t *)0xfe051038) +//======================================================================== +// EQ DRC - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe052000 +// ----------------------------------------------- +#define P_AED_COEF_RAM_CNTL ((volatile uint32_t *)0xfe052000) +#define P_AED_COEF_RAM_DATA ((volatile uint32_t *)0xfe052004) +#define P_AED_EQ_EN ((volatile uint32_t *)0xfe052008) +#define P_AED_EQ_TAP_CNTL ((volatile uint32_t *)0xfe05200c) +#define P_AED_EQ_VOLUME ((volatile uint32_t *)0xfe052010) +#define P_AED_EQ_VOLUME_SLEW_CNT ((volatile uint32_t *)0xfe052014) +#define P_AED_MUTE ((volatile uint32_t *)0xfe052018) +#define P_AED_DRC_CNTL ((volatile uint32_t *)0xfe05201c) +#define P_AED_DRC_RMS_COEF0 ((volatile uint32_t *)0xfe052020) +#define P_AED_DRC_RMS_COEF1 ((volatile uint32_t *)0xfe052024) +#define P_AED_DRC_THD0 ((volatile uint32_t *)0xfe052028) +#define P_AED_DRC_THD1 ((volatile uint32_t *)0xfe05202c) +#define P_AED_DRC_THD2 ((volatile uint32_t *)0xfe052030) +#define P_AED_DRC_THD3 ((volatile uint32_t *)0xfe052034) +#define P_AED_DRC_THD4 ((volatile uint32_t *)0xfe052038) +#define P_AED_DRC_K0 ((volatile uint32_t *)0xfe05203c) +#define P_AED_DRC_K1 ((volatile uint32_t *)0xfe052040) +#define P_AED_DRC_K2 ((volatile uint32_t *)0xfe052044) +#define P_AED_DRC_K3 ((volatile uint32_t *)0xfe052048) +#define P_AED_DRC_K4 ((volatile uint32_t *)0xfe05204c) +#define P_AED_DRC_K5 ((volatile uint32_t *)0xfe052050) +#define P_AED_DRC_THD_OUT0 ((volatile uint32_t *)0xfe052054) +#define P_AED_DRC_THD_OUT1 ((volatile uint32_t *)0xfe052058) +#define P_AED_DRC_THD_OUT2 ((volatile uint32_t *)0xfe05205c) +#define P_AED_DRC_THD_OUT3 ((volatile uint32_t *)0xfe052060) +#define P_AED_DRC_OFFSET ((volatile uint32_t *)0xfe052064) +#define P_AED_DRC_RELEASE_COEF00 ((volatile uint32_t *)0xfe052068) +#define P_AED_DRC_RELEASE_COEF01 ((volatile uint32_t *)0xfe05206c) +#define P_AED_DRC_RELEASE_COEF10 ((volatile uint32_t *)0xfe052070) +#define P_AED_DRC_RELEASE_COEF11 ((volatile uint32_t *)0xfe052074) +#define P_AED_DRC_RELEASE_COEF20 ((volatile uint32_t *)0xfe052078) +#define P_AED_DRC_RELEASE_COEF21 ((volatile uint32_t *)0xfe05207c) +#define P_AED_DRC_RELEASE_COEF30 ((volatile uint32_t *)0xfe052080) +#define P_AED_DRC_RELEASE_COEF31 ((volatile uint32_t *)0xfe052084) +#define P_AED_DRC_RELEASE_COEF40 ((volatile uint32_t *)0xfe052088) +#define P_AED_DRC_RELEASE_COEF41 ((volatile uint32_t *)0xfe05208c) +#define P_AED_DRC_RELEASE_COEF50 ((volatile uint32_t *)0xfe052090) +#define P_AED_DRC_RELEASE_COEF51 ((volatile uint32_t *)0xfe052094) +#define P_AED_DRC_ATTACK_COEF00 ((volatile uint32_t *)0xfe052098) +#define P_AED_DRC_ATTACK_COEF01 ((volatile uint32_t *)0xfe05209c) +#define P_AED_DRC_ATTACK_COEF10 ((volatile uint32_t *)0xfe0520a0) +#define P_AED_DRC_ATTACK_COEF11 ((volatile uint32_t *)0xfe0520a4) +#define P_AED_DRC_ATTACK_COEF20 ((volatile uint32_t *)0xfe0520a8) +#define P_AED_DRC_ATTACK_COEF21 ((volatile uint32_t *)0xfe0520ac) +#define P_AED_DRC_ATTACK_COEF30 ((volatile uint32_t *)0xfe0520b0) +#define P_AED_DRC_ATTACK_COEF31 ((volatile uint32_t *)0xfe0520b4) +#define P_AED_DRC_ATTACK_COEF40 ((volatile uint32_t *)0xfe0520b8) +#define P_AED_DRC_ATTACK_COEF41 ((volatile uint32_t *)0xfe0520bc) +#define P_AED_DRC_ATTACK_COEF50 ((volatile uint32_t *)0xfe0520c0) +#define P_AED_DRC_ATTACK_COEF51 ((volatile uint32_t *)0xfe0520c4) +#define P_AED_DRC_LOOPBACK_CNTL ((volatile uint32_t *)0xfe0520c8) +#define P_AED_MDRC_CNTL ((volatile uint32_t *)0xfe0520cc) +#define P_AED_MDRC_RMS_COEF00 ((volatile uint32_t *)0xfe0520d0) +#define P_AED_MDRC_RMS_COEF01 ((volatile uint32_t *)0xfe0520d4) +#define P_AED_MDRC_RELEASE_COEF00 ((volatile uint32_t *)0xfe0520d8) +#define P_AED_MDRC_RELEASE_COEF01 ((volatile uint32_t *)0xfe0520dc) +#define P_AED_MDRC_ATTACK_COEF00 ((volatile uint32_t *)0xfe0520e0) +#define P_AED_MDRC_ATTACK_COEF01 ((volatile uint32_t *)0xfe0520e4) +#define P_AED_MDRC_THD0 ((volatile uint32_t *)0xfe0520e8) +#define P_AED_MDRC_K0 ((volatile uint32_t *)0xfe0520ec) +#define P_AED_MDRC_LOW_GAIN ((volatile uint32_t *)0xfe0520f0) +#define P_AED_MDRC_OFFSET0 ((volatile uint32_t *)0xfe0520f4) +#define P_AED_MDRC_RMS_COEF10 ((volatile uint32_t *)0xfe0520f8) +#define P_AED_MDRC_RMS_COEF11 ((volatile uint32_t *)0xfe0520fc) +#define P_AED_MDRC_RELEASE_COEF10 ((volatile uint32_t *)0xfe052100) +#define P_AED_MDRC_RELEASE_COEF11 ((volatile uint32_t *)0xfe052104) +#define P_AED_MDRC_ATTACK_COEF10 ((volatile uint32_t *)0xfe052108) +#define P_AED_MDRC_ATTACK_COEF11 ((volatile uint32_t *)0xfe05210c) +#define P_AED_MDRC_THD1 ((volatile uint32_t *)0xfe052110) +#define P_AED_MDRC_K1 ((volatile uint32_t *)0xfe052114) +#define P_AED_MDRC_OFFSET1 ((volatile uint32_t *)0xfe052118) +#define P_AED_MDRC_MID_GAIN ((volatile uint32_t *)0xfe05211c) +#define P_AED_MDRC_RMS_COEF20 ((volatile uint32_t *)0xfe052120) +#define P_AED_MDRC_RMS_COEF21 ((volatile uint32_t *)0xfe052124) +#define P_AED_MDRC_RELEASE_COEF20 ((volatile uint32_t *)0xfe052128) +#define P_AED_MDRC_RELEASE_COEF21 ((volatile uint32_t *)0xfe05212c) +#define P_AED_MDRC_ATTACK_COEF20 ((volatile uint32_t *)0xfe052130) +#define P_AED_MDRC_ATTACK_COEF21 ((volatile uint32_t *)0xfe052134) +#define P_AED_MDRC_THD2 ((volatile uint32_t *)0xfe052138) +#define P_AED_MDRC_K2 ((volatile uint32_t *)0xfe05213c) +#define P_AED_MDRC_OFFSET2 ((volatile uint32_t *)0xfe052140) +#define P_AED_MDRC_HIGH_GAIN ((volatile uint32_t *)0xfe052144) +#define P_AED_ED_CNTL ((volatile uint32_t *)0xfe052148) +#define P_AED_DC_EN ((volatile uint32_t *)0xfe05214c) +#define P_AED_ND_LOW_THD ((volatile uint32_t *)0xfe052150) +#define P_AED_ND_HIGH_THD ((volatile uint32_t *)0xfe052154) +#define P_AED_ND_CNT_THD ((volatile uint32_t *)0xfe052158) +#define P_AED_ND_SUM_NUM ((volatile uint32_t *)0xfe05215c) +#define P_AED_ND_CZ_NUM ((volatile uint32_t *)0xfe052160) +#define P_AED_ND_SUM_THD0 ((volatile uint32_t *)0xfe052164) +#define P_AED_ND_SUM_THD1 ((volatile uint32_t *)0xfe052168) +#define P_AED_ND_CZ_THD0 ((volatile uint32_t *)0xfe05216c) +#define P_AED_ND_CZ_THD1 ((volatile uint32_t *)0xfe052170) +#define P_AED_ND_COND_CNTL ((volatile uint32_t *)0xfe052174) +#define P_AED_ND_RELEASE_COEF0 ((volatile uint32_t *)0xfe052178) +#define P_AED_ND_RELEASE_COEF1 ((volatile uint32_t *)0xfe05217c) +#define P_AED_ND_ATTACK_COEF0 ((volatile uint32_t *)0xfe052180) +#define P_AED_ND_ATTACK_COEF1 ((volatile uint32_t *)0xfe052184) +#define P_AED_ND_CNTL ((volatile uint32_t *)0xfe052188) +#define P_AED_MIX0_LL ((volatile uint32_t *)0xfe05218c) +#define P_AED_MIX0_RL ((volatile uint32_t *)0xfe052190) +#define P_AED_MIX0_LR ((volatile uint32_t *)0xfe052194) +#define P_AED_MIX0_RR ((volatile uint32_t *)0xfe052198) +#define P_AED_CLIP_THD ((volatile uint32_t *)0xfe05219c) +#define P_AED_CH1_ND_SUM_OUT ((volatile uint32_t *)0xfe0521a0) +#define P_AED_CH2_ND_SUM_OUT ((volatile uint32_t *)0xfe0521a4) +#define P_AED_CH1_ND_CZ_OUT ((volatile uint32_t *)0xfe0521a8) +#define P_AED_CH2_ND_CZ_OUT ((volatile uint32_t *)0xfe0521ac) +#define P_AED_NOISE_STATUS ((volatile uint32_t *)0xfe0521b0) +#define P_AED_POW_CURRENT_S0 ((volatile uint32_t *)0xfe0521b4) +#define P_AED_POW_CURRENT_S1 ((volatile uint32_t *)0xfe0521b8) +#define P_AED_POW_CURRENT_S2 ((volatile uint32_t *)0xfe0521bc) +#define P_AED_POW_OUT0 ((volatile uint32_t *)0xfe0521c0) +#define P_AED_POW_OUT1 ((volatile uint32_t *)0xfe0521c4) +#define P_AED_POW_OUT2 ((volatile uint32_t *)0xfe0521c8) +#define P_AED_POW_ADJ_INDEX0 ((volatile uint32_t *)0xfe0521cc) +#define P_AED_POW_ADJ_INDEX1 ((volatile uint32_t *)0xfe0521d0) +#define P_AED_POW_ADJ_INDEX2 ((volatile uint32_t *)0xfe0521d4) +#define P_AED_DRC_GAIN_INDEX0 ((volatile uint32_t *)0xfe0521d8) +#define P_AED_DRC_GAIN_INDEX1 ((volatile uint32_t *)0xfe0521dc) +#define P_AED_DRC_GAIN_INDEX2 ((volatile uint32_t *)0xfe0521e0) +#define P_AED_CH1_VOLUME_STATE ((volatile uint32_t *)0xfe0521e4) +#define P_AED_CH2_VOLUME_STATE ((volatile uint32_t *)0xfe0521e8) +#define P_AED_CH1_VOLUME_GAIN ((volatile uint32_t *)0xfe0521ec) +#define P_AED_CH2_VOLUME_GAIN ((volatile uint32_t *)0xfe0521f0) +#define P_AED_FULL_POW_CURRENT ((volatile uint32_t *)0xfe0521f4) +#define P_AED_FULL_POW_OUT ((volatile uint32_t *)0xfe0521f8) +#define P_AED_FULL_POW_ADJ ((volatile uint32_t *)0xfe0521fc) +#define P_AED_FULL_DRC_GAIN ((volatile uint32_t *)0xfe052200) +#define P_AED_MASTER_VOLUME_STATE ((volatile uint32_t *)0xfe052204) +#define P_AED_MASTER_VOLUME_GAIN ((volatile uint32_t *)0xfe052208) +#define P_AED_TOP_CTL0 ((volatile uint32_t *)0xfe05220c) +#define P_AED_TOP_CTL1 ((volatile uint32_t *)0xfe052210) +#define P_AED_TOP_CTL2 ((volatile uint32_t *)0xfe052214) +//======================================================================== +// AUDIO locker - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe051400 +// ----------------------------------------------- +#define P_AUD_LOCK_EN ((volatile uint32_t *)0xfe051400) +#define P_AUD_LOCK_SW_RESET ((volatile uint32_t *)0xfe051404) +#define P_AUD_LOCK_SW_LATCH ((volatile uint32_t *)0xfe051408) +#define P_AUD_LOCK_HW_LATCH ((volatile uint32_t *)0xfe05140c) +#define P_AUD_LOCK_REFCLK_SRC ((volatile uint32_t *)0xfe051410) +#define P_AUD_LOCK_REFCLK_LAT_INT ((volatile uint32_t *)0xfe051414) +#define P_AUD_LOCK_IMCLK_LAT_INT ((volatile uint32_t *)0xfe051418) +#define P_AUD_LOCK_OMCLK_LAT_INT ((volatile uint32_t *)0xfe05141c) +#define P_AUD_LOCK_REFCLK_DS_INT ((volatile uint32_t *)0xfe051420) +#define P_AUD_LOCK_IMCLK_DS_INT ((volatile uint32_t *)0xfe051424) +#define P_AUD_LOCK_OMCLK_DS_INT ((volatile uint32_t *)0xfe051428) +#define P_AUD_LOCK_INT_CLR ((volatile uint32_t *)0xfe05142c) +#define P_AUD_LOCK_GCLK_CTRL ((volatile uint32_t *)0xfe051430) +#define P_AUD_LOCK_INT_CTRL ((volatile uint32_t *)0xfe051434) +#define P_RO_REF2IMCLK_CNT_L ((volatile uint32_t *)0xfe051440) +#define P_RO_REF2IMCLK_CNT_H ((volatile uint32_t *)0xfe051444) +#define P_RO_REF2OMCLK_CNT_L ((volatile uint32_t *)0xfe051448) +#define P_RO_REF2OMCLK_CNT_H ((volatile uint32_t *)0xfe05144c) +#define P_RO_IMCLK2REF_CNT_L ((volatile uint32_t *)0xfe051450) +#define P_RO_IMCLK2REF_CNT_H ((volatile uint32_t *)0xfe051454) +#define P_RO_OMCLK2REF_CNT_L ((volatile uint32_t *)0xfe051458) +#define P_RO_OMCLK2REF_CNT_H ((volatile uint32_t *)0xfe05145c) +#define P_RO_REFCLK_PKG_CNT ((volatile uint32_t *)0xfe051460) +#define P_RO_IMCLK_PKG_CNT ((volatile uint32_t *)0xfe051464) +#define P_RO_OMCLK_PKG_CNT ((volatile uint32_t *)0xfe051468) +#define P_RO_AUD_LOCK_INT_STATUS ((volatile uint32_t *)0xfe05146c) +//======================================================================== +// AUDIO VAD - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe051800 +// ----------------------------------------------- +// +// Reading file: VAD_REG.h +// +#define P_VAD_TOP_CTRL0 ((volatile uint32_t *)0xfe051800) +#define P_VAD_TOP_CTRL1 ((volatile uint32_t *)0xfe051804) +#define P_VAD_TOP_CTRL2 ((volatile uint32_t *)0xfe051808) +#define P_VAD_FIR_CTRL ((volatile uint32_t *)0xfe05180c) +#define P_VAD_FIR_EMP ((volatile uint32_t *)0xfe051810) +#define P_VAD_FIR_COEF0 ((volatile uint32_t *)0xfe051814) +#define P_VAD_FIR_COEF1 ((volatile uint32_t *)0xfe051818) +#define P_VAD_FIR_COEF2 ((volatile uint32_t *)0xfe05181c) +#define P_VAD_FIR_COEF3 ((volatile uint32_t *)0xfe051820) +#define P_VAD_FIR_COEF4 ((volatile uint32_t *)0xfe051824) +#define P_VAD_FIR_COEF5 ((volatile uint32_t *)0xfe051828) +#define P_VAD_FIR_COEF6 ((volatile uint32_t *)0xfe05182c) +#define P_VAD_FIR_COEF7 ((volatile uint32_t *)0xfe051830) +#define P_VAD_FIR_COEF8 ((volatile uint32_t *)0xfe051834) +#define P_VAD_FIR_COEF9 ((volatile uint32_t *)0xfe051838) +#define P_VAD_FIR_COEF10 ((volatile uint32_t *)0xfe05183c) +#define P_VAD_FIR_COEF11 ((volatile uint32_t *)0xfe051840) +#define P_VAD_FIR_COEF12 ((volatile uint32_t *)0xfe051844) +#define P_VAD_FRAME_CTRL0 ((volatile uint32_t *)0xfe051848) +#define P_VAD_FRAME_CTRL1 ((volatile uint32_t *)0xfe05184c) +#define P_VAD_FRAME_CTRL2 ((volatile uint32_t *)0xfe051850) +#define P_VAD_CEP_CTRL0 ((volatile uint32_t *)0xfe051854) +#define P_VAD_CEP_CTRL1 ((volatile uint32_t *)0xfe051858) +#define P_VAD_CEP_CTRL2 ((volatile uint32_t *)0xfe05185c) +#define P_VAD_CEP_CTRL3 ((volatile uint32_t *)0xfe051860) +#define P_VAD_CEP_CTRL4 ((volatile uint32_t *)0xfe051864) +#define P_VAD_CEP_CTRL5 ((volatile uint32_t *)0xfe051868) +#define P_VAD_DEC_CTRL ((volatile uint32_t *)0xfe05186c) +#define P_VAD_TOP_STS0 ((volatile uint32_t *)0xfe051870) +#define P_VAD_TOP_STS1 ((volatile uint32_t *)0xfe051874) +#define P_VAD_TOP_STS2 ((volatile uint32_t *)0xfe051878) +#define P_VAD_FIR_STS0 ((volatile uint32_t *)0xfe05187c) +#define P_VAD_FIR_STS1 ((volatile uint32_t *)0xfe051880) +#define P_VAD_POW_STS0 ((volatile uint32_t *)0xfe051884) +#define P_VAD_POW_STS1 ((volatile uint32_t *)0xfe051888) +#define P_VAD_POW_STS2 ((volatile uint32_t *)0xfe05188c) +#define P_VAD_FFT_STS0 ((volatile uint32_t *)0xfe051890) +#define P_VAD_FFT_STS1 ((volatile uint32_t *)0xfe051894) +#define P_VAD_SPE_STS0 ((volatile uint32_t *)0xfe051898) +#define P_VAD_SPE_STS1 ((volatile uint32_t *)0xfe05189c) +#define P_VAD_SPE_STS2 ((volatile uint32_t *)0xfe0518a0) +#define P_VAD_SPE_STS3 ((volatile uint32_t *)0xfe0518a4) +#define P_VAD_DEC_STS0 ((volatile uint32_t *)0xfe0518a8) +#define P_VAD_DEC_STS1 ((volatile uint32_t *)0xfe0518ac) +#define P_VAD_LUT_CTRL ((volatile uint32_t *)0xfe0518b0) +#define P_VAD_LUT_WR ((volatile uint32_t *)0xfe0518b4) +#define P_VAD_LUT_RD ((volatile uint32_t *)0xfe0518b8) +#define P_VAD_IN_SEL0 ((volatile uint32_t *)0xfe0518bc) +#define P_VAD_IN_SEL1 ((volatile uint32_t *)0xfe0518c0) +#define P_VAD_TO_DDR ((volatile uint32_t *)0xfe0518c4) +// +// Closing file: VAD_REG.h +// +//======================================================================== +// AUDIO RESAMPLEA - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe051c00 +// ----------------------------------------------- +// +// Reading file: RESAMPLE.h +// +#define P_AUDIO_RSAMP_CTRL0 ((volatile uint32_t *)0xfe051c00) +//Bit 31:3 reserved +//Bit 2 reg_lock_rst //unsigned , default =0; +//Bit 1 reg_rsamp_rst //unsigned , default =0; +//Bit 0 reg_sw_rst //unsigned , default =0; +#define P_AUDIO_RSAMP_CTRL1 ((volatile uint32_t *)0xfe051c04) +//Bit 31:26 reserved //unsigned , default =0; +//Bit 25 reg_rsamp_rst_sel //unsigned , default =0; +//Bit 24 reg_module_bypas //unsigned , default =0; +//Bit 23:18 reg_gclk_ctrl //unsigned , default =0; +//Bit 17:13 reg_in_msb //unsigned , default =23; +//Bit 12 reg_output_en //unsigned , default =0; +//Bit 11 reg_rsamp_en //unsigned , default =0; +//Bit 10 reg_filt_en //unsigned , default =0; +//Bit 9 reg_post_en //unsigned , default =0; +//Bit 8 reg_inp_mux_mode //unsigned , default =0; +//Bit 7:4 reserved //unsigned , default =2; +//Bit 3:0 reg_inp_mux //unsigned , default =0; +#define P_AUDIO_RSAMP_CTRL2 ((volatile uint32_t *)0xfe051c08) +//Bit 31:30 reserved //unsigned , default =0; +//Bit 29:24 reg_chx_size //unsigned , default =2; +//Bit 23:18 reserved //unsigned , default =0; +//Bit 17:16 reg_scl_step //unsigned , default =0; 0: 1/1 1: 1/2 2: 1/4 +//Bit 15:8 reg_filt_tap //unsigned , default =63; +//Bit 7:0 reg_intp_tap //unsigned , default =63; +#define P_AUDIO_RSAMP_PHSINIT ((volatile uint32_t *)0xfe051c0c) +//Bit 31:28 reserved //unsigned , default = 0; +//Bit 27:0 reg_init_phs //unsigned , default = 0; +#define P_AUDIO_RSAMP_PHSSTEP ((volatile uint32_t *)0xfe051c10) +//Bit 31 reserved //unsigned , default = 0; +//Bit 30:0 reg_rsamp_step //unsigned , default = 134217728;//'h800_0000 +#define P_AUDIO_RSAMP_SHIFT ((volatile uint32_t *)0xfe051c14) +//Bit 31:24 reg_rsft_iir //unsigned , default = 23; +//Bit 23:16 reg_rsft_blnd //unsigned , default = 21; +//Bit 15:8 reg_rsft_sinc //unsigned , default = 31; +//Bit 7:0 reg_rsft_aa //unsigned , default = 31; +#define P_AUDIO_RSAMP_ADJ_CTRL0 ((volatile uint32_t *)0xfe051c18) +//Bit 31:3 reserved //unsigned +//Bit 2 reg_rsamp_adj_out_inv //unsigned , default = 0; +//Bit 1 reg_rsamp_adj_force_en //unsigned , default = 0; +//Bit 0 reg_rsamp_adj_en //unsigned , default = 0; +#define P_AUDIO_RSAMP_ADJ_CTRL1 ((volatile uint32_t *)0xfe051c1c) +//Bit 31:16 reg_rsamp_adj_odet_step //unsigned , default = 8; +//Bit 15:0 reg_rsamp_adj_kmax //unsigned , default = 32768; +#define P_AUDIO_RSAMP_ADJ_SFT ((volatile uint32_t *)0xfe051c20) +//Bit 31:30 reserved //unsigned , default = 0; +//Bit 29 reg_rsamp_adj_dif_sel //unsigned , default = 0; +//Bit 28:24 reg_rsamp_adj_ki //unsigned , default = 9; +//Bit 23:21 reserved //unsigned , default = 0; +//Bit 20:16 reg_rsamp_adj_kp //unsigned , default = 1; +//Bit 15:13 reserved //unsigned , default = 0; +//Bit 12:8 reg_rsamp_adj_ki_sft //unsigned , default = 6; +//Bit 7:6 reserved //unsigned , default = 0; +//Bit 5:0 reg_rsamp_adj_out_sft //unsigned , default = 12; +#define P_AUDIO_RSAMP_ADJ_IDET_LEN ((volatile uint32_t *)0xfe051c24) +//Bit 31:0 reg_rsamp_adj_idet_len //unsigned , default = 10000; +#define P_AUDIO_RSAMP_ADJ_FORCE ((volatile uint32_t *)0xfe051c28) +//Bit 31:0 reg_rsamp_adj_force_err //signed , default = 8; +#define P_AUDIO_RSAMP_ADJ_KI_FORCE ((volatile uint32_t *)0xfe051c2c) +//Bit 31:0 reg_rsamp_adj_ki_force //signed , default = 0; +#define P_AUDIO_RSAMP_RO_STATUS ((volatile uint32_t *)0xfe051c40) +//Bit 31:0 ro_rsamp_stat //{din_chx_chk_err,is_idle_st,rsamp_fifo_over_cnt[7:0]} +#define P_AUDIO_RSAMP_RO_ADJ_FREQ ((volatile uint32_t *)0xfe051c44) +//Bit 31:0 ro_rsamp_adj_freq +#define P_AUDIO_RSAMP_RO_ADJ_DIFF_BAK ((volatile uint32_t *)0xfe051c48) +//Bit 31:0 ro_det_diff_bak +#define P_AUDIO_RSAMP_RO_ADJ_DIFF_DLT ((volatile uint32_t *)0xfe051c4c) +//Bit 31:0 ro_det_diff_dlt +#define P_AUDIO_RSAMP_RO_ADJ_PHS_ERR ((volatile uint32_t *)0xfe051c50) +//Bit 31:0 ro_det_phase_err +#define P_AUDIO_RSAMP_RO_ADJ_KI_OUT ((volatile uint32_t *)0xfe051c54) +//Bit 31:0 ro_rsamp_ki_out +#define P_AUDIO_RSAMP_RO_IN_CNT ((volatile uint32_t *)0xfe051c58) +//Bit 31:0 ro_rsamp_in_cnt +#define P_AUDIO_RSAMP_RO_OUT_CNT ((volatile uint32_t *)0xfe051c5c) +//Bit 31:0 ro_rsamp_out_cnt +#define P_AUDIO_RSAMP_POST_COEF0 ((volatile uint32_t *)0xfe051c80) +//Bit 31:0 reg_post_coef0 //signed , default = 0; +#define P_AUDIO_RSAMP_POST_COEF1 ((volatile uint32_t *)0xfe051c84) +//Bit 31:0 reg_post_coef1 //signed , default = 0; +#define P_AUDIO_RSAMP_POST_COEF2 ((volatile uint32_t *)0xfe051c88) +//Bit 31:0 reg_post_coef2 //signed , default = 0; +#define P_AUDIO_RSAMP_POST_COEF3 ((volatile uint32_t *)0xfe051c8c) +//Bit 31:0 reg_post_coef3 //signed , default = 0; +#define P_AUDIO_RSAMP_POST_COEF4 ((volatile uint32_t *)0xfe051c90) +//Bit 31:0 reg_post_coef4 //signed , default = 0; +#define P_AUDIO_RSAMP_AA_COEF_ADDR ((volatile uint32_t *)0xfe051cc0) +//Bit 31:0 reg_aa_coef_addr //unsigned, default = 0; +#define P_AUDIO_RSAMP_AA_COEF_DATA ((volatile uint32_t *)0xfe051cc4) +//Bit 31:0 reg_aa_coef_data //signed , default = 0; +#define P_AUDIO_RSAMP_SINC_COEF_ADDR ((volatile uint32_t *)0xfe051d00) +//Bit 31:0 reg_sinc_coef_addr //unsigned, default = 0; +#define P_AUDIO_RSAMP_SINC_COEF_DATA ((volatile uint32_t *)0xfe051d04) +//Bit 31:0 reg_sinc_coef_data //signed , default = 0; +// +// Closing file: RESAMPLE.h +// +//======================================================================== +// AUDIO TOP_VAD - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe054800 +// ----------------------------------------------- +#define P_EE_AUDIO2_CLK81_CTRL ((volatile uint32_t *)0xfe054800) +#define P_EE_AUDIO2_CLK81_EN ((volatile uint32_t *)0xfe054804) +#define P_EE_AUDIO2_SW_RESET0 ((volatile uint32_t *)0xfe054808) +#define P_EE_AUDIO2_CLK_GATE_EN0 ((volatile uint32_t *)0xfe05480c) +#define P_EE_AUDIO2_SECURITY_CTRL0 ((volatile uint32_t *)0xfe054810) +#define P_EE_AUDIO2_MCLK_VAD_CTRL ((volatile uint32_t *)0xfe054840) +#define P_EE_AUDIO2_VAD_CLK_CTRL ((volatile uint32_t *)0xfe054844) +#define P_EE_AUDIO2_MST_DLY_CTRL0 ((volatile uint32_t *)0xfe054848) +#define P_EE_AUDIO2_MST_VAD_SCLK_CTRL0 ((volatile uint32_t *)0xfe05484c) +#define P_EE_AUDIO2_MST_VAD_SCLK_CTRL1 ((volatile uint32_t *)0xfe054850) +#define P_EE_AUDIO2_CLK_TDMIN_VAD_CTRL ((volatile uint32_t *)0xfe054854) +#define P_EE_AUDIO2_CLK_PDMIN_CTRL0 ((volatile uint32_t *)0xfe054858) +#define P_EE_AUDIO2_CLK_PDMIN_CTRL1 ((volatile uint32_t *)0xfe05485c) +#define P_EE_AUDIO2_TOVAD_CTRL0 ((volatile uint32_t *)0xfe054880) +#define P_EE_AUDIO2_TODDR_VAD_CTRL0 ((volatile uint32_t *)0xfe0548c0) +#define P_EE_AUDIO2_TODDR_VAD_CTRL1 ((volatile uint32_t *)0xfe0548c4) +#define P_EE_AUDIO2_TODDR_VAD_CTRL2 ((volatile uint32_t *)0xfe0548c8) +#define P_EE_AUDIO2_TODDR_VAD_START_ADDR ((volatile uint32_t *)0xfe0548cc) +#define P_EE_AUDIO2_TODDR_VAD_INIT_ADDR ((volatile uint32_t *)0xfe0548d0) +#define P_EE_AUDIO2_TODDR_VAD_FINISH_ADDR ((volatile uint32_t *)0xfe0548d4) +#define P_EE_AUDIO2_TODDR_VAD_START_ADDRB ((volatile uint32_t *)0xfe0548d8) +#define P_EE_AUDIO2_TODDR_VAD_FINISH_ADDRB ((volatile uint32_t *)0xfe0548dc) +#define P_EE_AUDIO2_TODDR_VAD_INT_ADDR ((volatile uint32_t *)0xfe0548e0) +#define P_EE_AUDIO2_TODDR_VAD_STATUS1 ((volatile uint32_t *)0xfe0548e4) +#define P_EE_AUDIO2_TODDR_VAD_STATUS2 ((volatile uint32_t *)0xfe0548e8) +#define P_EE_AUDIO2_TDMIN_VAD_CTRL ((volatile uint32_t *)0xfe054900) +#define P_EE_AUDIO2_TDMIN_VAD_SWAP0 ((volatile uint32_t *)0xfe054904) +#define P_EE_AUDIO2_TDMIN_VAD_SWAP1 ((volatile uint32_t *)0xfe054908) +#define P_EE_AUDIO2_TDMIN_VAD_MUTE_VAL ((volatile uint32_t *)0xfe05490c) +#define P_EE_AUDIO2_TDMIN_VAD_STAT ((volatile uint32_t *)0xfe054910) +#define P_EE_AUDIO2_TDMIN_VAD_MUTE0 ((volatile uint32_t *)0xfe054940) +#define P_EE_AUDIO2_TDMIN_VAD_MUTE1 ((volatile uint32_t *)0xfe054944) +#define P_EE_AUDIO2_TDMIN_VAD_MUTE2 ((volatile uint32_t *)0xfe054948) +#define P_EE_AUDIO2_TDMIN_VAD_MUTE3 ((volatile uint32_t *)0xfe05494c) +#define P_EE_AUDIO2_TDMIN_VAD_MUTE4 ((volatile uint32_t *)0xfe054950) +#define P_EE_AUDIO2_TDMIN_VAD_MUTE5 ((volatile uint32_t *)0xfe054954) +#define P_EE_AUDIO2_TDMIN_VAD_MUTE6 ((volatile uint32_t *)0xfe054958) +#define P_EE_AUDIO2_TDMIN_VAD_MUTE7 ((volatile uint32_t *)0xfe05495c) +#define P_EE_AUDIO2_TDMIN_VAD_MASK0 ((volatile uint32_t *)0xfe054960) +#define P_EE_AUDIO2_TDMIN_VAD_MASK1 ((volatile uint32_t *)0xfe054964) +#define P_EE_AUDIO2_TDMIN_VAD_MASK2 ((volatile uint32_t *)0xfe054968) +#define P_EE_AUDIO2_TDMIN_VAD_MASK3 ((volatile uint32_t *)0xfe05496c) +#define P_EE_AUDIO2_TDMIN_VAD_MASK4 ((volatile uint32_t *)0xfe054970) +#define P_EE_AUDIO2_TDMIN_VAD_MASK5 ((volatile uint32_t *)0xfe054974) +#define P_EE_AUDIO2_TDMIN_VAD_MASK6 ((volatile uint32_t *)0xfe054978) +#define P_EE_AUDIO2_TDMIN_VAD_MASK7 ((volatile uint32_t *)0xfe05497c) +// +// Closing file: REG_LIST_AUDIO_RTL.h +// +// +// Reading file: ../spifc/rtl/spifc_reg.vh +// +//`ifdef SPIFC_REG_DEFINE +//`else +//`define SPIFC_REG_DEFINE +//`define SPIFC BASE ADDR 32'hfd000400 +// ----------------------------------------------- +// APB_BASE: APB2_BASE_ADDR = 0xfd000400 +// ----------------------------------------------- +//AHB domain regsiter. +#define P_SPIFC_AHB_CTRL ((volatile uint32_t *)0xfd000400) +//bit 31 AHB BUS enable. 1 enable ahb request. 0: disable ahb request. +//bit 30. decerr_en for (AXI->AHB bridge). +//bit 29. force_incr. for ( AXI->AHB bridge). +//bit 19. critical word first. CWF_EN. 1: enable. 0 : disable. +//bit 18:17 RDBUF_SIZE . 00: 64bytes. 01: 32 bytes. 10: 16 bytes. 11: reserved. +//bit 16 AHB MASTER enable. if enabled, each master use one dedicated HRDATA buffer inside ahb2api model. total 3 HRDATA buffers inside ahb2spi. +//if disabled the 3 HRDATA buffer will random be used for all masters. +//bit 14 write 1 to clean the HRDATA buffer 2. read 0 finished clean operation. +//bit 13 write 1 to clean the HRDATA buffer 1. read 0 finished clean operation. +//bit 12 write 1 to clean the HRDATA buffer 0. read 0 finished clean operation. +//bit 11:0. not used. +#define P_SPIFC_CLK_CTRL ((volatile uint32_t *)0xfd000404) +//bit 14 asynchronous buffer ahb clock disable. 1 = disable. 0 = enable. +//bit 13 ahb2spi ahb clock disable. 1 = disable. 0 = enable. +//bit 12 ahb_arb ahb clock disable. 1 = disable. 0 = enable. +//bit 10 asynchronous buffer ahb clock auto gating enable. 1 = enable. 0 = disable. +//bit 9 ahb2spi ahb clock auto gating enable. 1 = enable. 0 = disable. +//bit 8 ahbarb ahb clock auto gating enable. 1 = enable. 0 = disable. +//bit 2. asynchronous AHB clock domain software reset. 1 = reset. 0 = normal working mode. +//bit 1. ahb2spi ahb clock domain software reset. 1 = reset. 0 = normal working mode. +//bit 0. not used. +#define P_SPIFC_SEC_CTRL ((volatile uint32_t *)0xfd000408) +//bit 31. ADDRESS security range enable. 1 = enable; 0: disable. +//bit 14. range6 enable: 1: enable; 0 : disable. +//bit 13. range5 enable: 1: enable; 0 : disable. +//bit 12. range4 enable: 1: enable; 0 : disable. +//bit 11. range3 enable: 1: enable; 0 : disable. +//bit 10. range2 enable: 1: enable; 0 : disable. +//bit 9. range1 enable: 1: enable; 0 : disable. +//bit 8. range0 enable: 1: enable; 0 : disable. +//bit 7:4 to control spi clock register security. bit 7 = 1, APB bus can access spi clock domain register. bit 7 == 0 : only PPROT[0] == bit 4, the APB can access spic clock domain register. +//bit 3:0 to control ahb clock domain register secruity. bit 3 = 1, APB bus can access ahb clock domain register. bit 3 ==0; only PPROT[0] == bit 0, the APB can access ahb clock domain register. +#define P_SPIFC_RANGE0_STA ((volatile uint32_t *)0xfd000440) +//bit 28 :6. +//AHB security range 0 start address in unit of 64Byte. related to HADDR bit 28:6. +//bit 5:0. always 0. +#define P_SPIFC_RANGE0_EDA ((volatile uint32_t *)0xfd000444) +//bit 28 :6. +//AHB security range 0 end address in unit of 64Byte. related to HADDR bit 28:6. +//bit 5:0. always 0. +#define P_SPIFC_RANGE0_CTRL ((volatile uint32_t *)0xfd000448) +// AHB secruity range 0 control. +//bit 15:8 range 0 access control for DMA access. +//bit 15 range 0 access control for DMA thread 7 +//bit 14 range 0 access control for DMA Thread 6 +//bit 13 range 0 access control for DMA Thread 5. +//bit 12 range 0 access control for DMA Thread 4. +// bit 11. range 0 access control for DMA thread 3 +// bit 10. range 0 access control for DMA Thread 2 +// bit 9. range 0 access control for DMA Thread 1. +// bit 8. range 0 access control for DMA Thread 0. +// bit 7. range 0 access control for HMASTER == 7 Not used. +// bit 6. range 0 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA. +// bit 5. range 0 access control for HMASTER == 5 //DSPB non secure +// bit 4. range 0 access control for HMASTER == 4 //DSPB non secure +// bit 3. range 0 access control for HMASTER == 3 //DSPA secure +// bit 2. range 0 access control for HMASTER == 2 //DSPA non secure +// bit 1. range 0 access control for HMASTER == 1 //CPU secure access +// bit 0. range 0 access control for HMASTER == 0 //CPU non secure. +#define P_SPIFC_RANGE1_STA ((volatile uint32_t *)0xfd00044c) +//bit 28 :6. +//AHB security range 1 start address in unit of 64Byte. related to HADDR bit 28:6. +//bit 5:0. always 0. +#define P_SPIFC_RANGE1_EDA ((volatile uint32_t *)0xfd000450) +//bit 28 :6. +//AHB security range 1 end address in unit of 64Byte. related to HADDR bit 28:6. +//bit 5:0. always 0. +#define P_SPIFC_RANGE1_CTRL ((volatile uint32_t *)0xfd000454) +// AHB secruity range 1 control. +//bit 15:8 range 1 access control for DMA access. +//bit 15 range 1 access control for DMA thread 7 +//bit 14 range 1 access control for DMA Thread 6 +//bit 13 range 1 access control for DMA Thread 5. +//bit 12 range 1 access control for DMA Thread 4. +// bit 11. range 1 access control for DMA thread 3 +// bit 10. range 1 access control for DMA Thread 2 +// bit 9. range 1 access control for DMA Thread 1. +// bit 8. range 1 access control for DMA Thread 0. +// bit 7. range 1 access control for HMASTER == 7 Not used. +// bit 6. range 1 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA. +// bit 5. range 1 access control for HMASTER == 5 //DSPB non secure +// bit 4. range 1 access control for HMASTER == 4 //DSPB non secure +// bit 3. range 1 access control for HMASTER == 3 //DSPA secure +// bit 2. range 1 access control for HMASTER == 2 //DSPA non secure +// bit 1. range 1 access control for HMASTER == 1 //CPU secure access +// bit 0. range 1 access control for HMASTER == 0 //CPU non secure. +#define P_SPIFC_RANGE2_STA ((volatile uint32_t *)0xfd000458) +//bit 28 :6. +//AHB security range 2 start address in unit of 64Byte. related to HADDR bit 28:6. +//bit 5:0. always 0. +#define P_SPIFC_RANGE2_EDA ((volatile uint32_t *)0xfd00045c) +//bit 28 :6. +//AHB security range 2 end address in unit of 64Byte. related to HADDR bit 28:6. +//bit 5:0. always 0. +#define P_SPIFC_RANGE2_CTRL ((volatile uint32_t *)0xfd000460) +// AHB secruity range 2 control. +//bit 15:8 range 2 access control for DMA access. +//bit 15 range 2 access control for DMA thread 7 +//bit 14 range 2 access control for DMA Thread 6 +//bit 13 range 2 access control for DMA Thread 5. +//bit 12 range 2 access control for DMA Thread 4. +// bit 11. range 2 access control for DMA thread 3 +// bit 10. range 2 access control for DMA Thread 2 +// bit 9. range 2 access control for DMA Thread 1. +// bit 8. range 2 access control for DMA Thread 0. +// bit 7. range 2 access control for HMASTER == 7 Not used. +// bit 6. range 2 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA. +// bit 5. range 2 access control for HMASTER == 5 //DSPB non secure +// bit 4. range 2 access control for HMASTER == 4 //DSPB non secure +// bit 3. range 2 access control for HMASTER == 3 //DSPA secure +// bit 2. range 2 access control for HMASTER == 2 //DSPA non secure +// bit 1. range 2 access control for HMASTER == 1 //CPU secure access +// bit 0. range 2 access control for HMASTER == 0 //CPU non secure. +#define P_SPIFC_RANGE3_STA ((volatile uint32_t *)0xfd000464) +//bit 28 :6. +//AHB security range 3 start address in unit of 64Byte. related to HADDR bit 28:6. +//bit 5:0. always 0. +#define P_SPIFC_RANGE3_EDA ((volatile uint32_t *)0xfd000468) +//bit 28 :6. +//AHB security range 3 end address in unit of 64Byte. related to HADDR bit 28:6. +//bit 5:0. always 0. +#define P_SPIFC_RANGE3_CTRL ((volatile uint32_t *)0xfd00046c) +// AHB secruity range 3 control. +//bit 15:8 range 3 access control for DMA access. +//bit 15 range 3 access control for DMA thread 7 +//bit 14 range 3 access control for DMA Thread 6 +//bit 13 range 3 access control for DMA Thread 5. +//bit 12 range 3 access control for DMA Thread 4. +// bit 11. range 3 access control for DMA thread 3 +// bit 10. range 3 access control for DMA Thread 2 +// bit 9. range 3 access control for DMA Thread 1. +// bit 8. range 3 access control for DMA Thread 0. +// bit 7. range 3 access control for HMASTER == 7 Not used. +// bit 6. range 3 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA. +// bit 5. range 3 access control for HMASTER == 5 //DSPB non secure +// bit 4. range 3 access control for HMASTER == 4 //DSPB non secure +// bit 3. range 3 access control for HMASTER == 3 //DSPA secure +// bit 2. range 3 access control for HMASTER == 2 //DSPA non secure +// bit 1. range 3 access control for HMASTER == 1 //CPU secure access +// bit 0. range 3 access control for HMASTER == 0 //CPU non secure. +#define P_SPIFC_RANGE4_STA ((volatile uint32_t *)0xfd000470) +//bit 28 :6. +//AHB security range 4 start address in unit of 64Byte. related to HADDR bit 28:6. +//bit 5:0. always 0. +#define P_SPIFC_RANGE4_EDA ((volatile uint32_t *)0xfd000474) +//bit 28 :6. +//AHB security range 4 end address in unit of 64Byte. related to HADDR bit 28:6. +//bit 5:0. always 0. +#define P_SPIFC_RANGE4_CTRL ((volatile uint32_t *)0xfd000478) +// AHB secruity range 4 control. +//bit 15:8 range 4 access control for DMA access. +//bit 15 range 4 access control for DMA thread 7 +//bit 14 range 4 access control for DMA Thread 6 +//bit 13 range 4 access control for DMA Thread 5. +//bit 12 range 4 access control for DMA Thread 4. +// bit 11. range 4 access control for DMA thread 3 +// bit 10. range 4 access control for DMA Thread 2 +// bit 9. range 4 access control for DMA Thread 1. +// bit 8. range 4 access control for DMA Thread 0. +// bit 7. range 4 access control for HMASTER == 7 Not used. +// bit 6. range 4 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA. +// bit 5. range 4 access control for HMASTER == 5 //DSPB non secure +// bit 4. range 4 access control for HMASTER == 4 //DSPB non secure +// bit 3. range 4 access control for HMASTER == 3 //DSPA secure +// bit 2. range 4 access control for HMASTER == 2 //DSPA non secure +// bit 1. range 4 access control for HMASTER == 1 //CPU secure access +// bit 0. range 4 access control for HMASTER == 0 //CPU non secure. +#define P_SPIFC_RANGE5_STA ((volatile uint32_t *)0xfd00047c) +//bit 28 :6. +//AHB security range 5 start address in unit of 64Byte. related to HADDR bit 28:6. +//bit 5:0. always 0. +#define P_SPIFC_RANGE5_EDA ((volatile uint32_t *)0xfd000484) +//bit 28 :6. +//AHB security range 5 end address in unit of 64Byte. related to HADDR bit 28:6. +//bit 5:0. always 0. +#define P_SPIFC_RANGE5_CTRL ((volatile uint32_t *)0xfd000480) +// AHB secruity range 5 control. +//bit 15:8 range 5 access control for DMA access. +//bit 15 range 5 access control for DMA thread 7 +//bit 14 range 5 access control for DMA Thread 6 +//bit 13 range 5 access control for DMA Thread 5. +//bit 12 range 5 access control for DMA Thread 4. +// bit 11. range 5 access control for DMA thread 3 +// bit 10. range 5 access control for DMA Thread 2 +// bit 9. range 5 access control for DMA Thread 1. +// bit 8. range 5 access control for DMA Thread 0. +// bit 7. range 5 access control for HMASTER == 7 Not used. +// bit 6. range 5 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA. +// bit 5. range 5 access control for HMASTER == 5 //DSPB non secure +// bit 4. range 5 access control for HMASTER == 4 //DSPB non secure +// bit 3. range 5 access control for HMASTER == 3 //DSPA secure +// bit 2. range 5 access control for HMASTER == 2 //DSPA non secure +// bit 1. range 5 access control for HMASTER == 1 //CPU secure access +// bit 0. range 5 access control for HMASTER == 0 //CPU non secure. +#define P_SPIFC_RANGE6_STA ((volatile uint32_t *)0xfd000488) +//bit 28 :6. +//AHB security range 6 start address in unit of 64Byte. related to HADDR bit 28:6. +//bit 5:0. always 0. +#define P_SPIFC_RANGE6_EDA ((volatile uint32_t *)0xfd00048c) +//bit 28 :6. +//AHB security range 6 end address in unit of 64Byte. related to HADDR bit 28:6. +//bit 5:0. always 0. +#define P_SPIFC_RANGE6_CTRL ((volatile uint32_t *)0xfd000490) +// AHB secruity range 6 control. +//bit 15:8 range 6 access control for DMA access. +//bit 15 range 6 access control for DMA thread 7 +//bit 14 range 6 access control for DMA Thread 6 +//bit 13 range 6 access control for DMA Thread 5. +//bit 12 range 6 access control for DMA Thread 4. +// bit 11. range 6 access control for DMA thread 3 +// bit 10. range 6 access control for DMA Thread 2 +// bit 9. range 6 access control for DMA Thread 1. +// bit 8. range 6 access control for DMA Thread 0. +// bit 7. range 6 access control for HMASTER == 7 Not used. +// bit 6. range 6 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA. +// bit 5. range 6 access control for HMASTER == 5 //DSPB non secure +// bit 4. range 6 access control for HMASTER == 4 //DSPB non secure +// bit 3. range 6 access control for HMASTER == 3 //DSPA secure +// bit 2. range 6 access control for HMASTER == 2 //DSPA non secure +// bit 1. range 6 access control for HMASTER == 1 //CPU secure access +// bit 0. range 6 access control for HMASTER == 0 //CPU non secure. +#define P_SPIFC_RANGE7_CTRL ((volatile uint32_t *)0xfd000494) +// AHB secruity range 7( default range) control. +//bit 15:8 range 7 access control for DMA access. +//bit 15 range 7 access control for DMA thread 7 +//bit 14 range 7 access control for DMA Thread 6 +//bit 13 range 7 access control for DMA Thread 5. +//bit 12 range 7 access control for DMA Thread 4. +// bit 11. range 7 access control for DMA thread 3 +// bit 10. range 7 access control for DMA Thread 2 +// bit 9. range 7 access control for DMA Thread 1. +// bit 8. range 7 access control for DMA Thread 0. +// bit 7. range 7 access control for HMASTER == 7 Not used. +// bit 6. range 7 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA. +// bit 5. range 7 access control for HMASTER == 5 //DSPB non secure +// bit 4. range 7 access control for HMASTER == 4 //DSPB non secure +// bit 3. range 7 access control for HMASTER == 3 //DSPA secure +// bit 2. range 7 access control for HMASTER == 2 //DSPA non secure +// bit 1. range 7 access control for HMASTER == 1 //CPU secure access +// bit 0. range 7 access control for HMASTER == 0 //CPU non secure. +#define P_SPIFC_AHB_WTCH_CTRL ((volatile uint32_t *)0xfd000498) +//bit 15:0. ahb bus watch dog timer. if AHB bus not response, the timer over this number, the SPIFC will send back a error response. +#define P_SPIFC_SEC_VIO0 ((volatile uint32_t *)0xfd00049c) +//bit 31:0 VIO ADDR +#define P_SPIFC_SEC_VIO1 ((volatile uint32_t *)0xfd0004a0) +//bit 31. AHB VIO status. write 1 to clear the error info. +//bit 6:5 HMASTER. +//bit 4:2 HPROT. +//bit 1 HNONSEC. +//bit 0 HWRITE. +#define P_SPIFC_AHB_STS ((volatile uint32_t *)0xfd0004a4) +//bit 31. AHB IDLE. when ahb disabled, to show ahb status. 1, no more ahb request or ahb requent is holded. 0, ahb is still busy. +//bit 30. AHB data cycle status, when ahb disabled, to show ahb data cycle status. 1, data cycle is holded, 0 : not in data cycle or data cycle is processing. +//bit 29. AHB bus spi requst status. 1: still waiting for spi data. 0: idle. +//bit 28:0. not used. +//SPI cts_spi_clk domain regsiter. +#define P_SPIFC_USER_CTRL0 ((volatile uint32_t *)0xfd000600) +//bit 31. user request enable. write 1 to enable. read 0, means user command accepted by the SPI_CTRL. +//bit 30. user request finish bit. write 0 when enable user request. read 1 means SPI_CTRL finished this user command. +//bit 0. user data updated. write 0 when enable user request. 1 means there's datas/status read from SPI flash. +#define P_SPIFC_USER_CTRL1 ((volatile uint32_t *)0xfd000604) +//bit 31. not used. +//bit 30. user command cycle enable. 1) enable. 0) don't send command in usr command period. +//bit 29:28. user command mode. 00 = SPI extend mode. 01 : dual mode. 10: quad mode. +//bit 27:20. user command code. the code need to send in command period. +//bit 19. user address cycle enable. +//bit 18:17 user address mode: 00 = SPI extend mode. 01 : dual mode. 10: quad mode. +//bit 16:15 user address Byte length 00 = 1 byte. 01 = 2 bytes. 10 = 3 bytes. 11 = 4bytes. +//bit 14 user datout enable. +//bit 13 user dataout AES enable. 1: dataout through AES describle. 0 : original data. +//bit 12 user data output source. 0: from data buffer. 1: from status register. +//bit 11:10 user dataout mode: 00 SPI extend model. 01 : dual model. 10. quad mode. +//bit 9:0 User data out bytes num. +#define P_SPIFC_USER_CTRL2 ((volatile uint32_t *)0xfd000608) +//bit 31 usr_dummy_en 1: enable dummy cycles. 0 : no dummy cycles. +//bit 30: 29 usr_dummy_mode 2'b00 = SPI extend mode. 01 dual mode. 10 Quad mode. +//bit 28:23 user dummy clock cycle number. +//bit 19:16. user command input/output direction control. 000000: right after the last output. +// 1: after the first cycle of dummy cycle. +// ..... +// 4'hf: right before the datin cycle. +//bit 15:8. data on the dummy cycle after the first byte. +//bit 7:0 The first bytes data showed on dummy cycle. some flash may need special data for enhance performance mode or XIP mode. +#define P_SPIFC_USER_CTRL3 ((volatile uint32_t *)0xfd00060c) +//bit 31 usr_datin_en 1: datain cycle enabled. 0: no datain cycle. +//bit 30: datin_dest. 1: save the input data to STATUS register. 0 save the input data to data buffer. +//bit 29: 1: enable datain data AES describle. 0: not use AES. +//bit 28:27. datin mode. 2'b00 SPI extend mode. 01: dual mode. 10 Quad mode. +//bit 25:16. user data in data bytes. how many bytes of user datain expected. +#define P_SPIFC_USER_ADDR ((volatile uint32_t *)0xfd000610) +//bit 31:0. 32bits user address. +#define P_SPIFC_AHB_REQ_CTRL ((volatile uint32_t *)0xfd000614) +//bit 31. AHB request enable. +//bit 30 AHB cmd_en. command cycle enable. +//bit 29:28. ahb command mode. 2'b00: spi mode. 01: dual mode. 10 Quad mode. +//bit 27:20:.AHB command code. +//bit 19. ahb request address cycle enable. +//bit 18:17 AHB ADDRESS mode. 2'b00: spi mode. 01: dual mode. 10 Quad mode. +//bit 16:15 AHB ADDRESS data width. 2'b00: 1byte. 2'b01 : 2bytes. 2'b10: 3bytes. 2'b11 4bytes. +//bit 13:10 AHB request spi bus input switch time. 0 : after address cycle. 1: the frist dummy cycles. ... 0xf. after dummy cycle. +//bit 9:8 AHB DATAIN mode. 2'b00: spi mode. 01: dual mode. 10 Quad mode. +//bit 7 DATA IN AES enable. 1: enable 0: disable. +//bit 1:0 AHB REQ DATA size. 2'b00: 64bytes. 2'b01: 32 bytes. 2'b10 : 16 bytes. 2'b11: reserved. this bit settign should be same as RDBUF_SIZE setting. +#define P_SPIFC_AHB_REQ_CTRL1 ((volatile uint32_t *)0xfd000618) +//bit 31. ahb Dummy enable. +//bit 30:29. ahb dummy mode. +//bit 28:23. ahb request dummy clock cycles. +//bit 15:0. ahb dummy period output data. +#define P_SPIFC_AHB_REQ_CTRL2 ((volatile uint32_t *)0xfd00061c) +//bit 1:0 AHB address position. this settign depend on SPIFC_AHB_CTRL register CWF_EN bit and RDBUF_SIZE. +// if CWF_EN is enabled. these bit should be set to 2'b10 (16BYTE boundary). +// if CWF_EN is disabled. these bit should be set to same as the RDBUF_SIZE and AHB REQ DATA SIZE. +//00 : 64byte boundary. +//01 : 32byte boundary. +//10 : 16byte boundary. +//11 : reserved. +#define P_SPIFC_ACTIMING0 ((volatile uint32_t *)0xfd000620) +//bit 31:30. tSLCH +//bit 29:28 tCLSH +//bit 20:16 tSHWL +//bit 15:12 tSHSL2 +//bit 11:8 tSHSL1 +//bit 7:0 tWHSL +#define P_SPIFC_ACTIMING1 ((volatile uint32_t *)0xfd000624) +//bit 31. D2 pin WP_n function enable. +//bit 30. D2 Pin value in WP_n fucntion. +//bit 29. D3 Pin HOLD_n function enable. +//bit 8. DTR mode. not support. +//bit 6:4. Clock turn around delay. use it to set the system SPI clock read data delay. +//bit 3:0. not used. +#define P_SPIFC_ACTIMING2 ((volatile uint32_t *)0xfd000628) +//bit 31. spi clock input pin enable. SPIFC controller used this pin as clock to latch the input data. +//bit [3:0] spi clock input pin delay adjustment. +//SPI DATA BUFFER. There's a total 512Byte + 64byte(orgnized as 36x128bits) SRAM . +// since each APB access is 32bits. So we use word address as APB read/write address. +// But for SPI side we have to use 128bit boundary. That's the first Pragram/read SPI with data buffer must start at data buffer 128bit boundary. that means the SPIFC_USE_DBUF_ADDR last 2 bits must be 0. +#define P_SPIFC_DBUF_CTRL ((volatile uint32_t *)0xfd000640) +//bit 31. 1 = write DBUF. 0 : read DBUF. +//bit 30. 1. = auto update address. 0 don't change address. +//bit 7:0 DBUF address unit 32bits. +#define P_SPIFC_DBUF_DATA ((volatile uint32_t *)0xfd000644) +//bit 31:0. if SPIFC_DBUF_CTRL bit 31 = 1. write to this register will trigger one write to DBUF. and the data will be writen to DBUF. +#define P_SPIFC_USER_DBUF_ADDR ((volatile uint32_t *)0xfd000648) +//bit 7:0. the DBUF ADDRESS used to send to or receive from SPI FLASH. the last 2 bits must be 0. +#define P_SPIFC_FLASH_STATUS ((volatile uint32_t *)0xfd000680) +#define P_SPIFC_STATUS ((volatile uint32_t *)0xfd000684) +//bit 1. AES KEY valid. read only 1 : The aes key is ready to use. 0: the aes key is not ready. +//bit 0. SPI CTRL STATE IDLE. read only. 1 = idle; 0 = busy. +#define P_SPIFC_CTRL ((volatile uint32_t *)0xfd000688) +//bit 15:14. mempd for DBUF MEMORY. +//bit 13 spifc asynchronous buffer clock disable. 1 = disable. 0 = enable. +//bit 12. spifc controller clock disable. 1 = disable. 0 = enable. +//bit 9. spifc asynchronous bufer clock auto gate enable. 1 = enable. 0 = disable. +//bit 8. spifc controller clock auto gate enable. 1 = enable. 0 = disable. +//bit 2. spifc interface reset. 1 = RESET. 0 = normal working mode. +//bit 1. spifc asynchronous buffer spi clock side reset. 1 = RESET. 0 : normal working mode. +//bit 0. spifc controller reset. 1 = RESET. 0 : normal working mode. +//`endif +// +// Closing file: ../spifc/rtl/spifc_reg.vh +// +// +// Reading file: ../psram/rtl/psram_reg.vh +// +//`ifdef PSRAM_REG_DEFINE +//`else +//`define PSRAM_REG_DEFINE +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe007400 +// ----------------------------------------------- +#define P_PSRAM_AXI_INTF_CTRL ((volatile uint32_t *)0xfe007400) +//bit 3 axi interface soft reset. 1 = reset AXI interface. 0 = normal. +//bit 2 disable axi interface clock. 1 = disable; 0 = enable. +//bit 1 axi interface auto clock gating enable. 1 = enable; 0 = disable. +//bit 0 axi interface AXI request enable. 1 = enable. 0 = disable. +#define P_PSRAM_DBUF_CTRL ((volatile uint32_t *)0xfe007404) +//bit 16. MWRITE_EN. 1 : enabel mask write(with DM pin). 0 not enable. +//bit 15:0 DBUF AGE to write back to PSRAM if DBUF is dirty. but whole DBUF data is not READ to write.(with MWRITE enabled). +#define P_PSRAM_DBUF_CTRL1 ((volatile uint32_t *)0xfe007408) +//bit 15:0 DBUF AGE to write back to psram if DBUF is dirty and whole DBUF data is ready to write. +#define P_PSRAM_APB_CTRL ((volatile uint32_t *)0xfe00740c) +//7:4 PSRAM PHY register APB secure contrl. +//bit 7, 1: no secure control. 0 : use bit 4 to match PPROT[0] bit. +//bit 4. when bit 7 == 0, bit 4 must match PPROT[0] to access. +//3:0 PCTL_CTRL APB bus control regsiters secure control. +//bit 3, 1: no secure control. 0 : use bit 0 to match PPROT[0] bit. +//bit 0. when bit 3 == 0, bit 0 must match PPROT[0] to access. +#define P_PSRAM_SEC_CTRL ((volatile uint32_t *)0xfe007410) +//bit 31. ADDRESS security range enable. 1 = enable; 0: disable. +//if scruity range disabled, but AXI data describle enabled key0 is selected. +//bit 23 range 7 des key selection 0 : key0; 1: key1; +//bit 22 range 6 des key selection 0 : key0; 1: key1; +//bit 21 range 5 des key selection 0 : key0; 1: key1; +//bit 20 range 4 des key selection 0 : key0; 1: key1; +//bit 19 range 3 des key selection 0 : key0; 1: key1; +//bit 18 range 2 des key selection 0 : key0; 1: key1; +//bit 17 range 1 des key selection 0 : key0; 1: key1; +//bit 16 range0 des key selection 0 : key0; 1: key1; +//bit 6. range6 enable: 1: enable; 0 : disable. +//bit 5. range5 enable: 1: enable; 0 : disable. +//bit 4. range4 enable: 1: enable; 0 : disable. +//bit 3. range3 enable: 1: enable; 0 : disable. +//bit 2. range2 enable: 1: enable; 0 : disable. +//bit 1. range1 enable: 1: enable; 0 : disable. +//bit 0. range0 enable: 1: enable; 0 : disable. +#define P_PSRAM_DES_PADDING ((volatile uint32_t *)0xfe007414) +//bit 31 :0 Padding, with address together to generate describle 64 bits input. +#define P_PSRAM_RANGE0_STA ((volatile uint32_t *)0xfe007440) +//bit 22 :0. +//AXI security range 0 start address in unit of 64Byte. related to HADDR bit 28:6. +#define P_PSRAM_RANGE0_EDA ((volatile uint32_t *)0xfe007444) +//bit 22 :0. +//AXI security range 0 end address in unit of 64Byte. related to HADDR bit 28:6. +#define P_PSRAM_RANGE0_CTRL0 ((volatile uint32_t *)0xfe007448) +// AXI secruity range 0 control. +#define P_PSRAM_RANGE0_CTRL1 ((volatile uint32_t *)0xfe00744c) +// AXI secruity range 0 control. +#define P_PSRAM_RANGE1_STA ((volatile uint32_t *)0xfe007450) +//bit 22 :0. +//AXI security range 1 start address in unit of 64Byte. related to HADDR bit 28:6. +#define P_PSRAM_RANGE1_EDA ((volatile uint32_t *)0xfe007454) +//bit 22 :0. +//AXI security range 1 end address in unit of 64Byte. related to HADDR bit 28:6. +#define P_PSRAM_RANGE1_CTRL0 ((volatile uint32_t *)0xfe007458) +// AXI secruity range 1 control. +#define P_PSRAM_RANGE1_CTRL1 ((volatile uint32_t *)0xfe00745c) +// AXI secruity range 1 control. +#define P_PSRAM_RANGE2_STA ((volatile uint32_t *)0xfe007460) +//bit 31 : 6. +//AXI security range 2 start address in unit of 64Byte. related to HADDR bit 28:6. +#define P_PSRAM_RANGE2_EDA ((volatile uint32_t *)0xfe007464) +//bit 31 :6. +//AXI security range 2 end address in unit of 64Byte. related to HADDR bit 28:6. +#define P_PSRAM_RANGE2_CTRL0 ((volatile uint32_t *)0xfe007468) +#define P_PSRAM_RANGE2_CTRL1 ((volatile uint32_t *)0xfe00746c) +#define P_PSRAM_RANGE3_STA ((volatile uint32_t *)0xfe007470) +//bit 31 : 6. +//AXI security range 3 start address in unit of 64Byte. related to HADDR bit 28:6. +#define P_PSRAM_RANGE3_EDA ((volatile uint32_t *)0xfe007474) +//bit 31 :6. +//AXI security range 3 end address in unit of 64Byte. related to HADDR bit 28:6. +#define P_PSRAM_RANGE3_CTRL0 ((volatile uint32_t *)0xfe007478) +// AXI secruity range 3 control. +#define P_PSRAM_RANGE3_CTRL1 ((volatile uint32_t *)0xfe00747c) +// AXI secruity range 3 control. +#define P_PSRAM_RANGE4_STA ((volatile uint32_t *)0xfe007480) +//bit 31 :6. +//AXI security range 4 start address in unit of 64Byte. related to HADDR bit 28:6. +#define P_PSRAM_RANGE4_EDA ((volatile uint32_t *)0xfe007484) +//bit 31 :6. +//AXI security range 4 end address in unit of 64Byte. related to HADDR bit 28:6. +#define P_PSRAM_RANGE4_CTRL0 ((volatile uint32_t *)0xfe007488) +// AXI secruity range 4 control. +#define P_PSRAM_RANGE4_CTRL1 ((volatile uint32_t *)0xfe00748c) +#define P_PSRAM_RANGE5_STA ((volatile uint32_t *)0xfe007490) +//bit 22 :0. +//AXI security range 5 start address in unit of 64Byte. related to HADDR bit 28:6. +#define P_PSRAM_RANGE5_EDA ((volatile uint32_t *)0xfe007494) +//bit 22 :0. +//AXI security range 5 end address in unit of 64Byte. related to HADDR bit 28:6. +#define P_PSRAM_RANGE5_CTRL0 ((volatile uint32_t *)0xfe007498) +// AXI secruity range 5 control. +#define P_PSRAM_RANGE5_CTRL1 ((volatile uint32_t *)0xfe00749c) +// AXI secruity range 5 control. +#define P_PSRAM_RANGE6_STA ((volatile uint32_t *)0xfe0074a0) +//bit 22 :0. +//AXI security range 6 start address in unit of 64Byte. related to HADDR bit 28:6. +#define P_PSRAM_RANGE6_EDA ((volatile uint32_t *)0xfe0074a4) +//bit 22 :0. +//AXI security range 6 end address in unit of 64Byte. related to HADDR bit 28:6. +#define P_PSRAM_RANGE6_CTRL0 ((volatile uint32_t *)0xfe0074a8) +// AXI secruity range 6 control. +#define P_PSRAM_RANGE6_CTRL1 ((volatile uint32_t *)0xfe0074ac) +// AXI secruity range 6 control. +#define P_PSRAM_RANGE7_CTRL0 ((volatile uint32_t *)0xfe0074b0) +#define P_PSRAM_RANGE7_CTRL1 ((volatile uint32_t *)0xfe0074b4) +#define P_PSRAM_VIO_STATUS ((volatile uint32_t *)0xfe0074b8) +//bit 31: security violation. write 1 to clean security violation status. +//bit 30. 1 : AXI write violation. 0 : axi read violation. +//bit 18:16. AXI ARPROT/AWPROT> +//bit 11:0. AXI violation ID. +#define P_PSRAM_VIO_ADDR ((volatile uint32_t *)0xfe0074bc) +//read only +//31:0 AXI violation address. +#define P_PSRAM_USER_CTRL0 ((volatile uint32_t *)0xfe007600) +//bit 31. user request enable. write 1 to enable. read 0, means user command accepted by the SPI_CTRL. +//bit 30. usr request done. after user command done. this bit set to 1. +//bit 29. USR COMMAND enable. +//bit 28. command type0. 1 READ command. 0 write command. +//bit 27. command type1. 1 for register. 0 : for memory. +//bit 21~16. USR command clock cycles +//bit 15~0. USR COMMAND CODE. +#define P_PSRAM_USER_CTRL1 ((volatile uint32_t *)0xfe007604) +//bit 31. USR_ADDR_EN +//bit 30:29. USR_ADDR_DW +//bit 28~20. USR address clock cycle number. +//bit 19:16 USR data output/input switch postion +//bit 15. USR DUMMY ENABLE +//bit 13~8. USR DUMMY clock cycles. +//bit 5:0 USR data DQS read enable postion. +#define P_PSRAM_USER_CTRL2 ((volatile uint32_t *)0xfe007608) +//bit 31 usr des key selection. 1 : key 1; 0 : key 0. +//bit 30. usr check latency. for Winbond PSRAM data read/write, DQS input indentify the latency is doubled or not. +//bit 29. usr data des enable. +//bit 28 usr datain enable. +//bit 27. usr datain destination. 1 : write to CFG_STS register. 0 : write to DATA REGISTERs. +//bit 26~16 usr data in clock cycle number. +//bit 15. usr datout enable. +//bit 14. usr data out source 1 : from CFG_STS register. 0 from DATA register. +//bit 13~11. not used. +//bit 10~0. usr dataout clock cycles. +#define P_PSRAM_USER_CTRL3 ((volatile uint32_t *)0xfe00760c) +//bit 17:16. which cycle to ask phy to check read/write latency at PSRAM SEND COMMOND stage. +//since PSRAM send command stage only 3 clock cycle. So this number only can chose 0, 1, 2. +//bit 15:0. user dummy data when output in dummy cycle. +#define P_PSRAM_USER_ADDR ((volatile uint32_t *)0xfe007610) +//bit 31:0. 32bits user address. +#define P_PSRAM_AXI_REQ_CTRL0 ((volatile uint32_t *)0xfe007614) +//bit 31. AXI request enable. +//bit 30 AXI cmd_en. command cycle enable. +//bit 29:24. AXI request command cycle clock numbers. +//bit 22. AXI request address cycle enable. +//bit 21:16. AXI request address cycle clock number. +//bit 15:14. AXI address cycle data width. +//bit 13:12. at which clock cycle to send signal to phy to check latency flag for WINBOND PSRAM flexible latency. +//since PSRAM send command stage only 3 clock cycle. So this number only can chose 0, 1, 2. +//bit 6 // AXI Write dummy enable. +//bit 5:0 // axi write dummy clock cycle number. +#define P_PSRAM_AXI_REQ_CTRL1 ((volatile uint32_t *)0xfe007618) +//bit 31:16. AXI request psram READ command code. +//bit 15:0. AXI request psram write command code. +#define P_PSRAM_AXI_REQ_CTRL2 ((volatile uint32_t *)0xfe00761c) +//bit 31. AXI read request Dummy enable. +//bit 30. Check latency enable for WINBOND PSRAM flexible latency. +//bit 27:22. clock cycles in dummy stage to eanble PSRAM PHY reading logic. +//bit 21:16. axi_read dummy clock cycles number. +//bit 15:0. dummy data if output in dummy cycles. +#define P_PSRAM_AXI_REQ_CTRL3 ((volatile uint32_t *)0xfe007620) +//bit 31 des enable. +//bit 26:16. DATA input clock cycles. +//bit 10:0. DATA output clock cycles. +#define P_PSRAM_ACTIMING0 ((volatile uint32_t *)0xfe007624) +//bit 31:30. tSLCH +//bit 29:28 tCLSH +//bit 20:16 tSHWL +//bit 15:12 tSHSL2 +//bit 11:8 tSHSL1 +//bit 7:0 tWHSL +#define P_PSRAM_ACTIMING1 ((volatile uint32_t *)0xfe007628) +//bit 7:0 tRWR for winbond PSRAM, = tRWR -3. Winbond PSRAM include one CS cycle and 2 command cycle. +//for APMEMORY should be same value of tCPH +#define P_PSRAM_ACTIMING2 ((volatile uint32_t *)0xfe00762c) +#define P_PSRAM_WDG_CTRL ((volatile uint32_t *)0xfe007630) +//bit [31] 1: force to reset PSRAM PCTL and PHY logic. 0: normal. +//bit [30] 1: automatic reset PSRAM PCTL and PHY logic if watch dog triggered. +//bit 12:0. watch dog timer. for Winbond PSRAM should be 1us for tRC. for APMEMORY should be 1us for tCEM. +//SPI DATA BUFFER. There's a total 512KByte + 64byte(orgnized as 36x128bits) SRAM . +// since each APB access is 32bits. So we use word address as APB read/write address. +// But for SPI side we have to use 128bit boundary. That's the first Pragram/read SPI with data buffer must start at data buffer 128bit boundary. that means the PSRAM_USE_DBUF_ADDR last 2 bits must be 0. +#define P_PSRAM_DBUF_0 ((volatile uint32_t *)0xfe007640) +#define P_PSRAM_DBUF_1 ((volatile uint32_t *)0xfe007644) +#define P_PSRAM_DBUF_2 ((volatile uint32_t *)0xfe007648) +#define P_PSRAM_DBUF_3 ((volatile uint32_t *)0xfe00764c) +#define P_PSRAM_DBUF_4 ((volatile uint32_t *)0xfe007650) +#define P_PSRAM_DBUF_5 ((volatile uint32_t *)0xfe007654) +#define P_PSRAM_DBUF_6 ((volatile uint32_t *)0xfe007658) +#define P_PSRAM_DBUF_7 ((volatile uint32_t *)0xfe00765c) +#define P_PSRAM_DBUF_8 ((volatile uint32_t *)0xfe007660) +#define P_PSRAM_DBUF_9 ((volatile uint32_t *)0xfe007664) +#define P_PSRAM_DBUF_A ((volatile uint32_t *)0xfe007668) +#define P_PSRAM_DBUF_B ((volatile uint32_t *)0xfe00766c) +#define P_PSRAM_DBUF_C ((volatile uint32_t *)0xfe007670) +#define P_PSRAM_DBUF_D ((volatile uint32_t *)0xfe007674) +#define P_PSRAM_DBUF_E ((volatile uint32_t *)0xfe007678) +#define P_PSRAM_DBUF_F ((volatile uint32_t *)0xfe00767c) +#define P_PSRAM_CFG_STS ((volatile uint32_t *)0xfe007680) +//32bits register to save the USR read command read back values. +#define P_PSRAM_STATUS ((volatile uint32_t *)0xfe007684) +//bit 31. usr_req_done flag. 1 : user request done . write 1 to clean. +//bit 30~11. +//bit 10:8 +//bit 7:3. +//bit 2. axi_data buffer idle bit. 1 : idle. 0 : working. +//bit 1. axi interface idle bit. 1 : idle. 0 : working. +//bit 0. psram ctrl idle bit. 1 : idle. 0 : working. +#define P_PSRAM_CTRL ((volatile uint32_t *)0xfe007688) +//bit 31. PSRAM in DTR mode. +//bit 30. psram input data latch clock select. 1: from clock input pin. 0: from DQS +//if use clock input pin as data input latch clock, bit 13:12 should select 01. +//bit 29:27. PSRAM mode. +//'b000 : STR SPI mode. +//'b001 : STR QPI mode. +//'b010 : DTR QPI mode. +//'b011 : DTR OPI FLASH. +//'b100 : APmemory PSRAM mode. +//'b101 : Winbond PSRAM mode. +//bit 26. enable to generation interruption after usr request done. 1: enable. 0: disable. +//bit 25. to enable APMEMORY 2 command cycle mode. 1 : enable : 0: 3 command cycles. +//bit 24. to enable the psram clock output always enable. 1 : enable. 0: disable. +//bit 23. to enable the psram clock output extend mode to cover APMEMORY tCPI. +//bit 22. to disable the CKN output. 1: disable PSRAM CK_N pin output. 0: CK_N working normal. +//bit 21. PSRAM DATA IN/OUT high 8bit and low 8 bit endian. 1 : rising edge is low byte. falling edge data is high byte. 0 : rising edge is high byte. falling edge data is low byte. +//bit 20. PSRAM ADDRESS unit. 1: Byte. 0 : word. +// APMEMORY used byte address. Winbond use word address. +//bit 19. DQSEN generation. if use dqs to latch input data, this bit should be set to 1 to ask DMC generate ENABLE singal in dummy stage. 0: not generate DQS_EN. +//bit 18. PSRAM RESET I/O oe_n value. if need RESET pin. +//bit 17. PSRAM RESET I/O output vale. if need reset pin. +//bit 16. force CS output low. for APMEMORY exit DPPD mode. 1: to force cs output low : 0 output normal working mode. +//bit 13:12. psram data in clock enable selection. 00: use DQSEN. 01: use clkin cnt. +//bit 11. DM Disable. 1: disable DM output. 0: with dmoutput. +//bit 9. psram pctl auto clock gating enable. 1: enable. 0 : disable. +//bit 8. psram pctl clock disable. 1: disable. 0 : enable. +//bit 2 PSRAM SPI mode, DQ2 works as WP(write protection mode). +//bit 1. DQ2 WP mode value. +//bit 0. PSRAM SPI mode, DQ3 works as HOLD function. +#define P_PSRAM_PIN_CTRL ((volatile uint32_t *)0xfe00768c) +//bit 30:28 DATA 6 DQ pin selection. +//bit 27:24 DATA 6 DQ pin selection. +//bit 22:20 DATA 5 DQ pin selection. +//bit 18:16 DATA 4 DQ pin selection. +//bit 14:12 DATA 3 DQ pin selection. +//bit 10:8 DATA 2 DQ pin selection. +//bit 6:4 DATA 1 DQ pin selection. +//bit 2:0 DATA 0 DQ pin selection. +//0 : from DQ[0] +//1 : from DQ[1] +//2 : from DQ[2] +//3 : from DQ[3] +//4 : from DQ[4] +//5 : from DQ[5] +//6 : from DQ[6] +//7 : from DQ[7] +//psram_dly_16 is used for all DQ[0~] in/out/oen delay adjustment. +//psram_dly_16 consists of 15 delay cells, one delay cell is 50ps delay( typical corner). +//psram_dly_16 is control by delay_sel[3:0]. 0 = no delay. 1~15 controls how many delay cells used. +//psram_dly_16 can be controlled by each control register either with real delay mode or VT updated with 4xclock period. +//psram_lcdl is used for DQS/DQSN input and CK/CKN output delay 90degree delay generation and/or delay fine tune. +//psram_lcdl consits of 96 delay cells, same delay cell used in psram_dly_16. +//psram_lcdl should be calibrated with the psram_4xclock. and tracked with psram_4xclock with VT updated. +#define P_PSRAM_DQ0_DIN_DLY ((volatile uint32_t *)0xfe007700) +//bit 6:0. DQ0 DIN delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_DQ1_DIN_DLY ((volatile uint32_t *)0xfe007704) +//bit 6:0. DQ1 input delay control. in DLY16 read mode, only [3:0] is valid. +#define P_PSRAM_DQ2_DIN_DLY ((volatile uint32_t *)0xfe007708) +//bit 6:0. DQ2 input delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_DQ3_DIN_DLY ((volatile uint32_t *)0xfe00770c) +//bit 6:0. DQ3 input delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_DQ4_DIN_DLY ((volatile uint32_t *)0xfe007710) +//bit 6:0. DQ4 input delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_DQ5_DIN_DLY ((volatile uint32_t *)0xfe007714) +//bit 6:0. DQ5 input delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_DQ6_DIN_DLY ((volatile uint32_t *)0xfe007718) +//bit 6:0. DQ6 input delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_DQ7_DIN_DLY ((volatile uint32_t *)0xfe00771c) +//bit 6:0. DQ7 input delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_DQ0_DOUT_DLY ((volatile uint32_t *)0xfe007720) +//bit 6:0. DQ0 DOUT delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_DQ1_DOUT_DLY ((volatile uint32_t *)0xfe007724) +//bit 6:0. DQ1 output delay control. in DLY16 read mode, only [3:0] is valid. +#define P_PSRAM_DQ2_DOUT_DLY ((volatile uint32_t *)0xfe007728) +//bit 6:0. DQ2 output delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_DQ3_DOUT_DLY ((volatile uint32_t *)0xfe00772c) +//bit 6:0. DQ3 output delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_DQ4_DOUT_DLY ((volatile uint32_t *)0xfe007730) +//bit 6:0. DQ4 output delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_DQ5_DOUT_DLY ((volatile uint32_t *)0xfe007734) +//bit 6:0. DQ5 output delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_DQ6_DOUT_DLY ((volatile uint32_t *)0xfe007738) +//bit 6:0. DQ6 output delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_DQ7_DOUT_DLY ((volatile uint32_t *)0xfe00773c) +//bit 6:0. DQ7 output delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_DQ0_OEN_DLY ((volatile uint32_t *)0xfe007740) +//bit 6:0. DQ0 OEN delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_DQ1_OEN_DLY ((volatile uint32_t *)0xfe007744) +//bit 6:0. DQ1 output enable delay control. in DLY16 read mode, only [3:0] is valid. +#define P_PSRAM_DQ2_OEN_DLY ((volatile uint32_t *)0xfe007748) +//bit 6:0. DQ2 output enable delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_DQ3_OEN_DLY ((volatile uint32_t *)0xfe00774c) +//bit 6:0. DQ3 output enable delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_DQ4_OEN_DLY ((volatile uint32_t *)0xfe007750) +//bit 6:0. DQ4 output enable delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_DQ5_OEN_DLY ((volatile uint32_t *)0xfe007754) +//bit 6:0. DQ5 output enable delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_DQ6_OEN_DLY ((volatile uint32_t *)0xfe007758) +//bit 6:0. DQ6 output enable delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_DQ7_OEN_DLY ((volatile uint32_t *)0xfe00775c) +//bit 6:0. DQ7 output enable delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_DM_DOUT_DLY ((volatile uint32_t *)0xfe007760) +//bit 6:0. DM output delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_DM_OEN_DLY ((volatile uint32_t *)0xfe007764) +//bit 6:0. DM output enable delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_CS_DOUT_DLY ((volatile uint32_t *)0xfe007768) +//bit 6:0. CS output delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_DQS_DIN_DLY ((volatile uint32_t *)0xfe00776c) +//bit 6:0. DQS input delay control. unit = 1/64 UI with PSRAM_LCDL_CTRL bit 28 = 0; +// unit = 1 delay cell, with PSRAM_LCDL_CTRL bit 28 = 1; +#define P_PSRAM_DQSN_DIN_DLY ((volatile uint32_t *)0xfe007770) +//bit 6:0. DQSN input delay control. unit = 1/64 UI with PSRAM_LCDL_CTRL bit 28 = 0; +// unit = 1 delay cell, with PSRAM_LCDL_CTRL bit 28 = 1; +#define P_PSRAM_CKN_DOUT_DLY ((volatile uint32_t *)0xfe007774) +//bit 6:0. CKN output delay control. unit = 1/64 UI with PSRAM_LCDL_CTRL bit 28 = 0; +// unit = 1 delay cell, with PSRAM_LCDL_CTRL bit 28 = 1; +#define P_PSRAM_CK_DOUT_DLY ((volatile uint32_t *)0xfe007778) +//bit 6:0. CK output delay control. unit = 1/64 UI with PSRAM_LCDL_CTRL bit 28 = 0; +// unit = 1 delay cell, with PSRAM_LCDL_CTRL bit 28 = 1; +#define P_PSRAM_RDEN_DLY ((volatile uint32_t *)0xfe00777c) +//bit 10:7. READ enable phase delay. unit = 1UI. for AP QPI PSRAM. PSRAM only send one cycle DQS preamble. +// We have to used this UI delay to compensate the whole clock output delay and the DQS input delay. +// if run high frequency, this delay need to be trained. the valid value from 0 ~ 12. Since one UI is 1/4 of PSRAM clock, +// the total delay of the clock output delay + input delay should be less than 3 PSRAM clock. +//bit 6:0. READ enable fine tune delay control. unit = 1/64 UI with PSRAM_LCDL_CTRL bit 28 = 0; +// unit = 1 delay cell, with PSRAM_LCDL_CTRL bit 28 = 1; +#define P_PSRAM_LCDL_CTRL ((volatile uint32_t *)0xfe0077c0) +//bit 31. write 1 to update all delay cell delays control. +//bit 30. write 1 to calibration LCDL. +//bit 29. LCDL track enable. 1: enable LCDL auto track VT changes. +//bit 28. LCDL delay control mode. +//1 : real delay mode. For DQS/DQSN/CKN/CK/RDEN delay control register, one number means one delay cells. +//0 : UI MODE. For DQS/DQSN/CKN/CK/RDEN delay control register, one number means 1/64 psram_4xclk period. +//bit 27. DLY16 ( psram_dly_16 cell) delay control mode. +//1 : real delay mode. For all data delay control register, one number means one delay cells. +//0 : UI MODE. For all data delay control register, one number means 1/64 psram_4xclk period. +//bit 27:24. not used. +//bit 23:0. timer do trigger LCDL track the VT once. each track will compensate the UI with 1/16 delay cell delay. +//LCDL calibration ctroller. +#define P_PSRAM_LCDL_CAL_CTRL1 ((volatile uint32_t *)0xfe0077c4) +//27:24. which LCDL delay line used to run calibration. +//19:16. LCDL calibration loop end position. +//15:12. LCDL calibration loop initial position. +//10:0. LCDL calibration initial phase counter. +#define P_PSRAM_LCDL_CAL_CTRL2 ((volatile uint32_t *)0xfe0077c8) +//26:16 LCDL phase lock limit. if the lcdl phase counter difference between 2 calibration loops is less than this number, The LCDL would be locked and stop the calibration. +//10:0. deta_init. the first loop phase changing number. +#define P_PSRAM_LCDL_CAL_CTRL3 ((volatile uint32_t *)0xfe0077cc) +//29:25 to configure LCDL calibration step 5 position. +//24:20 to configure LCDL calibration step 4 position. +//19:15 to configure LCDL calibration step 3 position. +//14:10 to configure LCDL calibration step 2 position. +//9:5 to configure LCDL calibration step 1 position. +//4:0 to configure LCDL calibration step 0 position. +#define P_PSRAM_LCDL_CAL_CTRL4 ((volatile uint32_t *)0xfe0077d0) +//19:15 to configure LCDL calibration step 9 position. +//14:10 to configure LCDL calibration step 8 position. +//9:5 to configure LCDL calibration step 7 position. +//4:0 to configure LCDL calibration step 6 position. +#define P_PSRAM_CLK_UI ((volatile uint32_t *)0xfe0077d4) +//bit 6:0. 4xCLOCK period delay measured from LCDL calibration. +#define P_PSRAM_LCDL_PH ((volatile uint32_t *)0xfe0077d8) +//10:0 LCDL phase counter after calibration. +#define P_PSRAM_LCDL_STATUS ((volatile uint32_t *)0xfe0077dc) +//bit 31. LCDL lock status. 1: LCDL locked to 4x clock. +//`endif +// +// Closing file: ../psram/rtl/psram_reg.vh +// +// +// Reading file: ../mmc_lp4/dmc/rtl/dmc_sec.vh +// +//`ifdef DMC_SEC_REG_DEFINE +//`else +//`define DMC_SEC_REG_DEFINE +// ----------------------------------------------- +// APB_BASE: APB1_BASE_ADDR = 0xfd021000 +// ----------------------------------------------- +//`define DMC_SEC_REG_BASE 32'hfd021000 +// ID assignment inside DMC.. +// id[12 :0] total 13 bit ID. +// id[12] == 1: for DMC internal TEST module. +// id[12] == 0: for AXI port input. +// id[11:0] == AXI port ID. +// id[2:0] == 0 : A55 CPU. +// id[2:0] == 1 : DSPA +// id[2:0] == 2 : DSPB +// id[2:0] == 3 : Not used. +// id[2:0] == 4 : for Device. +//Device sublevel ID. +//id[9:7] == 5 : for audio. id[3] == 0: audio +//id[9:7] == 6 : for DMA. id[6:4] for DMA thread id. id[3] for DMC security level. +//id[9:7] == others: for device other masters. +// id[2:0] == 5 : for USB device. +// id[2:0] == 6 : for I2C debug input. +// id[2:0] == 7 : for USB host. +#define P_DMC_SEC_RANGE0_STA ((volatile uint32_t *)0xfd021000) +//bit 31:12. range0 start address. in 4KB boundary. +#define P_DMC_SEC_RANGE0_EDA ((volatile uint32_t *)0xfd021004) +//bit 31:12. range0 end address. in 4KB boundary. +#define P_DMC_SEC_RANGE0_RID_CTRL ((volatile uint32_t *)0xfd021008) +//range 0 read access enable based on DMC ID assignments. +//bit 28. for AXI port 3. Not used in A1. should be 0. +//bit 27. for dmc_test. 1 = enable. 0 = disable. +//bit 26. for usbhost. 1 = enable. 0 = disable. +//bit 25. for i2c. 1 = enable. 0 = disable. +//bit 24. for usbdevide. 1 = enable. 0 = disable. +//bit 23. for AXI device sublevel id 7. 1 = enable. 0 = disable. +//bit 22:18.for AXI device sub level id 5 ~ 0. +//bit 17:10.for AXI device DMA thread 7 ~ thread 0.( in A1, DMA only has thread 3 to thread 0). +//bit 9:6. for AXI device audio read subid 3~0. (in A1, audio read only has subid 1 and subid 0). +//bit 5:4. for AXI DSPB. bit 5 for security access. bit 4 for non secure access. +//bit 3:2. for AXI DSPA. bit 3 for security access. bit 2 for non secure access. +//bit 1:0. for AXI A55 CPU. bit 1 for security access. bit 0 for non secure access. +#define P_DMC_SEC_RANGE0_WID_CTRL ((volatile uint32_t *)0xfd02100c) +//range 0 write access enable based on DMC ID assignments. +//bit 28. for AXI port 3. Not used in A1. should be 0. +//bit 27. for dmc_test. 1 = enable. 0 = disable. +//bit 26. for usbhost. 1 = enable. 0 = disable. +//bit 25. for i2c. 1 = enable. 0 = disable. +//bit 24. for usbdevide. 1 = enable. 0 = disable. +//bit 23. for AXI device sublevel id 7. 1 = enable. 0 = disable. +//bit 22:18.for AXI device sub level id 5 ~ 0. +//bit 17:10.for AXI device DMA thread 7 ~ thread 0.( in A1, DMA only 4 threads from thread 3 to thread 0). +//bit 9:6. for AXI device audio write subid 7~4. (in A1, audio write only 2 masters usey subid 4 and subid 5). +//bit 5:4. for AXI DSPB. bit 5 for security access. bit 4 for non secure access. +//bit 3:2. for AXI DSPA. bit 3 for security access. bit 2 for non secure access. +//bit 1:0. for AXI A55 CPU. bit 1 for security access. bit 0 for non secure access. +#define P_DMC_SEC_RANGE1_STA ((volatile uint32_t *)0xfd021010) +//bit 31:12. range1 start address. in 4KB boundary. +#define P_DMC_SEC_RANGE1_EDA ((volatile uint32_t *)0xfd021014) +//bit 31:12. range0 end address. in 4KB boundary. +#define P_DMC_SEC_RANGE1_RID_CTRL ((volatile uint32_t *)0xfd021018) +//range 1 read access enable based on DMC ID assignments. +//bit 28. for AXI port 3. Not used in A1. should be 0. +//bit 27. for dmc_test. 1 = enable. 0 = disable. +//bit 26. for usbhost. 1 = enable. 0 = disable. +//bit 25. for i2c. 1 = enable. 0 = disable. +//bit 24. for usbdevide. 1 = enable. 0 = disable. +//bit 23. for AXI device sublevel id 7. 1 = enable. 0 = disable. +//bit 22:18.for AXI device sub level id 5 ~ 0. +//bit 17:10.for AXI device DMA thread 7 ~ thread 0.( in A1, DMA only has thread 3 to thread 0). +//bit 9:6. for AXI device audio read subid 3~0. (in A1, audio read only has subid 1 and subid 0). +//bit 5:4. for AXI DSPB. bit 5 for security access. bit 4 for non secure access. +//bit 3:2. for AXI DSPA. bit 3 for security access. bit 2 for non secure access. +//bit 1:0. for AXI A55 CPU. bit 1 for security access. bit 0 for non secure access. +#define P_DMC_SEC_RANGE1_WID_CTRL ((volatile uint32_t *)0xfd02101c) +//range 1 write access enable based on DMC ID assignments. +//bit 28. for AXI port 3. Not used in A1. should be 0. +//bit 27. for dmc_test. 1 = enable. 0 = disable. +//bit 26. for usbhost. 1 = enable. 0 = disable. +//bit 25. for i2c. 1 = enable. 0 = disable. +//bit 24. for usbdevide. 1 = enable. 0 = disable. +//bit 23. for AXI device sublevel id 7. 1 = enable. 0 = disable. +//bit 22:18.for AXI device sub level id 5 ~ 0. +//bit 17:10.for AXI device DMA thread 7 ~ thread 0.( in A1, DMA only 4 threads from thread 3 to thread 0). +//bit 9:6. for AXI device audio write subid 7~4. (in A1, audio write only 2 masters usey subid 4 and subid 5). +//bit 5:4. for AXI DSPB. bit 5 for security access. bit 4 for non secure access. +//bit 3:2. for AXI DSPA. bit 3 for security access. bit 2 for non secure access. +//bit 1:0. for AXI A55 CPU. bit 1 for security access. bit 0 for non secure access. +#define P_DMC_SEC_RANGE2_STA ((volatile uint32_t *)0xfd021020) +//bit 31:12. range2 start address. in 4KB boundary. +#define P_DMC_SEC_RANGE2_EDA ((volatile uint32_t *)0xfd021024) +//bit 31:12. range2 end address. in 4KB boundary. +#define P_DMC_SEC_RANGE2_RID_CTRL ((volatile uint32_t *)0xfd021028) +//range 2 read access enable based on DMC ID assignments. +//bit 28. for AXI port 3. Not used in A1. should be 0. +//bit 27. for dmc_test. 1 = enable. 0 = disable. +//bit 26. for usbhost. 1 = enable. 0 = disable. +//bit 25. for i2c. 1 = enable. 0 = disable. +//bit 24. for usbdevide. 1 = enable. 0 = disable. +//bit 23. for AXI device sublevel id 7. 1 = enable. 0 = disable. +//bit 22:18.for AXI device sub level id 5 ~ 0. +//bit 17:10.for AXI device DMA thread 7 ~ thread 0.( in A1, DMA only has thread 3 to thread 0). +//bit 9:6. for AXI device audio read subid 3~0. (in A1, audio read only has subid 1 and subid 0). +//bit 5:4. for AXI DSPB. bit 5 for security access. bit 4 for non secure access. +//bit 3:2. for AXI DSPA. bit 3 for security access. bit 2 for non secure access. +//bit 1:0. for AXI A55 CPU. bit 1 for security access. bit 0 for non secure access. +#define P_DMC_SEC_RANGE2_WID_CTRL ((volatile uint32_t *)0xfd02102c) +//range 2 write access enable based on DMC ID assignments. +//bit 28. for AXI port 3. Not used in A1. should be 0. +//bit 27. for dmc_test. 1 = enable. 0 = disable. +//bit 26. for usbhost. 1 = enable. 0 = disable. +//bit 25. for i2c. 1 = enable. 0 = disable. +//bit 24. for usbdevide. 1 = enable. 0 = disable. +//bit 23. for AXI device sublevel id 7. 1 = enable. 0 = disable. +//bit 22:18.for AXI device sub level id 5 ~ 0. +//bit 17:10.for AXI device DMA thread 7 ~ thread 0.( in A1, DMA only 4 threads from thread 3 to thread 0). +//bit 9:6. for AXI device audio write subid 7~4. (in A1, audio write only 2 masters usey subid 4 and subid 5). +//bit 5:4. for AXI DSPB. bit 5 for security access. bit 4 for non secure access. +//bit 3:2. for AXI DSPA. bit 3 for security access. bit 2 for non secure access. +//bit 1:0. for AXI A55 CPU. bit 1 for security access. bit 0 for non secure access. +#define P_DMC_SEC_RANGE3_STA ((volatile uint32_t *)0xfd021030) +//bit 31:12. range3 start address. in 4KB boundary. +#define P_DMC_SEC_RANGE3_EDA ((volatile uint32_t *)0xfd021034) +//bit 31:12. range3 end address. in 4KB boundary. +#define P_DMC_SEC_RANGE3_RID_CTRL ((volatile uint32_t *)0xfd021038) +//range 3 read access enable based on DMC ID assignments. +//check DMC_SEC_RANGE0_RID_CTRL for each bit define. +#define P_DMC_SEC_RANGE3_WID_CTRL ((volatile uint32_t *)0xfd02103c) +//range 3 write access enable based on DMC ID assignments. +//check DMC_SEC_RANGE0_WID_CTRL for each bit define. +#define P_DMC_SEC_RANGE4_STA ((volatile uint32_t *)0xfd021040) +//bit 31:12. range4 start address. in 4KB boundary. +#define P_DMC_SEC_RANGE4_EDA ((volatile uint32_t *)0xfd021044) +//bit 31:12. range4 end address. in 4KB boundary. +#define P_DMC_SEC_RANGE4_RID_CTRL ((volatile uint32_t *)0xfd021048) +//range 4 read access enable based on DMC ID assignments. +//check DMC_SEC_RANGE0_RID_CTRL for each bit define. +#define P_DMC_SEC_RANGE4_WID_CTRL ((volatile uint32_t *)0xfd02104c) +//range 4 write access enable based on DMC ID assignments. +//check DMC_SEC_RANGE0_WID_CTRL for each bit define. +#define P_DMC_SEC_RANGE5_STA ((volatile uint32_t *)0xfd021050) +//bit 31:12. range5 start address. in 4KB boundary. +#define P_DMC_SEC_RANGE5_EDA ((volatile uint32_t *)0xfd021054) +//bit 31:12. range5 end address. in 4KB boundary. +#define P_DMC_SEC_RANGE5_RID_CTRL ((volatile uint32_t *)0xfd021058) +//range 5 read access enable based on DMC ID assignments. +//check DMC_SEC_RANGE0_RID_CTRL for each bit define. +#define P_DMC_SEC_RANGE5_WID_CTRL ((volatile uint32_t *)0xfd02105c) +//range 5 write access enable based on DMC ID assignments. +//check DMC_SEC_RANGE0_WID_CTRL for each bit define. +#define P_DMC_SEC_RANGE6_STA ((volatile uint32_t *)0xfd021060) +//bit 31:12. range5 start address. in 4KB boundary. +#define P_DMC_SEC_RANGE6_EDA ((volatile uint32_t *)0xfd021064) +//bit 31:12. range6 end address. in 4KB boundary. +#define P_DMC_SEC_RANGE6_RID_CTRL ((volatile uint32_t *)0xfd021068) +//range 6 read access enable based on DMC ID assignments. +//check DMC_SEC_RANGE0_RID_CTRL for each bit define. +#define P_DMC_SEC_RANGE6_WID_CTRL ((volatile uint32_t *)0xfd02106c) +//range 6 write access enable based on DMC ID assignments. +//check DMC_SEC_RANGE0_WID_CTRL for each bit define. +//range 7 is default range if the access not hit any of the previous 7 range, if would hit range 7. +#define P_DMC_SEC_RANGE7_RID_CTRL ((volatile uint32_t *)0xfd021070) +//range 7 read access enable based on DMC ID assignments. +//check DMC_SEC_RANGE0_RID_CTRL for each bit define. +#define P_DMC_SEC_RANGE7_WID_CTRL ((volatile uint32_t *)0xfd021074) +//range 7 write access enable based on DMC ID assignments. +//check DMC_SEC_RANGE0_WID_CTRL for each bit define. +#define P_DMC_SEC_RANGE_CTRL ((volatile uint32_t *)0xfd021078) +//bit 23:16 8 range security level. to chosse with DES KEY to use data describle. +//bit 7:0 8 range enable. each bit for one range to indentify the range is enabled or not. +//registers to check the security protection and watch point error information. +#define P_DMC_DES_CTRL ((volatile uint32_t *)0xfd021080) +//bit 1 data describle enable. +//bit 0 wirte 1 to block DES CTRL and DES PADDING read/write. +#define P_DMC_DES_PADDING ((volatile uint32_t *)0xfd021084) +#define P_DMC_SEC_STATUS ((volatile uint32_t *)0xfd0212e0) +//bit 31~2. not used. +//bit 1 write security violation. +//bit 0. read security violation. +#define P_DMC_VIO_ADDR0 ((volatile uint32_t *)0xfd0212e4) +//ddr0 write secure violation address. +#define P_DMC_VIO_ADDR1 ((volatile uint32_t *)0xfd0212e8) +//bit 31:18 . not used. always 0. +//17 ddr0 secure check violation. +//16 ddr0 write address overflow. write out of DDR size. +//15:13. ddr0 write violation AWPROT bits. +//12:0 ddr0_write violation ID. Please check ID assignment for ID bit defines. +#define P_DMC_VIO_ADDR2 ((volatile uint32_t *)0xfd0212ec) +//ddr0 write secure violation address. +#define P_DMC_VIO_ADDR3 ((volatile uint32_t *)0xfd0212f0) +//bit 31:18 . not used. always 0. +//17 ddr0 secure check violation. +//16 ddr0 read address overflow. write out of DDR size. +//15:13. ddr0 read violation AWPROT bits. +//12:0 ddr0_read violation ID. please ID assignment for ID bit defines. +//DDR0_ADDRMAP is used for RANK0 bank, row, col address mapping from AXI 32bits linear address. +#define P_DDR0_ADDRMAP_0 ((volatile uint32_t *)0xfd021340) +//29:25 ca8. +//24:20 ca7. +//19:15 ca6. +//14:10 ca5. +//9:5 ca4. +//4:0 ca3. +#define P_DDR0_ADDRMAP_1 ((volatile uint32_t *)0xfd021344) +//29:25 ra2. +//24:20 ra1. +//19:15 ra0. +//14:10 ca11. +//9:5 ca10. +//4:0 ca9. +#define P_DDR0_ADDRMAP_2 ((volatile uint32_t *)0xfd021348) +//29:25 ra8. +//24:20 ra7. +//19:15 ra6. +//14:10 ra5. +//9:5 ra4. +//4:0 ra3. +#define P_DDR0_ADDRMAP_3 ((volatile uint32_t *)0xfd02134c) +//29:25 ra14. +//24:20 ra13. +//19:15 ra12. +//14:10 ra11. +//9:5 ra10. +//4:0 ra9. +#define P_DDR0_ADDRMAP_4 ((volatile uint32_t *)0xfd021350) +//29:25 ra16 for DDR4 SDRAM +//24:20 bg1 for DDR4 SDRAM. +//19:15 ba2. or bg0 for DDR4. +//14:10 ba1. +//9:5 ba0. +//4:0 ra15. +#define P_DMC_DDR_CTRL ((volatile uint32_t *)0xfd021368) +// DDR PHY and DMC only supports 16bits and rank0 only. +//bit 24:22 3'b000 : ddr3 mode. +//3'b001 : ddr4 mode. +//3'b010 : lpddr3 mode. +//3'b011 : lpddr4 mode. +//bit 20 DDR4 BG1 enable bit. +//bit 3:0 : DDR rank 0 size bit [2:0]. +//4'b0000 : DDR rank 0 is 128Mbyte. +//4'b0001 : DDR rank 0 is 256Mbyte. +//4'b0010 : DDR rank 0 is 512Mbyte. +//4'b0011 : DDR rank 0 is 1Gbyte. +//4'b0100 : DDR rank 0 is 2Gbyte. +//4'b0101 : DDR rank 0 is 4Gbyte. +//4'b1000 : DDR rank 0 is 4Gbyte. +//4'b1001 : DDR rank 0 is 4Gbyte. +//others : reserved. +#define P_DMC_APB_SEC_CTRL ((volatile uint32_t *)0xfd02136c) +//bit 19:16. DMC normal APB register secure control. +//bit 19: 1: all can write those register. 0: the APB_PROT[0] must match the bit 16 to access those regsiter. +//Bit15:12. DMC sticky APB regsiter secure control. +//bit 15. 1: All APB bus can write those registers. 0: The APB_PROT[0] must match the bit 12 to access those register. +//bit 11:8. not used. +//Bit 7:4. DMC DDR SDRAM protocal contorl register contorl +//bit 11. 1: All APB bus can write those registers. 0: The APB_PROT[0] must match the bit 4 to access those register. +//bit 3:0. PHY APB regsiter secure control. +//bit 3. 1: All APB bus can write those registers. 0: The APB_PROT[0] must match the bit 0 to access those register. +#define P_DMC_DDR_PHY_CTRL ((volatile uint32_t *)0xfd0212fc) +//bit 4 PwrOkIn +//bit 3. PHY APB soft reset_n +//bit 2. PHY soft reset_n +//bit 1. PHY DfiClk enable. +//bit 0. PHY DfiCtlClk enable. +// ----------------------------------------------- +// APB_BASE: APB1_BASE_ADDR = 0xfd021400 +// ----------------------------------------------- +//`define DMC_TEST_REG_BASE 32'hfd021400 +#define P_DMC_TEST_WRCMD_ADDR ((volatile uint32_t *)0xfd021770) +// the current write cmd address. +#define P_DMC_TEST_RDRSP_ADDR ((volatile uint32_t *)0xfd021774) +// the failed read response address(for error data ) +#define P_DMC_TEST_RDCMD_ADDR ((volatile uint32_t *)0xfd021778) +// the current read command address. +#define P_DMC_TEST_WDG ((volatile uint32_t *)0xfd02177c) +//31:16. write response watch dog. +//15:0. read response watch dog. +#define P_DMC_TEST_STA ((volatile uint32_t *)0xfd021780) +//test start address. for non-sha mode, the last 5 bits would be ignored. the test address at 32bytes boundary. +// for sha mode, address must be in 64 bytes boundary. that mean the last 6 bits must be 0. +#define P_DMC_TEST_EDA ((volatile uint32_t *)0xfd021784) +//test end address. for non-sha mode, the last 5 bits would be ignored. the test address at 32bytes boundary. +// for sha mode, address must be in 64 bytes boundary. that mean the last 6bits must be 1. +#define P_DMC_TEST_CTRL ((volatile uint32_t *)0xfd021788) +//bit 31. enable test. +//bit 30. when enable test, enable the write to DDR function. +//bit 29. when enable test, enable the read from DDR function. +//bit 28. Not used. +//bit 27. enabe to compare data. when do the read enable to enable the error comparaion. suppose the read data should be same as the data in the write buffer. +//bit 26. Not used. +//bit 25. address generation type. 0: continuous increase the address in the range of test start address and test end address. +// 1: test module would pick the random address from test start address and test end address. +//bit 24. done type. 0 : use the DMC_TEST_NUM register as the counter of test numbers. +// for write if the write command number == the DMC_TEST_NUM, the write is done. +// for read if the read command number == the DMC TEST_num, the read id done. for one read command can be repeated repeat number times. +// 1 : finshed at end address. +//bit 23. wdata type. 1 : the first write is {WD3, WD2,WD1,WD0}, then the latter is the previous data plus a pattern.( { + WD7, + WD6, + WD5, + WD4}). +// 0 : the WDATA is the data in write register. +//bit 23. Not used. +//bit 22:20. read repeat times. for non-sha function, we can define multi times of the read. the test module would repeat the same adddress repeat times. +//bit 19. limit write. 0: no outstanding write request limitation. +// 1: limit the outstanding write commands to the number of bits [15:8] +//bit 18. limit read. 0. no outstanding read request limitation. +// 1. limit the read outstanding request to the number of bits[7:0]. +//bit 17:16. Not used. +//bit 15:8. write outstanding commands limit. +//bit 7:0. read outstanding commands limit. +#define P_DMC_TEST_NUM ((volatile uint32_t *)0xfd02178c) +// how many test command for the test if the DMC_TEST_CTRL bit 24 is 0. +#define P_DMC_TEST_WD0 ((volatile uint32_t *)0xfd021790) +// write data 0 for write command. also for read back data comparision. +#define P_DMC_TEST_WD1 ((volatile uint32_t *)0xfd021794) +// write data 1 for write command. also for read back data comparision. +#define P_DMC_TEST_WD2 ((volatile uint32_t *)0xfd021798) +// write data 2 for write command. also for read back data comparision. +#define P_DMC_TEST_WD3 ((volatile uint32_t *)0xfd02179c) +// write data 3 for write command. also for read back data comparision. +#define P_DMC_TEST_WD4 ((volatile uint32_t *)0xfd0217a0) +// write data 4 for write command. also for read back data comparision. +#define P_DMC_TEST_WD5 ((volatile uint32_t *)0xfd0217a4) +// write data 5 for write command. also for read back data comparision. +#define P_DMC_TEST_WD6 ((volatile uint32_t *)0xfd0217a8) +// write data 6 for write command. also for read back data comparision. +#define P_DMC_TEST_WD7 ((volatile uint32_t *)0xfd0217ac) +// write data 7 for write command. also for read back data comparision. +#define P_DMC_TEST_RD0 ((volatile uint32_t *)0xfd0217b0) +// the read back data 0. if error happens, it would capture the first error data. +#define P_DMC_TEST_RD1 ((volatile uint32_t *)0xfd0217b4) +// the read back data 1. if error happens, it would capture the first error data. +#define P_DMC_TEST_RD2 ((volatile uint32_t *)0xfd0217b8) +// the read back data 2. if error happens, it would capture the first error data. +#define P_DMC_TEST_RD3 ((volatile uint32_t *)0xfd0217bc) +// the read back data 3. if error happens, it would capture the first error data. +#define P_DMC_TEST_RD4 ((volatile uint32_t *)0xfd0217c0) +// the read back data 4. if error happens, it would capture the first error data. +#define P_DMC_TEST_RD5 ((volatile uint32_t *)0xfd0217c4) +// the read back data 5. if error happens, it would capture the first error data. +#define P_DMC_TEST_RD6 ((volatile uint32_t *)0xfd0217c8) +// the read back data 6. if error happens, it would capture the first error data. +#define P_DMC_TEST_RD7 ((volatile uint32_t *)0xfd0217cc) +// the read back data 7. if error happens, it would capture the first error data. +#define P_DMC_TEST_ERR_ADDR ((volatile uint32_t *)0xfd0217d0) +// it capature the first error address. +#define P_DMC_TEST_ERR_CNT ((volatile uint32_t *)0xfd0217d4) +// how many data error happens in the whole test period. +#define P_DMC_TEST_STS ((volatile uint32_t *)0xfd0217d8) +//bit 31, test done bit. write 1 to clean. +//bit 30, indicate address err +//bit 29~7. not used. +//bit 6. read data resp error(caused by security or rd latency). +//bit 5. test MRR/MPR rd latency error. write 1 clear +//bit 4, sha done. write 1 to clean. +//bit 3, write done. write 1 to clean. +//bit 2, read done. write 1 to clean +//bit 1, write watchdog triggered. write 1 to clean +//bit 0, read watchdog triggered. write 1 to clean. +#define P_DMC_TEST_COMP_MASK ((volatile uint32_t *)0xfd0214cc) +//32bits for DMC TEST COMPARE bit enable. +//1 : to MASK this bit. 0: compare this bit. +#define P_DMC_TEST_RDBI0 ((volatile uint32_t *)0xfd0214d0) +//MPC RD FIFO command DBI read back data +//bit 31:16 the second cycle. +//bit 15:0 the first cycle. +#define P_DMC_TEST_RDBI1 ((volatile uint32_t *)0xfd0214d4) +//MPC RD FIFO command DBI read back data +//bit 31:16. the Forth cycle. +//bit 15:0. the third cycle. +#define P_DMC_TEST_WSTRB0 ((volatile uint32_t *)0xfd0214d8) +//MPC WR FIFO command DM bit write data +//bit 31:16 the second cycle. +//bit 15:0 the first cycle. +#define P_DMC_TEST_DRAM_CMD ((volatile uint32_t *)0xfd0214e0) +//bit 31. cmd done. write 0 to clean. +//bit 30. data done. write 0 to clean. +//bit 4:0. only one bit can be 1. read data stored in DMC_TEST_RD* write data from DMC_TEST_W +//bit 4. LPDDR4 MPC write data command( MPC WR FIFO). Not support LPDDR4 in A1. +//bit 3. LPDDR4 MPC read data command (MPC RD Calibration and RD FIFO).Not support LPDDR4 in A1. +//bit 2. LPDDR4 MPC-1 command ( NOP, Start DQS interval ....)Not support LPDDR4 in A1. +//bit 1. mrr comand. +//bit 0. mrw command. +#define P_DMC_TEST_DRAM_CMD_CODE ((volatile uint32_t *)0xfd0214e4) +//bit 27:26. 128bits data cycles . 0: 1 clock cycles; 1: 2 clock cycles; 2: 3 clock cycles; 3:4 clock cycles. +// LPDDR4 32bits: 4 clock cycles; LPDDR4 16bits: 2 clock cycles; +// DDR3/4/LPDDR3 32 bits : 2 clock cycles. DDR3/4 16bits: 1 cycles. +//bit 25 MRW/MRR/MPC command rank 1 select. 1: select. 0: not select. In A1, only rank0 supported. +//bit 24. MRW/MRR/MPC command rank 0 select. 1: select. 0: not select.In A1, only rank0 supported. +//bit 23:16 MR addr. DDR4 case : 18:16 ba[2:0]. 20:19 BG[1:0]. +//bit 15:0 opcode. +#define P_DMC_TEST_DRAM_CMD_TIME ((volatile uint32_t *)0xfd0214e8) +//bit 31:16 PRE CMD timer. //delay how many cycle to start the command. +//bit 15:0 POST CMD timer //delay how many cycle after the command execute. +//`endif +// +// Closing file: ../mmc_lp4/dmc/rtl/dmc_sec.vh +// +// +// Reading file: ../mmc_lp4/dmc/rtl/dmc_reg.vh +// +//`ifdef DMC_REG_DEFINE +//`else +//`define DMC_REG_DEFINE +// ----------------------------------------------- +// APB_BASE: APB1_BASE_ADDR = 0xfd020000 +// ----------------------------------------------- +//`define DMC_REG_BASE 32'hfd020000 +#define P_DMC_SOFT_RST2 ((volatile uint32_t *)0xfd02000c) +//bit 31~11. reserved for future. +//bit 10 DMC DFI cmd soft reset_n +//bit 9 DMC DFI MISC soft reset_n +//bit 8 DMC DFI data soft reset_n +//bit 7 DMC DFI dcu soft reset_n +//bit 6 DMC siu soft reset_n +//bit 5. DMC test soft reset_n. 0 : reset. 1 : normal working mode. +//bit 4. DMC low power control moudle soft reset_n. 0 : reset. 1 : normal working mode. +//bit 3. DMC QOS monitor module soft reset_n. 0 : reset. 1 : normal working mode. +//bit 2. DMC register modle soft reset_n. 0 : reset. 1 : normal working mode. +//bit 1. DMC canvas transfer module soft reset_n. 0 : reset. 1 : normal working mode. +//bit 0. DMC command buffers and command generation modules soft reset. 0 = reset. 1: +#define P_DMC_VERSION ((volatile uint32_t *)0xfd020014) +//read only 32'h000b0000. for A1 +#define P_DMC_MON_CTRL0 ((volatile uint32_t *)0xfd020080) +//bit 31. qos_mon_en. write 1 to trigger the enable. polling this bit 0, means finished. or use interrupt to check finish. +//bit 30. qos_mon interrupt clear. clear the qos monitor result. read 1 = qos mon finish interrupt. +//bit 1. qos monitor 1 enable. +//bit 0. qos monitor 0 enable. +#define P_DMC_MON_CTRL1 ((volatile uint32_t *)0xfd020084) +//bit 8:0. qos monitor 0 channel select. +//bit 8 to select DMC TEST +//bit 7:0 each bit enable one AXI subID. +#define P_DMC_MON_CTRL2 ((volatile uint32_t *)0xfd020088) +//bit 8. to enabe monitor 0 second level subID selection for example device. +//bit 7:0 each bit to enable one second level subID inside device. +#define P_DMC_MON_CTRL3 ((volatile uint32_t *)0xfd02008c) +//bit 8:0. qos monitor 1 channel select. +//bit 8 to select DMC TEST +//bit 7:0 each bit enable one AXI subID. +#define P_DMC_MON_CTRL4 ((volatile uint32_t *)0xfd020090) +//bit 8. to enabe monitor 1 second level subID selection for example device. +//bit 7:0 each bit to enable one second level subID inside device. +#define P_DMC_MON_ALL_REQ_CNT ((volatile uint32_t *)0xfd0200a4) +// at the test period, the whole MMC request time. +#define P_DMC_MON_ALL_GRANT_CNT ((volatile uint32_t *)0xfd0200a8) +// at the test period, the whole MMC granted data cycles. 64bits unit. +#define P_DMC_MON_ONE_GRANT_CNT ((volatile uint32_t *)0xfd0200ac) +// at the test period, the granted data cycles for the selected channel and ports. +#define P_DMC_MON_SEC_GRANT_CNT ((volatile uint32_t *)0xfd0200b0) +// at the test period, the granted data cycles for the selected channel and ports. +#define P_DMC_MON_TIMER ((volatile uint32_t *)0xfd0200bc) +// timer for the monitor period. +#define P_DMC_CLKG_CTRL2 ((volatile uint32_t *)0xfd0200c8) +//bit 10 enable auto clock gating for dfi command generation +//bit 9 enable auto clock gating for dram cntroller +//bit 8 enable auto clock gating for dfi data path. +//bit 7. enalbe auto clock gating for write rsp generation. +//bit 6. enalbe auto clock gating for read rsp generation. +//bit 5. enalbe auto clock gating for ddr0 command filter. +//bit 4. enalbe auto clock gating for ddr0 write reorder buffer. +//bit 3. enalbe auto clock gating for ddr0 write data buffer. +//bit 2. enalbe auto clock gating for ddr0 read reorder buffer. +//bit 1. reserved +//bit 0. reserved +#define P_DMC_CLKG_CTRL3 ((volatile uint32_t *)0xfd0200cc) +//bit 10 force to disable the clock of dfi command generation +//bit 9 force to disable the clock of dram cntroller +//bit 8 force to disable the clock of dfi data path. +//bit 7. force to disalbe the clock of write rsp generation. +//bit 6. force to disalbe the clock of read rsp generation. +//bit 5. force to disalbe the clock of command filter. +//bit 4. force to disalbe the clock of write reorder buffer. +//bit 3. force to disalbe the clock of write data buffer. +//bit 2. force to disalbe the clock of read reorder buffer. +//bit 1. reserved. +//bit 0. reserved. +#define P_DMC_CHAN_STS ((volatile uint32_t *)0xfd0200d8) +//bit 4 always 1 +//bit 3 ddr0 write data buffer idle. 1 : idle 0: busy. +//bit 2 always 1. +//bit 1 ddr0 wbuf idle. 1 : idle 0: busy. +//bit 0. axi0 channel idle. 1 : idle 0: busy. +#define P_DMC_CMD_FILTER_CTRL3 ((volatile uint32_t *)0xfd020108) +//bit 31. force wbuf empty. +//bit 30:26 wbuf high level number +//bit 25:21 wbuf mid level number +//bit 20:16 wbuf low level number +//bit 14:10 rbuf high level number +//bit 9:5 rbuf middle level number +//bit 4:0 rbuf low level number +#define P_DMC_CMD_FILTER_CTRL4 ((volatile uint32_t *)0xfd02010c) +//bit 29:25. tITW.long +//bit 24:20. tITW. short +//bit 19:12 tAP auto precharge the bank not used if idle that long time. +//bit 11:6 write to read accesses if there write hit request. +//bit 5:0 read to write accesses if there write hit request. +#define P_DMC_CMD_FILTER_CTRL5 ((volatile uint32_t *)0xfd020110) +//bit 31:24 Once ddr data bus switch to read, the maxmum read command number to give up the bus when there's write request pending for write buffer. +//bit 23:16 Once ddr data bus switch to write, the maxmum write command number to give up the bus when there's read request pending too long. +//bit 15:8. Once ddr data bus switch to read, the minimum read command number to transfer back to write stage if there's still pending read request. +//bit 7:0. Once ddr data bus switch to write, the minimum write command number to transfer back to read stage if there's still pending write request. +#define P_DMC_CMD_FILTER_CTRL6 ((volatile uint32_t *)0xfd020114) +//bit 31:24 write urgent 3 request pending hold num. +//bit 23:16 write urgent 2 request pending hold num. +//bit 15:8. write urgent 1 request pending hold num. +//bit 7:0. write urgent 0 request pending hold num. +#define P_DMC_CMD_FILTER_CTRL7 ((volatile uint32_t *)0xfd020118) +//bit 15:8 write to read waiting cycles if there write hit request. +//bit 7:0 read to write waiting cycles if there write hit request. +#define P_DMC_CMD_BUFFER_CTRL ((volatile uint32_t *)0xfd02011c) +//bit 31:26 total write buffer number. default 32. +//bit 25:20 total read buffer number. default 32. +//bit 19:8 reserved. +//bit 7:0 aw_pending_inc_num. incease write ugent level 1 when write command waiting to in write buffer that long. +#define P_DMC_CMD_BUFFER_CTRL1 ((volatile uint32_t *)0xfd020120) +//bit 29:24 read buffer number in non-urgent request. +//bit 23:16 read buffer bank miss watch dog threshold. +//bit 15:12 read buffer urgent level 3 counter inc weight. +//bit 11:8 read buffer urgent level 2 counter inc weight. +//bit 7:4 read buffer urgent level 1 counter inc weight. +//bit 3:0 read buffer urgent level 0 counter inc weight. +#define P_DMC_AXI0_CHAN_CTRL ((volatile uint32_t *)0xfd020200) +//bit 31 AXI interface request enable. +//bit 19 AXI interface auto clock gating enable. 1: enable; 0 disable. +//bit 18 AXI interface clock disable. 1 : disable clock. 0 enable clock. +//bit 17 AXI interface dmc clock domain soft reset. 0 : reset. 1 : normal working mode. +//bit 16 AXI interface s0 clock domain soft reset. 0 : reset. 1 : normal working mode. +//bit 15:12 ugt3 QOS level. +//bit 11:8 ugt2 QOS level. +//bit 7:4 ugt1 QOS level. +//bit 3:0 not used. +#define P_DMC_AXI0_HOLD_CTRL ((volatile uint32_t *)0xfd020204) +//31:24 write hold num. max outstanding request number. +//23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request. +//15:8 read hold num. max outstanding request number. +//7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request. +#define P_DMC_AXI5_HOLD_CTRL ((volatile uint32_t *)0xfd020254) +//31:24 write hold num. max outstanding request number. +//23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request. +//15:8 read hold num. max outstanding request number. +//7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request. +//`endif +// +// Closing file: ../mmc_lp4/dmc/rtl/dmc_reg.vh +// +// +// Reading file: ../mmc_lp4/dmc/rtl/dmc_siu_reg.vh +// +//`ifdef DMC_SIU_REG_DEFINE +//`else +//`define DMC_SIU_REG_DEFINE +// ----------------------------------------------- +// APB_BASE: APB1_BASE_ADDR = 0xfd020400 +// ----------------------------------------------- +//`define DMC_DRAM_REG_BASE 32'hfd020400 +//in A1 project, don't support hardware controlled frequency change. +#define P_DMC_DRAM_TMRD ((volatile uint32_t *)0xfd020400) +//bit 3:0. tMRD. +#define P_DMC_DRAM_TRFC ((volatile uint32_t *)0xfd020404) +//bit 9:0 tRFC +#define P_DMC_DRAM_TRP ((volatile uint32_t *)0xfd020408) +//bit 21:16. tRP for precharge all banks. +//bit 5:0. tRP for precharge one bank. +#define P_DMC_DRAM_TRTW ((volatile uint32_t *)0xfd02040c) +//bit 5:0 tRTW +#define P_DMC_DRAM_TCL ((volatile uint32_t *)0xfd020410) +//bit 5:0 tCL/tRL. read latency. +#define P_DMC_DRAM_TCWL ((volatile uint32_t *)0xfd020414) +//bit 5:0. CWL: write latency. +#define P_DMC_DRAM_TRAS ((volatile uint32_t *)0xfd020418) +//bit 7:0. tRAS. minimum active to precharge time for same bank. +#define P_DMC_DRAM_TRC ((volatile uint32_t *)0xfd02041c) +//bit 7:0. tRC. minimum active to active time for same bank. +#define P_DMC_DRAM_TRCD ((volatile uint32_t *)0xfd020420) +//bit 7:0 tRCD active to read/write timing for same bank. +#define P_DMC_DRAM_TRRD ((volatile uint32_t *)0xfd020424) +//bit 21:16. tRRD_l active bank A to active B in same band group for DDR4. +//bit 5:0. tRRD/tRRD_s active bank A to active bank b time. +//tRRD_s: active bank A to active bank b in different bank grousp for DDR4. +#define P_DMC_DRAM_TFAW ((volatile uint32_t *)0xfd020428) +//bit 8:0 tFAW. four active command windows +#define P_DMC_DRAM_TRTP ((volatile uint32_t *)0xfd02042c) +//bit 5:0 tRTP. +#define P_DMC_DRAM_TWR ((volatile uint32_t *)0xfd020430) +//bit 5:0 tWR. +#define P_DMC_DRAM_TWTR ((volatile uint32_t *)0xfd020434) +//bit 5:0 tWTR. +#define P_DMC_DRAM_TCCD ((volatile uint32_t *)0xfd020438) +//bit 19:16. tCCD/tCCD_l. +//bit 3:0 tCCD/tCCD_s read to read command time or write to write command time. +#define P_DMC_DRAM_TEXSR ((volatile uint32_t *)0xfd02043c) +//bit 9:0. tEXSR. EXIT SELF-REFRESH to read/write command. +#define P_DMC_DRAM_TXS ((volatile uint32_t *)0xfd020440) +//bit 9:0 tXS. EXIT SELF_REFRESH to other command time +#define P_DMC_DRAM_TXP ((volatile uint32_t *)0xfd020444) +//bit 3:0. tXP. EXIT power down to other command time +#define P_DMC_DRAM_TXPDLL ((volatile uint32_t *)0xfd020448) +//bit 9:0. tXPDLL, EXIT power down to read/write command time(need to relock PLL). +#define P_DMC_DRAM_TZQCS ((volatile uint32_t *)0xfd02044c) +//bit 11:0. ZQCS command to other command time. +#define P_DMC_DRAM_TCKSRE ((volatile uint32_t *)0xfd020450) +//bit 4:0. enter self refresh to disable clock time. +#define P_DMC_DRAM_TCKSRX ((volatile uint32_t *)0xfd020454) +//bit 4:0. enable clock to exit self refresh time. +#define P_DMC_DRAM_TCKE ((volatile uint32_t *)0xfd020458) +//bit 4:0. CKE high or low minimum time. +#define P_DMC_DRAM_TMOD ((volatile uint32_t *)0xfd02045c) +//bit 4:0 tMOD. MRR/MRW to other command time. +#define P_DMC_DRAM_TDQS ((volatile uint32_t *)0xfd020460) +//bit 3:0 tDQS. the delay to access different rank. +#define P_DMC_DRAM_TRSTL ((volatile uint32_t *)0xfd020464) +//not used. +#define P_DMC_DRAM_TZQLAT ((volatile uint32_t *)0xfd020468) +//bit 5:0 ZQ LATCH command to other comand timing in LPDDR4 mode. +#define P_DMC_DRAM_TMRR ((volatile uint32_t *)0xfd02046c) +//bit 7:0 tMRR not used in DMC. not support MR READ. +#define P_DMC_DRAM_TCKESR ((volatile uint32_t *)0xfd020470) +//bit 9:0 tCKESR. CKE low minimum pulse in self refresh mode. +#define P_DMC_DRAM_TDPD ((volatile uint32_t *)0xfd020474) +//not support. +#define P_DMC_DRAM_DFITCTRLDELAY ((volatile uint32_t *)0xfd020478) +//bit 3:0. DFI_t_ctrldealy +#define P_DMC_DRAM_DFITPHYWRDATA ((volatile uint32_t *)0xfd02047c) +//bit 5:0. dfi_t_phy_wrdata. +#define P_DMC_DRAM_DFITPHYWRLAT ((volatile uint32_t *)0xfd020480) +//bit 5:0. dfi_t_phy_wrlat. in DDR3/4/LPDDR3 mode: WL -5. in LPDDR4 mode: WL -5 + 2. +#define P_DMC_DRAM_DFITRDDATAEN ((volatile uint32_t *)0xfd020484) +//bit 5:0. dfi_t_rddata_en. in DDR3/4/LPDDR3 mode: RL -5. in LPDDR4 mode : RL -5 + 1. +#define P_DMC_DRAM_DFITPHYRDLAT ((volatile uint32_t *)0xfd020488) +//bit 5:0. dfi_t_rdlat. +#define P_DMC_DRAM_DFITCTRLUPDMIN ((volatile uint32_t *)0xfd02048c) +//bit 7:0. CTRLUPD_MIN minimux clock cycle to maintain CTRLUPD_REQ. +#define P_DMC_DRAM_DFITCTRLUPDMAX ((volatile uint32_t *)0xfd020490) +//bit 7:0 CTRLUPD_MAX. maxmum clock cycle to maintain CTRLUPD_REQ if no CTRLUPD_ACK response. +#define P_DMC_DRAM_DFITMSTRRESP ((volatile uint32_t *)0xfd020494) +//not used. +#define P_DMC_DRAM_DFITREFMSKI ((volatile uint32_t *)0xfd020498) +//not used. +#define P_DMC_DRAM_DFITCTRLUPDI ((volatile uint32_t *)0xfd02049c) +//not used. +#define P_DMC_DRAM_DFITDRAMCLK ((volatile uint32_t *)0xfd0204a0) +//bit 17 dram clk1 enable. +//bit 16 dram clk0 enable. +//bit 15:8 DRAM CLK disable waiting time +//bit 7:0 DRAM CLK enable enable timer +#define P_DMC_DRAM_DFITLPRESP ((volatile uint32_t *)0xfd0204a8) +//bit 3:0. dfi_lp_ctrl_req response time. after dfi_lp_ctrl_req asserted, and after response time if there's still no dfi_lp_ack respone, then drop the dfi_lp_ctrl_req. +#define P_DMC_DRAM_DFITPHYMSTR ((volatile uint32_t *)0xfd0204ac) +//bit 15 1: enable DFIPHYMASTER INTERFACE 0 disable DFIPHYMSTR en response. +// always 0 we would use DFI_RETRAIN function for PHY retrain required from LPDDR4. +#define P_DMC_DRAM_TCKECK ((volatile uint32_t *)0xfd0204b0) +//bit 4:0. tCKECK from CKE low to assert dfi_dram_clk_disable time. this time + dfi_t_ctrl_delay +#define P_DMC_DRAM_TREFI ((volatile uint32_t *)0xfd0204b4) +//write this register will update the auto refresh related register to the auto refresh control logic. +//bit 31:24: tZQCI dmc send zqci period. unit is how much auto refresh period. +//bit 23:16 pvti dmc send dfi_ctrlupd_req period. unit is one auto refresh period. +//bit 15:8. tREFI.dmc send auto refresh command period. unit is 100ns. +//bit 7:0. t100ns period. unit is dmc clock cycles +#define P_DMC_DRAM_TSR ((volatile uint32_t *)0xfd0204b8) +//bit 5:0 tSR. self resfresh enter to exit time. +#define P_DMC_DRAM_TCCDMW ((volatile uint32_t *)0xfd0204bc) +//bit 5:0. 4*tCCD in LPDDR4 mask write. +#define P_DMC_DRAM_TESCKE ((volatile uint32_t *)0xfd0204c0) +//bit 5:0 tESCKE. enter self refresh to power time for LPDDR4. +#define P_DMC_DRAM_TREFI_DDR3 ((volatile uint32_t *)0xfd0204c4) +//7:0. 8*DDR3 SDRAM tREFI time . the unit is t100ns. use this to check in 8*tREFI time, the DMC should sent more than 16 auto REFRESH command. +#define P_DMC_DRAM_TZQCAL ((volatile uint32_t *)0xfd0204c8) +//7:0. ZQCAL for LPDDR4. +#define P_DMC_DRAM_T10US ((volatile uint32_t *)0xfd0204cc) +//10us clock cycle number used for LP2 mode. +#define P_DMC_DRAM_TMRRI ((volatile uint32_t *)0xfd0204d0) +//bit 7:0 tMRRI for MRR +#define P_DMC_DRAM_DFITPHYUPDTYPE0 ((volatile uint32_t *)0xfd020600) +//dfi_phyupd_ack hold time for dfi_phyupd_req type = 0. +#define P_DMC_DRAM_DFITPHYUPDTYPE1 ((volatile uint32_t *)0xfd020604) +//dfi_phyupd_ack hold time for dfi_phyupd_req type = 1. +#define P_DMC_DRAM_DFITPHYUPDTYPE2 ((volatile uint32_t *)0xfd020608) +//dfi_phyupd_ack hold time for dfi_phyupd_req type = 2. +#define P_DMC_DRAM_DFITPHYUPDTYPE3 ((volatile uint32_t *)0xfd02060c) +//dfi_phyupd_ack hold time for dfi_phyupd_req type = 3. +#define P_DMC_DRAM_DFIODTCFG ((volatile uint32_t *)0xfd020610) +//bit 12. rank1 ODT default. default vulue for ODT[1] pins if theres no read/write activity. +//bit 11. rank1 ODT write sel. enable ODT[1] if there's write occur in rank1. +//bit 10. rank1 ODT write nsel. enable ODT[1] if theres's write occur in rank0. +//bit 9. rank1 odt read sel. enable ODT[1] if there's read occur in rank1. +//bit 8. rank1 odt read nsel. enable ODT[1] if there's read occure in rank0. +//bit 4. rank0 ODT default. default vulue for ODT[0] pins if theres no read/write activity. +//bit 3. rank0 ODT write sel. enable ODT[0] if there's write occur in rank0. +//bit 2. rank0 ODT write nsel. enable ODT[0] if theres's write occur in rank1. +//bit 1. rank0 odt read sel. enable ODT[0] if there's read occur in rank0. +//bit 0. rank0 odt read nsel. enable ODT[0] if there's read occure in rank1. +#define P_DMC_DRAM_DFIODTCFG1 ((volatile uint32_t *)0xfd020614) +//bit 27:24 ODT length for BL8 read transfer. +//bit 19:16. ODT length for BL8 write transfer. +//bit 12:8. ODT latency for reads. suppose to be 0. +//bit 4:0. ODT latency for writes. suppose to be 0. +#define P_DMC_DRAM_MCFG ((volatile uint32_t *)0xfd020618) +//bit 14. 1: cke init low. 0 : cke init high. +//bit 13 1: dbi write enable only for LPDDR4. +//bit 12. 1: dbi read inversion. 0: dbi read high inversion. +//bit 11. 1: dbi read enable. 0: dbi not enabled. +//bit 10 1: enable staggered chip select for 2 ranks DRAM. +//bit 9 1: enable send auto refresh command to DDR SDRAM when PCTL is in CFG/STOP state. +//bit 8 send auto refr cmd before enter register triggered self refresh +//bit 7 send auto refr cmd after exit regsiter triggered self refresh mode. +//bit 6 disable dram clock after enter register triggered self refresh. +//bit 5 send DFI_LP_REQ to PHY after enter register triggered elf refresh mode. +//bit 4 send DRAM to power down mode after enter self refresh. ONLY for LPDDR4. +//bit 3 send DFI_CTRLUPD_REQ after exit register triggered self refresh. +//bit 2 send ZQCS command after exit register triggered self refresh. +//bit 1 enable PHY triggered DFI_PHYUPD_REQ. +//bit 0 2T mode. always 1 in DDR3/4 mode. +#define P_DMC_DRAM_DFI_CTRL ((volatile uint32_t *)0xfd020624) +//bit 31 siu_dfi_lat err generation enable. 1: if dfi read latency violation, generate data error. 0 : disable. +//bit 30:0. not used. +#define P_DMC_DRAM_DFIINITCFG ((volatile uint32_t *)0xfd020628) +//bit 31. dfi_init_complete status. read only. +//bit 15:14. Frequency set 1 dfi_freq_ratio value. Not used in A1 +//bit 12:8 Frequency set 1 dfi_freq value. Not used in A1 +//bit 7:6 Frequency set 0 dfi_freq_ratio value. +//bit 5:1 Frequency set 0 dfi_freq value. +//bit 0. dfi_init_start value can be use manually config dfi_init_start signal. +#define P_DMC_DRAM_ZQ_CTRL ((volatile uint32_t *)0xfd02062c) +// only bit 0 can be enable in A1. +//bit 2 send ZQCS command to RANK0 then send comand to RANK1. +//bit 1. send ZQCS command to both RANK0 and RANK1 together. +//bit 0. send ZQCS command to only rank0. +#define P_DMC_DRAM_APD_CTRL ((volatile uint32_t *)0xfd020630) +//bit 19:16 DFI_LP_WAKEUP value in APD DFI_LP_REQ mode +//bit 12 1: exit power down slow mode(waiting PLL LOCK). 0 : fast mode. +//bit 11 enable DFI_LP_REQ when enter Auto power down mode. +//bit 10 disable DFI_clk_disable when enter auto power down mode. +//bit 9:0 0 disable auto power down mode. +//non zero value to enable auto power down when DMC is in idle state for this number of clock cycles. +#define P_DMC_DRAM_ASR_CTRL ((volatile uint32_t *)0xfd020634) +//bit [25] LP2 mode PHYCLK enable. 1 : keep PHY clock enable after enter LP2 mode. 0 : shutdown PHY clock after enter LP2 mode. +//bit [24] LP2 mode SRX waiting enable. if Self refresh too long, waiting 10us for the PHY stable before DDR SDRAM exit from self refresh state. +//bit [23:20] DFI_LP_WAKEUP value in self refresh DFI_LP_REQ mode. +//bit 17 : send REFRESH command after exit from auto self refersh mode(ASR). +//bit 16 : send REFERSH command before enter to Auto self refresh mode(ASR). +//bit 15 : send ZQCS command after exit from Auto self refresh mode(ASR). +//bit 14 : send dfi_ctrl_upd after exit from ASR mode +//bit 13 : send power down command when enter ASR mode. //for LPDDR4 only. +//bit 12 : set the PHY enter LP2 mode after enter ASR mode. +//bit 11 : send DFI_LP_REQ after enter ASR mode. +//bit 10 : set DFI_CLK_DISABLE after enter ASR mode. +//bit 9:0. 0 disable auto ASR mode. +// Non-zero valule enable ASR mode. when DMC is in idle state for this number of clock cycles, the DMC will enter ASR mode. +#define P_DMC_DRAM_PHYMSTR_CTRL ((volatile uint32_t *)0xfd020640) +//not used in A1. should be all 0. +#define P_DMC_DRAM_DFIODTRANKMAP ((volatile uint32_t *)0xfd020644) +//not used in A1. +#define P_DMC_DRAM_REFR_CTRL ((volatile uint32_t *)0xfd020648) +//bit 17:8 auto refresh request pending cnt if there's page hit request. +//bit 6 Disabled auto refresh command if over 16 auto refresh command sent in 2 TREFI_DDR3 period +//bit 5 enable dmc send ZQCS command . +//bit 4. enable dmc send DFI_CTRUPD_REQ. +//bit 3:1. how many refresh command send for one period. = this number + 1 +//bit 0. enable dmc send auto refresh command. +#define P_DMC_DRAM_FREQ_CTRL ((volatile uint32_t *)0xfd02064c) +//bit 31 . wiret 1 to change freqency read 0: finished. +//bit 30:9. not used. +//bit 9. 1 : FREQ MRW done. let FREQ change machine continue. +//bit 8 FREQ WAIT. 1 when freq change finishes, state machine stop at self refresh state in case there's something need to handle. +// 0 after freq change finishes the state machine go back to access state. +//bit 7 when change PLL setting, disable dmc clock +//bit 6 when change PLL setting, disable PHY DfiClk and DfiCtlClk. +//bit 5 check vpu_sleep_en ==1 when do FREQ change. if vpu_sleep_en == 0, just wait. +//bit 4 nxt frequency selection. 1 = freq1. 0 = freq0. +//bit 3:1. not used. +//bit 0. current frequency selection. +#define P_DMC_DRAM_SCFG ((volatile uint32_t *)0xfd020650) +// bit 2:0 only one bit can be high at same time. +// bit 2 1 : to ask PCTL enter ACCESS STATE. 0 : deassert the request. +// bit 1 1 : to ask PCTL enter SELF REFRESH STATE. 0 : deassert the request. +// bit 0 1 : to ask PCTL enter STOP/CONFIG STATE . 0 : deassert the request. +#define P_DMC_DRAM_STAT ((volatile uint32_t *)0xfd020654) +//bit 31 rd latency error. 1: means after dfiphytrdlat cycles, the read data still not back. +//bit 28:24 dram_sr_state +//bit 23:20 stop_st +//bit 19:15 sleep_st +//bit 14:12 ACCESS STATUS 0 : ACCESS is in normal working mode. +//1 : ACCESS sending precharege command. +//2 : ACCESS sending AUTO REFESH command. +//3 : ACCESS sending DIF_CTRLUPD_REQ command. +//4 : ACCESS sending ZQCS command to DDR DRAM(ZQCAL for LPDDR4). +//5 : ACCESS sending ZQLATCH command to LPDDR4 only. +//bit 11:8 APD STATUS: 0 : APD_IDLE +//1 : APD sending PRECHARGE command +//2 : APD sending CKE low command +//3 : APD sending DISABLE DRAM CLOCK command +//4 : APD sending DFI_LP_CTRL_REQ +//5 : APD in Auto Power down mode. +//6 : APD deassert DFI_LP_CTRL_REQ +//7 : APD sending enable DRAM CLOCK command +//8 : APD sending out CKE high command. +//bit 7:4: DRAM_STATUS: 0 : DRAM IDLE +//1 : DRAM_STOP/DRAM_CFG +//2 : DRAM_ACCESS +//3 : DRAM_SLEEP +//4 : DRAM APD(AUTO POWER DOWN). +//5 : IDLE -> STOP/CONFIG +//6 : STOP -> SLEEP +//7 : STOP -> ACCESS +//8 : ACCESS -> SLEEP. +//9 : ACCESS -> STOP +//A : ACCESS -> APD +//B : SLEEP -> STOP +//C : SLEEP -> ACCESS +//D : APD -> ACCESS +//bit 3 reserved. +//bit 2 1 : DRAM enter normal working state. +//bit 1 1 : DRAM enter sleep state. self refresh state. +//bit 0 1 : dram enter cfg state. +#define P_DMC_DRAM_STAT1 ((volatile uint32_t *)0xfd020658) +//bit 11:8 freq_st. +//bit 7:5 train_st +//bit 4:0 dram_phy_st +#define P_DMC_PHY_RETRAINING_CTRL ((volatile uint32_t *)0xfd02065c) +// A1 not support LPDDR4 so this register is not used in A1. +//bit 31 : phy_retraining enable. +//bit 30 : check vpu sleep_en. +//bit 25:24 : retraining dfi_freq[4:3], the [2:0] bit still use the dfi_freq bits to keep the frequency. +//bit 23:0: retraining period unit : 100ns. +#define P_DMC_DFI_ERR_STAT ((volatile uint32_t *)0xfd020660) +//LPDDR4 PHY DFI error infomation. +//bit 31:20. not used. +//bit 9. ddr0_dfi_error +//bit 8:5 ddr0_dfi_error_info. +//bit 4. ddr1_dfi_error. +//bit 3:0. ddr1_dfi_error_info. +#define P_DMC_LP2_TIMER ((volatile uint32_t *)0xfd020668) +//bit 15:0. timer setting to measure how long the chip is entered LP2 mode. +//this timer is 40bits counter with DMC PCLK. +//we use the high 16bits to compare this register. if the counter is large than this number, that means the PHY need addition 10us after wakeup the PHY and before exit self_refresh mode. +#define P_DMC_DRAM_DFI_SWAP_0 ((volatile uint32_t *)0xfd020680) +//bit 5:0. dfi_act_n function select +// 6'h00 : the function itself. +// 6'h01 : act_n. +// 6'h02 : ras_n. +// 6'h03 : cas_n. +// 6'h04 : we_n. +// 6'h05 : bg[0]. +// 6'h06 : bg[1]. +// 6'h07 : ba[0]. +// 6'h08 : ba[1]. +// 6'h09 : ba[2]. +// 6'h0a : a[0]. +// 6'h0b : a[1]. +// 6'h0c : a[2]. +// 6'h0d : a[3]. +// 6'h0e : a[4]. +// 6'h0f : a[5]. +// 6'h10 : a[6]. +// 6'h11 : a[7]. +// 6'h12 : a[8]. +// 6'h13 : a[9]. +// 6'h14 : a[10]. +// 6'h15 : a[11]. +// 6'h16 : a[12]. +// 6'h17 : a[13]. +// 6'h18 : a[14]. +// 6'h19 : a[15]. +// 6'h1a : a[16]. +// 6'h1b : a[17]. +#define P_DMC_DRAM_DFI_SWAP_1 ((volatile uint32_t *)0xfd020684) +//bit 5:0. dfi_ras_n function select +// 6'h00 : the function itself. +// 6'h01 : act_n. +// 6'h02 : ras_n. +// 6'h03 : cas_n. +// 6'h04 : we_n. +// 6'h05 : bg[0]. +// 6'h06 : bg[1]. +// 6'h07 : ba[0]. +// 6'h08 : ba[1]. +// 6'h09 : ba[2]. +// 6'h0a : a[0]. +// 6'h0b : a[1]. +// 6'h0c : a[2]. +// 6'h0d : a[3]. +// 6'h0e : a[4]. +// 6'h0f : a[5]. +// 6'h10 : a[6]. +// 6'h11 : a[7]. +// 6'h12 : a[8]. +// 6'h13 : a[9]. +// 6'h14 : a[10]. +// 6'h15 : a[11]. +// 6'h16 : a[12]. +// 6'h17 : a[13]. +// 6'h18 : a[14]. +// 6'h19 : a[15]. +// 6'h1a : a[16]. +// 6'h1b : a[17]. +#define P_DMC_DRAM_DFI_SWAP_2 ((volatile uint32_t *)0xfd020688) +//bit 5:0. dfi_cas_n function select +// 6'h00 : the function itself. +// 6'h01 : act_n. +// 6'h02 : ras_n. +// 6'h03 : cas_n. +// 6'h04 : we_n. +// 6'h05 : bg[0]. +// 6'h06 : bg[1]. +// 6'h07 : ba[0]. +// 6'h08 : ba[1]. +// 6'h09 : ba[2]. +// 6'h0a : a[0]. +// 6'h0b : a[1]. +// 6'h0c : a[2]. +// 6'h0d : a[3]. +// 6'h0e : a[4]. +// 6'h0f : a[5]. +// 6'h10 : a[6]. +// 6'h11 : a[7]. +// 6'h12 : a[8]. +// 6'h13 : a[9]. +// 6'h14 : a[10]. +// 6'h15 : a[11]. +// 6'h16 : a[12]. +// 6'h17 : a[13]. +// 6'h18 : a[14]. +// 6'h19 : a[15]. +// 6'h1a : a[16]. +// 6'h1b : a[17]. +#define P_DMC_DRAM_DFI_SWAP_3 ((volatile uint32_t *)0xfd02068c) +//bit 5:0. dfi_we_n function select +// 6'h00 : the function itself. +// 6'h01 : act_n. +// 6'h02 : ras_n. +// 6'h03 : cas_n. +// 6'h04 : we_n. +// 6'h05 : bg[0]. +// 6'h06 : bg[1]. +// 6'h07 : ba[0]. +// 6'h08 : ba[1]. +// 6'h09 : ba[2]. +// 6'h0a : a[0]. +// 6'h0b : a[1]. +// 6'h0c : a[2]. +// 6'h0d : a[3]. +// 6'h0e : a[4]. +// 6'h0f : a[5]. +// 6'h10 : a[6]. +// 6'h11 : a[7]. +// 6'h12 : a[8]. +// 6'h13 : a[9]. +// 6'h14 : a[10]. +// 6'h15 : a[11]. +// 6'h16 : a[12]. +// 6'h17 : a[13]. +// 6'h18 : a[14]. +// 6'h19 : a[15]. +// 6'h1a : a[16]. +// 6'h1b : a[17]. +#define P_DMC_DRAM_DFI_SWAP_4 ((volatile uint32_t *)0xfd020690) +//bit 5:0. dfi_bg0 function select +// 6'h00 : the function itself. +// 6'h01 : act_n. +// 6'h02 : ras_n. +// 6'h03 : cas_n. +// 6'h04 : we_n. +// 6'h05 : bg[0]. +// 6'h06 : bg[1]. +// 6'h07 : ba[0]. +// 6'h08 : ba[1]. +// 6'h09 : ba[2]. +// 6'h0a : a[0]. +// 6'h0b : a[1]. +// 6'h0c : a[2]. +// 6'h0d : a[3]. +// 6'h0e : a[4]. +// 6'h0f : a[5]. +// 6'h10 : a[6]. +// 6'h11 : a[7]. +// 6'h12 : a[8]. +// 6'h13 : a[9]. +// 6'h14 : a[10]. +// 6'h15 : a[11]. +// 6'h16 : a[12]. +// 6'h17 : a[13]. +// 6'h18 : a[14]. +// 6'h19 : a[15]. +// 6'h1a : a[16]. +// 6'h1b : a[17]. +#define P_DMC_DRAM_DFI_SWAP_5 ((volatile uint32_t *)0xfd020694) +//bit 5:0. dfi_bg[1] function select +// 6'h00 : the function itself. +// 6'h01 : act_n. +// 6'h02 : ras_n. +// 6'h03 : cas_n. +// 6'h04 : we_n. +// 6'h05 : bg[0]. +// 6'h06 : bg[1]. +// 6'h07 : ba[0]. +// 6'h08 : ba[1]. +// 6'h09 : ba[2]. +// 6'h0a : a[0]. +// 6'h0b : a[1]. +// 6'h0c : a[2]. +// 6'h0d : a[3]. +// 6'h0e : a[4]. +// 6'h0f : a[5]. +// 6'h10 : a[6]. +// 6'h11 : a[7]. +// 6'h12 : a[8]. +// 6'h13 : a[9]. +// 6'h14 : a[10]. +// 6'h15 : a[11]. +// 6'h16 : a[12]. +// 6'h17 : a[13]. +// 6'h18 : a[14]. +// 6'h19 : a[15]. +// 6'h1a : a[16]. +// 6'h1b : a[17]. +#define P_DMC_DRAM_DFI_SWAP_6 ((volatile uint32_t *)0xfd020698) +//bit 5:0. dfi_ba[0] function select +// 6'h00 : the function itself. +// 6'h01 : act_n. +// 6'h02 : ras_n. +// 6'h03 : cas_n. +// 6'h04 : we_n. +// 6'h05 : bg[0]. +// 6'h06 : bg[1]. +// 6'h07 : ba[0]. +// 6'h08 : ba[1]. +// 6'h09 : ba[2]. +// 6'h0a : a[0]. +// 6'h0b : a[1]. +// 6'h0c : a[2]. +// 6'h0d : a[3]. +// 6'h0e : a[4]. +// 6'h0f : a[5]. +// 6'h10 : a[6]. +// 6'h11 : a[7]. +// 6'h12 : a[8]. +// 6'h13 : a[9]. +// 6'h14 : a[10]. +// 6'h15 : a[11]. +// 6'h16 : a[12]. +// 6'h17 : a[13]. +// 6'h18 : a[14]. +// 6'h19 : a[15]. +// 6'h1a : a[16]. +// 6'h1b : a[17]. +#define P_DMC_DRAM_DFI_SWAP_7 ((volatile uint32_t *)0xfd02069c) +//bit 5:0. dfi_ba[1] function select +// 6'h00 : the function itself. +// 6'h01 : act_n. +// 6'h02 : ras_n. +// 6'h03 : cas_n. +// 6'h04 : we_n. +// 6'h05 : bg[0]. +// 6'h06 : bg[1]. +// 6'h07 : ba[0]. +// 6'h08 : ba[1]. +// 6'h09 : ba[2]. +// 6'h0a : a[0]. +// 6'h0b : a[1]. +// 6'h0c : a[2]. +// 6'h0d : a[3]. +// 6'h0e : a[4]. +// 6'h0f : a[5]. +// 6'h10 : a[6]. +// 6'h11 : a[7]. +// 6'h12 : a[8]. +// 6'h13 : a[9]. +// 6'h14 : a[10]. +// 6'h15 : a[11]. +// 6'h16 : a[12]. +// 6'h17 : a[13]. +// 6'h18 : a[14]. +// 6'h19 : a[15]. +// 6'h1a : a[16]. +// 6'h1b : a[17]. +#define P_DMC_DRAM_DFI_SWAP_8 ((volatile uint32_t *)0xfd0206a0) +//bit 5:0. dfi_ba[2] function select +// 6'h00 : the function itself. +// 6'h01 : act_n. +// 6'h02 : ras_n. +// 6'h03 : cas_n. +// 6'h04 : we_n. +// 6'h05 : bg[0]. +// 6'h06 : bg[1]. +// 6'h07 : ba[0]. +// 6'h08 : ba[1]. +// 6'h09 : ba[2]. +// 6'h0a : a[0]. +// 6'h0b : a[1]. +// 6'h0c : a[2]. +// 6'h0d : a[3]. +// 6'h0e : a[4]. +// 6'h0f : a[5]. +// 6'h10 : a[6]. +// 6'h11 : a[7]. +// 6'h12 : a[8]. +// 6'h13 : a[9]. +// 6'h14 : a[10]. +// 6'h15 : a[11]. +// 6'h16 : a[12]. +// 6'h17 : a[13]. +// 6'h18 : a[14]. +// 6'h19 : a[15]. +// 6'h1a : a[16]. +// 6'h1b : a[17]. +#define P_DMC_DRAM_DFI_SWAP_9 ((volatile uint32_t *)0xfd0206a4) +//bit 5:0. dfi_a[0] function select +// 6'h00 : the function itself. +// 6'h01 : act_n. +// 6'h02 : ras_n. +// 6'h03 : cas_n. +// 6'h04 : we_n. +// 6'h05 : bg[0]. +// 6'h06 : bg[1]. +// 6'h07 : ba[0]. +// 6'h08 : ba[1]. +// 6'h09 : ba[2]. +// 6'h0a : a[0]. +// 6'h0b : a[1]. +// 6'h0c : a[2]. +// 6'h0d : a[3]. +// 6'h0e : a[4]. +// 6'h0f : a[5]. +// 6'h10 : a[6]. +// 6'h11 : a[7]. +// 6'h12 : a[8]. +// 6'h13 : a[9]. +// 6'h14 : a[10]. +// 6'h15 : a[11]. +// 6'h16 : a[12]. +// 6'h17 : a[13]. +// 6'h18 : a[14]. +// 6'h19 : a[15]. +// 6'h1a : a[16]. +// 6'h1b : a[17]. +#define P_DMC_DRAM_DFI_SWAP_10 ((volatile uint32_t *)0xfd0206a8) +//bit 5:0. dfi_a[1] function select +#define P_DMC_DRAM_DFI_SWAP_11 ((volatile uint32_t *)0xfd0206ac) +//bit 5:0. dfi_a[2] function select +#define P_DMC_DRAM_DFI_SWAP_12 ((volatile uint32_t *)0xfd0206b0) +//bit 5:0. dfi_a[3] function select +#define P_DMC_DRAM_DFI_SWAP_13 ((volatile uint32_t *)0xfd0206b4) +//bit 5:0. dfi_a[4] function select +#define P_DMC_DRAM_DFI_SWAP_14 ((volatile uint32_t *)0xfd0206b8) +//bit 5:0. dfi_a[5] function select +#define P_DMC_DRAM_DFI_SWAP_15 ((volatile uint32_t *)0xfd0206bc) +//bit 5:0. dfi_a[6] function select +#define P_DMC_DRAM_DFI_SWAP_16 ((volatile uint32_t *)0xfd0206c0) +//bit 5:0. dfi_a[7] function select +#define P_DMC_DRAM_DFI_SWAP_17 ((volatile uint32_t *)0xfd0206c4) +//bit 5:0. dfi_a[8] function select +#define P_DMC_DRAM_DFI_SWAP_18 ((volatile uint32_t *)0xfd0206c8) +//bit 5:0. dfi_a[9] function select +#define P_DMC_DRAM_DFI_SWAP_19 ((volatile uint32_t *)0xfd0206cc) +//bit 5:0. dfi_a[10] function select +#define P_DMC_DRAM_DFI_SWAP_20 ((volatile uint32_t *)0xfd0206d0) +//bit 5:0. dfi_a[11] function select +#define P_DMC_DRAM_DFI_SWAP_21 ((volatile uint32_t *)0xfd0206d4) +//bit 5:0. dfi_a[12] function select +#define P_DMC_DRAM_DFI_SWAP_22 ((volatile uint32_t *)0xfd0206d8) +//bit 5:0. dfi_a[13] function select +#define P_DMC_DRAM_DFI_SWAP_23 ((volatile uint32_t *)0xfd0206dc) +//bit 5:0. dfi_a[14] function select +#define P_DMC_DRAM_DFI_SWAP_24 ((volatile uint32_t *)0xfd0206e0) +//bit 5:0. dfi_a[15] function select +#define P_DMC_DRAM_DFI_SWAP_25 ((volatile uint32_t *)0xfd0206e4) +//bit 5:0. dfi_a[16] function select +#define P_DMC_DRAM_DFI_SWAP_26 ((volatile uint32_t *)0xfd0206ec) +//bit 5:0. dfi_a[17] function select +// +// Closing file: ../mmc_lp4/dmc/rtl/dmc_siu_reg.vh +// +// +// Reading file: ../mmc_lp4/dmc/rtl/dmc_sticky_reg.vh +// +//`ifdef DMC_STICKY_REG_DEFINE +//`else +//`define DMC_STICKY_REG_DEFINE +// ----------------------------------------------- +// APB_BASE: APB1_BASE_ADDR = 0xfd020800 +// ----------------------------------------------- +//`define DMC_STICKY_REG_BASE 32'hfd020800 +//those register is for software save some tempary value. and because it's in RAM. it won't lose if DMC get reseted. +#define P_DMC_STICKY_0 ((volatile uint32_t *)0xfd020800) +#define P_DMC_STICKY_1 ((volatile uint32_t *)0xfd020804) +#define P_DMC_STICKY_2 ((volatile uint32_t *)0xfd020808) +#define P_DMC_STICKY_3 ((volatile uint32_t *)0xfd02080c) +#define P_DMC_STICKY_4 ((volatile uint32_t *)0xfd020810) +#define P_DMC_STICKY_5 ((volatile uint32_t *)0xfd020814) +#define P_DMC_STICKY_6 ((volatile uint32_t *)0xfd020818) +#define P_DMC_STICKY_7 ((volatile uint32_t *)0xfd02081c) +#define P_DMC_STICKY_8 ((volatile uint32_t *)0xfd020820) +#define P_DMC_STICKY_9 ((volatile uint32_t *)0xfd020824) +#define P_DMC_STICKY_10 ((volatile uint32_t *)0xfd020828) +#define P_DMC_STICKY_11 ((volatile uint32_t *)0xfd02082c) +#define P_DMC_STICKY_12 ((volatile uint32_t *)0xfd020830) +#define P_DMC_STICKY_13 ((volatile uint32_t *)0xfd020834) +#define P_DMC_STICKY_14 ((volatile uint32_t *)0xfd020838) +#define P_DMC_STICKY_15 ((volatile uint32_t *)0xfd02083c) +#define P_DMC_STICKY_16 ((volatile uint32_t *)0xfd020840) +#define P_DMC_STICKY_17 ((volatile uint32_t *)0xfd020844) +#define P_DMC_STICKY_18 ((volatile uint32_t *)0xfd020848) +#define P_DMC_STICKY_19 ((volatile uint32_t *)0xfd02084c) +#define P_DMC_STICKY_20 ((volatile uint32_t *)0xfd020850) +#define P_DMC_STICKY_21 ((volatile uint32_t *)0xfd020854) +#define P_DMC_STICKY_22 ((volatile uint32_t *)0xfd020858) +#define P_DMC_STICKY_23 ((volatile uint32_t *)0xfd02085c) +#define P_DMC_STICKY_24 ((volatile uint32_t *)0xfd020860) +#define P_DMC_STICKY_25 ((volatile uint32_t *)0xfd020864) +#define P_DMC_STICKY_26 ((volatile uint32_t *)0xfd020868) +#define P_DMC_STICKY_27 ((volatile uint32_t *)0xfd02086c) +#define P_DMC_STICKY_28 ((volatile uint32_t *)0xfd020870) +#define P_DMC_STICKY_29 ((volatile uint32_t *)0xfd020874) +#define P_DMC_STICKY_30 ((volatile uint32_t *)0xfd020878) +#define P_DMC_STICKY_31 ((volatile uint32_t *)0xfd02087c) +#define P_DMC_STICKY_32 ((volatile uint32_t *)0xfd020880) +#define P_DMC_STICKY_33 ((volatile uint32_t *)0xfd020884) +#define P_DMC_STICKY_34 ((volatile uint32_t *)0xfd020888) +#define P_DMC_STICKY_35 ((volatile uint32_t *)0xfd02088c) +#define P_DMC_STICKY_36 ((volatile uint32_t *)0xfd020890) +#define P_DMC_STICKY_37 ((volatile uint32_t *)0xfd020894) +#define P_DMC_STICKY_38 ((volatile uint32_t *)0xfd020898) +#define P_DMC_STICKY_39 ((volatile uint32_t *)0xfd02089c) +#define P_DMC_STICKY_40 ((volatile uint32_t *)0xfd0208a0) +#define P_DMC_STICKY_41 ((volatile uint32_t *)0xfd0208a4) +#define P_DMC_STICKY_42 ((volatile uint32_t *)0xfd0208a8) +#define P_DMC_STICKY_43 ((volatile uint32_t *)0xfd0208ac) +#define P_DMC_STICKY_44 ((volatile uint32_t *)0xfd0208b0) +#define P_DMC_STICKY_45 ((volatile uint32_t *)0xfd0208b4) +#define P_DMC_STICKY_46 ((volatile uint32_t *)0xfd0208b8) +#define P_DMC_STICKY_47 ((volatile uint32_t *)0xfd0208bc) +#define P_DMC_STICKY_48 ((volatile uint32_t *)0xfd0208c0) +#define P_DMC_STICKY_49 ((volatile uint32_t *)0xfd0208c4) +#define P_DMC_STICKY_50 ((volatile uint32_t *)0xfd0208c8) +#define P_DMC_STICKY_51 ((volatile uint32_t *)0xfd0208cc) +#define P_DMC_STICKY_52 ((volatile uint32_t *)0xfd0208d0) +#define P_DMC_STICKY_53 ((volatile uint32_t *)0xfd0208d4) +#define P_DMC_STICKY_54 ((volatile uint32_t *)0xfd0208d8) +#define P_DMC_STICKY_55 ((volatile uint32_t *)0xfd0208dc) +#define P_DMC_STICKY_56 ((volatile uint32_t *)0xfd0208e0) +#define P_DMC_STICKY_57 ((volatile uint32_t *)0xfd0208e4) +#define P_DMC_STICKY_58 ((volatile uint32_t *)0xfd0208e8) +#define P_DMC_STICKY_59 ((volatile uint32_t *)0xfd0208ec) +#define P_DMC_STICKY_60 ((volatile uint32_t *)0xfd0208f0) +#define P_DMC_STICKY_61 ((volatile uint32_t *)0xfd0208f4) +#define P_DMC_STICKY_62 ((volatile uint32_t *)0xfd0208f8) +#define P_DMC_STICKY_63 ((volatile uint32_t *)0xfd0208fc) +//`endif +// +// Closing file: ../mmc_lp4/dmc/rtl/dmc_sticky_reg.vh +// +//======================================================================== +// APB0_RESET_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe000000 +// ----------------------------------------------- +#define P_RESETCTRL_RESET0 ((volatile uint32_t *)0xfe000000) +#define P_RESETCTRL_RESET1 ((volatile uint32_t *)0xfe000004) +#define P_RESETCTRL_RESET2 ((volatile uint32_t *)0xfe000008) +#define P_RESETCTRL_RESET0_LEVEL ((volatile uint32_t *)0xfe000040) +#define P_RESETCTRL_RESET1_LEVEL ((volatile uint32_t *)0xfe000044) +#define P_RESETCTRL_RESET2_LEVEL ((volatile uint32_t *)0xfe000048) +#define P_RESETCTRL_RESET0_MASK ((volatile uint32_t *)0xfe000080) +#define P_RESETCTRL_RESET1_MASK ((volatile uint32_t *)0xfe000084) +#define P_RESETCTRL_RESET2_MASK ((volatile uint32_t *)0xfe000088) +#define P_RESETCTRL_RESET_HOLD_CYC ((volatile uint32_t *)0xfe0000c0) +#define P_RESETCTRL_WATCHDOG_CTRL0 ((volatile uint32_t *)0xfe000100) +#define P_RESETCTRL_WATCHDOG_CTRL1 ((volatile uint32_t *)0xfe000104) +#define P_RESETCTRL_WATCHDOG_CNT ((volatile uint32_t *)0xfe000108) +#define P_RESETCTRL_WATCHDOG_CLR ((volatile uint32_t *)0xfe00010c) +#define P_RESETCTRL_SEC_RESET0 ((volatile uint32_t *)0xfe000140) +#define P_RESETCTRL_SEC_RESET0_LEVEL ((volatile uint32_t *)0xfe000144) +#define P_RESETCTRL_SEC_RESET0_MASK ((volatile uint32_t *)0xfe000148) +//======================================================================== +// APB0_PAD_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe000400 +// ----------------------------------------------- +#define P_PADCTRL_PIN_MUX_REG0 ((volatile uint32_t *)0xfe000400) +#define P_PADCTRL_PIN_MUX_REG1 ((volatile uint32_t *)0xfe000404) +#define P_PADCTRL_PIN_MUX_REG2 ((volatile uint32_t *)0xfe000408) +#define P_PADCTRL_PIN_MUX_REG3 ((volatile uint32_t *)0xfe00040c) +#define P_PADCTRL_PIN_MUX_REG4 ((volatile uint32_t *)0xfe000410) +#define P_PADCTRL_PIN_MUX_REG5 ((volatile uint32_t *)0xfe000414) +#define P_PADCTRL_PIN_MUX_REG6 ((volatile uint32_t *)0xfe000418) +#define P_PADCTRL_PIN_MUX_REG7 ((volatile uint32_t *)0xfe00041c) +#define P_PADCTRL_PIN_MUX_REG8 ((volatile uint32_t *)0xfe000420) +#define P_PADCTRL_PIN_MUX_REG9 ((volatile uint32_t *)0xfe000424) +#define P_PADCTRL_PIN_MUX_REGA ((volatile uint32_t *)0xfe000428) +#define P_PADCTRL_PIN_MUX_REGB ((volatile uint32_t *)0xfe00042c) +#define P_PADCTRL_PIN_MUX_REGC ((volatile uint32_t *)0xfe000430) +#define P_PADCTRL_PIN_MUX_REGD ((volatile uint32_t *)0xfe000434) +#define P_PADCTRL_PIN_MUX_REGE ((volatile uint32_t *)0xfe000438) +#define P_PADCTRL_PIN_MUX_REGF ((volatile uint32_t *)0xfe00043c) +#define P_PADCTRL_GPIO_IRQ_CTRL0 ((volatile uint32_t *)0xfe000440) +#define P_PADCTRL_GPIO_IRQ_CTRL1 ((volatile uint32_t *)0xfe000444) +#define P_PADCTRL_GPIO_IRQ_CTRL2 ((volatile uint32_t *)0xfe000448) +#define P_PADCTRL_GPIO_IRQ_CTRL3 ((volatile uint32_t *)0xfe00044c) +#define P_PADCTRL_GPIO_IRQ_CTRL4 ((volatile uint32_t *)0xfe000450) +#define P_PADCTRL_WORLDSYNC_CTRL0 ((volatile uint32_t *)0xfe000460) +#define P_PADCTRL_GPIO_MSR_CTRL0 ((volatile uint32_t *)0xfe000464) +#define P_PADCTRL_GPIOP_I ((volatile uint32_t *)0xfe000480) +#define P_PADCTRL_GPIOP_O ((volatile uint32_t *)0xfe000484) +#define P_PADCTRL_GPIOP_OEN ((volatile uint32_t *)0xfe000488) +#define P_PADCTRL_GPIOP_PULL_EN ((volatile uint32_t *)0xfe00048c) +#define P_PADCTRL_GPIOP_PULL_UP ((volatile uint32_t *)0xfe000490) +#define P_PADCTRL_GPIOP_DS ((volatile uint32_t *)0xfe000494) +#define P_PADCTRL_GPIOB_I ((volatile uint32_t *)0xfe0004c0) +#define P_PADCTRL_GPIOB_O ((volatile uint32_t *)0xfe0004c4) +#define P_PADCTRL_GPIOB_OEN ((volatile uint32_t *)0xfe0004c8) +#define P_PADCTRL_GPIOB_PULL_EN ((volatile uint32_t *)0xfe0004cc) +#define P_PADCTRL_GPIOB_PULL_UP ((volatile uint32_t *)0xfe0004d0) +#define P_PADCTRL_GPIOB_DS ((volatile uint32_t *)0xfe0004d4) +#define P_PADCTRL_GPIOX_I ((volatile uint32_t *)0xfe000500) +#define P_PADCTRL_GPIOX_O ((volatile uint32_t *)0xfe000504) +#define P_PADCTRL_GPIOX_OEN ((volatile uint32_t *)0xfe000508) +#define P_PADCTRL_GPIOX_PULL_EN ((volatile uint32_t *)0xfe00050c) +#define P_PADCTRL_GPIOX_PULL_UP ((volatile uint32_t *)0xfe000510) +#define P_PADCTRL_GPIOX_DS ((volatile uint32_t *)0xfe000514) +#define P_PADCTRL_GPIOX_DS_EXT ((volatile uint32_t *)0xfe000518) +#define P_PADCTRL_GPIOF_I ((volatile uint32_t *)0xfe000540) +#define P_PADCTRL_GPIOF_O ((volatile uint32_t *)0xfe000544) +#define P_PADCTRL_GPIOF_OEN ((volatile uint32_t *)0xfe000548) +#define P_PADCTRL_GPIOF_PULL_EN ((volatile uint32_t *)0xfe00054c) +#define P_PADCTRL_GPIOF_PULL_UP ((volatile uint32_t *)0xfe000550) +#define P_PADCTRL_GPIOF_DS ((volatile uint32_t *)0xfe000554) +#define P_PADCTRL_GPIOA_I ((volatile uint32_t *)0xfe000580) +#define P_PADCTRL_GPIOA_O ((volatile uint32_t *)0xfe000584) +#define P_PADCTRL_GPIOA_OEN ((volatile uint32_t *)0xfe000588) +#define P_PADCTRL_GPIOA_PULL_EN ((volatile uint32_t *)0xfe00058c) +#define P_PADCTRL_GPIOA_PULL_UP ((volatile uint32_t *)0xfe000590) +#define P_PADCTRL_GPIOA_DS ((volatile uint32_t *)0xfe000594) +#define P_PADCTRL_TESTN_I ((volatile uint32_t *)0xfe0005c0) +#define P_PADCTRL_TESTN_O ((volatile uint32_t *)0xfe0005c4) +#define P_PADCTRL_TESTN_OEN ((volatile uint32_t *)0xfe0005c8) +#define P_PADCTRL_TESTN_PULL_EN ((volatile uint32_t *)0xfe0005cc) +#define P_PADCTRL_TESTN_PULL_UP ((volatile uint32_t *)0xfe0005d0) +#define P_PADCTRL_TESTN_DS ((volatile uint32_t *)0xfe0005d4) +#define P_PADCTRL_MUTE_CTRL ((volatile uint32_t *)0xfe000600) +//======================================================================== +// APB0_CLK_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe000800 +// ----------------------------------------------- +#define P_CLKTREE_SYS_OSCIN_CTRL ((volatile uint32_t *)0xfe000800) +#define P_CLKTREE_RTC_BY_OSCIN_CTRL0 ((volatile uint32_t *)0xfe000804) +#define P_CLKTREE_RTC_BY_OSCIN_CTRL1 ((volatile uint32_t *)0xfe000808) +#define P_CLKTREE_RTC_CTRL ((volatile uint32_t *)0xfe00080c) +#define P_CLKTREE_SYS_CLK_CTRL0 ((volatile uint32_t *)0xfe000810) +#define P_CLKTREE_AXI_CLK_CTRL0 ((volatile uint32_t *)0xfe000814) +#define P_CLKTREE_SYS_CLK_EN0 ((volatile uint32_t *)0xfe00081c) +#define P_CLKTREE_SYS_CLK_EN1 ((volatile uint32_t *)0xfe000820) +#define P_CLKTREE_AXI_CLK_EN ((volatile uint32_t *)0xfe000824) +#define P_CLKTREE_DSPA_CLK_EN ((volatile uint32_t *)0xfe000828) +#define P_CLKTREE_DSPB_CLK_EN ((volatile uint32_t *)0xfe00082c) +#define P_CLKTREE_DSPA_CLK_CTRL0 ((volatile uint32_t *)0xfe000830) +#define P_CLKTREE_DSPB_CLK_CTRL0 ((volatile uint32_t *)0xfe000834) +#define P_CLKTREE_CLK12_24_CTRL ((volatile uint32_t *)0xfe000838) +#define P_CLKTREE_GEN_CLK_CTRL ((volatile uint32_t *)0xfe00083c) +#define P_CLKTREE_TIMESTAMP_CTRL0 ((volatile uint32_t *)0xfe000840) +#define P_CLKTREE_TIMESTAMP_CTRL1 ((volatile uint32_t *)0xfe000844) +#define P_CLKTREE_TIMESTAMP_CTRL2 ((volatile uint32_t *)0xfe000848) +#define P_CLKTREE_TIMESTAMP_VAL0 ((volatile uint32_t *)0xfe00084c) +#define P_CLKTREE_TIMESTAMP_VAL1 ((volatile uint32_t *)0xfe000850) +#define P_CLKTREE_TIMEBASE_CTRL0 ((volatile uint32_t *)0xfe000854) +#define P_CLKTREE_TIMEBASE_CTRL1 ((volatile uint32_t *)0xfe000858) +#define P_CLKTREE_SAR_ADC_CLK_CTRL ((volatile uint32_t *)0xfe0008c0) +#define P_CLKTREE_PWM_CLK_AB_CTRL ((volatile uint32_t *)0xfe0008c4) +#define P_CLKTREE_PWM_CLK_CD_CTRL ((volatile uint32_t *)0xfe0008c8) +#define P_CLKTREE_PWM_CLK_EF_CTRL ((volatile uint32_t *)0xfe0008cc) +#define P_CLKTREE_SPICC_CLK_CTRL ((volatile uint32_t *)0xfe0008d0) +#define P_CLKTREE_TS_CLK_CTRL ((volatile uint32_t *)0xfe0008d4) +#define P_CLKTREE_SPIFC_CLK_CTRL ((volatile uint32_t *)0xfe0008d8) +#define P_CLKTREE_USB_BUSCLK_CTRL ((volatile uint32_t *)0xfe0008dc) +#define P_CLKTREE_SD_EMMC_CLK_CTRL ((volatile uint32_t *)0xfe0008e0) +#define P_CLKTREE_CECA_CLK_CTRL0 ((volatile uint32_t *)0xfe0008e4) +#define P_CLKTREE_CECA_CLK_CTRL1 ((volatile uint32_t *)0xfe0008e8) +#define P_CLKTREE_CECB_CLK_CTRL0 ((volatile uint32_t *)0xfe0008ec) +#define P_CLKTREE_CECB_CLK_CTRL1 ((volatile uint32_t *)0xfe0008f0) +#define P_CLKTREE_PSRAM_CLK_CTRL ((volatile uint32_t *)0xfe0008f4) +#define P_CLKTREE_DMC_CLK_CTRL ((volatile uint32_t *)0xfe0008f8) +#define P_CLKTREE_FCLK_DIV1_SEL ((volatile uint32_t *)0xfe0008fc) +#define P_CLKTREE_TST_CTRL0 ((volatile uint32_t *)0xfe000900) +//======================================================================== +// APB0_CEC - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe000c00 +// ----------------------------------------------- +#define P_CECA_GEN_CNTL ((volatile uint32_t *)0xfe000c00) +#define P_CECA_RW_REG ((volatile uint32_t *)0xfe000c04) +#define P_CECA_INTR_MASKN ((volatile uint32_t *)0xfe000c08) +#define P_CECA_INTR_CLR ((volatile uint32_t *)0xfe000c0c) +#define P_CECA_INTR_STAT ((volatile uint32_t *)0xfe000c10) +#define P_CECB_GEN_CNTL ((volatile uint32_t *)0xfe000c40) +#define P_CECB_RW_REG ((volatile uint32_t *)0xfe000c44) +#define P_CECB_INTR_MASKN ((volatile uint32_t *)0xfe000c48) +#define P_CECB_INTR_CLR ((volatile uint32_t *)0xfe000c4c) +#define P_CECB_INTR_STAT ((volatile uint32_t *)0xfe000c50) +//======================================================================== +// APB0_IR_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe001000 +// ----------------------------------------------- +#define P_IRCTRL_IR_DEC_LDR_ACTIVE ((volatile uint32_t *)0xfe001000) +#define P_IRCTRL_IR_DEC_LDR_IDLE ((volatile uint32_t *)0xfe001004) +#define P_IRCTRL_IR_DEC_LDR_REPEAT ((volatile uint32_t *)0xfe001008) +#define P_IRCTRL_IR_DEC_BIT_0 ((volatile uint32_t *)0xfe00100c) +#define P_IRCTRL_IR_DEC_REG0 ((volatile uint32_t *)0xfe001010) +#define P_IRCTRL_IR_DEC_FRAME ((volatile uint32_t *)0xfe001014) +#define P_IRCTRL_IR_DEC_STATUS ((volatile uint32_t *)0xfe001018) +#define P_IRCTRL_IR_DEC_REG1 ((volatile uint32_t *)0xfe00101c) +#define P_IRCTRL_MF_IR_DEC_LDR_ACTIVE ((volatile uint32_t *)0xfe001040) +#define P_IRCTRL_MF_IR_DEC_LDR_IDLE ((volatile uint32_t *)0xfe001044) +#define P_IRCTRL_MF_IR_DEC_LDR_REPEAT ((volatile uint32_t *)0xfe001048) +#define P_IRCTRL_MF_IR_DEC_BIT_0 ((volatile uint32_t *)0xfe00104c) +#define P_IRCTRL_MF_IR_DEC_REG0 ((volatile uint32_t *)0xfe001050) +#define P_IRCTRL_MF_IR_DEC_FRAME ((volatile uint32_t *)0xfe001054) +#define P_IRCTRL_MF_IR_DEC_STATUS ((volatile uint32_t *)0xfe001058) +#define P_IRCTRL_MF_IR_DEC_REG1 ((volatile uint32_t *)0xfe00105c) +#define P_IRCTRL_MF_IR_DEC_REG2 ((volatile uint32_t *)0xfe001060) +#define P_IRCTRL_MF_IR_DEC_DURATN2 ((volatile uint32_t *)0xfe001064) +#define P_IRCTRL_MF_IR_DEC_DURATN3 ((volatile uint32_t *)0xfe001068) +#define P_IRCTRL_MF_IR_DEC_FRAME1 ((volatile uint32_t *)0xfe00106c) +#define P_IRCTRL_MF_IR_DEC_STATUS1 ((volatile uint32_t *)0xfe001070) +#define P_IRCTRL_MF_IR_DEC_STATUS2 ((volatile uint32_t *)0xfe001074) +#define P_IRCTRL_MF_IR_DEC_REG3 ((volatile uint32_t *)0xfe001078) +#define P_IRCTRL_MF_IR_DEC_FRAME_RSV0 ((volatile uint32_t *)0xfe00107c) +#define P_IRCTRL_MF_IR_DEC_FRAME_RSV1 ((volatile uint32_t *)0xfe001080) +#define P_IRCTRL_MF_IR_DEC_FILTE ((volatile uint32_t *)0xfe001084) +#define P_IRCTRL_MF_IR_DEC_IRQ_CTL ((volatile uint32_t *)0xfe001088) +#define P_IRCTRL_MF_IR_DEC_FIFO_CTL ((volatile uint32_t *)0xfe00108c) +#define P_IRCTRL_MF_IR_DEC_WIDTH_NEW ((volatile uint32_t *)0xfe001090) +#define P_IRCTRL_MF_IR_DEC_REPEAT_DET ((volatile uint32_t *)0xfe001094) +#define P_IRCTRL_IR_DEC_DEMOD_CNTL0 ((volatile uint32_t *)0xfe0010c0) +#define P_IRCTRL_IR_DEC_DEMOD_CNTL1 ((volatile uint32_t *)0xfe0010c4) +#define P_IRCTRL_IR_DEC_DEMOD_IIR_THD ((volatile uint32_t *)0xfe0010c8) +#define P_IRCTRL_IR_DEC_DEMOD_THD0 ((volatile uint32_t *)0xfe0010cc) +#define P_IRCTRL_IR_DEC_DEMOD_THD1 ((volatile uint32_t *)0xfe0010d0) +#define P_IRCTRL_IR_DEC_DEMOD_SUM_CNT0 ((volatile uint32_t *)0xfe0010d4) +#define P_IRCTRL_IR_DEC_DEMOD_SUM_CNT1 ((volatile uint32_t *)0xfe0010d8) +#define P_IRCTRL_IR_DEC_DEMOD_CNT0 ((volatile uint32_t *)0xfe0010dc) +#define P_IRCTRL_IR_DEC_DEMOD_CNT1 ((volatile uint32_t *)0xfe0010e0) +#define P_IRCTRL_IR_BLASTER_ADDR0 ((volatile uint32_t *)0xfe00110c) +#define P_IRCTRL_IR_BLASTER_ADDR1 ((volatile uint32_t *)0xfe001110) +#define P_IRCTRL_IR_BLASTER_ADDR2 ((volatile uint32_t *)0xfe001114) +#define P_IRCTRL_IR_BLASTER_ADDR3 ((volatile uint32_t *)0xfe001118) +//======================================================================== +// APB0_I2C_M - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe001400 +// ----------------------------------------------- +#define P_I2C_M_A_CONTROL_REG ((volatile uint32_t *)0xfe001400) +#define P_I2C_M_A_SLAVE_ADDR ((volatile uint32_t *)0xfe001404) +#define P_I2C_M_A_TOKEN_LIST0 ((volatile uint32_t *)0xfe001408) +#define P_I2C_M_A_TOKEN_LIST1 ((volatile uint32_t *)0xfe00140c) +#define P_I2C_M_A_WDATA_REG0 ((volatile uint32_t *)0xfe001410) +#define P_I2C_M_A_WDATA_REG1 ((volatile uint32_t *)0xfe001414) +#define P_I2C_M_A_RDATA_REG0 ((volatile uint32_t *)0xfe001418) +#define P_I2C_M_A_RDATA_REG1 ((volatile uint32_t *)0xfe00141c) +#define P_I2C_M_A_TIMEOUT_TH ((volatile uint32_t *)0xfe001420) +//======================================================================== +// APB0_I2C_S - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe001800 +// ----------------------------------------------- +#define P_I2C_S_A_CONTROL_REG ((volatile uint32_t *)0xfe001800) +#define P_I2C_S_A_SEND_REG ((volatile uint32_t *)0xfe001804) +#define P_I2C_S_A_RECV_REG ((volatile uint32_t *)0xfe001808) +#define P_I2C_S_A_CNTL1_REG ((volatile uint32_t *)0xfe00180c) +//======================================================================== +// APB0_UART_A - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe001c00 +// ----------------------------------------------- +#define P_UART_A_WFIFO ((volatile uint32_t *)0xfe001c00) +#define P_UART_A_RFIFO ((volatile uint32_t *)0xfe001c04) +#define P_UART_A_CONTROL ((volatile uint32_t *)0xfe001c08) +#define P_UART_A_STATUS ((volatile uint32_t *)0xfe001c0c) +#define P_UART_A_MISC ((volatile uint32_t *)0xfe001c10) +#define P_UART_A_REG5 ((volatile uint32_t *)0xfe001c14) +//======================================================================== +// APB0_UART_B - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe002000 +// ----------------------------------------------- +#define P_UART_B_WFIFO ((volatile uint32_t *)0xfe002000) +#define P_UART_B_RFIFO ((volatile uint32_t *)0xfe002004) +#define P_UART_B_CONTROL ((volatile uint32_t *)0xfe002008) +#define P_UART_B_STATUS ((volatile uint32_t *)0xfe00200c) +#define P_UART_B_MISC ((volatile uint32_t *)0xfe002010) +#define P_UART_B_REG5 ((volatile uint32_t *)0xfe002014) +//======================================================================== +// APB0_PWM_AB - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe002400 +// ----------------------------------------------- +#define P_PWMAB_PWM_A ((volatile uint32_t *)0xfe002400) +#define P_PWMAB_PWM_B ((volatile uint32_t *)0xfe002404) +#define P_PWMAB_MISC_REG_AB ((volatile uint32_t *)0xfe002408) +#define P_PWMAB_DELTA_SIGMA_AB ((volatile uint32_t *)0xfe00240c) +#define P_PWMAB_TIME_AB ((volatile uint32_t *)0xfe002410) +#define P_PWMAB_A2 ((volatile uint32_t *)0xfe002414) +#define P_PWMAB_B2 ((volatile uint32_t *)0xfe002418) +#define P_PWMAB_BLINK_AB ((volatile uint32_t *)0xfe00241c) +#define P_PWMAB_LOCK_AB ((volatile uint32_t *)0xfe002420) +//======================================================================== +// APB0_PWM_CD - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe002800 +// ----------------------------------------------- +#define P_PWMCD_PWM_C ((volatile uint32_t *)0xfe002800) +#define P_PWMCD_PWM_D ((volatile uint32_t *)0xfe002804) +#define P_PWMCD_MISC_REG_CD ((volatile uint32_t *)0xfe002808) +#define P_PWMCD_DELTA_SIGMA_CD ((volatile uint32_t *)0xfe00280c) +#define P_PWMCD_TIME_CD ((volatile uint32_t *)0xfe002810) +#define P_PWMCD_C2 ((volatile uint32_t *)0xfe002814) +#define P_PWMCD_D2 ((volatile uint32_t *)0xfe002818) +#define P_PWMCD_BLINK_CD ((volatile uint32_t *)0xfe00281c) +#define P_PWMCD_LOCK_CD ((volatile uint32_t *)0xfe002820) +//======================================================================== +// APB0_SARADC - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe002c00 +// ----------------------------------------------- +#define P_SAR_ADC_REG0 ((volatile uint32_t *)0xfe002c00) +#define P_SAR_ADC_CHAN_LIST ((volatile uint32_t *)0xfe002c04) +#define P_SAR_ADC_AVG_CNTL ((volatile uint32_t *)0xfe002c08) +#define P_SAR_ADC_REG3 ((volatile uint32_t *)0xfe002c0c) +#define P_SAR_ADC_DELAY ((volatile uint32_t *)0xfe002c10) +#define P_SAR_ADC_LAST_RD ((volatile uint32_t *)0xfe002c14) +#define P_SAR_ADC_FIFO_RD ((volatile uint32_t *)0xfe002c18) +#define P_SAR_ADC_AUX_SW ((volatile uint32_t *)0xfe002c1c) +#define P_SAR_ADC_CHAN_10_SW ((volatile uint32_t *)0xfe002c20) +#define P_SAR_ADC_DETECT_IDLE_SW ((volatile uint32_t *)0xfe002c24) +#define P_SAR_ADC_DELTA_10 ((volatile uint32_t *)0xfe002c28) +#define P_SAR_ADC_REG11 ((volatile uint32_t *)0xfe002c2c) +#define P_SAR_ADC_REG12 ((volatile uint32_t *)0xfe002c30) +#define P_SAR_ADC_REG13 ((volatile uint32_t *)0xfe002c34) +#define P_SAR_ADC_CHNL01 ((volatile uint32_t *)0xfe002c38) +#define P_SAR_ADC_CHNL23 ((volatile uint32_t *)0xfe002c3c) +#define P_SAR_ADC_CHNL45 ((volatile uint32_t *)0xfe002c40) +#define P_SAR_ADC_CHNL67 ((volatile uint32_t *)0xfe002c44) +//======================================================================== +// JTAGCTRL_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe003000 +// ----------------------------------------------- +#define P_JTAGCTRL_CTRL0 ((volatile uint32_t *)0xfe003000) +#define P_JTAGCTRL_PWD_CTRL0 ((volatile uint32_t *)0xfe003004) +#define P_JTAGCTRL_PWD_ADDR0 ((volatile uint32_t *)0xfe003008) +#define P_JTAGCTRL_PWD_ADDR1 ((volatile uint32_t *)0xfe00300c) +#define P_JTAGCTRL_PWD_ADDR2 ((volatile uint32_t *)0xfe003010) +#define P_JTAGCTRL_PWD_ADDR3 ((volatile uint32_t *)0xfe003014) +#define P_JTAGCTRL_PWD_VALUE0 ((volatile uint32_t *)0xfe003018) +#define P_JTAGCTRL_PWD_VALUE1 ((volatile uint32_t *)0xfe00301c) +#define P_JTAGCTRL_PWD_VALUE2 ((volatile uint32_t *)0xfe003020) +#define P_JTAGCTRL_PWD_VALUE3 ((volatile uint32_t *)0xfe003024) +#define P_JTAGCTRL_PWD_STS ((volatile uint32_t *)0xfe003028) +//======================================================================== +// APB0_MSR_CLK - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe003400 +// ----------------------------------------------- +#define P_MSR_CLK_REG0 ((volatile uint32_t *)0xfe003400) +#define P_MSR_CLK_REG1 ((volatile uint32_t *)0xfe003404) +#define P_MSR_CLK_REG2 ((volatile uint32_t *)0xfe003408) +#define P_MSR_CLK_REG3 ((volatile uint32_t *)0xfe00340c) +#define P_MSR_CLK_REG4 ((volatile uint32_t *)0xfe003410) +#define P_MSR_CLK_REG5 ((volatile uint32_t *)0xfe003414) +#define P_MSR_CLK_DUTY ((volatile uint32_t *)0xfe003418) +//======================================================================== +// APB0_SPICCA_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe003800 +// ----------------------------------------------- +#define P_SPICC_A_RXDATA ((volatile uint32_t *)0xfe003800) +#define P_SPICC_A_TXDATA ((volatile uint32_t *)0xfe003804) +#define P_SPICC_A_CONREG ((volatile uint32_t *)0xfe003808) +#define P_SPICC_A_INTREG ((volatile uint32_t *)0xfe00380c) +#define P_SPICC_A_DMAREG ((volatile uint32_t *)0xfe003810) +#define P_SPICC_A_STATREG ((volatile uint32_t *)0xfe003814) +#define P_SPICC_A_PERIODREG ((volatile uint32_t *)0xfe003818) +#define P_SPICC_A_TESTREG ((volatile uint32_t *)0xfe00381c) +#define P_SPICC_A_DRADDR ((volatile uint32_t *)0xfe003820) +#define P_SPICC_A_DWADDR ((volatile uint32_t *)0xfe003824) +#define P_SPICC_A_LD_CNTL0 ((volatile uint32_t *)0xfe003828) +#define P_SPICC_A_LD_CNTL1 ((volatile uint32_t *)0xfe00382c) +#define P_SPICC_A_LD_RADDR ((volatile uint32_t *)0xfe003830) +#define P_SPICC_A_LD_WADDR ((volatile uint32_t *)0xfe003834) +#define P_SPICC_A_ENHANCE_CNTL ((volatile uint32_t *)0xfe003838) +#define P_SPICC_A_ENHANCE_CNTL1 ((volatile uint32_t *)0xfe00383c) +#define P_SPICC_A_ENHANCE_CNTL2 ((volatile uint32_t *)0xfe003840) +//======================================================================== +// APB0_SPICCB_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe003c00 +// ----------------------------------------------- +#define P_SPICC_B_RXDATA ((volatile uint32_t *)0xfe003c00) +#define P_SPICC_B_TXDATA ((volatile uint32_t *)0xfe003c04) +#define P_SPICC_B_CONREG ((volatile uint32_t *)0xfe003c08) +#define P_SPICC_B_INTREG ((volatile uint32_t *)0xfe003c0c) +#define P_SPICC_B_DMAREG ((volatile uint32_t *)0xfe003c10) +#define P_SPICC_B_STATREG ((volatile uint32_t *)0xfe003c14) +#define P_SPICC_B_PERIODREG ((volatile uint32_t *)0xfe003c18) +#define P_SPICC_B_TESTREG ((volatile uint32_t *)0xfe003c1c) +#define P_SPICC_B_DRADDR ((volatile uint32_t *)0xfe003c20) +#define P_SPICC_B_DWADDR ((volatile uint32_t *)0xfe003c24) +#define P_SPICC_B_LD_CNTL0 ((volatile uint32_t *)0xfe003c28) +#define P_SPICC_B_LD_CNTL1 ((volatile uint32_t *)0xfe003c2c) +#define P_SPICC_B_LD_RADDR ((volatile uint32_t *)0xfe003c30) +#define P_SPICC_B_LD_WADDR ((volatile uint32_t *)0xfe003c34) +#define P_SPICC_B_ENHANCE_CNTL ((volatile uint32_t *)0xfe003c38) +#define P_SPICC_B_ENHANCE_CNTL1 ((volatile uint32_t *)0xfe003c3c) +#define P_SPICC_B_ENHANCE_CNTL2 ((volatile uint32_t *)0xfe003c40) +//======================================================================== +// USBCTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe004000 +// ----------------------------------------------- +#define P_USB_CTRL0 ((volatile uint32_t *)0xfe004000) +#define P_USB_CTRL1 ((volatile uint32_t *)0xfe004004) +#define P_USB_CTRL2 ((volatile uint32_t *)0xfe004008) +#define P_USB_CTRL3 ((volatile uint32_t *)0xfe00400c) +#define P_USB_CTRL4 ((volatile uint32_t *)0xfe004010) +#define P_USB_CTRL5 ((volatile uint32_t *)0xfe004014) +#define P_USB_CTRL6 ((volatile uint32_t *)0xfe004018) +#define P_USB_CTRL7 ((volatile uint32_t *)0xfe00401c) +#define P_USB_CTRL8 ((volatile uint32_t *)0xfe004020) +#define P_USB_CTRL9 ((volatile uint32_t *)0xfe004024) +#define P_USB_CTRL10 ((volatile uint32_t *)0xfe004028) +#define P_USB_CTRL11 ((volatile uint32_t *)0xfe00402c) +#define P_USB_CTRL12 ((volatile uint32_t *)0xfe004030) +#define P_USB_CTRL13 ((volatile uint32_t *)0xfe004034) +#define P_USB_CTRL14 ((volatile uint32_t *)0xfe004038) +#define P_USB_CTRL15 ((volatile uint32_t *)0xfe00403c) +#define P_USB_CTRL16 ((volatile uint32_t *)0xfe004040) +#define P_USB_CTRL17 ((volatile uint32_t *)0xfe004044) +#define P_USB_CTRL18 ((volatile uint32_t *)0xfe004048) +#define P_USB_CTRL19 ((volatile uint32_t *)0xfe00404c) +#define P_USB_CTRL20 ((volatile uint32_t *)0xfe004050) +#define P_USB_CTRL21 ((volatile uint32_t *)0xfe004054) +#define P_USB_CTRL22 ((volatile uint32_t *)0xfe004058) +#define P_USB_CTRL23 ((volatile uint32_t *)0xfe00405c) +#define P_USB_CTRL24 ((volatile uint32_t *)0xfe004060) +#define P_USB_CTRL25 ((volatile uint32_t *)0xfe004064) +#define P_USB_CTRL26 ((volatile uint32_t *)0xfe004068) +#define P_USB_CTRL27 ((volatile uint32_t *)0xfe00406c) +#define P_USB_CTRL28 ((volatile uint32_t *)0xfe004070) +#define P_USB_CTRL29 ((volatile uint32_t *)0xfe004074) +#define P_USB_CTRL30 ((volatile uint32_t *)0xfe004078) +#define P_USB_CTRL31 ((volatile uint32_t *)0xfe00407c) +//======================================================================== +// APB0_ACODEC_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe004800 +// ----------------------------------------------- +#define P_ACODEC_0 ((volatile uint32_t *)0xfe004800) +#define P_ACODEC_1 ((volatile uint32_t *)0xfe004804) +#define P_ACODEC_2 ((volatile uint32_t *)0xfe004808) +#define P_ACODEC_3 ((volatile uint32_t *)0xfe00480c) +#define P_ACODEC_4 ((volatile uint32_t *)0xfe004810) +#define P_ACODEC_5 ((volatile uint32_t *)0xfe004814) +#define P_ACODEC_6 ((volatile uint32_t *)0xfe004818) +#define P_ACODEC_7 ((volatile uint32_t *)0xfe00481c) +#define P_ACODEC_8 ((volatile uint32_t *)0xfe004820) +#define P_ACODEC_9 ((volatile uint32_t *)0xfe004824) +#define P_ACODEC_STS0 ((volatile uint32_t *)0xfe004840) +//======================================================================== +// APB0_TEMP_SENSOR - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe004c00 +// ----------------------------------------------- +#define P_TS_CFG_REG1 ((volatile uint32_t *)0xfe004c04) +#define P_TS_CFG_REG2 ((volatile uint32_t *)0xfe004c08) +#define P_TS_CFG_REG3 ((volatile uint32_t *)0xfe004c0c) +#define P_TS_CFG_REG4 ((volatile uint32_t *)0xfe004c10) +#define P_TS_CFG_REG5 ((volatile uint32_t *)0xfe004c14) +#define P_TS_CFG_REG6 ((volatile uint32_t *)0xfe004c18) +#define P_TS_CFG_REG7 ((volatile uint32_t *)0xfe004c1c) +#define P_TS_STAT0 ((volatile uint32_t *)0xfe004c40) +#define P_TS_STAT1 ((volatile uint32_t *)0xfe004c44) +#define P_TS_STAT2 ((volatile uint32_t *)0xfe004c48) +#define P_TS_STAT3 ((volatile uint32_t *)0xfe004c4c) +#define P_TS_STAT4 ((volatile uint32_t *)0xfe004c50) +#define P_TS_STAT5 ((volatile uint32_t *)0xfe004c54) +#define P_TS_STAT6 ((volatile uint32_t *)0xfe004c58) +#define P_TS_STAT7 ((volatile uint32_t *)0xfe004c5c) +#define P_TS_STAT8 ((volatile uint32_t *)0xfe004c60) +#define P_TS_STAT9 ((volatile uint32_t *)0xfe004c64) +//======================================================================== +// APB0_KL_EFUSE_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe005000 +// ----------------------------------------------- +// +// Reading file: ../crypto/crypto_reg.h +// +#define P_OTP_TEE_RDY ((volatile uint32_t *)0xfe005000) +#define P_OTP_TEE_CHK ((volatile uint32_t *)0xfe005004) +#define P_OTP_TEE_CFG ((volatile uint32_t *)0xfe005008) +#define P_OTP_TEE_WR_DAT0 ((volatile uint32_t *)0xfe005010) +#define P_OTP_TEE_WR_DAT1 ((volatile uint32_t *)0xfe005014) +#define P_OTP_TEE_WR_DAT2 ((volatile uint32_t *)0xfe005018) +#define P_OTP_TEE_WR_DAT3 ((volatile uint32_t *)0xfe00501c) +#define P_OTP_TEE_RD_DAT0 ((volatile uint32_t *)0xfe005020) +#define P_OTP_TEE_RD_DAT1 ((volatile uint32_t *)0xfe005024) +#define P_OTP_TEE_RD_DAT2 ((volatile uint32_t *)0xfe005028) +#define P_OTP_TEE_RD_DAT3 ((volatile uint32_t *)0xfe00502c) +#define P_OTP_RMA_PW0 ((volatile uint32_t *)0xfe005030) +#define P_OTP_RMA_PW1 ((volatile uint32_t *)0xfe005034) +#define P_OTP_RMA_PW2 ((volatile uint32_t *)0xfe005038) +#define P_OTP_RMA_PW3 ((volatile uint32_t *)0xfe00503c) +#define P_OTP_REE_RDY ((volatile uint32_t *)0xfe005040) +#define P_OTP_REE_CHK ((volatile uint32_t *)0xfe005044) +#define P_OTP_REE_CFG ((volatile uint32_t *)0xfe005048) +#define P_OTP_REE_RD_DAT0 ((volatile uint32_t *)0xfe005050) +#define P_OTP_REE_RD_DAT1 ((volatile uint32_t *)0xfe005054) +#define P_OTP_REE_RD_DAT2 ((volatile uint32_t *)0xfe005058) +#define P_OTP_REE_RD_DAT3 ((volatile uint32_t *)0xfe00505c) +#define P_OTP_LIC0 ((volatile uint32_t *)0xfe005060) +#define P_OTP_LIC1 ((volatile uint32_t *)0xfe005064) +#define P_OTP_LIC2 ((volatile uint32_t *)0xfe005068) +#define P_OTP_LIC3 ((volatile uint32_t *)0xfe00506c) +#define P_RNG_SEC_CONFIG_REG1 ((volatile uint32_t *)0xfe005104) +#define P_RNG_SEC_CONFIG_REG2 ((volatile uint32_t *)0xfe005108) +#define P_RNG_SEC_DATA ((volatile uint32_t *)0xfe005110) +#define P_RNG_SEC_STS ((volatile uint32_t *)0xfe005114) +#define P_RNG_USR_DATA ((volatile uint32_t *)0xfe005118) +#define P_RNG_USR_STS ((volatile uint32_t *)0xfe00511c) +#define P_KTE_SLOT0 ((volatile uint32_t *)0xfe005180) +#define P_KTE_SLOT1 ((volatile uint32_t *)0xfe005184) +#define P_KTE_SLOT2 ((volatile uint32_t *)0xfe005188) +#define P_KTE_SLOT3 ((volatile uint32_t *)0xfe00518c) +#define P_KTE_SLOT4 ((volatile uint32_t *)0xfe005190) +#define P_KTE_SLOT5 ((volatile uint32_t *)0xfe005194) +#define P_KTE_SLOT6 ((volatile uint32_t *)0xfe005198) +#define P_KTE_SLOT7 ((volatile uint32_t *)0xfe00519c) +#define P_MKL_TEE_RDY ((volatile uint32_t *)0xfe005200) +#define P_MKL_TEE_CHK ((volatile uint32_t *)0xfe005204) +#define P_MKL_TEE_CFG ((volatile uint32_t *)0xfe005208) +#define P_MKL_TEE_EK ((volatile uint32_t *)0xfe005210) +#define P_MKL_REE_RDY ((volatile uint32_t *)0xfe005280) +#define P_MKL_REE_CHK ((volatile uint32_t *)0xfe005284) +#define P_MKL_REE_CFG ((volatile uint32_t *)0xfe005288) +#define P_MKL_REE_EK ((volatile uint32_t *)0xfe005290) +// +// Closing file: ../crypto/crypto_reg.h +// +//======================================================================== +// APB0_PWM_EF - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe005400 +// ----------------------------------------------- +#define P_PWMEF_PWM_E ((volatile uint32_t *)0xfe005400) +#define P_PWMEF_PWM_F ((volatile uint32_t *)0xfe005404) +#define P_PWMEF_MISC_REG_EF ((volatile uint32_t *)0xfe005408) +#define P_PWMEF_DELTA_SIGMA_EF ((volatile uint32_t *)0xfe00540c) +#define P_PWMEF_TIME_EF ((volatile uint32_t *)0xfe005410) +#define P_PWMEF_E2 ((volatile uint32_t *)0xfe005414) +#define P_PWMEF_F2 ((volatile uint32_t *)0xfe005418) +#define P_PWMEF_BLINK_EF ((volatile uint32_t *)0xfe00541c) +#define P_PWMEF_LOCK_EF ((volatile uint32_t *)0xfe005420) +//======================================================================== +// APB0_SYS_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe005800 +// ----------------------------------------------- +#define P_SYSCTRL_METAL_REV0 ((volatile uint32_t *)0xfe005800) +#define P_SYSCTRL_METAL_REV1 ((volatile uint32_t *)0xfe005804) +//`define SYSCTRL_PROD_ENABLE 8'h0a +#define P_SYSCTRL_CHIP_ID ((volatile uint32_t *)0xfe00582c) +#define P_SYSCTRL_WRITEONCE1_REG0 ((volatile uint32_t *)0xfe005840) +#define P_SYSCTRL_WRITEONCE1_STICKY_REG0 ((volatile uint32_t *)0xfe005844) +#define P_SYSCTRL_WRITEONCE1_SEC_REG0 ((volatile uint32_t *)0xfe005848) +#define P_SYSCTRL_WRITEONCE1_STICKY_SEC_REG0 ((volatile uint32_t *)0xfe00584c) +#define P_SYSCTRL_WRITEONCE_REG0 ((volatile uint32_t *)0xfe005850) +#define P_SYSCTRL_WRITEONCE_REG1 ((volatile uint32_t *)0xfe005854) +#define P_SYSCTRL_WRITEONCE_SEC_REG0 ((volatile uint32_t *)0xfe005858) +#define P_SYSCTRL_WRITEONCE_STICKY_REG0 ((volatile uint32_t *)0xfe00585c) +#define P_SYSCTRL_WRITEONCE_STICKY_REG1 ((volatile uint32_t *)0xfe005860) +#define P_SYSCTRL_WRITEONCE_STICKY_SEC_REG0 ((volatile uint32_t *)0xfe005864) +#define P_SYSCTRL_TIMERA_CTRL ((volatile uint32_t *)0xfe0058c0) +#define P_SYSCTRL_TIMERA ((volatile uint32_t *)0xfe0058c4) +#define P_SYSCTRL_TIMERB_CTRL ((volatile uint32_t *)0xfe0058c8) +#define P_SYSCTRL_TIMERB ((volatile uint32_t *)0xfe0058cc) +#define P_SYSCTRL_TIMERC_CTRL ((volatile uint32_t *)0xfe0058d0) +#define P_SYSCTRL_TIMERC ((volatile uint32_t *)0xfe0058d4) +#define P_SYSCTRL_TIMERD_CTRL ((volatile uint32_t *)0xfe0058d8) +#define P_SYSCTRL_TIMERD ((volatile uint32_t *)0xfe0058dc) +#define P_SYSCTRL_SEC_TIMERA_CTRL ((volatile uint32_t *)0xfe0058e0) +#define P_SYSCTRL_SEC_TIMERA ((volatile uint32_t *)0xfe0058e4) +#define P_SYSCTRL_TIMERE_CTRL ((volatile uint32_t *)0xfe005900) +#define P_SYSCTRL_TIMERE ((volatile uint32_t *)0xfe005904) +#define P_SYSCTRL_TIMERE_HI ((volatile uint32_t *)0xfe005908) +#define P_SYSCTRL_TIMERF_CTRL ((volatile uint32_t *)0xfe00590c) +#define P_SYSCTRL_TIMERF ((volatile uint32_t *)0xfe005910) +#define P_SYSCTRL_TIMERF_HI ((volatile uint32_t *)0xfe005914) +#define P_SYSCTRL_SEC_TIMERE_CTRL ((volatile uint32_t *)0xfe005918) +#define P_SYSCTRL_SEC_TIMERE ((volatile uint32_t *)0xfe00591c) +#define P_SYSCTRL_SEC_TIMERE_HI ((volatile uint32_t *)0xfe005920) +#define P_SYSCTRL_OSC_RING_CTRL0 ((volatile uint32_t *)0xfe005940) +#define P_SYSCTRL_SEC_DDR_AXI_SEL ((volatile uint32_t *)0xfe005944) +#define P_SYSCTRL_AM2AXI_CTRL0 ((volatile uint32_t *)0xfe005948) +#define P_SYSCTRL_AM2AXI_STS ((volatile uint32_t *)0xfe00594c) +#define P_SYSCTRL_POC ((volatile uint32_t *)0xfe005980) +//`define SYSCTRL_PROD_PWD_VALUE0 8'h80 +//`define SYSCTRL_PROD_PWD_VALUE1 8'h81 +//`define SYSCTRL_PROD_PWD_VALUE2 8'h82 +//`define SYSCTRL_PROD_PWD_VALUE3 8'h83 +//`define SYSCTRL_PROD_STATUS 8'h84 +#define P_SYSCTRL_DEBUG_REG0 ((volatile uint32_t *)0xfe005a40) +#define P_SYSCTRL_DEBUG_REG1 ((volatile uint32_t *)0xfe005a44) +#define P_SYSCTRL_DEBUG_REG2 ((volatile uint32_t *)0xfe005a48) +#define P_SYSCTRL_DEBUG_REG3 ((volatile uint32_t *)0xfe005a4c) +#define P_SYSCTRL_DEBUG_REG4 ((volatile uint32_t *)0xfe005a50) +#define P_SYSCTRL_DEBUG_REG5 ((volatile uint32_t *)0xfe005a54) +#define P_SYSCTRL_DEBUG_REG6 ((volatile uint32_t *)0xfe005a58) +#define P_SYSCTRL_DEBUG_REG7 ((volatile uint32_t *)0xfe005a5c) +#define P_SYSCTRL_STATUS_REG0 ((volatile uint32_t *)0xfe005a80) +#define P_SYSCTRL_STATUS_REG1 ((volatile uint32_t *)0xfe005a84) +#define P_SYSCTRL_STATUS_REG2 ((volatile uint32_t *)0xfe005a88) +#define P_SYSCTRL_STATUS_REG3 ((volatile uint32_t *)0xfe005a8c) +#define P_SYSCTRL_STATUS_REG4 ((volatile uint32_t *)0xfe005a90) +#define P_SYSCTRL_STATUS_REG5 ((volatile uint32_t *)0xfe005a94) +#define P_SYSCTRL_STATUS_REG6 ((volatile uint32_t *)0xfe005a98) +#define P_SYSCTRL_STATUS_REG7 ((volatile uint32_t *)0xfe005a9c) +#define P_SYSCTRL_STICKY_REG0 ((volatile uint32_t *)0xfe005ac0) +#define P_SYSCTRL_STICKY_REG1 ((volatile uint32_t *)0xfe005ac4) +#define P_SYSCTRL_STICKY_REG2 ((volatile uint32_t *)0xfe005ac8) +#define P_SYSCTRL_STICKY_REG3 ((volatile uint32_t *)0xfe005acc) +#define P_SYSCTRL_STICKY_REG4 ((volatile uint32_t *)0xfe005ad0) +#define P_SYSCTRL_STICKY_REG5 ((volatile uint32_t *)0xfe005ad4) +#define P_SYSCTRL_STICKY_REG6 ((volatile uint32_t *)0xfe005ad8) +#define P_SYSCTRL_STICKY_REG7 ((volatile uint32_t *)0xfe005adc) +#define P_SYSCTRL_SEC_STATUS_REG0 ((volatile uint32_t *)0xfe005b00) +#define P_SYSCTRL_SEC_STATUS_REG1 ((volatile uint32_t *)0xfe005b04) +#define P_SYSCTRL_SEC_STATUS_REG2 ((volatile uint32_t *)0xfe005b08) +#define P_SYSCTRL_SEC_STATUS_REG3 ((volatile uint32_t *)0xfe005b0c) +#define P_SYSCTRL_SEC_STATUS_REG4 ((volatile uint32_t *)0xfe005b10) +#define P_SYSCTRL_SEC_STATUS_REG5 ((volatile uint32_t *)0xfe005b14) +#define P_SYSCTRL_SEC_STATUS_REG6 ((volatile uint32_t *)0xfe005b18) +#define P_SYSCTRL_SEC_STATUS_REG7 ((volatile uint32_t *)0xfe005b1c) +#define P_SYSCTRL_SEC_STATUS_REG8 ((volatile uint32_t *)0xfe005b20) +#define P_SYSCTRL_SEC_STATUS_REG9 ((volatile uint32_t *)0xfe005b24) +#define P_SYSCTRL_SEC_STATUS_REG10 ((volatile uint32_t *)0xfe005b28) +#define P_SYSCTRL_SEC_STATUS_REG11 ((volatile uint32_t *)0xfe005b2c) +#define P_SYSCTRL_SEC_STATUS_REG12 ((volatile uint32_t *)0xfe005b30) +#define P_SYSCTRL_SEC_STATUS_REG13 ((volatile uint32_t *)0xfe005b34) +#define P_SYSCTRL_SEC_STATUS_REG14 ((volatile uint32_t *)0xfe005b38) +#define P_SYSCTRL_SEC_STATUS_REG15 ((volatile uint32_t *)0xfe005b3c) +#define P_SYSCTRL_SEC_STATUS_REG16 ((volatile uint32_t *)0xfe005b40) +#define P_SYSCTRL_SEC_STATUS_REG17 ((volatile uint32_t *)0xfe005b44) +#define P_SYSCTRL_SEC_STATUS_REG18 ((volatile uint32_t *)0xfe005b48) +#define P_SYSCTRL_SEC_STATUS_REG19 ((volatile uint32_t *)0xfe005b4c) +#define P_SYSCTRL_SEC_STATUS_REG20 ((volatile uint32_t *)0xfe005b50) +#define P_SYSCTRL_SEC_STATUS_REG21 ((volatile uint32_t *)0xfe005b54) +#define P_SYSCTRL_SEC_STATUS_REG22 ((volatile uint32_t *)0xfe005b58) +#define P_SYSCTRL_SEC_STATUS_REG23 ((volatile uint32_t *)0xfe005b5c) +#define P_SYSCTRL_SEC_STICKY_REG0 ((volatile uint32_t *)0xfe005b80) +#define P_SYSCTRL_SEC_STICKY_REG1 ((volatile uint32_t *)0xfe005b84) +#define P_SYSCTRL_SEC_STICKY_REG2 ((volatile uint32_t *)0xfe005b88) +#define P_SYSCTRL_SEC_STICKY_REG3 ((volatile uint32_t *)0xfe005b8c) +#define P_SYSCTRL_SEC_STICKY_REG4 ((volatile uint32_t *)0xfe005b90) +#define P_SYSCTRL_SEC_STICKY_REG5 ((volatile uint32_t *)0xfe005b94) +#define P_SYSCTRL_SEC_STICKY_REG6 ((volatile uint32_t *)0xfe005b98) +#define P_SYSCTRL_SEC_STICKY_REG7 ((volatile uint32_t *)0xfe005b9c) +#define P_SYSCTRL_MSG_INDEX0_STICKY ((volatile uint32_t *)0xfe005bc0) +#define P_SYSCTRL_MSG_INDEX1_STICKY ((volatile uint32_t *)0xfe005bc4) +#define P_SYSCTRL_MSG_INDEX2_STICKY ((volatile uint32_t *)0xfe005bc8) +#define P_SYSCTRL_MSG_INDEX3_STICKY ((volatile uint32_t *)0xfe005bcc) +//======================================================================== +// APB0_I2C_M_B - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe005c00 +// ----------------------------------------------- +#define P_I2C_M_B_CONTROL_REG ((volatile uint32_t *)0xfe005c00) +#define P_I2C_M_B_SLAVE_ADDR ((volatile uint32_t *)0xfe005c04) +#define P_I2C_M_B_TOKEN_LIST0 ((volatile uint32_t *)0xfe005c08) +#define P_I2C_M_B_TOKEN_LIST1 ((volatile uint32_t *)0xfe005c0c) +#define P_I2C_M_B_WDATA_REG0 ((volatile uint32_t *)0xfe005c10) +#define P_I2C_M_B_WDATA_REG1 ((volatile uint32_t *)0xfe005c14) +#define P_I2C_M_B_RDATA_REG0 ((volatile uint32_t *)0xfe005c18) +#define P_I2C_M_B_RDATA_REG1 ((volatile uint32_t *)0xfe005c1c) +#define P_I2C_M_B_TIMEOUT_TH ((volatile uint32_t *)0xfe005c20) +//======================================================================== +// APB0_DMA - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe006000 +// ----------------------------------------------- +//TODO +//======================================================================== +// APB0_IRQ_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe006400 +// ----------------------------------------------- +#define P_IRQCTRL_IRQOUT_MASK0 ((volatile uint32_t *)0xfe006400) +#define P_IRQCTRL_IRQOUT_MASK1 ((volatile uint32_t *)0xfe006404) +#define P_IRQCTRL_IRQOUT_MASK2 ((volatile uint32_t *)0xfe006408) +#define P_IRQCTRL_IRQOUT_MASK3 ((volatile uint32_t *)0xfe00640c) +#define P_IRQCTRL_IRQOUT_INV0 ((volatile uint32_t *)0xfe006440) +#define P_IRQCTRL_IRQOUT_INV1 ((volatile uint32_t *)0xfe006444) +#define P_IRQCTRL_IRQOUT_INV2 ((volatile uint32_t *)0xfe006448) +#define P_IRQCTRL_IRQOUT_INV3 ((volatile uint32_t *)0xfe00644c) +//`define APB0_IRQIN_MASK0_CLK_USB 8'h00 +//`define APB0_IRQIN_MASK0_CLK_CPU 8'h01 +//`define APB0_IRQIN_MASK0_CLK_SYS 8'h02 +//`define APB0_IRQIN_MASK1_CLK_SYS 8'h03 +//`define APB0_IRQIN_MASK0_CLK_DSPA 8'h04 +//`define APB0_IRQIN_MASK0_CLK_DSPB 8'h05 +//`define APB0_IRQIN_CLRLVL_CLK_USB 8'h10 +//`define APB0_IRQIN_CLRLVL_CLK_DSPA 8'h11 +//`define APB0_IRQIN_CLRLVL_CLK_DSPB 8'h12 +//======================================================================== +// APB0_I2C_M - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe006800 +// ----------------------------------------------- +#define P_I2C_M_C_CONTROL_REG ((volatile uint32_t *)0xfe006800) +#define P_I2C_M_C_SLAVE_ADDR ((volatile uint32_t *)0xfe006804) +#define P_I2C_M_C_TOKEN_LIST0 ((volatile uint32_t *)0xfe006808) +#define P_I2C_M_C_TOKEN_LIST1 ((volatile uint32_t *)0xfe00680c) +#define P_I2C_M_C_WDATA_REG0 ((volatile uint32_t *)0xfe006810) +#define P_I2C_M_C_WDATA_REG1 ((volatile uint32_t *)0xfe006814) +#define P_I2C_M_C_RDATA_REG0 ((volatile uint32_t *)0xfe006818) +#define P_I2C_M_C_RDATA_REG1 ((volatile uint32_t *)0xfe00681c) +#define P_I2C_M_C_TIMEOUT_TH ((volatile uint32_t *)0xfe006820) +//======================================================================== +// APB0_I2C_M - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe006c00 +// ----------------------------------------------- +#define P_I2C_M_D_CONTROL_REG ((volatile uint32_t *)0xfe006c00) +#define P_I2C_M_D_SLAVE_ADDR ((volatile uint32_t *)0xfe006c04) +#define P_I2C_M_D_TOKEN_LIST0 ((volatile uint32_t *)0xfe006c08) +#define P_I2C_M_D_TOKEN_LIST1 ((volatile uint32_t *)0xfe006c0c) +#define P_I2C_M_D_WDATA_REG0 ((volatile uint32_t *)0xfe006c10) +#define P_I2C_M_D_WDATA_REG1 ((volatile uint32_t *)0xfe006c14) +#define P_I2C_M_D_RDATA_REG0 ((volatile uint32_t *)0xfe006c18) +#define P_I2C_M_D_RDATA_REG1 ((volatile uint32_t *)0xfe006c1c) +#define P_I2C_M_D_TIMEOUT_TH ((volatile uint32_t *)0xfe006c20) +//======================================================================== +// APB0_UART_C - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe007000 +// ----------------------------------------------- +#define P_UART_C_WFIFO ((volatile uint32_t *)0xfe007000) +#define P_UART_C_RFIFO ((volatile uint32_t *)0xfe007004) +#define P_UART_C_CONTROL ((volatile uint32_t *)0xfe007008) +#define P_UART_C_STATUS ((volatile uint32_t *)0xfe00700c) +#define P_UART_C_MISC ((volatile uint32_t *)0xfe007010) +#define P_UART_C_REG5 ((volatile uint32_t *)0xfe007014) +//======================================================================== +// APB0_PWR_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe007800 +// ----------------------------------------------- +#define P_PWRCTRL_PWR_ACK0 ((volatile uint32_t *)0xfe007800) +#define P_PWRCTRL_ISO_EN0 ((volatile uint32_t *)0xfe007804) +#define P_PWRCTRL_PWR_OFF0 ((volatile uint32_t *)0xfe007808) +#define P_PWRCTRL_SAVE_EN0 ((volatile uint32_t *)0xfe00780c) +#define P_PWRCTRL_RESTORE_EN0 ((volatile uint32_t *)0xfe007810) +#define P_PWRCTRL_MEM_PD0 ((volatile uint32_t *)0xfe007840) +#define P_PWRCTRL_MEM_PD1 ((volatile uint32_t *)0xfe007844) +#define P_PWRCTRL_MEM_PD2 ((volatile uint32_t *)0xfe007848) +#define P_PWRCTRL_MEM_PD3 ((volatile uint32_t *)0xfe00784c) +#define P_PWRCTRL_MEM_PD4 ((volatile uint32_t *)0xfe007850) +#define P_PWRCTRL_R_ISO_EN0 ((volatile uint32_t *)0xfe007880) +#define P_PWRCTRL_R_PWR_OFF0 ((volatile uint32_t *)0xfe007884) +#define P_PWRCTRL_R_MEM_PD0 ((volatile uint32_t *)0xfe007888) +#define P_PWRCTRL_R_MEM_PD1 ((volatile uint32_t *)0xfe00788c) +#define P_PWRCTRL_R_MEM_PD2 ((volatile uint32_t *)0xfe007890) +#define P_PWRCTRL_R_MEM_PD3 ((volatile uint32_t *)0xfe007894) +#define P_PWRCTRL_R_MEM_PD4 ((volatile uint32_t *)0xfe007898) +//`define PWRCTRL_MEM_PD_DSPA 8'h10 +//`define PWRCTRL_MEM_PD_DSPB 8'h11 +//`define PWRCTRL_MEM_PD_RAMA 8'h12 +//`define PWRCTRL_MEM_PD_RAMB 8'h13 +//`define PWRCTRL_MEM_PD_CPU 8'h14 +//`define PWRCTRL_MEM_PD_AUDIO 8'h20 +//`define PWRCTRL_MEM_PD_USBCTRL 8'h21 +//`define PWRCTRL_MEM_PD_SPICC 8'h22 +//`define PWRCTRL_MEM_PD_SPIFC 8'h23 +//`define PWRCTRL_MEM_PD_IR 8'h24 +//`define PWRCTRL_MEM_PD_SDIO 8'h25 +//`define PWRCTRL_MEM_PD_KLEFUSE 8'h26 +//`define PWRCTRL_MEM_PD_PSRAM 8'h27 +//`define PWRCTRL_MEM_PD_DDR 8'h28 +//`define PWRCTRL_MEM_PD_DMC 8'h29 +#define P_PWRCTRL_AUTO_OFF_CTRL ((volatile uint32_t *)0xfe0078c0) +#define P_PWRCTRL_AUTO_OFF ((volatile uint32_t *)0xfe0078c4) +#define P_PWRCTRL_AUTO_OFF_STS ((volatile uint32_t *)0xfe0078c8) +#define P_PWRCTRL_TIMER_TH_01 ((volatile uint32_t *)0xfe0078cc) +#define P_PWRCTRL_TIMER_TH_23 ((volatile uint32_t *)0xfe0078d0) +#define P_PWRCTRL_TIMER_TH_45 ((volatile uint32_t *)0xfe0078d4) +#define P_PWRCTRL_TIMER_TH_67 ((volatile uint32_t *)0xfe0078d8) +#define P_PWRCTRL_MASK_PWR_ACK0 ((volatile uint32_t *)0xfe007900) +#define P_PWRCTRL_MASK_RSTN_OFF0 ((volatile uint32_t *)0xfe007904) +#define P_PWRCTRL_MASK_RSTN_ON0 ((volatile uint32_t *)0xfe007908) +#define P_PWRCTRL_MASK_PWR_OFF0 ((volatile uint32_t *)0xfe00790c) +#define P_PWRCTRL_MASK_PWR_ON0 ((volatile uint32_t *)0xfe007910) +#define P_PWRCTRL_MASK_ISO_OFF0 ((volatile uint32_t *)0xfe007914) +#define P_PWRCTRL_MASK_ISO_ON0 ((volatile uint32_t *)0xfe007918) +#define P_PWRCTRL_MASK_MEM_OFF0 ((volatile uint32_t *)0xfe007940) +#define P_PWRCTRL_MASK_MEM_OFF1 ((volatile uint32_t *)0xfe007944) +#define P_PWRCTRL_MASK_MEM_OFF2 ((volatile uint32_t *)0xfe007948) +#define P_PWRCTRL_MASK_MEM_OFF3 ((volatile uint32_t *)0xfe00794c) +#define P_PWRCTRL_MASK_MEM_OFF4 ((volatile uint32_t *)0xfe007950) +#define P_PWRCTRL_MASK_MEM_ON0 ((volatile uint32_t *)0xfe007960) +#define P_PWRCTRL_MASK_MEM_ON1 ((volatile uint32_t *)0xfe007964) +#define P_PWRCTRL_MASK_MEM_ON2 ((volatile uint32_t *)0xfe007968) +#define P_PWRCTRL_MASK_MEM_ON3 ((volatile uint32_t *)0xfe00796c) +#define P_PWRCTRL_MASK_MEM_ON4 ((volatile uint32_t *)0xfe007970) +//======================================================================== +// APB0_ANA_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe007c00 +// ----------------------------------------------- +#define P_ANACTRL_FIXPLL_CTRL0 ((volatile uint32_t *)0xfe007c80) +#define P_ANACTRL_FIXPLL_CTRL1 ((volatile uint32_t *)0xfe007c84) +#define P_ANACTRL_FIXPLL_CTRL2 ((volatile uint32_t *)0xfe007c88) +#define P_ANACTRL_FIXPLL_CTRL3 ((volatile uint32_t *)0xfe007c8c) +#define P_ANACTRL_FIXPLL_CTRL4 ((volatile uint32_t *)0xfe007c90) +#define P_ANACTRL_FIXPLL_STS ((volatile uint32_t *)0xfe007c94) +#define P_ANACTRL_SYSPLL_CTRL0 ((volatile uint32_t *)0xfe007d00) +#define P_ANACTRL_SYSPLL_CTRL1 ((volatile uint32_t *)0xfe007d04) +#define P_ANACTRL_SYSPLL_CTRL2 ((volatile uint32_t *)0xfe007d08) +#define P_ANACTRL_SYSPLL_CTRL3 ((volatile uint32_t *)0xfe007d0c) +#define P_ANACTRL_SYSPLL_CTRL4 ((volatile uint32_t *)0xfe007d10) +#define P_ANACTRL_SYSPLL_STS ((volatile uint32_t *)0xfe007d14) +#define P_ANACTRL_HIFIPLL_CTRL0 ((volatile uint32_t *)0xfe007d40) +#define P_ANACTRL_HIFIPLL_CTRL1 ((volatile uint32_t *)0xfe007d44) +#define P_ANACTRL_HIFIPLL_CTRL2 ((volatile uint32_t *)0xfe007d48) +#define P_ANACTRL_HIFIPLL_CTRL3 ((volatile uint32_t *)0xfe007d4c) +#define P_ANACTRL_HIFIPLL_CTRL4 ((volatile uint32_t *)0xfe007d50) +#define P_ANACTRL_HIFIPLL_STS ((volatile uint32_t *)0xfe007d54) +#define P_ANACTRL_AUDDDS_CTRL0 ((volatile uint32_t *)0xfe007d80) +#define P_ANACTRL_AUDDDS_CTRL1 ((volatile uint32_t *)0xfe007d84) +#define P_ANACTRL_AUDDDS_CTRL2 ((volatile uint32_t *)0xfe007d88) +#define P_ANACTRL_AUDDDS_CTRL3 ((volatile uint32_t *)0xfe007d8c) +#define P_ANACTRL_AUDDDS_CTRL4 ((volatile uint32_t *)0xfe007d90) +#define P_ANACTRL_AUDDDS_STS ((volatile uint32_t *)0xfe007d94) +#define P_ANACTRL_MISCTOP_CTRL0 ((volatile uint32_t *)0xfe007dc0) +#define P_ANACTRL_POR_CNTL ((volatile uint32_t *)0xfe007e08) +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe020000 +// ----------------------------------------------- +#define P_RSA_BASE ((volatile uint32_t *)0xfe020000) +//======================================================================== +// CPUCTRL_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB1_BASE_ADDR = 0xfd000000 +// ----------------------------------------------- +#define P_CPUCTRL_CTRL0 ((volatile uint32_t *)0xfd000000) +#define P_CPUCTRL_CTRL1 ((volatile uint32_t *)0xfd000004) +#define P_CPUCTRL_CTRL2 ((volatile uint32_t *)0xfd000008) +#define P_CPUCTRL_CTRL3 ((volatile uint32_t *)0xfd00000c) +#define P_CPUCTRL_CTRL4 ((volatile uint32_t *)0xfd000010) +#define P_CPUCTRL_CTRL5 ((volatile uint32_t *)0xfd000014) +#define P_CPUCTRL_CTRL6 ((volatile uint32_t *)0xfd000018) +#define P_CPUCTRL_CTRL7 ((volatile uint32_t *)0xfd00001c) +#define P_CPUCTRL_CTRL8 ((volatile uint32_t *)0xfd000020) +#define P_CPUCTRL_CTRL9 ((volatile uint32_t *)0xfd000024) +#define P_CPUCTRL_CTRL10 ((volatile uint32_t *)0xfd000028) +#define P_CPUCTRL_CTRL11 ((volatile uint32_t *)0xfd00002c) +#define P_CPUCTRL_CTRL12 ((volatile uint32_t *)0xfd000030) +#define P_CPUCTRL_CTRL13 ((volatile uint32_t *)0xfd000034) +#define P_CPUCTRL_CTRL14 ((volatile uint32_t *)0xfd000038) +#define P_CPUCTRL_CTRL15 ((volatile uint32_t *)0xfd00003c) +#define P_CPUCTRL_STS0 ((volatile uint32_t *)0xfd000040) +#define P_CPUCTRL_STS1 ((volatile uint32_t *)0xfd000044) +#define P_CPUCTRL_STS2 ((volatile uint32_t *)0xfd000048) +#define P_CPUCTRL_STS3 ((volatile uint32_t *)0xfd00004c) +#define P_CPUCTRL_STS4 ((volatile uint32_t *)0xfd000050) +#define P_CPUCTRL_STS5 ((volatile uint32_t *)0xfd000054) +#define P_CPUCTRL_STS6 ((volatile uint32_t *)0xfd000058) +#define P_CPUCTRL_STS7 ((volatile uint32_t *)0xfd00005c) +#define P_CPUCTRL_STS8 ((volatile uint32_t *)0xfd000060) +#define P_CPUCTRL_STS9 ((volatile uint32_t *)0xfd000064) +#define P_CPUCTRL_CLK_CTRL0 ((volatile uint32_t *)0xfd000080) +#define P_CPUCTRL_CLK_CTRL1 ((volatile uint32_t *)0xfd000084) +#define P_CPUCTRL_CLK_CTRL2 ((volatile uint32_t *)0xfd000088) +#define P_CPUCTRL_CLK_CTRL3 ((volatile uint32_t *)0xfd00008c) +#define P_CPUCTRL_CLK_CTRL4 ((volatile uint32_t *)0xfd000090) +#define P_CPUCTRL_CLK_CTRL5 ((volatile uint32_t *)0xfd000094) +#define P_CPUCTRL_CLK_CTRL6 ((volatile uint32_t *)0xfd000098) +#define P_CPUCTRL_CLK_CTRL7 ((volatile uint32_t *)0xfd00009c) +#define P_CPUCTRL_RESET_CTRL ((volatile uint32_t *)0xfd0000c0) +#define P_CPUCTRL_ROM_DISABLE ((volatile uint32_t *)0xfd0000c4) +//======================================================================== +// RAMA_SEC_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB1_BASE_ADDR = 0xfd000800 +// ----------------------------------------------- +#define P_SRAM_RANGE0_STA ((volatile uint32_t *)0xfd000800) +#define P_SRAM_RANGE1_STA ((volatile uint32_t *)0xfd000804) +#define P_SRAM_RANGE2_STA ((volatile uint32_t *)0xfd000808) +#define P_SRAM_RANGE3_STA ((volatile uint32_t *)0xfd00080c) +#define P_SRAM_RANGE4_STA ((volatile uint32_t *)0xfd000810) +#define P_SRAM_RANGE5_STA ((volatile uint32_t *)0xfd000814) +#define P_SRAM_RANGE6_STA ((volatile uint32_t *)0xfd000818) +#define P_SRAM_RANGE0_EDA ((volatile uint32_t *)0xfd00081c) +#define P_SRAM_RANGE1_EDA ((volatile uint32_t *)0xfd000820) +#define P_SRAM_RANGE2_EDA ((volatile uint32_t *)0xfd000824) +#define P_SRAM_RANGE3_EDA ((volatile uint32_t *)0xfd000828) +#define P_SRAM_RANGE4_EDA ((volatile uint32_t *)0xfd00082c) +#define P_SRAM_RANGE5_EDA ((volatile uint32_t *)0xfd000830) +#define P_SRAM_RANGE6_EDA ((volatile uint32_t *)0xfd000834) +#define P_SRAM_RANGE0_CTRL0 ((volatile uint32_t *)0xfd000838) +#define P_SRAM_RANGE1_CTRL0 ((volatile uint32_t *)0xfd00083c) +#define P_SRAM_RANGE2_CTRL0 ((volatile uint32_t *)0xfd000840) +#define P_SRAM_RANGE3_CTRL0 ((volatile uint32_t *)0xfd000844) +#define P_SRAM_RANGE4_CTRL0 ((volatile uint32_t *)0xfd000848) +#define P_SRAM_RANGE5_CTRL0 ((volatile uint32_t *)0xfd00084c) +#define P_SRAM_RANGE6_CTRL0 ((volatile uint32_t *)0xfd000850) +#define P_SRAM_RANGE7_CTRL0 ((volatile uint32_t *)0xfd000854) +#define P_SRAM_RANGE0_CTRL1 ((volatile uint32_t *)0xfd000858) +#define P_SRAM_RANGE1_CTRL1 ((volatile uint32_t *)0xfd00085c) +#define P_SRAM_RANGE2_CTRL1 ((volatile uint32_t *)0xfd000860) +#define P_SRAM_RANGE3_CTRL1 ((volatile uint32_t *)0xfd000864) +#define P_SRAM_RANGE4_CTRL1 ((volatile uint32_t *)0xfd000868) +#define P_SRAM_RANGE5_CTRL1 ((volatile uint32_t *)0xfd00086c) +#define P_SRAM_RANGE6_CTRL1 ((volatile uint32_t *)0xfd000870) +#define P_SRAM_RANGE7_CTRL1 ((volatile uint32_t *)0xfd000874) +#define P_SRAM_SEC_CTRL0 ((volatile uint32_t *)0xfd000878) +#define P_SRAM_REG_LOCK ((volatile uint32_t *)0xfd00087c) +//======================================================================== +// RAMB_SEC_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB1_BASE_ADDR = 0xfd000c00 +// ----------------------------------------------- +#define P_SRAM_RANGE0_STA_B ((volatile uint32_t *)0xfd000c00) +#define P_SRAM_RANGE1_STA_B ((volatile uint32_t *)0xfd000c04) +#define P_SRAM_RANGE2_STA_B ((volatile uint32_t *)0xfd000c08) +#define P_SRAM_RANGE3_STA_B ((volatile uint32_t *)0xfd000c0c) +#define P_SRAM_RANGE4_STA_B ((volatile uint32_t *)0xfd000c10) +#define P_SRAM_RANGE5_STA_B ((volatile uint32_t *)0xfd000c14) +#define P_SRAM_RANGE6_STA_B ((volatile uint32_t *)0xfd000c18) +#define P_SRAM_RANGE0_EDA_B ((volatile uint32_t *)0xfd000c1c) +#define P_SRAM_RANGE1_EDA_B ((volatile uint32_t *)0xfd000c20) +#define P_SRAM_RANGE2_EDA_B ((volatile uint32_t *)0xfd000c24) +#define P_SRAM_RANGE3_EDA_B ((volatile uint32_t *)0xfd000c28) +#define P_SRAM_RANGE4_EDA_B ((volatile uint32_t *)0xfd000c2c) +#define P_SRAM_RANGE5_EDA_B ((volatile uint32_t *)0xfd000c30) +#define P_SRAM_RANGE6_EDA_B ((volatile uint32_t *)0xfd000c34) +#define P_SRAM_RANGE0_CTRL0_B ((volatile uint32_t *)0xfd000c38) +#define P_SRAM_RANGE1_CTRL0_B ((volatile uint32_t *)0xfd000c3c) +#define P_SRAM_RANGE2_CTRL0_B ((volatile uint32_t *)0xfd000c40) +#define P_SRAM_RANGE3_CTRL0_B ((volatile uint32_t *)0xfd000c44) +#define P_SRAM_RANGE4_CTRL0_B ((volatile uint32_t *)0xfd000c48) +#define P_SRAM_RANGE5_CTRL0_B ((volatile uint32_t *)0xfd000c4c) +#define P_SRAM_RANGE6_CTRL0_B ((volatile uint32_t *)0xfd000c50) +#define P_SRAM_RANGE7_CTRL0_B ((volatile uint32_t *)0xfd000c54) +#define P_SRAM_RANGE0_CTRL1_B ((volatile uint32_t *)0xfd000c58) +#define P_SRAM_RANGE1_CTRL1_B ((volatile uint32_t *)0xfd000c5c) +#define P_SRAM_RANGE2_CTRL1_B ((volatile uint32_t *)0xfd000c60) +#define P_SRAM_RANGE3_CTRL1_B ((volatile uint32_t *)0xfd000c64) +#define P_SRAM_RANGE4_CTRL1_B ((volatile uint32_t *)0xfd000c68) +#define P_SRAM_RANGE5_CTRL1_B ((volatile uint32_t *)0xfd000c6c) +#define P_SRAM_RANGE6_CTRL1_B ((volatile uint32_t *)0xfd000c70) +#define P_SRAM_RANGE7_CTRL1_B ((volatile uint32_t *)0xfd000c74) +#define P_SRAM_SEC_CTRL0_B ((volatile uint32_t *)0xfd000c78) +#define P_SRAM_REG_LOCK_B ((volatile uint32_t *)0xfd000c7c) +// +// Reading file: REG_LIST_DSP_RTL.h +// +// synopsys translate_off +// synopsys translate_on +//======================================================================== +// DSPA - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe030000 +// ----------------------------------------------- +#define P_DSP_CFG0 ((volatile uint32_t *)0xfe030000) +#define P_DSP_CFG1 ((volatile uint32_t *)0xfe030004) +#define P_DSP_CFG2 ((volatile uint32_t *)0xfe030008) +#define P_DSP_IMPWIRE ((volatile uint32_t *)0xfe03000c) +#define P_DSP_RESET_VEC ((volatile uint32_t *)0xfe030010) +#define P_DSP_SEC_CFG0 ((volatile uint32_t *)0xfe030018) +#define P_DSP_SEC_CFG1 ((volatile uint32_t *)0xfe03001c) +#define P_DSP_IRQ_CTRL0 ((volatile uint32_t *)0xfe030040) +#define P_DSP_IRQ_CTRL1 ((volatile uint32_t *)0xfe030044) +#define P_DSP_IRQ_CTRL2 ((volatile uint32_t *)0xfe030048) +#define P_DSP_IRQ_CTRL3 ((volatile uint32_t *)0xfe03004c) +#define P_DSP_IRQ_CTRL4 ((volatile uint32_t *)0xfe030050) +#define P_DSP_IRQ_CTRL5 ((volatile uint32_t *)0xfe030054) +#define P_DSP_IRQ_CTRL6 ((volatile uint32_t *)0xfe030058) +#define P_DSP_IRQ_CTRL7 ((volatile uint32_t *)0xfe03005c) +#define P_DSP_IRQ_CTRL8 ((volatile uint32_t *)0xfe030060) +#define P_DSP_IRQ_STS ((volatile uint32_t *)0xfe03007c) +#define P_DSP_REMAP0 ((volatile uint32_t *)0xfe030080) +#define P_DSP_REMAP1 ((volatile uint32_t *)0xfe030084) +#define P_DSP_REMAP2 ((volatile uint32_t *)0xfe030088) +#define P_DSP_STS0 ((volatile uint32_t *)0xfe030100) +#define P_DSP_STS1 ((volatile uint32_t *)0xfe030104) +#define P_DSP_STS2 ((volatile uint32_t *)0xfe030108) +#define P_DSP_STS3 ((volatile uint32_t *)0xfe03010c) +#define P_DSP_STS4 ((volatile uint32_t *)0xfe030110) +#define P_DSP_STS5 ((volatile uint32_t *)0xfe030114) +#define P_DSP_MAILBOX_SET_0 ((volatile uint32_t *)0xfe030140) +#define P_DSP_MAILBOX_SET_1 ((volatile uint32_t *)0xfe030144) +#define P_DSP_MAILBOX_SET_2 ((volatile uint32_t *)0xfe030148) +#define P_DSP_MAILBOX_SET_3 ((volatile uint32_t *)0xfe03014c) +#define P_DSP_MAILBOX_SET_4 ((volatile uint32_t *)0xfe030150) +#define P_DSP_MAILBOX_SET_5 ((volatile uint32_t *)0xfe030154) +#define P_DSP_MAILBOX_SET_6 ((volatile uint32_t *)0xfe030158) +#define P_DSP_MAILBOX_SET_7 ((volatile uint32_t *)0xfe03015c) +#define P_DSP_MAILBOX_SET_8 ((volatile uint32_t *)0xfe030160) +#define P_DSP_MAILBOX_SET_9 ((volatile uint32_t *)0xfe030164) +#define P_DSP_MAILBOX_SET_10 ((volatile uint32_t *)0xfe030168) +#define P_DSP_MAILBOX_SET_11 ((volatile uint32_t *)0xfe03016c) +#define P_DSP_MAILBOX_CLR_0 ((volatile uint32_t *)0xfe030180) +#define P_DSP_MAILBOX_CLR_1 ((volatile uint32_t *)0xfe030184) +#define P_DSP_MAILBOX_CLR_2 ((volatile uint32_t *)0xfe030188) +#define P_DSP_MAILBOX_CLR_3 ((volatile uint32_t *)0xfe03018c) +#define P_DSP_MAILBOX_CLR_4 ((volatile uint32_t *)0xfe030190) +#define P_DSP_MAILBOX_CLR_5 ((volatile uint32_t *)0xfe030194) +#define P_DSP_MAILBOX_CLR_6 ((volatile uint32_t *)0xfe030198) +#define P_DSP_MAILBOX_CLR_7 ((volatile uint32_t *)0xfe03019c) +#define P_DSP_MAILBOX_CLR_8 ((volatile uint32_t *)0xfe0301a0) +#define P_DSP_MAILBOX_CLR_9 ((volatile uint32_t *)0xfe0301a4) +#define P_DSP_MAILBOX_CLR_10 ((volatile uint32_t *)0xfe0301a8) +#define P_DSP_MAILBOX_CLR_11 ((volatile uint32_t *)0xfe0301ac) +#define P_DSP_MAILBOX_STAT_0 ((volatile uint32_t *)0xfe0301c0) +#define P_DSP_MAILBOX_STAT_1 ((volatile uint32_t *)0xfe0301c4) +#define P_DSP_MAILBOX_STAT_2 ((volatile uint32_t *)0xfe0301c8) +#define P_DSP_MAILBOX_STAT_3 ((volatile uint32_t *)0xfe0301cc) +#define P_DSP_MAILBOX_STAT_4 ((volatile uint32_t *)0xfe0301d0) +#define P_DSP_MAILBOX_STAT_5 ((volatile uint32_t *)0xfe0301d4) +#define P_DSP_MAILBOX_STAT_6 ((volatile uint32_t *)0xfe0301d8) +#define P_DSP_MAILBOX_STAT_7 ((volatile uint32_t *)0xfe0301dc) +#define P_DSP_MAILBOX_STAT_8 ((volatile uint32_t *)0xfe0301e0) +#define P_DSP_MAILBOX_STAT_9 ((volatile uint32_t *)0xfe0301e4) +#define P_DSP_MAILBOX_STAT_10 ((volatile uint32_t *)0xfe0301e8) +#define P_DSP_MAILBOX_STAT_11 ((volatile uint32_t *)0xfe0301ec) +#define P_DSP_QIF_CTRL ((volatile uint32_t *)0xfe030200) +#define P_DSP_QIF_STS ((volatile uint32_t *)0xfe030204) +#define P_DSP_WRFIFO_TOCPUA ((volatile uint32_t *)0xfe030208) +#define P_DSP_WRFIFO_TOCPUB ((volatile uint32_t *)0xfe03020c) +#define P_DSP_WRFIFO_TODSP ((volatile uint32_t *)0xfe030210) +#define P_DSP_RDFIFO_FRCPUA ((volatile uint32_t *)0xfe030220) +#define P_DSP_RDFIFO_FRCPUB ((volatile uint32_t *)0xfe030224) +#define P_DSP_RDFIFO_FRDSP ((volatile uint32_t *)0xfe030228) +//======================================================================== +// DSPB - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe040000 +// ----------------------------------------------- +#define P_DSPB_CFG0 ((volatile uint32_t *)0xfe040000) +#define P_DSPB_CFG1 ((volatile uint32_t *)0xfe040004) +#define P_DSPB_CFG2 ((volatile uint32_t *)0xfe040008) +#define P_DSPB_IMPWIRE ((volatile uint32_t *)0xfe04000c) +#define P_DSPB_RESET_VEC ((volatile uint32_t *)0xfe040010) +#define P_DSPB_SEC_CFG0 ((volatile uint32_t *)0xfe040018) +#define P_DSPB_SEC_CFG1 ((volatile uint32_t *)0xfe04001c) +#define P_DSPB_IRQ_CTRL0 ((volatile uint32_t *)0xfe040040) +#define P_DSPB_IRQ_CTRL1 ((volatile uint32_t *)0xfe040044) +#define P_DSPB_IRQ_CTRL2 ((volatile uint32_t *)0xfe040048) +#define P_DSPB_IRQ_CTRL3 ((volatile uint32_t *)0xfe04004c) +#define P_DSPB_IRQ_CTRL4 ((volatile uint32_t *)0xfe040050) +#define P_DSPB_IRQ_CTRL5 ((volatile uint32_t *)0xfe040054) +#define P_DSPB_IRQ_CTRL6 ((volatile uint32_t *)0xfe040058) +#define P_DSPB_IRQ_CTRL7 ((volatile uint32_t *)0xfe04005c) +#define P_DSPB_IRQ_CTRL8 ((volatile uint32_t *)0xfe040060) +#define P_DSPB_IRQ_STS ((volatile uint32_t *)0xfe04007c) +#define P_DSPB_REMAP0 ((volatile uint32_t *)0xfe040080) +#define P_DSPB_REMAP1 ((volatile uint32_t *)0xfe040084) +#define P_DSPB_REMAP2 ((volatile uint32_t *)0xfe040088) +#define P_DSPB_STS0 ((volatile uint32_t *)0xfe040100) +#define P_DSPB_STS1 ((volatile uint32_t *)0xfe040104) +#define P_DSPB_STS2 ((volatile uint32_t *)0xfe040108) +#define P_DSPB_STS3 ((volatile uint32_t *)0xfe04010c) +#define P_DSPB_STS4 ((volatile uint32_t *)0xfe040110) +#define P_DSPB_STS5 ((volatile uint32_t *)0xfe040114) +#define P_DSPB_MAILBOX_SET_0 ((volatile uint32_t *)0xfe040140) +#define P_DSPB_MAILBOX_SET_1 ((volatile uint32_t *)0xfe040144) +#define P_DSPB_MAILBOX_SET_2 ((volatile uint32_t *)0xfe040148) +#define P_DSPB_MAILBOX_SET_3 ((volatile uint32_t *)0xfe04014c) +#define P_DSPB_MAILBOX_SET_4 ((volatile uint32_t *)0xfe040150) +#define P_DSPB_MAILBOX_SET_5 ((volatile uint32_t *)0xfe040154) +#define P_DSPB_MAILBOX_SET_6 ((volatile uint32_t *)0xfe040158) +#define P_DSPB_MAILBOX_SET_7 ((volatile uint32_t *)0xfe04015c) +#define P_DSPB_MAILBOX_SET_8 ((volatile uint32_t *)0xfe040160) +#define P_DSPB_MAILBOX_SET_9 ((volatile uint32_t *)0xfe040164) +#define P_DSPB_MAILBOX_SET_10 ((volatile uint32_t *)0xfe040168) +#define P_DSPB_MAILBOX_SET_11 ((volatile uint32_t *)0xfe04016c) +#define P_DSPB_MAILBOX_CLR_0 ((volatile uint32_t *)0xfe040180) +#define P_DSPB_MAILBOX_CLR_1 ((volatile uint32_t *)0xfe040184) +#define P_DSPB_MAILBOX_CLR_2 ((volatile uint32_t *)0xfe040188) +#define P_DSPB_MAILBOX_CLR_3 ((volatile uint32_t *)0xfe04018c) +#define P_DSPB_MAILBOX_CLR_4 ((volatile uint32_t *)0xfe040190) +#define P_DSPB_MAILBOX_CLR_5 ((volatile uint32_t *)0xfe040194) +#define P_DSPB_MAILBOX_CLR_6 ((volatile uint32_t *)0xfe040198) +#define P_DSPB_MAILBOX_CLR_7 ((volatile uint32_t *)0xfe04019c) +#define P_DSPB_MAILBOX_CLR_8 ((volatile uint32_t *)0xfe0401a0) +#define P_DSPB_MAILBOX_CLR_9 ((volatile uint32_t *)0xfe0401a4) +#define P_DSPB_MAILBOX_CLR_10 ((volatile uint32_t *)0xfe0401a8) +#define P_DSPB_MAILBOX_CLR_11 ((volatile uint32_t *)0xfe0401ac) +#define P_DSPB_MAILBOX_STAT_0 ((volatile uint32_t *)0xfe0401c0) +#define P_DSPB_MAILBOX_STAT_1 ((volatile uint32_t *)0xfe0401c4) +#define P_DSPB_MAILBOX_STAT_2 ((volatile uint32_t *)0xfe0401c8) +#define P_DSPB_MAILBOX_STAT_3 ((volatile uint32_t *)0xfe0401cc) +#define P_DSPB_MAILBOX_STAT_4 ((volatile uint32_t *)0xfe0401d0) +#define P_DSPB_MAILBOX_STAT_5 ((volatile uint32_t *)0xfe0401d4) +#define P_DSPB_MAILBOX_STAT_6 ((volatile uint32_t *)0xfe0401d8) +#define P_DSPB_MAILBOX_STAT_7 ((volatile uint32_t *)0xfe0401dc) +#define P_DSPB_MAILBOX_STAT_8 ((volatile uint32_t *)0xfe0401e0) +#define P_DSPB_MAILBOX_STAT_9 ((volatile uint32_t *)0xfe0401e4) +#define P_DSPB_MAILBOX_STAT_10 ((volatile uint32_t *)0xfe0401e8) +#define P_DSPB_MAILBOX_STAT_11 ((volatile uint32_t *)0xfe0401ec) +#define P_DSPB_QIF_CTRL ((volatile uint32_t *)0xfe040200) +#define P_DSPB_QIF_STS ((volatile uint32_t *)0xfe040204) +#define P_DSPB_WRFIFO_TOCPUA ((volatile uint32_t *)0xfe040208) +#define P_DSPB_WRFIFO_TOCPUB ((volatile uint32_t *)0xfe04020c) +#define P_DSPB_WRFIFO_TODSP ((volatile uint32_t *)0xfe040210) +#define P_DSPB_RDFIFO_FRCPUA ((volatile uint32_t *)0xfe040220) +#define P_DSPB_RDFIFO_FRCPUB ((volatile uint32_t *)0xfe040224) +#define P_DSPB_RDFIFO_FRDSP ((volatile uint32_t *)0xfe040228) +// synopsys translate_off +// synopsys translate_on +// +// Closing file: REG_LIST_DSP_RTL.h +// +// synopsys translate_off +// synopsys translate_on +// +// Closing file: ./REG_LIST_RTL.h +// + +#endif // P_REGISTER_H +
diff --git a/arch/arm/include/asm/arch-a1/pinctrl_init.h b/arch/arm/include/asm/arch-a1/pinctrl_init.h new file mode 100644 index 0000000..cfbc42a --- /dev/null +++ b/arch/arm/include/asm/arch-a1/pinctrl_init.h
@@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef _MESON_PINCTRL_INIT_H_ +#define _MESON_PINCTRL_INIT_H_ + +#define PIN_CONTROLLER_NUM 2 +extern int pinctrl_devices_active(int pinctrl_num); + +#endif /* _MESON_PINCTRL_INIT_H_ */
diff --git a/arch/arm/include/asm/arch-a1/pll.h b/arch/arm/include/asm/arch-a1/pll.h new file mode 100644 index 0000000..14c4c68 --- /dev/null +++ b/arch/arm/include/asm/arch-a1/pll.h
@@ -0,0 +1,125 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __PLL_H +#define __PLL_H + +#define PLL_TEST_SYS_TOTAL 8 +#define PLL_TEST_HDMI_TOTAL 3 + +typedef struct sys_pll_set_s { + unsigned int cpu_clk; + unsigned int pll_cntl0; + unsigned int pll_cntl1; + unsigned int pll_cntl2; + unsigned int pll_cntl3; + unsigned int pll_cntl4; +}sys_pll_set_t; + +typedef struct hifi_pll_set_s { + unsigned int pll_clk; + unsigned int pll_cntl0; + unsigned int pll_cntl1; + unsigned int pll_cntl2; + unsigned int pll_cntl3; + unsigned int pll_cntl4; +}hifi_pll_set_t; + +typedef struct usbphy_pll_set_s { + unsigned int pll_clk; + unsigned int pll_cntl0; + unsigned int pll_cntl1; + unsigned int pll_cntl2; +}usbphy_pll_set_t; + +typedef struct sys_pll_cfg_s { + sys_pll_set_t sys_pll[PLL_TEST_SYS_TOTAL]; +}sys_pll_cfg_t; + +typedef struct hifipll_rate_table_s { + unsigned int rate; + unsigned int m; + unsigned int n; + unsigned int od; +}hifipll_rate_table_t; + +#if 0 +unsigned int fix_pll_cfg[6] = { + /* CNTL, CNTL2, CNTL3, CNTL4, CNTL5, CNTL6*/ + /*2G*/ 0x600006FA, 0x59C80000, 0xCA753822, 0x00010006, 0x95520E1A, 0xFC454545, +}; + +unsigned int ddr_pll_cfg[][6] = { + {0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0}, +}; +#endif + +#if 0 +typedef struct hdmi_pll_set_s { + unsigned int pll_clk; + unsigned int pll_cntl0; + unsigned int pll_cntl1; + unsigned int pll_cntl2; + unsigned int pll_cntl3; + unsigned int pll_cntl4; + unsigned int pll_cntl5; + unsigned int pll_cntl6; +}hdmi_pll_set_t; + +typedef struct hdmi_pll_cfg_s { + hdmi_pll_set_t hdmi_pll[PLL_TEST_HDMI_TOTAL]; +}hdmi_pll_cfg_t; + +typedef struct gpll_rate_table_s { + unsigned int rate; + unsigned int m; + unsigned int n; + unsigned int od; +}gpll_rate_table_t; + +typedef struct gp0_pll_set_s { + unsigned int pll_clk; + unsigned int pll_cntl0; + unsigned int pll_cntl1; + unsigned int pll_cntl2; + unsigned int pll_cntl3; + unsigned int pll_cntl4; + unsigned int pll_cntl5; + unsigned int pll_cntl6; +}gp0_pll_set_t; +#endif + +#if 0 +unsigned int hdmi_pll_cfg[][7] = { + /* get from enc_clk_config.c */ + /* freq, cntl, cntl1, cntl2, cntl3, cntl4, cntl5 */ + {5940000, 0x4000027b, 0x800cb300, 0xc60f30e0, 0x0c8e0000, 0x001fa729, 0x01a31500}, + {5405400, 0x400002e1, 0x800cb0e6, 0x860f30c4, 0x0c8e0000, 0x001fa729, 0x01a31500}, + {4455000, 0x400002b9, 0x800cb280, 0x860f30c4, 0x0c8e0000, 0x001fa729, 0x01a31500}, + {4324320, 0x400002b4, 0x800cb0b8, 0x860f30c4, 0x0c8e0000, 0x001fa729, 0x01a31500}, + {3712500, 0x4000029a, 0x800cb2c0, 0x860f30c4, 0x0c8e0000, 0x001fa729, 0x01a31500}, + {3450000, 0x4000028f, 0x800cb300, 0x860f30c4, 0x0c8e0000, 0x001fa729, 0x01a31500}, + {3243240, 0x40000287, 0x800cb08a, 0x860f30c4, 0x0c8e0000, 0x001fa729, 0x01a31500}, + {2970000, 0x4000027b, 0x800cb300, 0x860f30c4, 0x0c8e0000, 0x001fa729, 0x01a31500}, +}; +#endif + +enum pll_enum { + PLL_SYS = 0, + PLL_FIX, + PLL_DDR, + PLL_HIFI, + PLL_USBPHY, + PLL_ENUM, +}; + +int pll_test(int argc, char * const argv[]); + +#endif /* __PLL_H */
diff --git a/arch/arm/include/asm/arch-a1/pwr_ctrl.h b/arch/arm/include/asm/arch-a1/pwr_ctrl.h new file mode 100644 index 0000000..3c9b152 --- /dev/null +++ b/arch/arm/include/asm/arch-a1/pwr_ctrl.h
@@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#define PWR_ON 1 +#define PWR_OFF 0 + +enum pm_e { + PM_CPU_PWR0, + PM_CPU_CORE0, + PM_CPU_CORE1, + PM_DSP_A = 8, + PM_DSP_B, + PM_UART, + PM_MMC, + PM_I2C, + PM_PSRAM, + PM_ACODEC, + PM_AUDIO, + PM_MKL_OTP, + PM_DMA, + PM_SDEMMC, + PM_SRAM_A, + PM_SRAM_B, + PM_IR, + PM_SPICC, + PM_SPIFC, + PM_USB, + PM_NIC, + PM_PDM, + PM_RSA +}; + +unsigned long pwr_ctrl_psci_smc(unsigned int power_domain, bool power_control); \ No newline at end of file
diff --git a/arch/arm/include/asm/arch-a1/register.h b/arch/arm/include/asm/arch-a1/register.h new file mode 100644 index 0000000..d800df7 --- /dev/null +++ b/arch/arm/include/asm/arch-a1/register.h
@@ -0,0 +1,4083 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifdef REGISTER_H +#else +#define REGISTER_H + +// +// Reading file: ./REG_LIST_RTL.h +// +// synopsys translate_off +// synopsys translate_on +// +// Reading file: REG_LIST_AUDIO_RTL.h +// +//======================================================================== +// AUDIO - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe050000 +// ----------------------------------------------- +#define EE_AUDIO_CLK_GATE_EN0 ((0x0000 << 2) + 0xfe050000) +#define EE_AUDIO_CLK_GATE_EN1 ((0x0001 << 2) + 0xfe050000) +#define EE_AUDIO_MCLK_A_CTRL ((0x0002 << 2) + 0xfe050000) +#define EE_AUDIO_MCLK_B_CTRL ((0x0003 << 2) + 0xfe050000) +#define EE_AUDIO_MCLK_C_CTRL ((0x0004 << 2) + 0xfe050000) +#define EE_AUDIO_MCLK_D_CTRL ((0x0005 << 2) + 0xfe050000) +#define EE_AUDIO_MCLK_E_CTRL ((0x0006 << 2) + 0xfe050000) +#define EE_AUDIO_MCLK_F_CTRL ((0x0007 << 2) + 0xfe050000) +#define EE_AUDIO_PAD_CTRL0 ((0x0008 << 2) + 0xfe050000) +#define EE_AUDIO_PAD_CTRL1 ((0x0009 << 2) + 0xfe050000) +#define EE_AUDIO_SW_RESET0 ((0x000a << 2) + 0xfe050000) +#define EE_AUDIO_SW_RESET1 ((0x000b << 2) + 0xfe050000) +#define EE_AUDIO_CLK81_CTRL ((0x000c << 2) + 0xfe050000) +#define EE_AUDIO_CLK81_EN ((0x000d << 2) + 0xfe050000) +#define EE_AUDIO_MST_A_SCLK_CTRL0 ((0x0010 << 2) + 0xfe050000) +#define EE_AUDIO_MST_A_SCLK_CTRL1 ((0x0011 << 2) + 0xfe050000) +#define EE_AUDIO_MST_B_SCLK_CTRL0 ((0x0012 << 2) + 0xfe050000) +#define EE_AUDIO_MST_B_SCLK_CTRL1 ((0x0013 << 2) + 0xfe050000) +#define EE_AUDIO_MST_C_SCLK_CTRL0 ((0x0014 << 2) + 0xfe050000) +#define EE_AUDIO_MST_C_SCLK_CTRL1 ((0x0015 << 2) + 0xfe050000) +#define EE_AUDIO_MST_D_SCLK_CTRL0 ((0x0016 << 2) + 0xfe050000) +#define EE_AUDIO_MST_D_SCLK_CTRL1 ((0x0017 << 2) + 0xfe050000) +#define EE_AUDIO_MST_E_SCLK_CTRL0 ((0x0018 << 2) + 0xfe050000) +#define EE_AUDIO_MST_E_SCLK_CTRL1 ((0x0019 << 2) + 0xfe050000) +#define EE_AUDIO_MST_F_SCLK_CTRL0 ((0x001a << 2) + 0xfe050000) +#define EE_AUDIO_MST_F_SCLK_CTRL1 ((0x001b << 2) + 0xfe050000) +#define EE_AUDIO_MST_DLY_CTRL0 ((0x001c << 2) + 0xfe050000) +#define EE_AUDIO_MST_DLY_CTRL1 ((0x001d << 2) + 0xfe050000) +#define EE_AUDIO_CLK_TDMIN_A_CTRL ((0x0020 << 2) + 0xfe050000) +#define EE_AUDIO_CLK_TDMIN_B_CTRL ((0x0021 << 2) + 0xfe050000) +#define EE_AUDIO_CLK_TDMIN_C_CTRL ((0x0022 << 2) + 0xfe050000) +#define EE_AUDIO_CLK_TDMIN_LB_CTRL ((0x0023 << 2) + 0xfe050000) +#define EE_AUDIO_CLK_TDMOUT_A_CTRL ((0x0024 << 2) + 0xfe050000) +#define EE_AUDIO_CLK_TDMOUT_B_CTRL ((0x0025 << 2) + 0xfe050000) +#define EE_AUDIO_CLK_TDMOUT_C_CTRL ((0x0026 << 2) + 0xfe050000) +#define EE_AUDIO_CLK_SPDIFIN_CTRL ((0x0027 << 2) + 0xfe050000) +#define EE_AUDIO_CLK_SPDIFOUT_CTRL ((0x0028 << 2) + 0xfe050000) +#define EE_AUDIO_CLK_RESAMPLEA_CTRL ((0x0029 << 2) + 0xfe050000) +#define EE_AUDIO_CLK_LOCKER_CTRL ((0x002a << 2) + 0xfe050000) +#define EE_AUDIO_CLK_PDMIN_CTRL0 ((0x002b << 2) + 0xfe050000) +#define EE_AUDIO_CLK_PDMIN_CTRL1 ((0x002c << 2) + 0xfe050000) +#define EE_AUDIO_CLK_SPDIFOUT_B_CTRL ((0x002d << 2) + 0xfe050000) +#define EE_AUDIO_CLK_RESAMPLEB_CTRL ((0x002e << 2) + 0xfe050000) +#define EE_AUDIO_CLK_SPDIFIN_LB_CTRL ((0x002f << 2) + 0xfe050000) +#define EE_AUDIO_CLK_EQDRC_CTRL0 ((0x0030 << 2) + 0xfe050000) +#define EE_AUDIO_VAD_CLK_CTRL ((0x0031 << 2) + 0xfe050000) +#define EE_AUDIO_EARCTX_CMDC_CLK_CTRL ((0x0032 << 2) + 0xfe050000) +#define EE_AUDIO_EARCTX_DMAC_CLK_CTRL ((0x0033 << 2) + 0xfe050000) +#define EE_AUDIO_EARCRX_CMDC_CLK_CTRL ((0x0034 << 2) + 0xfe050000) +#define EE_AUDIO_EARCRX_DMAC_CLK_CTRL ((0x0035 << 2) + 0xfe050000) +#define EE_AUDIO_CLK_LOCKERB_CTRL ((0x0036 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_A_CTRL0 ((0x0040 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_A_CTRL1 ((0x0041 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_A_START_ADDR ((0x0042 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_A_FINISH_ADDR ((0x0043 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_A_INT_ADDR ((0x0044 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_A_STATUS1 ((0x0045 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_A_STATUS2 ((0x0046 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_A_START_ADDRB ((0x0047 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_A_FINISH_ADDRB ((0x0048 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_A_INIT_ADDR ((0x0049 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_A_CTRL2 ((0x004a << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_B_CTRL0 ((0x0050 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_B_CTRL1 ((0x0051 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_B_START_ADDR ((0x0052 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_B_FINISH_ADDR ((0x0053 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_B_INT_ADDR ((0x0054 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_B_STATUS1 ((0x0055 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_B_STATUS2 ((0x0056 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_B_START_ADDRB ((0x0057 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_B_FINISH_ADDRB ((0x0058 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_B_INIT_ADDR ((0x0059 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_B_CTRL2 ((0x005a << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_C_CTRL0 ((0x0060 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_C_CTRL1 ((0x0061 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_C_START_ADDR ((0x0062 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_C_FINISH_ADDR ((0x0063 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_C_INT_ADDR ((0x0064 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_C_STATUS1 ((0x0065 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_C_STATUS2 ((0x0066 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_C_START_ADDRB ((0x0067 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_C_FINISH_ADDRB ((0x0068 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_C_INIT_ADDR ((0x0069 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_C_CTRL2 ((0x006a << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_A_CTRL0 ((0x0070 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_A_CTRL1 ((0x0071 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_A_START_ADDR ((0x0072 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_A_FINISH_ADDR ((0x0073 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_A_INT_ADDR ((0x0074 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_A_STATUS1 ((0x0075 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_A_STATUS2 ((0x0076 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_A_START_ADDRB ((0x0077 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_A_FINISH_ADDRB ((0x0078 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_A_INIT_ADDR ((0x0079 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_A_CTRL2 ((0x007a << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_B_CTRL0 ((0x0080 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_B_CTRL1 ((0x0081 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_B_START_ADDR ((0x0082 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_B_FINISH_ADDR ((0x0083 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_B_INT_ADDR ((0x0084 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_B_STATUS1 ((0x0085 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_B_STATUS2 ((0x0086 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_B_START_ADDRB ((0x0087 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_B_FINISH_ADDRB ((0x0088 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_B_INIT_ADDR ((0x0089 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_B_CTRL2 ((0x008a << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_C_CTRL0 ((0x0090 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_C_CTRL1 ((0x0091 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_C_START_ADDR ((0x0092 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_C_FINISH_ADDR ((0x0093 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_C_INT_ADDR ((0x0094 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_C_STATUS1 ((0x0095 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_C_STATUS2 ((0x0096 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_C_START_ADDRB ((0x0097 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_C_FINISH_ADDRB ((0x0098 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_C_INIT_ADDR ((0x0099 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_C_CTRL2 ((0x009a << 2) + 0xfe050000) +#define EE_AUDIO_ARB_CTRL ((0x00a0 << 2) + 0xfe050000) +#define EE_AUDIO_LB_A_CTRL0 ((0x00b0 << 2) + 0xfe050000) +#define EE_AUDIO_LB_A_CTRL1 ((0x00b1 << 2) + 0xfe050000) +#define EE_AUDIO_LB_A_CTRL2 ((0x00b2 << 2) + 0xfe050000) +#define EE_AUDIO_LB_A_CTRL3 ((0x00b3 << 2) + 0xfe050000) +#define EE_AUDIO_LB_A_DAT_CH_ID0 ((0x00b4 << 2) + 0xfe050000) +#define EE_AUDIO_LB_A_DAT_CH_ID1 ((0x00b5 << 2) + 0xfe050000) +#define EE_AUDIO_LB_A_DAT_CH_ID2 ((0x00b6 << 2) + 0xfe050000) +#define EE_AUDIO_LB_A_DAT_CH_ID3 ((0x00b7 << 2) + 0xfe050000) +#define EE_AUDIO_LB_A_LB_CH_ID0 ((0x00b8 << 2) + 0xfe050000) +#define EE_AUDIO_LB_A_LB_CH_ID1 ((0x00b9 << 2) + 0xfe050000) +#define EE_AUDIO_LB_A_LB_CH_ID2 ((0x00ba << 2) + 0xfe050000) +#define EE_AUDIO_LB_A_LB_CH_ID3 ((0x00bb << 2) + 0xfe050000) +#define EE_AUDIO_LB_A_STS ((0x00bc << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_A_CTRL ((0x00c0 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_A_SWAP0 ((0x00c1 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_A_MASK0 ((0x00c2 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_A_MASK1 ((0x00c3 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_A_MASK2 ((0x00c4 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_A_MASK3 ((0x00c5 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_A_STAT ((0x00c6 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_A_MUTE_VAL ((0x00c7 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_A_MUTE0 ((0x00c8 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_A_MUTE1 ((0x00c9 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_A_MUTE2 ((0x00ca << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_A_MUTE3 ((0x00cb << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_B_CTRL ((0x00d0 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_B_SWAP0 ((0x00d1 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_B_MASK0 ((0x00d2 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_B_MASK1 ((0x00d3 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_B_MASK2 ((0x00d4 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_B_MASK3 ((0x00d5 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_B_STAT ((0x00d6 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_B_MUTE_VAL ((0x00d7 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_B_MUTE0 ((0x00d8 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_B_MUTE1 ((0x00d9 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_B_MUTE2 ((0x00da << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_B_MUTE3 ((0x00db << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_C_CTRL ((0x00e0 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_C_SWAP0 ((0x00e1 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_C_MASK0 ((0x00e2 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_C_MASK1 ((0x00e3 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_C_MASK2 ((0x00e4 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_C_MASK3 ((0x00e5 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_C_STAT ((0x00e6 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_C_MUTE_VAL ((0x00e7 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_C_MUTE0 ((0x00e8 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_C_MUTE1 ((0x00e9 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_C_MUTE2 ((0x00ea << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_C_MUTE3 ((0x00eb << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_LB_CTRL ((0x00f0 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_LB_SWAP0 ((0x00f1 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_LB_MASK0 ((0x00f2 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_LB_MASK1 ((0x00f3 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_LB_MASK2 ((0x00f4 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_LB_MASK3 ((0x00f5 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_LB_STAT ((0x00f6 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_LB_MUTE_VAL ((0x00f7 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_LB_MUTE0 ((0x00f8 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_LB_MUTE1 ((0x00f9 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_LB_MUTE2 ((0x00fa << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_LB_MUTE3 ((0x00fb << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFIN_CTRL0 ((0x0100 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFIN_CTRL1 ((0x0101 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFIN_CTRL2 ((0x0102 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFIN_CTRL3 ((0x0103 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFIN_CTRL4 ((0x0104 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFIN_CTRL5 ((0x0105 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFIN_CTRL6 ((0x0106 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFIN_STAT0 ((0x0107 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFIN_STAT1 ((0x0108 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFIN_STAT2 ((0x0109 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFIN_MUTE_VAL ((0x010a << 2) + 0xfe050000) +#define EE_AUDIO_RESAMPLEA_CTRL0 ((0x0110 << 2) + 0xfe050000) +#define EE_AUDIO_RESAMPLEA_CTRL1 ((0x0111 << 2) + 0xfe050000) +#define EE_AUDIO_RESAMPLEA_CTRL2 ((0x0112 << 2) + 0xfe050000) +#define EE_AUDIO_RESAMPLEA_CTRL3 ((0x0113 << 2) + 0xfe050000) +#define EE_AUDIO_RESAMPLEA_COEF0 ((0x0114 << 2) + 0xfe050000) +#define EE_AUDIO_RESAMPLEA_COEF1 ((0x0115 << 2) + 0xfe050000) +#define EE_AUDIO_RESAMPLEA_COEF2 ((0x0116 << 2) + 0xfe050000) +#define EE_AUDIO_RESAMPLEA_COEF3 ((0x0117 << 2) + 0xfe050000) +#define EE_AUDIO_RESAMPLEA_COEF4 ((0x0118 << 2) + 0xfe050000) +#define EE_AUDIO_RESAMPLEA_STATUS1 ((0x0119 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_STAT ((0x0120 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_GAIN0 ((0x0121 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_GAIN1 ((0x0122 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_CTRL0 ((0x0123 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_CTRL1 ((0x0124 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_PREAMB ((0x0125 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_SWAP ((0x0126 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_CHSTS0 ((0x0127 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_CHSTS1 ((0x0128 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_CHSTS2 ((0x0129 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_CHSTS3 ((0x012a << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_CHSTS4 ((0x012b << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_CHSTS5 ((0x012c << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_CHSTS6 ((0x012d << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_CHSTS7 ((0x012e << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_CHSTS8 ((0x012f << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_CHSTS9 ((0x0130 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_CHSTSA ((0x0131 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_CHSTSB ((0x0132 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_MUTE_VAL ((0x0133 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_CTRL0 ((0x0140 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_CTRL1 ((0x0141 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_SWAP0 ((0x0142 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_MASK0 ((0x0143 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_MASK1 ((0x0144 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_MASK2 ((0x0145 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_MASK3 ((0x0146 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_STAT ((0x0147 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_GAIN0 ((0x0148 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_GAIN1 ((0x0149 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_MUTE_VAL ((0x014a << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_MUTE0 ((0x014b << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_MUTE1 ((0x014c << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_MUTE2 ((0x014d << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_MUTE3 ((0x014e << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_MASK_VAL ((0x014f << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_CTRL0 ((0x0150 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_CTRL1 ((0x0151 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_SWAP0 ((0x0152 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_MASK0 ((0x0153 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_MASK1 ((0x0154 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_MASK2 ((0x0155 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_MASK3 ((0x0156 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_STAT ((0x0157 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_GAIN0 ((0x0158 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_GAIN1 ((0x0159 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_MUTE_VAL ((0x015a << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_MUTE0 ((0x015b << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_MUTE1 ((0x015c << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_MUTE2 ((0x015d << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_MUTE3 ((0x015e << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_MASK_VAL ((0x015f << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_CTRL0 ((0x0160 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_CTRL1 ((0x0161 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_SWAP0 ((0x0162 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_MASK0 ((0x0163 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_MASK1 ((0x0164 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_MASK2 ((0x0165 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_MASK3 ((0x0166 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_STAT ((0x0167 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_GAIN0 ((0x0168 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_GAIN1 ((0x0169 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_MUTE_VAL ((0x016a << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_MUTE0 ((0x016b << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_MUTE1 ((0x016c << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_MUTE2 ((0x016d << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_MUTE3 ((0x016e << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_MASK_VAL ((0x016f << 2) + 0xfe050000) +//`define EE_AUDIO_POW_DET_CTRL0 10'h180 +//`define EE_AUDIO_POW_DET_CTRL1 10'h181 +//`define EE_AUDIO_POW_DET_TH_HI 10'h182 +//`define EE_AUDIO_POW_DET_TH_LO 10'h183 +//`define EE_AUDIO_POW_DET_VALUE 10'h184 +#define EE_AUDIO_SECURITY_CTRL0 ((0x0190 << 2) + 0xfe050000) +#define EE_AUDIO_SECURITY_CTRL1 ((0x0191 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_B_STAT ((0x01a0 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_B_GAIN0 ((0x01a1 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_B_GAIN1 ((0x01a2 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_B_CTRL0 ((0x01a3 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_B_CTRL1 ((0x01a4 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_B_PREAMB ((0x01a5 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_B_SWAP ((0x01a6 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_B_CHSTS0 ((0x01a7 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_B_CHSTS1 ((0x01a8 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_B_CHSTS2 ((0x01a9 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_B_CHSTS3 ((0x01aa << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_B_CHSTS4 ((0x01ab << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_B_CHSTS5 ((0x01ac << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_B_CHSTS6 ((0x01ad << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_B_CHSTS7 ((0x01ae << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_B_CHSTS8 ((0x01af << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_B_CHSTS9 ((0x01b0 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_B_CHSTSA ((0x01b1 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_B_CHSTSB ((0x01b2 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_B_MUTE_VAL ((0x01b3 << 2) + 0xfe050000) +#define EE_AUDIO_TORAM_CTRL0 ((0x01c0 << 2) + 0xfe050000) +#define EE_AUDIO_TORAM_CTRL1 ((0x01c1 << 2) + 0xfe050000) +#define EE_AUDIO_TORAM_START_ADDR ((0x01c2 << 2) + 0xfe050000) +#define EE_AUDIO_TORAM_FINISH_ADDR ((0x01c3 << 2) + 0xfe050000) +#define EE_AUDIO_TORAM_INT_ADDR ((0x01c4 << 2) + 0xfe050000) +#define EE_AUDIO_TORAM_STATUS1 ((0x01c5 << 2) + 0xfe050000) +#define EE_AUDIO_TORAM_STATUS2 ((0x01c6 << 2) + 0xfe050000) +#define EE_AUDIO_TORAM_INIT_ADDR ((0x01c7 << 2) + 0xfe050000) +#define EE_AUDIO_TOACODEC_CTRL0 ((0x01d0 << 2) + 0xfe050000) +#define EE_AUDIO_TOHDMITX_CTRL0 ((0x01d1 << 2) + 0xfe050000) +#define EE_AUDIO_TOVAD_CTRL0 ((0x01d2 << 2) + 0xfe050000) +#define EE_AUDIO_FRATV_CTRL0 ((0x01d3 << 2) + 0xfe050000) +#define EE_AUDIO_RESAMPLEB_CTRL0 ((0x01e0 << 2) + 0xfe050000) +#define EE_AUDIO_RESAMPLEB_CTRL1 ((0x01e1 << 2) + 0xfe050000) +#define EE_AUDIO_RESAMPLEB_CTRL2 ((0x01e2 << 2) + 0xfe050000) +#define EE_AUDIO_RESAMPLEB_CTRL3 ((0x01e3 << 2) + 0xfe050000) +#define EE_AUDIO_RESAMPLEB_COEF0 ((0x01e4 << 2) + 0xfe050000) +#define EE_AUDIO_RESAMPLEB_COEF1 ((0x01e5 << 2) + 0xfe050000) +#define EE_AUDIO_RESAMPLEB_COEF2 ((0x01e6 << 2) + 0xfe050000) +#define EE_AUDIO_RESAMPLEB_COEF3 ((0x01e7 << 2) + 0xfe050000) +#define EE_AUDIO_RESAMPLEB_COEF4 ((0x01e8 << 2) + 0xfe050000) +#define EE_AUDIO_RESAMPLEB_STATUS1 ((0x01e9 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFIN_LB_CTRL0 ((0x01f0 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFIN_LB_CTRL1 ((0x01f1 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFIN_LB_CTRL6 ((0x01f6 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFIN_LB_STAT0 ((0x01f7 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFIN_LB_STAT1 ((0x01f8 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFIN_LB_MUTE_VAL ((0x01fa << 2) + 0xfe050000) +#define EE_AUDIO_FRHDMIRX_CTRL0 ((0x0200 << 2) + 0xfe050000) +#define EE_AUDIO_FRHDMIRX_CTRL1 ((0x0201 << 2) + 0xfe050000) +#define EE_AUDIO_FRHDMIRX_CTRL2 ((0x0202 << 2) + 0xfe050000) +#define EE_AUDIO_FRHDMIRX_CTRL3 ((0x0203 << 2) + 0xfe050000) +#define EE_AUDIO_FRHDMIRX_CTRL4 ((0x0204 << 2) + 0xfe050000) +#define EE_AUDIO_FRHDMIRX_CTRL5 ((0x0205 << 2) + 0xfe050000) +#define EE_AUDIO_FRHDMIRX_STAT0 ((0x020a << 2) + 0xfe050000) +#define EE_AUDIO_FRHDMIRX_STAT1 ((0x020b << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_D_CTRL0 ((0x0210 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_D_CTRL1 ((0x0211 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_D_START_ADDR ((0x0212 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_D_FINISH_ADDR ((0x0213 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_D_INT_ADDR ((0x0214 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_D_STATUS1 ((0x0215 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_D_STATUS2 ((0x0216 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_D_START_ADDRB ((0x0217 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_D_FINISH_ADDRB ((0x0218 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_D_INIT_ADDR ((0x0219 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_D_CTRL2 ((0x021a << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_D_CTRL0 ((0x0220 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_D_CTRL1 ((0x0221 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_D_START_ADDR ((0x0222 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_D_FINISH_ADDR ((0x0223 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_D_INT_ADDR ((0x0224 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_D_STATUS1 ((0x0225 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_D_STATUS2 ((0x0226 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_D_START_ADDRB ((0x0227 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_D_FINISH_ADDRB ((0x0228 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_D_INIT_ADDR ((0x0229 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_D_CTRL2 ((0x022a << 2) + 0xfe050000) +#define EE_AUDIO_LB_B_CTRL0 ((0x0230 << 2) + 0xfe050000) +#define EE_AUDIO_LB_B_CTRL1 ((0x0231 << 2) + 0xfe050000) +#define EE_AUDIO_LB_B_CTRL2 ((0x0232 << 2) + 0xfe050000) +#define EE_AUDIO_LB_B_CTRL3 ((0x0233 << 2) + 0xfe050000) +#define EE_AUDIO_LB_B_DAT_CH_ID0 ((0x0234 << 2) + 0xfe050000) +#define EE_AUDIO_LB_B_DAT_CH_ID1 ((0x0235 << 2) + 0xfe050000) +#define EE_AUDIO_LB_B_DAT_CH_ID2 ((0x0236 << 2) + 0xfe050000) +#define EE_AUDIO_LB_B_DAT_CH_ID3 ((0x0237 << 2) + 0xfe050000) +#define EE_AUDIO_LB_B_LB_CH_ID0 ((0x0238 << 2) + 0xfe050000) +#define EE_AUDIO_LB_B_LB_CH_ID1 ((0x0239 << 2) + 0xfe050000) +#define EE_AUDIO_LB_B_LB_CH_ID2 ((0x023a << 2) + 0xfe050000) +#define EE_AUDIO_LB_B_LB_CH_ID3 ((0x023b << 2) + 0xfe050000) +#define EE_AUDIO_LB_B_STS ((0x023c << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_E_CTRL0 ((0x0240 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_E_CTRL1 ((0x0241 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_E_START_ADDR ((0x0242 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_E_FINISH_ADDR ((0x0243 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_E_INT_ADDR ((0x0244 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_E_STATUS1 ((0x0245 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_E_STATUS2 ((0x0246 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_E_START_ADDRB ((0x0247 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_E_FINISH_ADDRB ((0x0248 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_E_INIT_ADDR ((0x0249 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_E_CTRL2 ((0x024a << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_E_CTRL0 ((0x0250 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_E_CTRL1 ((0x0251 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_E_START_ADDR ((0x0252 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_E_FINISH_ADDR ((0x0253 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_E_INT_ADDR ((0x0254 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_E_STATUS1 ((0x0255 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_E_STATUS2 ((0x0256 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_E_START_ADDRB ((0x0257 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_E_FINISH_ADDRB ((0x0258 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_E_INIT_ADDR ((0x0259 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_E_CTRL2 ((0x025a << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_A_SWAP1 ((0x0260 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_A_MASK4 ((0x0261 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_A_MASK5 ((0x0262 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_A_MASK6 ((0x0263 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_A_MASK7 ((0x0264 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_A_MUTE4 ((0x0265 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_A_MUTE5 ((0x0266 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_A_MUTE6 ((0x0267 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_A_MUTE7 ((0x0268 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_B_SWAP1 ((0x0270 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_B_MASK4 ((0x0271 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_B_MASK5 ((0x0272 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_B_MASK6 ((0x0273 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_B_MASK7 ((0x0274 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_B_MUTE4 ((0x0275 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_B_MUTE5 ((0x0276 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_B_MUTE6 ((0x0277 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_B_MUTE7 ((0x0278 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_C_SWAP1 ((0x0280 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_C_MASK4 ((0x0281 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_C_MASK5 ((0x0282 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_C_MASK6 ((0x0283 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_C_MASK7 ((0x0284 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_C_MUTE4 ((0x0285 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_C_MUTE5 ((0x0286 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_C_MUTE6 ((0x0287 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_C_MUTE7 ((0x0288 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_LB_SWAP1 ((0x0290 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_LB_MASK4 ((0x0291 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_LB_MASK5 ((0x0292 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_LB_MASK6 ((0x0293 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_LB_MASK7 ((0x0294 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_LB_MUTE4 ((0x0295 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_LB_MUTE5 ((0x0296 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_LB_MUTE6 ((0x0297 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_LB_MUTE7 ((0x0298 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_CTRL2 ((0x02a0 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_SWAP1 ((0x02a1 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_GAIN2 ((0x02a2 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_GAIN3 ((0x02a3 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_MASK4 ((0x02a4 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_MASK5 ((0x02a5 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_MASK6 ((0x02a6 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_MASK7 ((0x02a7 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_MUTE4 ((0x02a8 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_MUTE5 ((0x02a9 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_MUTE6 ((0x02aa << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_MUTE7 ((0x02ab << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_CTRL2 ((0x02b0 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_SWAP1 ((0x02b1 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_GAIN2 ((0x02b2 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_GAIN3 ((0x02b3 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_MASK4 ((0x02b4 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_MASK5 ((0x02b5 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_MASK6 ((0x02b6 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_MASK7 ((0x02b7 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_MUTE4 ((0x02b8 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_MUTE5 ((0x02b9 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_MUTE6 ((0x02ba << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_MUTE7 ((0x02bb << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_CTRL2 ((0x02c0 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_SWAP1 ((0x02c1 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_GAIN2 ((0x02c2 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_GAIN3 ((0x02c3 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_MASK4 ((0x02c4 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_MASK5 ((0x02c5 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_MASK6 ((0x02c6 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_MASK7 ((0x02c7 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_MUTE4 ((0x02c8 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_MUTE5 ((0x02c9 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_MUTE6 ((0x02ca << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_MUTE7 ((0x02cb << 2) + 0xfe050000) +//======================================================================== +// PDM - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe051000 +// ----------------------------------------------- +#define PDM_CTRL ((0x0000 << 2) + 0xfe051000) + //bit 31: PDM enable. + //bit 30: invert the PDM_DCLK. + //bit 29: output mode: 1: 24bits. 0: 32 bits. + //bit 28: bypass mode. 1: bypass all filter. directly output the PDM input to DDR. 0: normal mode. + //bit 27~9: not used. + //bit 16:. PDM Asynchronous FIFO soft reset. write 1 to soft reset AFIFO. + //bit 15:8 PDM channel reset. 0: to reset each PDM channel. 1: normal mode. + //bit 7:0. PDM channel enable. each bit for one channel. +#define PDM_HCIC_CTRL1 ((0x0001 << 2) + 0xfe051000) + //bit 31 hcic filter enable. 1 use sinc filter. 0 bypass input to output. + //bit 29:24. hcic final gain shift parameter. + //bit 23:16 hcic final gain multiplier. + //bit 8:4 hcic down sample rate. + //bit 3:0 hcic stage number. must be between 3 to 9. +#define PDM_HCIC_CTRL2 ((0x0002 << 2) + 0xfe051000) + //Not used. +#define PDM_F1_CTRL ((0x0003 << 2) + 0xfe051000) + //bit 31 . filter 1 enable. + //bit 16:15. f1 round mode. 2'b00 : sign bit at bit 49. 28bits output [49:22] round at bit 21. 32bits output [49:18]. 24bits output [49:26] + // 2'b01 : sign bit at bit 50. 28bits output [50:23] round at bit 22. 32bits output [49:18]. 24bits output [49:26] + // 2'b10 : sign bit at bit 51. 28bits output [51:24] round at bit 23 32bits output [49:18]. 24bits output [49:26]. + //bit 15:12. filter 1 down sample rate. + //bit 8:0. filter 1 stage number. +#define PDM_F2_CTRL ((0x0004 << 2) + 0xfe051000) + //bit 31 . filter 2 enable. + //bit 16:15. f2 round mode. 2'b00 : round at bit 21. 2'b01 : round at bit 22. 2'b10 : round at bit 23. + //bit 15:12. filter 2 down sample rate. + //bit 8:0. filter 2 stage number. +#define PDM_F3_CTRL ((0x0005 << 2) + 0xfe051000) + //bit 31 . filter 3 enable. + //bit 16:15. f3 round mode. 2'b00 : round at bit 21. 2'b01 : round at bit 22. 2'b10 : round at bit 23. + //bit 15:12. filter 3 down sample rate. + //bit 8:0. filter 3 stage number. +#define PDM_HPF_CTRL ((0x0006 << 2) + 0xfe051000) + //bit 31 High pass filter enable. + //bit 20:16 high pass filter shift steps. 6~19 steps. + //bit 15:0 high pass filter output factor. +#define PDM_CHAN_CTRL ((0x0007 << 2) + 0xfe051000) + //bit 31:24. chan3 data sample pointer vs edge of the PDM_DCLK. + //bit 23:16 chan2 data sample pointer vs edge of the PDM_DCLK. + //bit 15:8. chan1 data sample pointer vs edge of the PDM_DCLK. + //bit 7:0 chan0 data sample pointer vs edge of the PDM_DCLK. +#define PDM_CHAN_CTRL1 ((0x0008 << 2) + 0xfe051000) + //bit 31:24. chan7 data sample pointer vs edge of the PDM_DCLK. + //bit 23:16 chan6 data sample pointer vs edge of the PDM_DCLK. + //bit 15:8. chan5 data sample pointer vs edge of the PDM_DCLK. + //bit 7:0 chan4 data sample pointer vs edge of the PDM_DCLK. +#define PDM_COEFF_ADDR ((0x0009 << 2) + 0xfe051000) + // address of the write/read of coeff data. +#define PDM_COEFF_DATA ((0x000a << 2) + 0xfe051000) + //write/read data to coeff memory. +#define PDM_CLKG_CTRL ((0x000b << 2) + 0xfe051000) + // auto clock gating control. 1: disable the clock gating function. the clock will awlays enabled. 0 : use RTL auto clock gating. + //31:7 not used. + //bit 6 filt_ctrl module auto clock gating control. + //bit 5 sinc fifo module auto clock gating control. + //bit 4 filter module auto clock gating control. + //bit 3 apb module auto clock gating control. + //bit 2 coeff memory module auto clock gating control. + //bit 1 each channel module auto clock gating control. + //bit 0 cts_pdm_clk auto clock gating control. +#define PDM_STS ((0x000c << 2) + 0xfe051000) +//bit 1 HPF filter output overflow. means the PCLK is too slow. +//bit 0 HCIC filter output overflow. means the CTS_PDM_CLK is too slow. can't finished the filter function. +#define PDM_MUTE_VALUE ((0x000d << 2) + 0xfe051000) +#define PDM_MASK_NUM ((0x000e << 2) + 0xfe051000) +//======================================================================== +// EQ DRC - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe052000 +// ----------------------------------------------- +#define AED_COEF_RAM_CNTL ((0x0000 << 2) + 0xfe052000) +#define AED_COEF_RAM_DATA ((0x0001 << 2) + 0xfe052000) +#define AED_EQ_EN ((0x0002 << 2) + 0xfe052000) +#define AED_EQ_TAP_CNTL ((0x0003 << 2) + 0xfe052000) +#define AED_EQ_VOLUME ((0x0004 << 2) + 0xfe052000) +#define AED_EQ_VOLUME_SLEW_CNT ((0x0005 << 2) + 0xfe052000) +#define AED_MUTE ((0x0006 << 2) + 0xfe052000) +#define AED_DRC_CNTL ((0x0007 << 2) + 0xfe052000) +#define AED_DRC_RMS_COEF0 ((0x0008 << 2) + 0xfe052000) +#define AED_DRC_RMS_COEF1 ((0x0009 << 2) + 0xfe052000) +#define AED_DRC_THD0 ((0x000a << 2) + 0xfe052000) +#define AED_DRC_THD1 ((0x000b << 2) + 0xfe052000) +#define AED_DRC_THD2 ((0x000c << 2) + 0xfe052000) +#define AED_DRC_THD3 ((0x000d << 2) + 0xfe052000) +#define AED_DRC_THD4 ((0x000e << 2) + 0xfe052000) +#define AED_DRC_K0 ((0x000f << 2) + 0xfe052000) +#define AED_DRC_K1 ((0x0010 << 2) + 0xfe052000) +#define AED_DRC_K2 ((0x0011 << 2) + 0xfe052000) +#define AED_DRC_K3 ((0x0012 << 2) + 0xfe052000) +#define AED_DRC_K4 ((0x0013 << 2) + 0xfe052000) +#define AED_DRC_K5 ((0x0014 << 2) + 0xfe052000) +#define AED_DRC_THD_OUT0 ((0x0015 << 2) + 0xfe052000) +#define AED_DRC_THD_OUT1 ((0x0016 << 2) + 0xfe052000) +#define AED_DRC_THD_OUT2 ((0x0017 << 2) + 0xfe052000) +#define AED_DRC_THD_OUT3 ((0x0018 << 2) + 0xfe052000) +#define AED_DRC_OFFSET ((0x0019 << 2) + 0xfe052000) +#define AED_DRC_RELEASE_COEF00 ((0x001a << 2) + 0xfe052000) +#define AED_DRC_RELEASE_COEF01 ((0x001b << 2) + 0xfe052000) +#define AED_DRC_RELEASE_COEF10 ((0x001c << 2) + 0xfe052000) +#define AED_DRC_RELEASE_COEF11 ((0x001d << 2) + 0xfe052000) +#define AED_DRC_RELEASE_COEF20 ((0x001e << 2) + 0xfe052000) +#define AED_DRC_RELEASE_COEF21 ((0x001f << 2) + 0xfe052000) +#define AED_DRC_RELEASE_COEF30 ((0x0020 << 2) + 0xfe052000) +#define AED_DRC_RELEASE_COEF31 ((0x0021 << 2) + 0xfe052000) +#define AED_DRC_RELEASE_COEF40 ((0x0022 << 2) + 0xfe052000) +#define AED_DRC_RELEASE_COEF41 ((0x0023 << 2) + 0xfe052000) +#define AED_DRC_RELEASE_COEF50 ((0x0024 << 2) + 0xfe052000) +#define AED_DRC_RELEASE_COEF51 ((0x0025 << 2) + 0xfe052000) +#define AED_DRC_ATTACK_COEF00 ((0x0026 << 2) + 0xfe052000) +#define AED_DRC_ATTACK_COEF01 ((0x0027 << 2) + 0xfe052000) +#define AED_DRC_ATTACK_COEF10 ((0x0028 << 2) + 0xfe052000) +#define AED_DRC_ATTACK_COEF11 ((0x0029 << 2) + 0xfe052000) +#define AED_DRC_ATTACK_COEF20 ((0x002a << 2) + 0xfe052000) +#define AED_DRC_ATTACK_COEF21 ((0x002b << 2) + 0xfe052000) +#define AED_DRC_ATTACK_COEF30 ((0x002c << 2) + 0xfe052000) +#define AED_DRC_ATTACK_COEF31 ((0x002d << 2) + 0xfe052000) +#define AED_DRC_ATTACK_COEF40 ((0x002e << 2) + 0xfe052000) +#define AED_DRC_ATTACK_COEF41 ((0x002f << 2) + 0xfe052000) +#define AED_DRC_ATTACK_COEF50 ((0x0030 << 2) + 0xfe052000) +#define AED_DRC_ATTACK_COEF51 ((0x0031 << 2) + 0xfe052000) +#define AED_DRC_LOOPBACK_CNTL ((0x0032 << 2) + 0xfe052000) +#define AED_MDRC_CNTL ((0x0033 << 2) + 0xfe052000) +#define AED_MDRC_RMS_COEF00 ((0x0034 << 2) + 0xfe052000) +#define AED_MDRC_RMS_COEF01 ((0x0035 << 2) + 0xfe052000) +#define AED_MDRC_RELEASE_COEF00 ((0x0036 << 2) + 0xfe052000) +#define AED_MDRC_RELEASE_COEF01 ((0x0037 << 2) + 0xfe052000) +#define AED_MDRC_ATTACK_COEF00 ((0x0038 << 2) + 0xfe052000) +#define AED_MDRC_ATTACK_COEF01 ((0x0039 << 2) + 0xfe052000) +#define AED_MDRC_THD0 ((0x003a << 2) + 0xfe052000) +#define AED_MDRC_K0 ((0x003b << 2) + 0xfe052000) +#define AED_MDRC_LOW_GAIN ((0x003c << 2) + 0xfe052000) +#define AED_MDRC_OFFSET0 ((0x003d << 2) + 0xfe052000) +#define AED_MDRC_RMS_COEF10 ((0x003e << 2) + 0xfe052000) +#define AED_MDRC_RMS_COEF11 ((0x003f << 2) + 0xfe052000) +#define AED_MDRC_RELEASE_COEF10 ((0x0040 << 2) + 0xfe052000) +#define AED_MDRC_RELEASE_COEF11 ((0x0041 << 2) + 0xfe052000) +#define AED_MDRC_ATTACK_COEF10 ((0x0042 << 2) + 0xfe052000) +#define AED_MDRC_ATTACK_COEF11 ((0x0043 << 2) + 0xfe052000) +#define AED_MDRC_THD1 ((0x0044 << 2) + 0xfe052000) +#define AED_MDRC_K1 ((0x0045 << 2) + 0xfe052000) +#define AED_MDRC_OFFSET1 ((0x0046 << 2) + 0xfe052000) +#define AED_MDRC_MID_GAIN ((0x0047 << 2) + 0xfe052000) +#define AED_MDRC_RMS_COEF20 ((0x0048 << 2) + 0xfe052000) +#define AED_MDRC_RMS_COEF21 ((0x0049 << 2) + 0xfe052000) +#define AED_MDRC_RELEASE_COEF20 ((0x004a << 2) + 0xfe052000) +#define AED_MDRC_RELEASE_COEF21 ((0x004b << 2) + 0xfe052000) +#define AED_MDRC_ATTACK_COEF20 ((0x004c << 2) + 0xfe052000) +#define AED_MDRC_ATTACK_COEF21 ((0x004d << 2) + 0xfe052000) +#define AED_MDRC_THD2 ((0x004e << 2) + 0xfe052000) +#define AED_MDRC_K2 ((0x004f << 2) + 0xfe052000) +#define AED_MDRC_OFFSET2 ((0x0050 << 2) + 0xfe052000) +#define AED_MDRC_HIGH_GAIN ((0x0051 << 2) + 0xfe052000) +#define AED_ED_CNTL ((0x0052 << 2) + 0xfe052000) +#define AED_DC_EN ((0x0053 << 2) + 0xfe052000) +#define AED_ND_LOW_THD ((0x0054 << 2) + 0xfe052000) +#define AED_ND_HIGH_THD ((0x0055 << 2) + 0xfe052000) +#define AED_ND_CNT_THD ((0x0056 << 2) + 0xfe052000) +#define AED_ND_SUM_NUM ((0x0057 << 2) + 0xfe052000) +#define AED_ND_CZ_NUM ((0x0058 << 2) + 0xfe052000) +#define AED_ND_SUM_THD0 ((0x0059 << 2) + 0xfe052000) +#define AED_ND_SUM_THD1 ((0x005a << 2) + 0xfe052000) +#define AED_ND_CZ_THD0 ((0x005b << 2) + 0xfe052000) +#define AED_ND_CZ_THD1 ((0x005c << 2) + 0xfe052000) +#define AED_ND_COND_CNTL ((0x005d << 2) + 0xfe052000) +#define AED_ND_RELEASE_COEF0 ((0x005e << 2) + 0xfe052000) +#define AED_ND_RELEASE_COEF1 ((0x005f << 2) + 0xfe052000) +#define AED_ND_ATTACK_COEF0 ((0x0060 << 2) + 0xfe052000) +#define AED_ND_ATTACK_COEF1 ((0x0061 << 2) + 0xfe052000) +#define AED_ND_CNTL ((0x0062 << 2) + 0xfe052000) +#define AED_MIX0_LL ((0x0063 << 2) + 0xfe052000) +#define AED_MIX0_RL ((0x0064 << 2) + 0xfe052000) +#define AED_MIX0_LR ((0x0065 << 2) + 0xfe052000) +#define AED_MIX0_RR ((0x0066 << 2) + 0xfe052000) +#define AED_CLIP_THD ((0x0067 << 2) + 0xfe052000) +#define AED_CH1_ND_SUM_OUT ((0x0068 << 2) + 0xfe052000) +#define AED_CH2_ND_SUM_OUT ((0x0069 << 2) + 0xfe052000) +#define AED_CH1_ND_CZ_OUT ((0x006a << 2) + 0xfe052000) +#define AED_CH2_ND_CZ_OUT ((0x006b << 2) + 0xfe052000) +#define AED_NOISE_STATUS ((0x006c << 2) + 0xfe052000) +#define AED_POW_CURRENT_S0 ((0x006d << 2) + 0xfe052000) +#define AED_POW_CURRENT_S1 ((0x006e << 2) + 0xfe052000) +#define AED_POW_CURRENT_S2 ((0x006f << 2) + 0xfe052000) +#define AED_POW_OUT0 ((0x0070 << 2) + 0xfe052000) +#define AED_POW_OUT1 ((0x0071 << 2) + 0xfe052000) +#define AED_POW_OUT2 ((0x0072 << 2) + 0xfe052000) +#define AED_POW_ADJ_INDEX0 ((0x0073 << 2) + 0xfe052000) +#define AED_POW_ADJ_INDEX1 ((0x0074 << 2) + 0xfe052000) +#define AED_POW_ADJ_INDEX2 ((0x0075 << 2) + 0xfe052000) +#define AED_DRC_GAIN_INDEX0 ((0x0076 << 2) + 0xfe052000) +#define AED_DRC_GAIN_INDEX1 ((0x0077 << 2) + 0xfe052000) +#define AED_DRC_GAIN_INDEX2 ((0x0078 << 2) + 0xfe052000) +#define AED_CH1_VOLUME_STATE ((0x0079 << 2) + 0xfe052000) +#define AED_CH2_VOLUME_STATE ((0x007a << 2) + 0xfe052000) +#define AED_CH1_VOLUME_GAIN ((0x007b << 2) + 0xfe052000) +#define AED_CH2_VOLUME_GAIN ((0x007c << 2) + 0xfe052000) +#define AED_FULL_POW_CURRENT ((0x007d << 2) + 0xfe052000) +#define AED_FULL_POW_OUT ((0x007e << 2) + 0xfe052000) +#define AED_FULL_POW_ADJ ((0x007f << 2) + 0xfe052000) +#define AED_FULL_DRC_GAIN ((0x0080 << 2) + 0xfe052000) +#define AED_MASTER_VOLUME_STATE ((0x0081 << 2) + 0xfe052000) +#define AED_MASTER_VOLUME_GAIN ((0x0082 << 2) + 0xfe052000) +#define AED_TOP_CTL0 ((0x0083 << 2) + 0xfe052000) +#define AED_TOP_CTL1 ((0x0084 << 2) + 0xfe052000) +#define AED_TOP_CTL2 ((0x0085 << 2) + 0xfe052000) +//======================================================================== +// AUDIO locker - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe051400 +// ----------------------------------------------- +#define AUD_LOCK_EN ((0x0000 << 2) + 0xfe051400) +#define AUD_LOCK_SW_RESET ((0x0001 << 2) + 0xfe051400) +#define AUD_LOCK_SW_LATCH ((0x0002 << 2) + 0xfe051400) +#define AUD_LOCK_HW_LATCH ((0x0003 << 2) + 0xfe051400) +#define AUD_LOCK_REFCLK_SRC ((0x0004 << 2) + 0xfe051400) +#define AUD_LOCK_REFCLK_LAT_INT ((0x0005 << 2) + 0xfe051400) +#define AUD_LOCK_IMCLK_LAT_INT ((0x0006 << 2) + 0xfe051400) +#define AUD_LOCK_OMCLK_LAT_INT ((0x0007 << 2) + 0xfe051400) +#define AUD_LOCK_REFCLK_DS_INT ((0x0008 << 2) + 0xfe051400) +#define AUD_LOCK_IMCLK_DS_INT ((0x0009 << 2) + 0xfe051400) +#define AUD_LOCK_OMCLK_DS_INT ((0x000a << 2) + 0xfe051400) +#define AUD_LOCK_INT_CLR ((0x000b << 2) + 0xfe051400) +#define AUD_LOCK_GCLK_CTRL ((0x000c << 2) + 0xfe051400) +#define AUD_LOCK_INT_CTRL ((0x000d << 2) + 0xfe051400) +#define RO_REF2IMCLK_CNT_L ((0x0010 << 2) + 0xfe051400) +#define RO_REF2IMCLK_CNT_H ((0x0011 << 2) + 0xfe051400) +#define RO_REF2OMCLK_CNT_L ((0x0012 << 2) + 0xfe051400) +#define RO_REF2OMCLK_CNT_H ((0x0013 << 2) + 0xfe051400) +#define RO_IMCLK2REF_CNT_L ((0x0014 << 2) + 0xfe051400) +#define RO_IMCLK2REF_CNT_H ((0x0015 << 2) + 0xfe051400) +#define RO_OMCLK2REF_CNT_L ((0x0016 << 2) + 0xfe051400) +#define RO_OMCLK2REF_CNT_H ((0x0017 << 2) + 0xfe051400) +#define RO_REFCLK_PKG_CNT ((0x0018 << 2) + 0xfe051400) +#define RO_IMCLK_PKG_CNT ((0x0019 << 2) + 0xfe051400) +#define RO_OMCLK_PKG_CNT ((0x001a << 2) + 0xfe051400) +#define RO_AUD_LOCK_INT_STATUS ((0x001b << 2) + 0xfe051400) +//======================================================================== +// AUDIO VAD - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe051800 +// ----------------------------------------------- +// +// Reading file: VAD_REG.h +// +#define VAD_TOP_CTRL0 ((0x0000 << 2) + 0xfe051800) +#define VAD_TOP_CTRL1 ((0x0001 << 2) + 0xfe051800) +#define VAD_TOP_CTRL2 ((0x0002 << 2) + 0xfe051800) +#define VAD_FIR_CTRL ((0x0003 << 2) + 0xfe051800) +#define VAD_FIR_EMP ((0x0004 << 2) + 0xfe051800) +#define VAD_FIR_COEF0 ((0x0005 << 2) + 0xfe051800) +#define VAD_FIR_COEF1 ((0x0006 << 2) + 0xfe051800) +#define VAD_FIR_COEF2 ((0x0007 << 2) + 0xfe051800) +#define VAD_FIR_COEF3 ((0x0008 << 2) + 0xfe051800) +#define VAD_FIR_COEF4 ((0x0009 << 2) + 0xfe051800) +#define VAD_FIR_COEF5 ((0x000a << 2) + 0xfe051800) +#define VAD_FIR_COEF6 ((0x000b << 2) + 0xfe051800) +#define VAD_FIR_COEF7 ((0x000c << 2) + 0xfe051800) +#define VAD_FIR_COEF8 ((0x000d << 2) + 0xfe051800) +#define VAD_FIR_COEF9 ((0x000e << 2) + 0xfe051800) +#define VAD_FIR_COEF10 ((0x000f << 2) + 0xfe051800) +#define VAD_FIR_COEF11 ((0x0010 << 2) + 0xfe051800) +#define VAD_FIR_COEF12 ((0x0011 << 2) + 0xfe051800) +#define VAD_FRAME_CTRL0 ((0x0012 << 2) + 0xfe051800) +#define VAD_FRAME_CTRL1 ((0x0013 << 2) + 0xfe051800) +#define VAD_FRAME_CTRL2 ((0x0014 << 2) + 0xfe051800) +#define VAD_CEP_CTRL0 ((0x0015 << 2) + 0xfe051800) +#define VAD_CEP_CTRL1 ((0x0016 << 2) + 0xfe051800) +#define VAD_CEP_CTRL2 ((0x0017 << 2) + 0xfe051800) +#define VAD_CEP_CTRL3 ((0x0018 << 2) + 0xfe051800) +#define VAD_CEP_CTRL4 ((0x0019 << 2) + 0xfe051800) +#define VAD_CEP_CTRL5 ((0x001a << 2) + 0xfe051800) +#define VAD_DEC_CTRL ((0x001b << 2) + 0xfe051800) +#define VAD_TOP_STS0 ((0x001c << 2) + 0xfe051800) +#define VAD_TOP_STS1 ((0x001d << 2) + 0xfe051800) +#define VAD_TOP_STS2 ((0x001e << 2) + 0xfe051800) +#define VAD_FIR_STS0 ((0x001f << 2) + 0xfe051800) +#define VAD_FIR_STS1 ((0x0020 << 2) + 0xfe051800) +#define VAD_POW_STS0 ((0x0021 << 2) + 0xfe051800) +#define VAD_POW_STS1 ((0x0022 << 2) + 0xfe051800) +#define VAD_POW_STS2 ((0x0023 << 2) + 0xfe051800) +#define VAD_FFT_STS0 ((0x0024 << 2) + 0xfe051800) +#define VAD_FFT_STS1 ((0x0025 << 2) + 0xfe051800) +#define VAD_SPE_STS0 ((0x0026 << 2) + 0xfe051800) +#define VAD_SPE_STS1 ((0x0027 << 2) + 0xfe051800) +#define VAD_SPE_STS2 ((0x0028 << 2) + 0xfe051800) +#define VAD_SPE_STS3 ((0x0029 << 2) + 0xfe051800) +#define VAD_DEC_STS0 ((0x002a << 2) + 0xfe051800) +#define VAD_DEC_STS1 ((0x002b << 2) + 0xfe051800) +#define VAD_LUT_CTRL ((0x002c << 2) + 0xfe051800) +#define VAD_LUT_WR ((0x002d << 2) + 0xfe051800) +#define VAD_LUT_RD ((0x002e << 2) + 0xfe051800) +#define VAD_IN_SEL0 ((0x002f << 2) + 0xfe051800) +#define VAD_IN_SEL1 ((0x0030 << 2) + 0xfe051800) +#define VAD_TO_DDR ((0x0031 << 2) + 0xfe051800) +// +// Closing file: VAD_REG.h +// +//======================================================================== +// AUDIO RESAMPLEA - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe051c00 +// ----------------------------------------------- +// +// Reading file: RESAMPLE.h +// +#define AUDIO_RSAMP_CTRL0 ((0x0000 << 2) + 0xfe051c00) +//Bit 31:3 reserved +//Bit 2 reg_lock_rst //unsigned , default =0; +//Bit 1 reg_rsamp_rst //unsigned , default =0; +//Bit 0 reg_sw_rst //unsigned , default =0; +#define AUDIO_RSAMP_CTRL1 ((0x0001 << 2) + 0xfe051c00) +//Bit 31:26 reserved //unsigned , default =0; +//Bit 25 reg_rsamp_rst_sel //unsigned , default =0; +//Bit 24 reg_module_bypas //unsigned , default =0; +//Bit 23:18 reg_gclk_ctrl //unsigned , default =0; +//Bit 17:13 reg_in_msb //unsigned , default =23; +//Bit 12 reg_output_en //unsigned , default =0; +//Bit 11 reg_rsamp_en //unsigned , default =0; +//Bit 10 reg_filt_en //unsigned , default =0; +//Bit 9 reg_post_en //unsigned , default =0; +//Bit 8 reg_inp_mux_mode //unsigned , default =0; +//Bit 7:4 reserved //unsigned , default =2; +//Bit 3:0 reg_inp_mux //unsigned , default =0; +#define AUDIO_RSAMP_CTRL2 ((0x0002 << 2) + 0xfe051c00) +//Bit 31:30 reserved //unsigned , default =0; +//Bit 29:24 reg_chx_size //unsigned , default =2; +//Bit 23:18 reserved //unsigned , default =0; +//Bit 17:16 reg_scl_step //unsigned , default =0; 0: 1/1 1: 1/2 2: 1/4 +//Bit 15:8 reg_filt_tap //unsigned , default =63; +//Bit 7:0 reg_intp_tap //unsigned , default =63; +#define AUDIO_RSAMP_PHSINIT ((0x0003 << 2) + 0xfe051c00) +//Bit 31:28 reserved //unsigned , default = 0; +//Bit 27:0 reg_init_phs //unsigned , default = 0; +#define AUDIO_RSAMP_PHSSTEP ((0x0004 << 2) + 0xfe051c00) +//Bit 31 reserved //unsigned , default = 0; +//Bit 30:0 reg_rsamp_step //unsigned , default = 134217728;//'h800_0000 +#define AUDIO_RSAMP_SHIFT ((0x0005 << 2) + 0xfe051c00) +//Bit 31:24 reg_rsft_iir //unsigned , default = 23; +//Bit 23:16 reg_rsft_blnd //unsigned , default = 21; +//Bit 15:8 reg_rsft_sinc //unsigned , default = 31; +//Bit 7:0 reg_rsft_aa //unsigned , default = 31; +#define AUDIO_RSAMP_ADJ_CTRL0 ((0x0006 << 2) + 0xfe051c00) +//Bit 31:3 reserved //unsigned +//Bit 2 reg_rsamp_adj_out_inv //unsigned , default = 0; +//Bit 1 reg_rsamp_adj_force_en //unsigned , default = 0; +//Bit 0 reg_rsamp_adj_en //unsigned , default = 0; +#define AUDIO_RSAMP_ADJ_CTRL1 ((0x0007 << 2) + 0xfe051c00) +//Bit 31:16 reg_rsamp_adj_odet_step //unsigned , default = 8; +//Bit 15:0 reg_rsamp_adj_kmax //unsigned , default = 32768; +#define AUDIO_RSAMP_ADJ_SFT ((0x0008 << 2) + 0xfe051c00) +//Bit 31:30 reserved //unsigned , default = 0; +//Bit 29 reg_rsamp_adj_dif_sel //unsigned , default = 0; +//Bit 28:24 reg_rsamp_adj_ki //unsigned , default = 9; +//Bit 23:21 reserved //unsigned , default = 0; +//Bit 20:16 reg_rsamp_adj_kp //unsigned , default = 1; +//Bit 15:13 reserved //unsigned , default = 0; +//Bit 12:8 reg_rsamp_adj_ki_sft //unsigned , default = 6; +//Bit 7:6 reserved //unsigned , default = 0; +//Bit 5:0 reg_rsamp_adj_out_sft //unsigned , default = 12; +#define AUDIO_RSAMP_ADJ_IDET_LEN ((0x0009 << 2) + 0xfe051c00) +//Bit 31:0 reg_rsamp_adj_idet_len //unsigned , default = 10000; +#define AUDIO_RSAMP_ADJ_FORCE ((0x000a << 2) + 0xfe051c00) +//Bit 31:0 reg_rsamp_adj_force_err //signed , default = 8; +#define AUDIO_RSAMP_ADJ_KI_FORCE ((0x000b << 2) + 0xfe051c00) +//Bit 31:0 reg_rsamp_adj_ki_force //signed , default = 0; +#define AUDIO_RSAMP_RO_STATUS ((0x0010 << 2) + 0xfe051c00) +//Bit 31:0 ro_rsamp_stat //{din_chx_chk_err,is_idle_st,rsamp_fifo_over_cnt[7:0]} +#define AUDIO_RSAMP_RO_ADJ_FREQ ((0x0011 << 2) + 0xfe051c00) +//Bit 31:0 ro_rsamp_adj_freq +#define AUDIO_RSAMP_RO_ADJ_DIFF_BAK ((0x0012 << 2) + 0xfe051c00) +//Bit 31:0 ro_det_diff_bak +#define AUDIO_RSAMP_RO_ADJ_DIFF_DLT ((0x0013 << 2) + 0xfe051c00) +//Bit 31:0 ro_det_diff_dlt +#define AUDIO_RSAMP_RO_ADJ_PHS_ERR ((0x0014 << 2) + 0xfe051c00) +//Bit 31:0 ro_det_phase_err +#define AUDIO_RSAMP_RO_ADJ_KI_OUT ((0x0015 << 2) + 0xfe051c00) +//Bit 31:0 ro_rsamp_ki_out +#define AUDIO_RSAMP_RO_IN_CNT ((0x0016 << 2) + 0xfe051c00) +//Bit 31:0 ro_rsamp_in_cnt +#define AUDIO_RSAMP_RO_OUT_CNT ((0x0017 << 2) + 0xfe051c00) +//Bit 31:0 ro_rsamp_out_cnt +#define AUDIO_RSAMP_POST_COEF0 ((0x0020 << 2) + 0xfe051c00) +//Bit 31:0 reg_post_coef0 //signed , default = 0; +#define AUDIO_RSAMP_POST_COEF1 ((0x0021 << 2) + 0xfe051c00) +//Bit 31:0 reg_post_coef1 //signed , default = 0; +#define AUDIO_RSAMP_POST_COEF2 ((0x0022 << 2) + 0xfe051c00) +//Bit 31:0 reg_post_coef2 //signed , default = 0; +#define AUDIO_RSAMP_POST_COEF3 ((0x0023 << 2) + 0xfe051c00) +//Bit 31:0 reg_post_coef3 //signed , default = 0; +#define AUDIO_RSAMP_POST_COEF4 ((0x0024 << 2) + 0xfe051c00) +//Bit 31:0 reg_post_coef4 //signed , default = 0; +#define AUDIO_RSAMP_AA_COEF_ADDR ((0x0030 << 2) + 0xfe051c00) +//Bit 31:0 reg_aa_coef_addr //unsigned, default = 0; +#define AUDIO_RSAMP_AA_COEF_DATA ((0x0031 << 2) + 0xfe051c00) +//Bit 31:0 reg_aa_coef_data //signed , default = 0; +#define AUDIO_RSAMP_SINC_COEF_ADDR ((0x0040 << 2) + 0xfe051c00) +//Bit 31:0 reg_sinc_coef_addr //unsigned, default = 0; +#define AUDIO_RSAMP_SINC_COEF_DATA ((0x0041 << 2) + 0xfe051c00) +//Bit 31:0 reg_sinc_coef_data //signed , default = 0; +// +// Closing file: RESAMPLE.h +// +//======================================================================== +// AUDIO TOP_VAD - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe054800 +// ----------------------------------------------- +#define EE_AUDIO2_CLK81_CTRL ((0x0000 << 2) + 0xfe054800) +#define EE_AUDIO2_CLK81_EN ((0x0001 << 2) + 0xfe054800) +#define EE_AUDIO2_SW_RESET0 ((0x0002 << 2) + 0xfe054800) +#define EE_AUDIO2_CLK_GATE_EN0 ((0x0003 << 2) + 0xfe054800) +#define EE_AUDIO2_SECURITY_CTRL0 ((0x0004 << 2) + 0xfe054800) +#define EE_AUDIO2_MCLK_VAD_CTRL ((0x0010 << 2) + 0xfe054800) +#define EE_AUDIO2_VAD_CLK_CTRL ((0x0011 << 2) + 0xfe054800) +#define EE_AUDIO2_MST_DLY_CTRL0 ((0x0012 << 2) + 0xfe054800) +#define EE_AUDIO2_MST_VAD_SCLK_CTRL0 ((0x0013 << 2) + 0xfe054800) +#define EE_AUDIO2_MST_VAD_SCLK_CTRL1 ((0x0014 << 2) + 0xfe054800) +#define EE_AUDIO2_CLK_TDMIN_VAD_CTRL ((0x0015 << 2) + 0xfe054800) +#define EE_AUDIO2_CLK_PDMIN_CTRL0 ((0x0016 << 2) + 0xfe054800) +#define EE_AUDIO2_CLK_PDMIN_CTRL1 ((0x0017 << 2) + 0xfe054800) +#define EE_AUDIO2_TOVAD_CTRL0 ((0x0020 << 2) + 0xfe054800) +#define EE_AUDIO2_TODDR_VAD_CTRL0 ((0x0030 << 2) + 0xfe054800) +#define EE_AUDIO2_TODDR_VAD_CTRL1 ((0x0031 << 2) + 0xfe054800) +#define EE_AUDIO2_TODDR_VAD_CTRL2 ((0x0032 << 2) + 0xfe054800) +#define EE_AUDIO2_TODDR_VAD_START_ADDR ((0x0033 << 2) + 0xfe054800) +#define EE_AUDIO2_TODDR_VAD_INIT_ADDR ((0x0034 << 2) + 0xfe054800) +#define EE_AUDIO2_TODDR_VAD_FINISH_ADDR ((0x0035 << 2) + 0xfe054800) +#define EE_AUDIO2_TODDR_VAD_START_ADDRB ((0x0036 << 2) + 0xfe054800) +#define EE_AUDIO2_TODDR_VAD_FINISH_ADDRB ((0x0037 << 2) + 0xfe054800) +#define EE_AUDIO2_TODDR_VAD_INT_ADDR ((0x0038 << 2) + 0xfe054800) +#define EE_AUDIO2_TODDR_VAD_STATUS1 ((0x0039 << 2) + 0xfe054800) +#define EE_AUDIO2_TODDR_VAD_STATUS2 ((0x003a << 2) + 0xfe054800) +#define EE_AUDIO2_TDMIN_VAD_CTRL ((0x0040 << 2) + 0xfe054800) +#define EE_AUDIO2_TDMIN_VAD_SWAP0 ((0x0041 << 2) + 0xfe054800) +#define EE_AUDIO2_TDMIN_VAD_SWAP1 ((0x0042 << 2) + 0xfe054800) +#define EE_AUDIO2_TDMIN_VAD_MUTE_VAL ((0x0043 << 2) + 0xfe054800) +#define EE_AUDIO2_TDMIN_VAD_STAT ((0x0044 << 2) + 0xfe054800) +#define EE_AUDIO2_TDMIN_VAD_MUTE0 ((0x0050 << 2) + 0xfe054800) +#define EE_AUDIO2_TDMIN_VAD_MUTE1 ((0x0051 << 2) + 0xfe054800) +#define EE_AUDIO2_TDMIN_VAD_MUTE2 ((0x0052 << 2) + 0xfe054800) +#define EE_AUDIO2_TDMIN_VAD_MUTE3 ((0x0053 << 2) + 0xfe054800) +#define EE_AUDIO2_TDMIN_VAD_MUTE4 ((0x0054 << 2) + 0xfe054800) +#define EE_AUDIO2_TDMIN_VAD_MUTE5 ((0x0055 << 2) + 0xfe054800) +#define EE_AUDIO2_TDMIN_VAD_MUTE6 ((0x0056 << 2) + 0xfe054800) +#define EE_AUDIO2_TDMIN_VAD_MUTE7 ((0x0057 << 2) + 0xfe054800) +#define EE_AUDIO2_TDMIN_VAD_MASK0 ((0x0058 << 2) + 0xfe054800) +#define EE_AUDIO2_TDMIN_VAD_MASK1 ((0x0059 << 2) + 0xfe054800) +#define EE_AUDIO2_TDMIN_VAD_MASK2 ((0x005a << 2) + 0xfe054800) +#define EE_AUDIO2_TDMIN_VAD_MASK3 ((0x005b << 2) + 0xfe054800) +#define EE_AUDIO2_TDMIN_VAD_MASK4 ((0x005c << 2) + 0xfe054800) +#define EE_AUDIO2_TDMIN_VAD_MASK5 ((0x005d << 2) + 0xfe054800) +#define EE_AUDIO2_TDMIN_VAD_MASK6 ((0x005e << 2) + 0xfe054800) +#define EE_AUDIO2_TDMIN_VAD_MASK7 ((0x005f << 2) + 0xfe054800) +// +// Closing file: REG_LIST_AUDIO_RTL.h +// +// +// Reading file: ../spifc/rtl/spifc_reg.vh +// +//`ifdef SPIFC_REG_DEFINE +//`else +//`define SPIFC_REG_DEFINE +//`define SPIFC BASE ADDR 32'hfd000400 +// ----------------------------------------------- +// APB_BASE: APB2_BASE_ADDR = 0xfd000400 +// ----------------------------------------------- +//AHB domain regsiter. +#define SPIFC_AHB_CTRL ((0x0000 << 2) + 0xfd000400) + //bit 31 AHB BUS enable. 1 enable ahb request. 0: disable ahb request. + //bit 30. decerr_en for (AXI->AHB bridge). + //bit 29. force_incr. for ( AXI->AHB bridge). + //bit 19. critical word first. CWF_EN. 1: enable. 0 : disable. + //bit 18:17 RDBUF_SIZE . 00: 64bytes. 01: 32 bytes. 10: 16 bytes. 11: reserved. + //bit 16 AHB MASTER enable. if enabled, each master use one dedicated HRDATA buffer inside ahb2api model. total 3 HRDATA buffers inside ahb2spi. + //if disabled the 3 HRDATA buffer will random be used for all masters. + //bit 14 write 1 to clean the HRDATA buffer 2. read 0 finished clean operation. + //bit 13 write 1 to clean the HRDATA buffer 1. read 0 finished clean operation. + //bit 12 write 1 to clean the HRDATA buffer 0. read 0 finished clean operation. + //bit 11:0. not used. +#define SPIFC_CLK_CTRL ((0x0001 << 2) + 0xfd000400) + //bit 14 asynchronous buffer ahb clock disable. 1 = disable. 0 = enable. + //bit 13 ahb2spi ahb clock disable. 1 = disable. 0 = enable. + //bit 12 ahb_arb ahb clock disable. 1 = disable. 0 = enable. + //bit 10 asynchronous buffer ahb clock auto gating enable. 1 = enable. 0 = disable. + //bit 9 ahb2spi ahb clock auto gating enable. 1 = enable. 0 = disable. + //bit 8 ahbarb ahb clock auto gating enable. 1 = enable. 0 = disable. + //bit 2. asynchronous AHB clock domain software reset. 1 = reset. 0 = normal working mode. + //bit 1. ahb2spi ahb clock domain software reset. 1 = reset. 0 = normal working mode. + //bit 0. not used. +#define SPIFC_SEC_CTRL ((0x0002 << 2) + 0xfd000400) + //bit 31. ADDRESS security range enable. 1 = enable; 0: disable. + //bit 14. range6 enable: 1: enable; 0 : disable. + //bit 13. range5 enable: 1: enable; 0 : disable. + //bit 12. range4 enable: 1: enable; 0 : disable. + //bit 11. range3 enable: 1: enable; 0 : disable. + //bit 10. range2 enable: 1: enable; 0 : disable. + //bit 9. range1 enable: 1: enable; 0 : disable. + //bit 8. range0 enable: 1: enable; 0 : disable. + //bit 7:4 to control spi clock register security. bit 7 = 1, APB bus can access spi clock domain register. bit 7 == 0 : only PPROT[0] == bit 4, the APB can access spic clock domain register. + //bit 3:0 to control ahb clock domain register secruity. bit 3 = 1, APB bus can access ahb clock domain register. bit 3 ==0; only PPROT[0] == bit 0, the APB can access ahb clock domain register. +#define SPIFC_RANGE0_STA ((0x0010 << 2) + 0xfd000400) + //bit 28 :6. + //AHB security range 0 start address in unit of 64Byte. related to HADDR bit 28:6. + //bit 5:0. always 0. +#define SPIFC_RANGE0_EDA ((0x0011 << 2) + 0xfd000400) + //bit 28 :6. + //AHB security range 0 end address in unit of 64Byte. related to HADDR bit 28:6. + //bit 5:0. always 0. +#define SPIFC_RANGE0_CTRL ((0x0012 << 2) + 0xfd000400) + // AHB secruity range 0 control. + //bit 15:8 range 0 access control for DMA access. + //bit 15 range 0 access control for DMA thread 7 + //bit 14 range 0 access control for DMA Thread 6 + //bit 13 range 0 access control for DMA Thread 5. + //bit 12 range 0 access control for DMA Thread 4. + // bit 11. range 0 access control for DMA thread 3 + // bit 10. range 0 access control for DMA Thread 2 + // bit 9. range 0 access control for DMA Thread 1. + // bit 8. range 0 access control for DMA Thread 0. + // bit 7. range 0 access control for HMASTER == 7 Not used. + // bit 6. range 0 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA. + // bit 5. range 0 access control for HMASTER == 5 //DSPB non secure + // bit 4. range 0 access control for HMASTER == 4 //DSPB non secure + // bit 3. range 0 access control for HMASTER == 3 //DSPA secure + // bit 2. range 0 access control for HMASTER == 2 //DSPA non secure + // bit 1. range 0 access control for HMASTER == 1 //CPU secure access + // bit 0. range 0 access control for HMASTER == 0 //CPU non secure. +#define SPIFC_RANGE1_STA ((0x0013 << 2) + 0xfd000400) + //bit 28 :6. + //AHB security range 1 start address in unit of 64Byte. related to HADDR bit 28:6. + //bit 5:0. always 0. +#define SPIFC_RANGE1_EDA ((0x0014 << 2) + 0xfd000400) + //bit 28 :6. + //AHB security range 1 end address in unit of 64Byte. related to HADDR bit 28:6. + //bit 5:0. always 0. +#define SPIFC_RANGE1_CTRL ((0x0015 << 2) + 0xfd000400) + // AHB secruity range 1 control. + //bit 15:8 range 1 access control for DMA access. + //bit 15 range 1 access control for DMA thread 7 + //bit 14 range 1 access control for DMA Thread 6 + //bit 13 range 1 access control for DMA Thread 5. + //bit 12 range 1 access control for DMA Thread 4. + // bit 11. range 1 access control for DMA thread 3 + // bit 10. range 1 access control for DMA Thread 2 + // bit 9. range 1 access control for DMA Thread 1. + // bit 8. range 1 access control for DMA Thread 0. + // bit 7. range 1 access control for HMASTER == 7 Not used. + // bit 6. range 1 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA. + // bit 5. range 1 access control for HMASTER == 5 //DSPB non secure + // bit 4. range 1 access control for HMASTER == 4 //DSPB non secure + // bit 3. range 1 access control for HMASTER == 3 //DSPA secure + // bit 2. range 1 access control for HMASTER == 2 //DSPA non secure + // bit 1. range 1 access control for HMASTER == 1 //CPU secure access + // bit 0. range 1 access control for HMASTER == 0 //CPU non secure. +#define SPIFC_RANGE2_STA ((0x0016 << 2) + 0xfd000400) + //bit 28 :6. + //AHB security range 2 start address in unit of 64Byte. related to HADDR bit 28:6. + //bit 5:0. always 0. +#define SPIFC_RANGE2_EDA ((0x0017 << 2) + 0xfd000400) + //bit 28 :6. + //AHB security range 2 end address in unit of 64Byte. related to HADDR bit 28:6. + //bit 5:0. always 0. +#define SPIFC_RANGE2_CTRL ((0x0018 << 2) + 0xfd000400) + // AHB secruity range 2 control. + //bit 15:8 range 2 access control for DMA access. + //bit 15 range 2 access control for DMA thread 7 + //bit 14 range 2 access control for DMA Thread 6 + //bit 13 range 2 access control for DMA Thread 5. + //bit 12 range 2 access control for DMA Thread 4. + // bit 11. range 2 access control for DMA thread 3 + // bit 10. range 2 access control for DMA Thread 2 + // bit 9. range 2 access control for DMA Thread 1. + // bit 8. range 2 access control for DMA Thread 0. + // bit 7. range 2 access control for HMASTER == 7 Not used. + // bit 6. range 2 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA. + // bit 5. range 2 access control for HMASTER == 5 //DSPB non secure + // bit 4. range 2 access control for HMASTER == 4 //DSPB non secure + // bit 3. range 2 access control for HMASTER == 3 //DSPA secure + // bit 2. range 2 access control for HMASTER == 2 //DSPA non secure + // bit 1. range 2 access control for HMASTER == 1 //CPU secure access + // bit 0. range 2 access control for HMASTER == 0 //CPU non secure. +#define SPIFC_RANGE3_STA ((0x0019 << 2) + 0xfd000400) + //bit 28 :6. + //AHB security range 3 start address in unit of 64Byte. related to HADDR bit 28:6. + //bit 5:0. always 0. +#define SPIFC_RANGE3_EDA ((0x001a << 2) + 0xfd000400) + //bit 28 :6. + //AHB security range 3 end address in unit of 64Byte. related to HADDR bit 28:6. + //bit 5:0. always 0. +#define SPIFC_RANGE3_CTRL ((0x001b << 2) + 0xfd000400) + // AHB secruity range 3 control. + //bit 15:8 range 3 access control for DMA access. + //bit 15 range 3 access control for DMA thread 7 + //bit 14 range 3 access control for DMA Thread 6 + //bit 13 range 3 access control for DMA Thread 5. + //bit 12 range 3 access control for DMA Thread 4. + // bit 11. range 3 access control for DMA thread 3 + // bit 10. range 3 access control for DMA Thread 2 + // bit 9. range 3 access control for DMA Thread 1. + // bit 8. range 3 access control for DMA Thread 0. + // bit 7. range 3 access control for HMASTER == 7 Not used. + // bit 6. range 3 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA. + // bit 5. range 3 access control for HMASTER == 5 //DSPB non secure + // bit 4. range 3 access control for HMASTER == 4 //DSPB non secure + // bit 3. range 3 access control for HMASTER == 3 //DSPA secure + // bit 2. range 3 access control for HMASTER == 2 //DSPA non secure + // bit 1. range 3 access control for HMASTER == 1 //CPU secure access + // bit 0. range 3 access control for HMASTER == 0 //CPU non secure. +#define SPIFC_RANGE4_STA ((0x001c << 2) + 0xfd000400) + //bit 28 :6. + //AHB security range 4 start address in unit of 64Byte. related to HADDR bit 28:6. + //bit 5:0. always 0. +#define SPIFC_RANGE4_EDA ((0x001d << 2) + 0xfd000400) + //bit 28 :6. + //AHB security range 4 end address in unit of 64Byte. related to HADDR bit 28:6. + //bit 5:0. always 0. +#define SPIFC_RANGE4_CTRL ((0x001e << 2) + 0xfd000400) + // AHB secruity range 4 control. + //bit 15:8 range 4 access control for DMA access. + //bit 15 range 4 access control for DMA thread 7 + //bit 14 range 4 access control for DMA Thread 6 + //bit 13 range 4 access control for DMA Thread 5. + //bit 12 range 4 access control for DMA Thread 4. + // bit 11. range 4 access control for DMA thread 3 + // bit 10. range 4 access control for DMA Thread 2 + // bit 9. range 4 access control for DMA Thread 1. + // bit 8. range 4 access control for DMA Thread 0. + // bit 7. range 4 access control for HMASTER == 7 Not used. + // bit 6. range 4 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA. + // bit 5. range 4 access control for HMASTER == 5 //DSPB non secure + // bit 4. range 4 access control for HMASTER == 4 //DSPB non secure + // bit 3. range 4 access control for HMASTER == 3 //DSPA secure + // bit 2. range 4 access control for HMASTER == 2 //DSPA non secure + // bit 1. range 4 access control for HMASTER == 1 //CPU secure access + // bit 0. range 4 access control for HMASTER == 0 //CPU non secure. +#define SPIFC_RANGE5_STA ((0x001f << 2) + 0xfd000400) + //bit 28 :6. + //AHB security range 5 start address in unit of 64Byte. related to HADDR bit 28:6. + //bit 5:0. always 0. +#define SPIFC_RANGE5_EDA ((0x0021 << 2) + 0xfd000400) + //bit 28 :6. + //AHB security range 5 end address in unit of 64Byte. related to HADDR bit 28:6. + //bit 5:0. always 0. +#define SPIFC_RANGE5_CTRL ((0x0020 << 2) + 0xfd000400) + // AHB secruity range 5 control. + //bit 15:8 range 5 access control for DMA access. + //bit 15 range 5 access control for DMA thread 7 + //bit 14 range 5 access control for DMA Thread 6 + //bit 13 range 5 access control for DMA Thread 5. + //bit 12 range 5 access control for DMA Thread 4. + // bit 11. range 5 access control for DMA thread 3 + // bit 10. range 5 access control for DMA Thread 2 + // bit 9. range 5 access control for DMA Thread 1. + // bit 8. range 5 access control for DMA Thread 0. + // bit 7. range 5 access control for HMASTER == 7 Not used. + // bit 6. range 5 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA. + // bit 5. range 5 access control for HMASTER == 5 //DSPB non secure + // bit 4. range 5 access control for HMASTER == 4 //DSPB non secure + // bit 3. range 5 access control for HMASTER == 3 //DSPA secure + // bit 2. range 5 access control for HMASTER == 2 //DSPA non secure + // bit 1. range 5 access control for HMASTER == 1 //CPU secure access + // bit 0. range 5 access control for HMASTER == 0 //CPU non secure. +#define SPIFC_RANGE6_STA ((0x0022 << 2) + 0xfd000400) + //bit 28 :6. + //AHB security range 6 start address in unit of 64Byte. related to HADDR bit 28:6. + //bit 5:0. always 0. +#define SPIFC_RANGE6_EDA ((0x0023 << 2) + 0xfd000400) + //bit 28 :6. + //AHB security range 6 end address in unit of 64Byte. related to HADDR bit 28:6. + //bit 5:0. always 0. +#define SPIFC_RANGE6_CTRL ((0x0024 << 2) + 0xfd000400) + // AHB secruity range 6 control. + //bit 15:8 range 6 access control for DMA access. + //bit 15 range 6 access control for DMA thread 7 + //bit 14 range 6 access control for DMA Thread 6 + //bit 13 range 6 access control for DMA Thread 5. + //bit 12 range 6 access control for DMA Thread 4. + // bit 11. range 6 access control for DMA thread 3 + // bit 10. range 6 access control for DMA Thread 2 + // bit 9. range 6 access control for DMA Thread 1. + // bit 8. range 6 access control for DMA Thread 0. + // bit 7. range 6 access control for HMASTER == 7 Not used. + // bit 6. range 6 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA. + // bit 5. range 6 access control for HMASTER == 5 //DSPB non secure + // bit 4. range 6 access control for HMASTER == 4 //DSPB non secure + // bit 3. range 6 access control for HMASTER == 3 //DSPA secure + // bit 2. range 6 access control for HMASTER == 2 //DSPA non secure + // bit 1. range 6 access control for HMASTER == 1 //CPU secure access + // bit 0. range 6 access control for HMASTER == 0 //CPU non secure. +#define SPIFC_RANGE7_CTRL ((0x0025 << 2) + 0xfd000400) + // AHB secruity range 7( default range) control. + //bit 15:8 range 7 access control for DMA access. + //bit 15 range 7 access control for DMA thread 7 + //bit 14 range 7 access control for DMA Thread 6 + //bit 13 range 7 access control for DMA Thread 5. + //bit 12 range 7 access control for DMA Thread 4. + // bit 11. range 7 access control for DMA thread 3 + // bit 10. range 7 access control for DMA Thread 2 + // bit 9. range 7 access control for DMA Thread 1. + // bit 8. range 7 access control for DMA Thread 0. + // bit 7. range 7 access control for HMASTER == 7 Not used. + // bit 6. range 7 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA. + // bit 5. range 7 access control for HMASTER == 5 //DSPB non secure + // bit 4. range 7 access control for HMASTER == 4 //DSPB non secure + // bit 3. range 7 access control for HMASTER == 3 //DSPA secure + // bit 2. range 7 access control for HMASTER == 2 //DSPA non secure + // bit 1. range 7 access control for HMASTER == 1 //CPU secure access + // bit 0. range 7 access control for HMASTER == 0 //CPU non secure. +#define SPIFC_AHB_WTCH_CTRL ((0x0026 << 2) + 0xfd000400) + //bit 15:0. ahb bus watch dog timer. if AHB bus not response, the timer over this number, the SPIFC will send back a error response. +#define SPIFC_SEC_VIO0 ((0x0027 << 2) + 0xfd000400) + //bit 31:0 VIO ADDR +#define SPIFC_SEC_VIO1 ((0x0028 << 2) + 0xfd000400) + //bit 31. AHB VIO status. write 1 to clear the error info. + //bit 6:5 HMASTER. + //bit 4:2 HPROT. + //bit 1 HNONSEC. + //bit 0 HWRITE. +#define SPIFC_AHB_STS ((0x0029 << 2) + 0xfd000400) + //bit 31. AHB IDLE. when ahb disabled, to show ahb status. 1, no more ahb request or ahb requent is holded. 0, ahb is still busy. + //bit 30. AHB data cycle status, when ahb disabled, to show ahb data cycle status. 1, data cycle is holded, 0 : not in data cycle or data cycle is processing. + //bit 29. AHB bus spi requst status. 1: still waiting for spi data. 0: idle. + //bit 28:0. not used. +//SPI cts_spi_clk domain regsiter. +#define SPIFC_USER_CTRL0 ((0x0080 << 2) + 0xfd000400) + //bit 31. user request enable. write 1 to enable. read 0, means user command accepted by the SPI_CTRL. + //bit 30. user request finish bit. write 0 when enable user request. read 1 means SPI_CTRL finished this user command. + //bit 0. user data updated. write 0 when enable user request. 1 means there's datas/status read from SPI flash. +#define SPIFC_USER_CTRL1 ((0x0081 << 2) + 0xfd000400) + //bit 31. not used. + //bit 30. user command cycle enable. 1) enable. 0) don't send command in usr command period. + //bit 29:28. user command mode. 00 = SPI extend mode. 01 : dual mode. 10: quad mode. + //bit 27:20. user command code. the code need to send in command period. + //bit 19. user address cycle enable. + //bit 18:17 user address mode: 00 = SPI extend mode. 01 : dual mode. 10: quad mode. + //bit 16:15 user address Byte length 00 = 1 byte. 01 = 2 bytes. 10 = 3 bytes. 11 = 4bytes. + //bit 14 user datout enable. + //bit 13 user dataout AES enable. 1: dataout through AES describle. 0 : original data. + //bit 12 user data output source. 0: from data buffer. 1: from status register. + //bit 11:10 user dataout mode: 00 SPI extend model. 01 : dual model. 10. quad mode. + //bit 9:0 User data out bytes num. +#define SPIFC_USER_CTRL2 ((0x0082 << 2) + 0xfd000400) + //bit 31 usr_dummy_en 1: enable dummy cycles. 0 : no dummy cycles. + //bit 30: 29 usr_dummy_mode 2'b00 = SPI extend mode. 01 dual mode. 10 Quad mode. + //bit 28:23 user dummy clock cycle number. + //bit 19:16. user command input/output direction control. 000000: right after the last output. + // 1: after the first cycle of dummy cycle. + // ..... + // 4'hf: right before the datin cycle. + //bit 15:8. data on the dummy cycle after the first byte. + //bit 7:0 The first bytes data showed on dummy cycle. some flash may need special data for enhance performance mode or XIP mode. +#define SPIFC_USER_CTRL3 ((0x0083 << 2) + 0xfd000400) + //bit 31 usr_datin_en 1: datain cycle enabled. 0: no datain cycle. + //bit 30: datin_dest. 1: save the input data to STATUS register. 0 save the input data to data buffer. + //bit 29: 1: enable datain data AES describle. 0: not use AES. + //bit 28:27. datin mode. 2'b00 SPI extend mode. 01: dual mode. 10 Quad mode. + //bit 25:16. user data in data bytes. how many bytes of user datain expected. +#define SPIFC_USER_ADDR ((0x0084 << 2) + 0xfd000400) + //bit 31:0. 32bits user address. +#define SPIFC_AHB_REQ_CTRL ((0x0085 << 2) + 0xfd000400) + //bit 31. AHB request enable. + //bit 30 AHB cmd_en. command cycle enable. + //bit 29:28. ahb command mode. 2'b00: spi mode. 01: dual mode. 10 Quad mode. + //bit 27:20:.AHB command code. + //bit 19. ahb request address cycle enable. + //bit 18:17 AHB ADDRESS mode. 2'b00: spi mode. 01: dual mode. 10 Quad mode. + //bit 16:15 AHB ADDRESS data width. 2'b00: 1byte. 2'b01 : 2bytes. 2'b10: 3bytes. 2'b11 4bytes. + //bit 13:10 AHB request spi bus input switch time. 0 : after address cycle. 1: the frist dummy cycles. ... 0xf. after dummy cycle. + //bit 9:8 AHB DATAIN mode. 2'b00: spi mode. 01: dual mode. 10 Quad mode. + //bit 7 DATA IN AES enable. 1: enable 0: disable. + //bit 1:0 AHB REQ DATA size. 2'b00: 64bytes. 2'b01: 32 bytes. 2'b10 : 16 bytes. 2'b11: reserved. this bit settign should be same as RDBUF_SIZE setting. +#define SPIFC_AHB_REQ_CTRL1 ((0x0086 << 2) + 0xfd000400) + //bit 31. ahb Dummy enable. + //bit 30:29. ahb dummy mode. + //bit 28:23. ahb request dummy clock cycles. + //bit 15:0. ahb dummy period output data. +#define SPIFC_AHB_REQ_CTRL2 ((0x0087 << 2) + 0xfd000400) + //bit 1:0 AHB address position. this settign depend on SPIFC_AHB_CTRL register CWF_EN bit and RDBUF_SIZE. + // if CWF_EN is enabled. these bit should be set to 2'b10 (16BYTE boundary). + // if CWF_EN is disabled. these bit should be set to same as the RDBUF_SIZE and AHB REQ DATA SIZE. + //00 : 64byte boundary. + //01 : 32byte boundary. + //10 : 16byte boundary. + //11 : reserved. +#define SPIFC_ACTIMING0 ((0x0088 << 2) + 0xfd000400) + //bit 31:30. tSLCH + //bit 29:28 tCLSH + //bit 20:16 tSHWL + //bit 15:12 tSHSL2 + //bit 11:8 tSHSL1 + //bit 7:0 tWHSL +#define SPIFC_ACTIMING1 ((0x0089 << 2) + 0xfd000400) + //bit 31. D2 pin WP_n function enable. + //bit 30. D2 Pin value in WP_n fucntion. + //bit 29. D3 Pin HOLD_n function enable. + //bit 8. DTR mode. not support. + //bit 6:4. Clock turn around delay. use it to set the system SPI clock read data delay. + //bit 3:0. not used. +#define SPIFC_ACTIMING2 ((0x008a << 2) + 0xfd000400) + //bit 31. spi clock input pin enable. SPIFC controller used this pin as clock to latch the input data. + //bit [3:0] spi clock input pin delay adjustment. +//SPI DATA BUFFER. There's a total 512Byte + 64byte(orgnized as 36x128bits) SRAM . +// since each APB access is 32bits. So we use word address as APB read/write address. +// But for SPI side we have to use 128bit boundary. That's the first Pragram/read SPI with data buffer must start at data buffer 128bit boundary. that means the SPIFC_USE_DBUF_ADDR last 2 bits must be 0. +#define SPIFC_DBUF_CTRL ((0x0090 << 2) + 0xfd000400) + //bit 31. 1 = write DBUF. 0 : read DBUF. + //bit 30. 1. = auto update address. 0 don't change address. + //bit 7:0 DBUF address unit 32bits. +#define SPIFC_DBUF_DATA ((0x0091 << 2) + 0xfd000400) + //bit 31:0. if SPIFC_DBUF_CTRL bit 31 = 1. write to this register will trigger one write to DBUF. and the data will be writen to DBUF. +#define SPIFC_USER_DBUF_ADDR ((0x0092 << 2) + 0xfd000400) + //bit 7:0. the DBUF ADDRESS used to send to or receive from SPI FLASH. the last 2 bits must be 0. +#define SPIFC_FLASH_STATUS ((0x00a0 << 2) + 0xfd000400) +#define SPIFC_STATUS ((0x00a1 << 2) + 0xfd000400) + //bit 1. AES KEY valid. read only 1 : The aes key is ready to use. 0: the aes key is not ready. + //bit 0. SPI CTRL STATE IDLE. read only. 1 = idle; 0 = busy. +#define SPIFC_CTRL ((0x00a2 << 2) + 0xfd000400) + //bit 15:14. mempd for DBUF MEMORY. + //bit 13 spifc asynchronous buffer clock disable. 1 = disable. 0 = enable. + //bit 12. spifc controller clock disable. 1 = disable. 0 = enable. + //bit 9. spifc asynchronous bufer clock auto gate enable. 1 = enable. 0 = disable. + //bit 8. spifc controller clock auto gate enable. 1 = enable. 0 = disable. + //bit 2. spifc interface reset. 1 = RESET. 0 = normal working mode. + //bit 1. spifc asynchronous buffer spi clock side reset. 1 = RESET. 0 : normal working mode. + //bit 0. spifc controller reset. 1 = RESET. 0 : normal working mode. +//`endif +// +// Closing file: ../spifc/rtl/spifc_reg.vh +// +// +// Reading file: ../psram/rtl/psram_reg.vh +// +//`ifdef PSRAM_REG_DEFINE +//`else +//`define PSRAM_REG_DEFINE +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe007400 +// ----------------------------------------------- +#define PSRAM_AXI_INTF_CTRL ((0x0000 << 2) + 0xfe007400) + //bit 3 axi interface soft reset. 1 = reset AXI interface. 0 = normal. + //bit 2 disable axi interface clock. 1 = disable; 0 = enable. + //bit 1 axi interface auto clock gating enable. 1 = enable; 0 = disable. + //bit 0 axi interface AXI request enable. 1 = enable. 0 = disable. +#define PSRAM_DBUF_CTRL ((0x0001 << 2) + 0xfe007400) + //bit 16. MWRITE_EN. 1 : enabel mask write(with DM pin). 0 not enable. + //bit 15:0 DBUF AGE to write back to PSRAM if DBUF is dirty. but whole DBUF data is not READ to write.(with MWRITE enabled). +#define PSRAM_DBUF_CTRL1 ((0x0002 << 2) + 0xfe007400) + //bit 15:0 DBUF AGE to write back to psram if DBUF is dirty and whole DBUF data is ready to write. +#define PSRAM_APB_CTRL ((0x0003 << 2) + 0xfe007400) + //7:4 PSRAM PHY register APB secure contrl. + //bit 7, 1: no secure control. 0 : use bit 4 to match PPROT[0] bit. + //bit 4. when bit 7 == 0, bit 4 must match PPROT[0] to access. + //3:0 PCTL_CTRL APB bus control regsiters secure control. + //bit 3, 1: no secure control. 0 : use bit 0 to match PPROT[0] bit. + //bit 0. when bit 3 == 0, bit 0 must match PPROT[0] to access. +#define PSRAM_SEC_CTRL ((0x0004 << 2) + 0xfe007400) + //bit 31. ADDRESS security range enable. 1 = enable; 0: disable. + //if scruity range disabled, but AXI data describle enabled key0 is selected. + //bit 23 range 7 des key selection 0 : key0; 1: key1; + //bit 22 range 6 des key selection 0 : key0; 1: key1; + //bit 21 range 5 des key selection 0 : key0; 1: key1; + //bit 20 range 4 des key selection 0 : key0; 1: key1; + //bit 19 range 3 des key selection 0 : key0; 1: key1; + //bit 18 range 2 des key selection 0 : key0; 1: key1; + //bit 17 range 1 des key selection 0 : key0; 1: key1; + //bit 16 range0 des key selection 0 : key0; 1: key1; + //bit 6. range6 enable: 1: enable; 0 : disable. + //bit 5. range5 enable: 1: enable; 0 : disable. + //bit 4. range4 enable: 1: enable; 0 : disable. + //bit 3. range3 enable: 1: enable; 0 : disable. + //bit 2. range2 enable: 1: enable; 0 : disable. + //bit 1. range1 enable: 1: enable; 0 : disable. + //bit 0. range0 enable: 1: enable; 0 : disable. +#define PSRAM_DES_PADDING ((0x0005 << 2) + 0xfe007400) + //bit 31 :0 Padding, with address together to generate describle 64 bits input. +#define PSRAM_RANGE0_STA ((0x0010 << 2) + 0xfe007400) + //bit 22 :0. + //AXI security range 0 start address in unit of 64Byte. related to HADDR bit 28:6. +#define PSRAM_RANGE0_EDA ((0x0011 << 2) + 0xfe007400) + //bit 22 :0. + //AXI security range 0 end address in unit of 64Byte. related to HADDR bit 28:6. +#define PSRAM_RANGE0_CTRL0 ((0x0012 << 2) + 0xfe007400) + // AXI secruity range 0 control. +#define PSRAM_RANGE0_CTRL1 ((0x0013 << 2) + 0xfe007400) + // AXI secruity range 0 control. +#define PSRAM_RANGE1_STA ((0x0014 << 2) + 0xfe007400) + //bit 22 :0. + //AXI security range 1 start address in unit of 64Byte. related to HADDR bit 28:6. +#define PSRAM_RANGE1_EDA ((0x0015 << 2) + 0xfe007400) + //bit 22 :0. + //AXI security range 1 end address in unit of 64Byte. related to HADDR bit 28:6. +#define PSRAM_RANGE1_CTRL0 ((0x0016 << 2) + 0xfe007400) + // AXI secruity range 1 control. +#define PSRAM_RANGE1_CTRL1 ((0x0017 << 2) + 0xfe007400) + // AXI secruity range 1 control. +#define PSRAM_RANGE2_STA ((0x0018 << 2) + 0xfe007400) + //bit 31 : 6. + //AXI security range 2 start address in unit of 64Byte. related to HADDR bit 28:6. +#define PSRAM_RANGE2_EDA ((0x0019 << 2) + 0xfe007400) + //bit 31 :6. + //AXI security range 2 end address in unit of 64Byte. related to HADDR bit 28:6. +#define PSRAM_RANGE2_CTRL0 ((0x001a << 2) + 0xfe007400) +#define PSRAM_RANGE2_CTRL1 ((0x001b << 2) + 0xfe007400) +#define PSRAM_RANGE3_STA ((0x001c << 2) + 0xfe007400) + //bit 31 : 6. + //AXI security range 3 start address in unit of 64Byte. related to HADDR bit 28:6. +#define PSRAM_RANGE3_EDA ((0x001d << 2) + 0xfe007400) + //bit 31 :6. + //AXI security range 3 end address in unit of 64Byte. related to HADDR bit 28:6. +#define PSRAM_RANGE3_CTRL0 ((0x001e << 2) + 0xfe007400) + // AXI secruity range 3 control. +#define PSRAM_RANGE3_CTRL1 ((0x001f << 2) + 0xfe007400) + // AXI secruity range 3 control. +#define PSRAM_RANGE4_STA ((0x0020 << 2) + 0xfe007400) + //bit 31 :6. + //AXI security range 4 start address in unit of 64Byte. related to HADDR bit 28:6. +#define PSRAM_RANGE4_EDA ((0x0021 << 2) + 0xfe007400) + //bit 31 :6. + //AXI security range 4 end address in unit of 64Byte. related to HADDR bit 28:6. +#define PSRAM_RANGE4_CTRL0 ((0x0022 << 2) + 0xfe007400) + // AXI secruity range 4 control. +#define PSRAM_RANGE4_CTRL1 ((0x0023 << 2) + 0xfe007400) +#define PSRAM_RANGE5_STA ((0x0024 << 2) + 0xfe007400) + //bit 22 :0. + //AXI security range 5 start address in unit of 64Byte. related to HADDR bit 28:6. +#define PSRAM_RANGE5_EDA ((0x0025 << 2) + 0xfe007400) + //bit 22 :0. + //AXI security range 5 end address in unit of 64Byte. related to HADDR bit 28:6. +#define PSRAM_RANGE5_CTRL0 ((0x0026 << 2) + 0xfe007400) + // AXI secruity range 5 control. +#define PSRAM_RANGE5_CTRL1 ((0x0027 << 2) + 0xfe007400) + // AXI secruity range 5 control. +#define PSRAM_RANGE6_STA ((0x0028 << 2) + 0xfe007400) + //bit 22 :0. + //AXI security range 6 start address in unit of 64Byte. related to HADDR bit 28:6. +#define PSRAM_RANGE6_EDA ((0x0029 << 2) + 0xfe007400) + //bit 22 :0. + //AXI security range 6 end address in unit of 64Byte. related to HADDR bit 28:6. +#define PSRAM_RANGE6_CTRL0 ((0x002a << 2) + 0xfe007400) + // AXI secruity range 6 control. +#define PSRAM_RANGE6_CTRL1 ((0x002b << 2) + 0xfe007400) + // AXI secruity range 6 control. +#define PSRAM_RANGE7_CTRL0 ((0x002c << 2) + 0xfe007400) +#define PSRAM_RANGE7_CTRL1 ((0x002d << 2) + 0xfe007400) +#define PSRAM_VIO_STATUS ((0x002e << 2) + 0xfe007400) + //bit 31: security violation. write 1 to clean security violation status. + //bit 30. 1 : AXI write violation. 0 : axi read violation. + //bit 18:16. AXI ARPROT/AWPROT> + //bit 11:0. AXI violation ID. +#define PSRAM_VIO_ADDR ((0x002f << 2) + 0xfe007400) + //read only + //31:0 AXI violation address. +#define PSRAM_USER_CTRL0 ((0x0080 << 2) + 0xfe007400) + //bit 31. user request enable. write 1 to enable. read 0, means user command accepted by the SPI_CTRL. + //bit 30. usr request done. after user command done. this bit set to 1. + //bit 29. USR COMMAND enable. + //bit 28. command type0. 1 READ command. 0 write command. + //bit 27. command type1. 1 for register. 0 : for memory. + //bit 21~16. USR command clock cycles + //bit 15~0. USR COMMAND CODE. +#define PSRAM_USER_CTRL1 ((0x0081 << 2) + 0xfe007400) + //bit 31. USR_ADDR_EN + //bit 30:29. USR_ADDR_DW + //bit 28~20. USR address clock cycle number. + //bit 19:16 USR data output/input switch postion + //bit 15. USR DUMMY ENABLE + //bit 13~8. USR DUMMY clock cycles. + //bit 5:0 USR data DQS read enable postion. +#define PSRAM_USER_CTRL2 ((0x0082 << 2) + 0xfe007400) + //bit 31 usr des key selection. 1 : key 1; 0 : key 0. + //bit 30. usr check latency. for Winbond PSRAM data read/write, DQS input indentify the latency is doubled or not. + //bit 29. usr data des enable. + //bit 28 usr datain enable. + //bit 27. usr datain destination. 1 : write to CFG_STS register. 0 : write to DATA REGISTERs. + //bit 26~16 usr data in clock cycle number. + //bit 15. usr datout enable. + //bit 14. usr data out source 1 : from CFG_STS register. 0 from DATA register. + //bit 13~11. not used. + //bit 10~0. usr dataout clock cycles. +#define PSRAM_USER_CTRL3 ((0x0083 << 2) + 0xfe007400) + //bit 17:16. which cycle to ask phy to check read/write latency at PSRAM SEND COMMOND stage. + //since PSRAM send command stage only 3 clock cycle. So this number only can chose 0, 1, 2. + //bit 15:0. user dummy data when output in dummy cycle. +#define PSRAM_USER_ADDR ((0x0084 << 2) + 0xfe007400) + //bit 31:0. 32bits user address. +#define PSRAM_AXI_REQ_CTRL0 ((0x0085 << 2) + 0xfe007400) + //bit 31. AXI request enable. + //bit 30 AXI cmd_en. command cycle enable. + //bit 29:24. AXI request command cycle clock numbers. + //bit 22. AXI request address cycle enable. + //bit 21:16. AXI request address cycle clock number. + //bit 15:14. AXI address cycle data width. + //bit 13:12. at which clock cycle to send signal to phy to check latency flag for WINBOND PSRAM flexible latency. + //since PSRAM send command stage only 3 clock cycle. So this number only can chose 0, 1, 2. + //bit 6 // AXI Write dummy enable. + //bit 5:0 // axi write dummy clock cycle number. +#define PSRAM_AXI_REQ_CTRL1 ((0x0086 << 2) + 0xfe007400) + //bit 31:16. AXI request psram READ command code. + //bit 15:0. AXI request psram write command code. +#define PSRAM_AXI_REQ_CTRL2 ((0x0087 << 2) + 0xfe007400) + //bit 31. AXI read request Dummy enable. + //bit 30. Check latency enable for WINBOND PSRAM flexible latency. + //bit 27:22. clock cycles in dummy stage to eanble PSRAM PHY reading logic. + //bit 21:16. axi_read dummy clock cycles number. + //bit 15:0. dummy data if output in dummy cycles. +#define PSRAM_AXI_REQ_CTRL3 ((0x0088 << 2) + 0xfe007400) + //bit 31 des enable. + //bit 26:16. DATA input clock cycles. + //bit 10:0. DATA output clock cycles. +#define PSRAM_ACTIMING0 ((0x0089 << 2) + 0xfe007400) + //bit 31:30. tSLCH + //bit 29:28 tCLSH + //bit 20:16 tSHWL + //bit 15:12 tSHSL2 + //bit 11:8 tSHSL1 + //bit 7:0 tWHSL +#define PSRAM_ACTIMING1 ((0x008a << 2) + 0xfe007400) + //bit 7:0 tRWR for winbond PSRAM, = tRWR -3. Winbond PSRAM include one CS cycle and 2 command cycle. + //for APMEMORY should be same value of tCPH +#define PSRAM_ACTIMING2 ((0x008b << 2) + 0xfe007400) +#define PSRAM_WDG_CTRL ((0x008c << 2) + 0xfe007400) + //bit [31] 1: force to reset PSRAM PCTL and PHY logic. 0: normal. + //bit [30] 1: automatic reset PSRAM PCTL and PHY logic if watch dog triggered. + //bit 12:0. watch dog timer. for Winbond PSRAM should be 1us for tRC. for APMEMORY should be 1us for tCEM. +//SPI DATA BUFFER. There's a total 512KByte + 64byte(orgnized as 36x128bits) SRAM . +// since each APB access is 32bits. So we use word address as APB read/write address. +// But for SPI side we have to use 128bit boundary. That's the first Pragram/read SPI with data buffer must start at data buffer 128bit boundary. that means the PSRAM_USE_DBUF_ADDR last 2 bits must be 0. +#define PSRAM_DBUF_0 ((0x0090 << 2) + 0xfe007400) +#define PSRAM_DBUF_1 ((0x0091 << 2) + 0xfe007400) +#define PSRAM_DBUF_2 ((0x0092 << 2) + 0xfe007400) +#define PSRAM_DBUF_3 ((0x0093 << 2) + 0xfe007400) +#define PSRAM_DBUF_4 ((0x0094 << 2) + 0xfe007400) +#define PSRAM_DBUF_5 ((0x0095 << 2) + 0xfe007400) +#define PSRAM_DBUF_6 ((0x0096 << 2) + 0xfe007400) +#define PSRAM_DBUF_7 ((0x0097 << 2) + 0xfe007400) +#define PSRAM_DBUF_8 ((0x0098 << 2) + 0xfe007400) +#define PSRAM_DBUF_9 ((0x0099 << 2) + 0xfe007400) +#define PSRAM_DBUF_A ((0x009a << 2) + 0xfe007400) +#define PSRAM_DBUF_B ((0x009b << 2) + 0xfe007400) +#define PSRAM_DBUF_C ((0x009c << 2) + 0xfe007400) +#define PSRAM_DBUF_D ((0x009d << 2) + 0xfe007400) +#define PSRAM_DBUF_E ((0x009e << 2) + 0xfe007400) +#define PSRAM_DBUF_F ((0x009f << 2) + 0xfe007400) +#define PSRAM_CFG_STS ((0x00a0 << 2) + 0xfe007400) + //32bits register to save the USR read command read back values. +#define PSRAM_STATUS ((0x00a1 << 2) + 0xfe007400) + //bit 31. usr_req_done flag. 1 : user request done . write 1 to clean. + //bit 30~11. + //bit 10:8 + //bit 7:3. + //bit 2. axi_data buffer idle bit. 1 : idle. 0 : working. + //bit 1. axi interface idle bit. 1 : idle. 0 : working. + //bit 0. psram ctrl idle bit. 1 : idle. 0 : working. +#define PSRAM_CTRL ((0x00a2 << 2) + 0xfe007400) + //bit 31. PSRAM in DTR mode. + //bit 30. psram input data latch clock select. 1: from clock input pin. 0: from DQS + //if use clock input pin as data input latch clock, bit 13:12 should select 01. + //bit 29:27. PSRAM mode. + //'b000 : STR SPI mode. + //'b001 : STR QPI mode. + //'b010 : DTR QPI mode. + //'b011 : DTR OPI FLASH. + //'b100 : APmemory PSRAM mode. + //'b101 : Winbond PSRAM mode. + //bit 26. enable to generation interruption after usr request done. 1: enable. 0: disable. + //bit 25. to enable APMEMORY 2 command cycle mode. 1 : enable : 0: 3 command cycles. + //bit 24. to enable the psram clock output always enable. 1 : enable. 0: disable. + //bit 23. to enable the psram clock output extend mode to cover APMEMORY tCPI. + //bit 22. to disable the CKN output. 1: disable PSRAM CK_N pin output. 0: CK_N working normal. + //bit 21. PSRAM DATA IN/OUT high 8bit and low 8 bit endian. 1 : rising edge is low byte. falling edge data is high byte. 0 : rising edge is high byte. falling edge data is low byte. + //bit 20. PSRAM ADDRESS unit. 1: Byte. 0 : word. + // APMEMORY used byte address. Winbond use word address. + //bit 19. DQSEN generation. if use dqs to latch input data, this bit should be set to 1 to ask DMC generate ENABLE singal in dummy stage. 0: not generate DQS_EN. + //bit 18. PSRAM RESET I/O oe_n value. if need RESET pin. + //bit 17. PSRAM RESET I/O output vale. if need reset pin. + //bit 16. force CS output low. for APMEMORY exit DPPD mode. 1: to force cs output low : 0 output normal working mode. + //bit 13:12. psram data in clock enable selection. 00: use DQSEN. 01: use clkin cnt. + //bit 11. DM Disable. 1: disable DM output. 0: with dmoutput. + //bit 9. psram pctl auto clock gating enable. 1: enable. 0 : disable. + //bit 8. psram pctl clock disable. 1: disable. 0 : enable. + //bit 2 PSRAM SPI mode, DQ2 works as WP(write protection mode). + //bit 1. DQ2 WP mode value. + //bit 0. PSRAM SPI mode, DQ3 works as HOLD function. +#define PSRAM_PIN_CTRL ((0x00a3 << 2) + 0xfe007400) +//bit 30:28 DATA 6 DQ pin selection. +//bit 27:24 DATA 6 DQ pin selection. +//bit 22:20 DATA 5 DQ pin selection. +//bit 18:16 DATA 4 DQ pin selection. +//bit 14:12 DATA 3 DQ pin selection. +//bit 10:8 DATA 2 DQ pin selection. +//bit 6:4 DATA 1 DQ pin selection. +//bit 2:0 DATA 0 DQ pin selection. + //0 : from DQ[0] + //1 : from DQ[1] + //2 : from DQ[2] + //3 : from DQ[3] + //4 : from DQ[4] + //5 : from DQ[5] + //6 : from DQ[6] + //7 : from DQ[7] +//psram_dly_16 is used for all DQ[0~] in/out/oen delay adjustment. +//psram_dly_16 consists of 15 delay cells, one delay cell is 50ps delay( typical corner). +//psram_dly_16 is control by delay_sel[3:0]. 0 = no delay. 1~15 controls how many delay cells used. +//psram_dly_16 can be controlled by each control register either with real delay mode or VT updated with 4xclock period. +//psram_lcdl is used for DQS/DQSN input and CK/CKN output delay 90degree delay generation and/or delay fine tune. +//psram_lcdl consits of 96 delay cells, same delay cell used in psram_dly_16. +//psram_lcdl should be calibrated with the psram_4xclock. and tracked with psram_4xclock with VT updated. +#define PSRAM_DQ0_DIN_DLY ((0x00c0 << 2) + 0xfe007400) + //bit 6:0. DQ0 DIN delay control. in DLY16 real mode, only [3:0] is valid. +#define PSRAM_DQ1_DIN_DLY ((0x00c1 << 2) + 0xfe007400) + //bit 6:0. DQ1 input delay control. in DLY16 read mode, only [3:0] is valid. +#define PSRAM_DQ2_DIN_DLY ((0x00c2 << 2) + 0xfe007400) + //bit 6:0. DQ2 input delay control. in DLY16 real mode, only [3:0] is valid. +#define PSRAM_DQ3_DIN_DLY ((0x00c3 << 2) + 0xfe007400) + //bit 6:0. DQ3 input delay control. in DLY16 real mode, only [3:0] is valid. +#define PSRAM_DQ4_DIN_DLY ((0x00c4 << 2) + 0xfe007400) + //bit 6:0. DQ4 input delay control. in DLY16 real mode, only [3:0] is valid. +#define PSRAM_DQ5_DIN_DLY ((0x00c5 << 2) + 0xfe007400) + //bit 6:0. DQ5 input delay control. in DLY16 real mode, only [3:0] is valid. +#define PSRAM_DQ6_DIN_DLY ((0x00c6 << 2) + 0xfe007400) + //bit 6:0. DQ6 input delay control. in DLY16 real mode, only [3:0] is valid. +#define PSRAM_DQ7_DIN_DLY ((0x00c7 << 2) + 0xfe007400) + //bit 6:0. DQ7 input delay control. in DLY16 real mode, only [3:0] is valid. +#define PSRAM_DQ0_DOUT_DLY ((0x00c8 << 2) + 0xfe007400) + //bit 6:0. DQ0 DOUT delay control. in DLY16 real mode, only [3:0] is valid. +#define PSRAM_DQ1_DOUT_DLY ((0x00c9 << 2) + 0xfe007400) + //bit 6:0. DQ1 output delay control. in DLY16 read mode, only [3:0] is valid. +#define PSRAM_DQ2_DOUT_DLY ((0x00ca << 2) + 0xfe007400) + //bit 6:0. DQ2 output delay control. in DLY16 real mode, only [3:0] is valid. +#define PSRAM_DQ3_DOUT_DLY ((0x00cb << 2) + 0xfe007400) + //bit 6:0. DQ3 output delay control. in DLY16 real mode, only [3:0] is valid. +#define PSRAM_DQ4_DOUT_DLY ((0x00cc << 2) + 0xfe007400) + //bit 6:0. DQ4 output delay control. in DLY16 real mode, only [3:0] is valid. +#define PSRAM_DQ5_DOUT_DLY ((0x00cd << 2) + 0xfe007400) + //bit 6:0. DQ5 output delay control. in DLY16 real mode, only [3:0] is valid. +#define PSRAM_DQ6_DOUT_DLY ((0x00ce << 2) + 0xfe007400) + //bit 6:0. DQ6 output delay control. in DLY16 real mode, only [3:0] is valid. +#define PSRAM_DQ7_DOUT_DLY ((0x00cf << 2) + 0xfe007400) + //bit 6:0. DQ7 output delay control. in DLY16 real mode, only [3:0] is valid. +#define PSRAM_DQ0_OEN_DLY ((0x00d0 << 2) + 0xfe007400) + //bit 6:0. DQ0 OEN delay control. in DLY16 real mode, only [3:0] is valid. +#define PSRAM_DQ1_OEN_DLY ((0x00d1 << 2) + 0xfe007400) + //bit 6:0. DQ1 output enable delay control. in DLY16 read mode, only [3:0] is valid. +#define PSRAM_DQ2_OEN_DLY ((0x00d2 << 2) + 0xfe007400) + //bit 6:0. DQ2 output enable delay control. in DLY16 real mode, only [3:0] is valid. +#define PSRAM_DQ3_OEN_DLY ((0x00d3 << 2) + 0xfe007400) + //bit 6:0. DQ3 output enable delay control. in DLY16 real mode, only [3:0] is valid. +#define PSRAM_DQ4_OEN_DLY ((0x00d4 << 2) + 0xfe007400) + //bit 6:0. DQ4 output enable delay control. in DLY16 real mode, only [3:0] is valid. +#define PSRAM_DQ5_OEN_DLY ((0x00d5 << 2) + 0xfe007400) + //bit 6:0. DQ5 output enable delay control. in DLY16 real mode, only [3:0] is valid. +#define PSRAM_DQ6_OEN_DLY ((0x00d6 << 2) + 0xfe007400) + //bit 6:0. DQ6 output enable delay control. in DLY16 real mode, only [3:0] is valid. +#define PSRAM_DQ7_OEN_DLY ((0x00d7 << 2) + 0xfe007400) + //bit 6:0. DQ7 output enable delay control. in DLY16 real mode, only [3:0] is valid. +#define PSRAM_DM_DOUT_DLY ((0x00d8 << 2) + 0xfe007400) + //bit 6:0. DM output delay control. in DLY16 real mode, only [3:0] is valid. +#define PSRAM_DM_OEN_DLY ((0x00d9 << 2) + 0xfe007400) + //bit 6:0. DM output enable delay control. in DLY16 real mode, only [3:0] is valid. +#define PSRAM_CS_DOUT_DLY ((0x00da << 2) + 0xfe007400) + //bit 6:0. CS output delay control. in DLY16 real mode, only [3:0] is valid. +#define PSRAM_DQS_DIN_DLY ((0x00db << 2) + 0xfe007400) + //bit 6:0. DQS input delay control. unit = 1/64 UI with PSRAM_LCDL_CTRL bit 28 = 0; + // unit = 1 delay cell, with PSRAM_LCDL_CTRL bit 28 = 1; +#define PSRAM_DQSN_DIN_DLY ((0x00dc << 2) + 0xfe007400) + //bit 6:0. DQSN input delay control. unit = 1/64 UI with PSRAM_LCDL_CTRL bit 28 = 0; + // unit = 1 delay cell, with PSRAM_LCDL_CTRL bit 28 = 1; +#define PSRAM_CKN_DOUT_DLY ((0x00dd << 2) + 0xfe007400) + //bit 6:0. CKN output delay control. unit = 1/64 UI with PSRAM_LCDL_CTRL bit 28 = 0; + // unit = 1 delay cell, with PSRAM_LCDL_CTRL bit 28 = 1; +#define PSRAM_CK_DOUT_DLY ((0x00de << 2) + 0xfe007400) + //bit 6:0. CK output delay control. unit = 1/64 UI with PSRAM_LCDL_CTRL bit 28 = 0; + // unit = 1 delay cell, with PSRAM_LCDL_CTRL bit 28 = 1; +#define PSRAM_RDEN_DLY ((0x00df << 2) + 0xfe007400) + //bit 10:7. READ enable phase delay. unit = 1UI. for AP QPI PSRAM. PSRAM only send one cycle DQS preamble. + // We have to used this UI delay to compensate the whole clock output delay and the DQS input delay. + // if run high frequency, this delay need to be trained. the valid value from 0 ~ 12. Since one UI is 1/4 of PSRAM clock, + // the total delay of the clock output delay + input delay should be less than 3 PSRAM clock. + //bit 6:0. READ enable fine tune delay control. unit = 1/64 UI with PSRAM_LCDL_CTRL bit 28 = 0; + // unit = 1 delay cell, with PSRAM_LCDL_CTRL bit 28 = 1; +#define PSRAM_LCDL_CTRL ((0x00f0 << 2) + 0xfe007400) + //bit 31. write 1 to update all delay cell delays control. + //bit 30. write 1 to calibration LCDL. + //bit 29. LCDL track enable. 1: enable LCDL auto track VT changes. + //bit 28. LCDL delay control mode. + //1 : real delay mode. For DQS/DQSN/CKN/CK/RDEN delay control register, one number means one delay cells. + //0 : UI MODE. For DQS/DQSN/CKN/CK/RDEN delay control register, one number means 1/64 psram_4xclk period. + //bit 27. DLY16 ( psram_dly_16 cell) delay control mode. + //1 : real delay mode. For all data delay control register, one number means one delay cells. + //0 : UI MODE. For all data delay control register, one number means 1/64 psram_4xclk period. + //bit 27:24. not used. + //bit 23:0. timer do trigger LCDL track the VT once. each track will compensate the UI with 1/16 delay cell delay. +//LCDL calibration ctroller. +#define PSRAM_LCDL_CAL_CTRL1 ((0x00f1 << 2) + 0xfe007400) + //27:24. which LCDL delay line used to run calibration. + //19:16. LCDL calibration loop end position. + //15:12. LCDL calibration loop initial position. + //10:0. LCDL calibration initial phase counter. +#define PSRAM_LCDL_CAL_CTRL2 ((0x00f2 << 2) + 0xfe007400) + //26:16 LCDL phase lock limit. if the lcdl phase counter difference between 2 calibration loops is less than this number, The LCDL would be locked and stop the calibration. + //10:0. deta_init. the first loop phase changing number. +#define PSRAM_LCDL_CAL_CTRL3 ((0x00f3 << 2) + 0xfe007400) + //29:25 to configure LCDL calibration step 5 position. + //24:20 to configure LCDL calibration step 4 position. + //19:15 to configure LCDL calibration step 3 position. + //14:10 to configure LCDL calibration step 2 position. + //9:5 to configure LCDL calibration step 1 position. + //4:0 to configure LCDL calibration step 0 position. +#define PSRAM_LCDL_CAL_CTRL4 ((0x00f4 << 2) + 0xfe007400) + //19:15 to configure LCDL calibration step 9 position. + //14:10 to configure LCDL calibration step 8 position. + //9:5 to configure LCDL calibration step 7 position. + //4:0 to configure LCDL calibration step 6 position. +#define PSRAM_CLK_UI ((0x00f5 << 2) + 0xfe007400) + //bit 6:0. 4xCLOCK period delay measured from LCDL calibration. +#define PSRAM_LCDL_PH ((0x00f6 << 2) + 0xfe007400) + //10:0 LCDL phase counter after calibration. +#define PSRAM_LCDL_STATUS ((0x00f7 << 2) + 0xfe007400) + //bit 31. LCDL lock status. 1: LCDL locked to 4x clock. +//`endif +// +// Closing file: ../psram/rtl/psram_reg.vh +// +// +// Reading file: ../mmc_lp4/dmc/rtl/dmc_sec.vh +// +//`ifdef DMC_SEC_REG_DEFINE +//`else +//`define DMC_SEC_REG_DEFINE +// ----------------------------------------------- +// APB_BASE: APB1_BASE_ADDR = 0xfd021000 +// ----------------------------------------------- +//`define DMC_SEC_REG_BASE 32'hfd021000 +// ID assignment inside DMC.. +// id[12 :0] total 13 bit ID. +// id[12] == 1: for DMC internal TEST module. +// id[12] == 0: for AXI port input. +// id[11:0] == AXI port ID. +// id[2:0] == 0 : A55 CPU. +// id[2:0] == 1 : DSPA +// id[2:0] == 2 : DSPB +// id[2:0] == 3 : Not used. +// id[2:0] == 4 : for Device. + //Device sublevel ID. + //id[9:7] == 5 : for audio. id[3] == 0: audio + //id[9:7] == 6 : for DMA. id[6:4] for DMA thread id. id[3] for DMC security level. + //id[9:7] == others: for device other masters. +// id[2:0] == 5 : for USB device. +// id[2:0] == 6 : for I2C debug input. +// id[2:0] == 7 : for USB host. +#define DMC_SEC_RANGE0_STA ((0x0000 << 2) + 0xfd021000) + //bit 31:12. range0 start address. in 4KB boundary. +#define DMC_SEC_RANGE0_EDA ((0x0001 << 2) + 0xfd021000) + //bit 31:12. range0 end address. in 4KB boundary. +#define DMC_SEC_RANGE0_RID_CTRL ((0x0002 << 2) + 0xfd021000) + //range 0 read access enable based on DMC ID assignments. + //bit 28. for AXI port 3. Not used in A1. should be 0. + //bit 27. for dmc_test. 1 = enable. 0 = disable. + //bit 26. for usbhost. 1 = enable. 0 = disable. + //bit 25. for i2c. 1 = enable. 0 = disable. + //bit 24. for usbdevide. 1 = enable. 0 = disable. + //bit 23. for AXI device sublevel id 7. 1 = enable. 0 = disable. + //bit 22:18.for AXI device sub level id 5 ~ 0. + //bit 17:10.for AXI device DMA thread 7 ~ thread 0.( in A1, DMA only has thread 3 to thread 0). + //bit 9:6. for AXI device audio read subid 3~0. (in A1, audio read only has subid 1 and subid 0). + //bit 5:4. for AXI DSPB. bit 5 for security access. bit 4 for non secure access. + //bit 3:2. for AXI DSPA. bit 3 for security access. bit 2 for non secure access. + //bit 1:0. for AXI A55 CPU. bit 1 for security access. bit 0 for non secure access. +#define DMC_SEC_RANGE0_WID_CTRL ((0x0003 << 2) + 0xfd021000) + //range 0 write access enable based on DMC ID assignments. + //bit 28. for AXI port 3. Not used in A1. should be 0. + //bit 27. for dmc_test. 1 = enable. 0 = disable. + //bit 26. for usbhost. 1 = enable. 0 = disable. + //bit 25. for i2c. 1 = enable. 0 = disable. + //bit 24. for usbdevide. 1 = enable. 0 = disable. + //bit 23. for AXI device sublevel id 7. 1 = enable. 0 = disable. + //bit 22:18.for AXI device sub level id 5 ~ 0. + //bit 17:10.for AXI device DMA thread 7 ~ thread 0.( in A1, DMA only 4 threads from thread 3 to thread 0). + //bit 9:6. for AXI device audio write subid 7~4. (in A1, audio write only 2 masters usey subid 4 and subid 5). + //bit 5:4. for AXI DSPB. bit 5 for security access. bit 4 for non secure access. + //bit 3:2. for AXI DSPA. bit 3 for security access. bit 2 for non secure access. + //bit 1:0. for AXI A55 CPU. bit 1 for security access. bit 0 for non secure access. +#define DMC_SEC_RANGE1_STA ((0x0004 << 2) + 0xfd021000) + //bit 31:12. range1 start address. in 4KB boundary. +#define DMC_SEC_RANGE1_EDA ((0x0005 << 2) + 0xfd021000) + //bit 31:12. range0 end address. in 4KB boundary. +#define DMC_SEC_RANGE1_RID_CTRL ((0x0006 << 2) + 0xfd021000) + //range 1 read access enable based on DMC ID assignments. + //bit 28. for AXI port 3. Not used in A1. should be 0. + //bit 27. for dmc_test. 1 = enable. 0 = disable. + //bit 26. for usbhost. 1 = enable. 0 = disable. + //bit 25. for i2c. 1 = enable. 0 = disable. + //bit 24. for usbdevide. 1 = enable. 0 = disable. + //bit 23. for AXI device sublevel id 7. 1 = enable. 0 = disable. + //bit 22:18.for AXI device sub level id 5 ~ 0. + //bit 17:10.for AXI device DMA thread 7 ~ thread 0.( in A1, DMA only has thread 3 to thread 0). + //bit 9:6. for AXI device audio read subid 3~0. (in A1, audio read only has subid 1 and subid 0). + //bit 5:4. for AXI DSPB. bit 5 for security access. bit 4 for non secure access. + //bit 3:2. for AXI DSPA. bit 3 for security access. bit 2 for non secure access. + //bit 1:0. for AXI A55 CPU. bit 1 for security access. bit 0 for non secure access. +#define DMC_SEC_RANGE1_WID_CTRL ((0x0007 << 2) + 0xfd021000) + //range 1 write access enable based on DMC ID assignments. + //bit 28. for AXI port 3. Not used in A1. should be 0. + //bit 27. for dmc_test. 1 = enable. 0 = disable. + //bit 26. for usbhost. 1 = enable. 0 = disable. + //bit 25. for i2c. 1 = enable. 0 = disable. + //bit 24. for usbdevide. 1 = enable. 0 = disable. + //bit 23. for AXI device sublevel id 7. 1 = enable. 0 = disable. + //bit 22:18.for AXI device sub level id 5 ~ 0. + //bit 17:10.for AXI device DMA thread 7 ~ thread 0.( in A1, DMA only 4 threads from thread 3 to thread 0). + //bit 9:6. for AXI device audio write subid 7~4. (in A1, audio write only 2 masters usey subid 4 and subid 5). + //bit 5:4. for AXI DSPB. bit 5 for security access. bit 4 for non secure access. + //bit 3:2. for AXI DSPA. bit 3 for security access. bit 2 for non secure access. + //bit 1:0. for AXI A55 CPU. bit 1 for security access. bit 0 for non secure access. +#define DMC_SEC_RANGE2_STA ((0x0008 << 2) + 0xfd021000) + //bit 31:12. range2 start address. in 4KB boundary. +#define DMC_SEC_RANGE2_EDA ((0x0009 << 2) + 0xfd021000) + //bit 31:12. range2 end address. in 4KB boundary. +#define DMC_SEC_RANGE2_RID_CTRL ((0x000a << 2) + 0xfd021000) + //range 2 read access enable based on DMC ID assignments. + //bit 28. for AXI port 3. Not used in A1. should be 0. + //bit 27. for dmc_test. 1 = enable. 0 = disable. + //bit 26. for usbhost. 1 = enable. 0 = disable. + //bit 25. for i2c. 1 = enable. 0 = disable. + //bit 24. for usbdevide. 1 = enable. 0 = disable. + //bit 23. for AXI device sublevel id 7. 1 = enable. 0 = disable. + //bit 22:18.for AXI device sub level id 5 ~ 0. + //bit 17:10.for AXI device DMA thread 7 ~ thread 0.( in A1, DMA only has thread 3 to thread 0). + //bit 9:6. for AXI device audio read subid 3~0. (in A1, audio read only has subid 1 and subid 0). + //bit 5:4. for AXI DSPB. bit 5 for security access. bit 4 for non secure access. + //bit 3:2. for AXI DSPA. bit 3 for security access. bit 2 for non secure access. + //bit 1:0. for AXI A55 CPU. bit 1 for security access. bit 0 for non secure access. +#define DMC_SEC_RANGE2_WID_CTRL ((0x000b << 2) + 0xfd021000) + //range 2 write access enable based on DMC ID assignments. + //bit 28. for AXI port 3. Not used in A1. should be 0. + //bit 27. for dmc_test. 1 = enable. 0 = disable. + //bit 26. for usbhost. 1 = enable. 0 = disable. + //bit 25. for i2c. 1 = enable. 0 = disable. + //bit 24. for usbdevide. 1 = enable. 0 = disable. + //bit 23. for AXI device sublevel id 7. 1 = enable. 0 = disable. + //bit 22:18.for AXI device sub level id 5 ~ 0. + //bit 17:10.for AXI device DMA thread 7 ~ thread 0.( in A1, DMA only 4 threads from thread 3 to thread 0). + //bit 9:6. for AXI device audio write subid 7~4. (in A1, audio write only 2 masters usey subid 4 and subid 5). + //bit 5:4. for AXI DSPB. bit 5 for security access. bit 4 for non secure access. + //bit 3:2. for AXI DSPA. bit 3 for security access. bit 2 for non secure access. + //bit 1:0. for AXI A55 CPU. bit 1 for security access. bit 0 for non secure access. +#define DMC_SEC_RANGE3_STA ((0x000c << 2) + 0xfd021000) + //bit 31:12. range3 start address. in 4KB boundary. +#define DMC_SEC_RANGE3_EDA ((0x000d << 2) + 0xfd021000) + //bit 31:12. range3 end address. in 4KB boundary. +#define DMC_SEC_RANGE3_RID_CTRL ((0x000e << 2) + 0xfd021000) + //range 3 read access enable based on DMC ID assignments. + //check DMC_SEC_RANGE0_RID_CTRL for each bit define. +#define DMC_SEC_RANGE3_WID_CTRL ((0x000f << 2) + 0xfd021000) + //range 3 write access enable based on DMC ID assignments. + //check DMC_SEC_RANGE0_WID_CTRL for each bit define. +#define DMC_SEC_RANGE4_STA ((0x0010 << 2) + 0xfd021000) + //bit 31:12. range4 start address. in 4KB boundary. +#define DMC_SEC_RANGE4_EDA ((0x0011 << 2) + 0xfd021000) + //bit 31:12. range4 end address. in 4KB boundary. +#define DMC_SEC_RANGE4_RID_CTRL ((0x0012 << 2) + 0xfd021000) + //range 4 read access enable based on DMC ID assignments. + //check DMC_SEC_RANGE0_RID_CTRL for each bit define. +#define DMC_SEC_RANGE4_WID_CTRL ((0x0013 << 2) + 0xfd021000) + //range 4 write access enable based on DMC ID assignments. + //check DMC_SEC_RANGE0_WID_CTRL for each bit define. +#define DMC_SEC_RANGE5_STA ((0x0014 << 2) + 0xfd021000) + //bit 31:12. range5 start address. in 4KB boundary. +#define DMC_SEC_RANGE5_EDA ((0x0015 << 2) + 0xfd021000) + //bit 31:12. range5 end address. in 4KB boundary. +#define DMC_SEC_RANGE5_RID_CTRL ((0x0016 << 2) + 0xfd021000) + //range 5 read access enable based on DMC ID assignments. + //check DMC_SEC_RANGE0_RID_CTRL for each bit define. +#define DMC_SEC_RANGE5_WID_CTRL ((0x0017 << 2) + 0xfd021000) + //range 5 write access enable based on DMC ID assignments. + //check DMC_SEC_RANGE0_WID_CTRL for each bit define. +#define DMC_SEC_RANGE6_STA ((0x0018 << 2) + 0xfd021000) + //bit 31:12. range5 start address. in 4KB boundary. +#define DMC_SEC_RANGE6_EDA ((0x0019 << 2) + 0xfd021000) + //bit 31:12. range6 end address. in 4KB boundary. +#define DMC_SEC_RANGE6_RID_CTRL ((0x001a << 2) + 0xfd021000) + //range 6 read access enable based on DMC ID assignments. + //check DMC_SEC_RANGE0_RID_CTRL for each bit define. +#define DMC_SEC_RANGE6_WID_CTRL ((0x001b << 2) + 0xfd021000) + //range 6 write access enable based on DMC ID assignments. + //check DMC_SEC_RANGE0_WID_CTRL for each bit define. +//range 7 is default range if the access not hit any of the previous 7 range, if would hit range 7. +#define DMC_SEC_RANGE7_RID_CTRL ((0x001c << 2) + 0xfd021000) + //range 7 read access enable based on DMC ID assignments. + //check DMC_SEC_RANGE0_RID_CTRL for each bit define. +#define DMC_SEC_RANGE7_WID_CTRL ((0x001d << 2) + 0xfd021000) + //range 7 write access enable based on DMC ID assignments. + //check DMC_SEC_RANGE0_WID_CTRL for each bit define. +#define DMC_SEC_RANGE_CTRL ((0x001e << 2) + 0xfd021000) + //bit 23:16 8 range security level. to chosse with DES KEY to use data describle. + //bit 7:0 8 range enable. each bit for one range to indentify the range is enabled or not. +//registers to check the security protection and watch point error information. +#define DMC_DES_CTRL ((0x0020 << 2) + 0xfd021000) + //bit 1 data describle enable. + //bit 0 wirte 1 to block DES CTRL and DES PADDING read/write. +#define DMC_DES_PADDING ((0x0021 << 2) + 0xfd021000) +#define DMC_SEC_STATUS ((0x00b8 << 2) + 0xfd021000) + //bit 31~2. not used. + //bit 1 write security violation. + //bit 0. read security violation. +#define DMC_VIO_ADDR0 ((0x00b9 << 2) + 0xfd021000) + //ddr0 write secure violation address. +#define DMC_VIO_ADDR1 ((0x00ba << 2) + 0xfd021000) + //bit 31:18 . not used. always 0. + //17 ddr0 secure check violation. + //16 ddr0 write address overflow. write out of DDR size. + //15:13. ddr0 write violation AWPROT bits. + //12:0 ddr0_write violation ID. Please check ID assignment for ID bit defines. +#define DMC_VIO_ADDR2 ((0x00bb << 2) + 0xfd021000) + //ddr0 write secure violation address. +#define DMC_VIO_ADDR3 ((0x00bc << 2) + 0xfd021000) + //bit 31:18 . not used. always 0. + //17 ddr0 secure check violation. + //16 ddr0 read address overflow. write out of DDR size. + //15:13. ddr0 read violation AWPROT bits. + //12:0 ddr0_read violation ID. please ID assignment for ID bit defines. +//DDR0_ADDRMAP is used for RANK0 bank, row, col address mapping from AXI 32bits linear address. +#define DDR0_ADDRMAP_0 ((0x00d0 << 2) + 0xfd021000) + //29:25 ca8. + //24:20 ca7. + //19:15 ca6. + //14:10 ca5. + //9:5 ca4. + //4:0 ca3. +#define DDR0_ADDRMAP_1 ((0x00d1 << 2) + 0xfd021000) + //29:25 ra2. + //24:20 ra1. + //19:15 ra0. + //14:10 ca11. + //9:5 ca10. + //4:0 ca9. +#define DDR0_ADDRMAP_2 ((0x00d2 << 2) + 0xfd021000) + //29:25 ra8. + //24:20 ra7. + //19:15 ra6. + //14:10 ra5. + //9:5 ra4. + //4:0 ra3. +#define DDR0_ADDRMAP_3 ((0x00d3 << 2) + 0xfd021000) + //29:25 ra14. + //24:20 ra13. + //19:15 ra12. + //14:10 ra11. + //9:5 ra10. + //4:0 ra9. +#define DDR0_ADDRMAP_4 ((0x00d4 << 2) + 0xfd021000) + //29:25 ra16 for DDR4 SDRAM + //24:20 bg1 for DDR4 SDRAM. + //19:15 ba2. or bg0 for DDR4. + //14:10 ba1. + //9:5 ba0. + //4:0 ra15. +#define DMC_DDR_CTRL ((0x00da << 2) + 0xfd021000) + // DDR PHY and DMC only supports 16bits and rank0 only. + //bit 24:22 3'b000 : ddr3 mode. + //3'b001 : ddr4 mode. + //3'b010 : lpddr3 mode. + //3'b011 : lpddr4 mode. + //bit 20 DDR4 BG1 enable bit. + //bit 3:0 : DDR rank 0 size bit [2:0]. + //4'b0000 : DDR rank 0 is 128Mbyte. + //4'b0001 : DDR rank 0 is 256Mbyte. + //4'b0010 : DDR rank 0 is 512Mbyte. + //4'b0011 : DDR rank 0 is 1Gbyte. + //4'b0100 : DDR rank 0 is 2Gbyte. + //4'b0101 : DDR rank 0 is 4Gbyte. + //4'b1000 : DDR rank 0 is 4Gbyte. + //4'b1001 : DDR rank 0 is 4Gbyte. + //others : reserved. +#define DMC_APB_SEC_CTRL ((0x00db << 2) + 0xfd021000) + //bit 19:16. DMC normal APB register secure control. + //bit 19: 1: all can write those register. 0: the APB_PROT[0] must match the bit 16 to access those regsiter. + //Bit15:12. DMC sticky APB regsiter secure control. + //bit 15. 1: All APB bus can write those registers. 0: The APB_PROT[0] must match the bit 12 to access those register. + //bit 11:8. not used. + //Bit 7:4. DMC DDR SDRAM protocal contorl register contorl + //bit 11. 1: All APB bus can write those registers. 0: The APB_PROT[0] must match the bit 4 to access those register. + //bit 3:0. PHY APB regsiter secure control. + //bit 3. 1: All APB bus can write those registers. 0: The APB_PROT[0] must match the bit 0 to access those register. +#define DMC_DDR_PHY_CTRL ((0x00bf << 2) + 0xfd021000) + //bit 4 PwrOkIn + //bit 3. PHY APB soft reset_n + //bit 2. PHY soft reset_n + //bit 1. PHY DfiClk enable. + //bit 0. PHY DfiCtlClk enable. +// ----------------------------------------------- +// APB_BASE: APB1_BASE_ADDR = 0xfd021400 +// ----------------------------------------------- +//`define DMC_TEST_REG_BASE 32'hfd021400 +#define DMC_TEST_WRCMD_ADDR ((0x00dc << 2) + 0xfd021400) + // the current write cmd address. +#define DMC_TEST_RDRSP_ADDR ((0x00dd << 2) + 0xfd021400) + // the failed read response address(for error data ) +#define DMC_TEST_RDCMD_ADDR ((0x00de << 2) + 0xfd021400) + // the current read command address. +#define DMC_TEST_WDG ((0x00df << 2) + 0xfd021400) + //31:16. write response watch dog. + //15:0. read response watch dog. +#define DMC_TEST_STA ((0x00e0 << 2) + 0xfd021400) + //test start address. for non-sha mode, the last 5 bits would be ignored. the test address at 32bytes boundary. + // for sha mode, address must be in 64 bytes boundary. that mean the last 6 bits must be 0. +#define DMC_TEST_EDA ((0x00e1 << 2) + 0xfd021400) + //test end address. for non-sha mode, the last 5 bits would be ignored. the test address at 32bytes boundary. + // for sha mode, address must be in 64 bytes boundary. that mean the last 6bits must be 1. +#define DMC_TEST_CTRL ((0x00e2 << 2) + 0xfd021400) + //bit 31. enable test. + //bit 30. when enable test, enable the write to DDR function. + //bit 29. when enable test, enable the read from DDR function. + //bit 28. Not used. + //bit 27. enabe to compare data. when do the read enable to enable the error comparaion. suppose the read data should be same as the data in the write buffer. + //bit 26. Not used. + //bit 25. address generation type. 0: continuous increase the address in the range of test start address and test end address. + // 1: test module would pick the random address from test start address and test end address. + //bit 24. done type. 0 : use the DMC_TEST_NUM register as the counter of test numbers. + // for write if the write command number == the DMC_TEST_NUM, the write is done. + // for read if the read command number == the DMC TEST_num, the read id done. for one read command can be repeated repeat number times. + // 1 : finshed at end address. + //bit 23. wdata type. 1 : the first write is {WD3, WD2,WD1,WD0}, then the latter is the previous data plus a pattern.( { + WD7, + WD6, + WD5, + WD4}). + // 0 : the WDATA is the data in write register. + //bit 23. Not used. + //bit 22:20. read repeat times. for non-sha function, we can define multi times of the read. the test module would repeat the same adddress repeat times. + //bit 19. limit write. 0: no outstanding write request limitation. + // 1: limit the outstanding write commands to the number of bits [15:8] + //bit 18. limit read. 0. no outstanding read request limitation. + // 1. limit the read outstanding request to the number of bits[7:0]. + //bit 17:16. Not used. + //bit 15:8. write outstanding commands limit. + //bit 7:0. read outstanding commands limit. +#define DMC_TEST_NUM ((0x00e3 << 2) + 0xfd021400) + // how many test command for the test if the DMC_TEST_CTRL bit 24 is 0. +#define DMC_TEST_WD0 ((0x00e4 << 2) + 0xfd021400) + // write data 0 for write command. also for read back data comparision. +#define DMC_TEST_WD1 ((0x00e5 << 2) + 0xfd021400) + // write data 1 for write command. also for read back data comparision. +#define DMC_TEST_WD2 ((0x00e6 << 2) + 0xfd021400) + // write data 2 for write command. also for read back data comparision. +#define DMC_TEST_WD3 ((0x00e7 << 2) + 0xfd021400) + // write data 3 for write command. also for read back data comparision. +#define DMC_TEST_WD4 ((0x00e8 << 2) + 0xfd021400) + // write data 4 for write command. also for read back data comparision. +#define DMC_TEST_WD5 ((0x00e9 << 2) + 0xfd021400) + // write data 5 for write command. also for read back data comparision. +#define DMC_TEST_WD6 ((0x00ea << 2) + 0xfd021400) + // write data 6 for write command. also for read back data comparision. +#define DMC_TEST_WD7 ((0x00eb << 2) + 0xfd021400) + // write data 7 for write command. also for read back data comparision. +#define DMC_TEST_RD0 ((0x00ec << 2) + 0xfd021400) + // the read back data 0. if error happens, it would capture the first error data. +#define DMC_TEST_RD1 ((0x00ed << 2) + 0xfd021400) + // the read back data 1. if error happens, it would capture the first error data. +#define DMC_TEST_RD2 ((0x00ee << 2) + 0xfd021400) + // the read back data 2. if error happens, it would capture the first error data. +#define DMC_TEST_RD3 ((0x00ef << 2) + 0xfd021400) + // the read back data 3. if error happens, it would capture the first error data. +#define DMC_TEST_RD4 ((0x00f0 << 2) + 0xfd021400) + // the read back data 4. if error happens, it would capture the first error data. +#define DMC_TEST_RD5 ((0x00f1 << 2) + 0xfd021400) + // the read back data 5. if error happens, it would capture the first error data. +#define DMC_TEST_RD6 ((0x00f2 << 2) + 0xfd021400) + // the read back data 6. if error happens, it would capture the first error data. +#define DMC_TEST_RD7 ((0x00f3 << 2) + 0xfd021400) + // the read back data 7. if error happens, it would capture the first error data. +#define DMC_TEST_ERR_ADDR ((0x00f4 << 2) + 0xfd021400) + // it capature the first error address. +#define DMC_TEST_ERR_CNT ((0x00f5 << 2) + 0xfd021400) + // how many data error happens in the whole test period. +#define DMC_TEST_STS ((0x00f6 << 2) + 0xfd021400) + //bit 31, test done bit. write 1 to clean. + //bit 30, indicate address err + //bit 29~7. not used. + //bit 6. read data resp error(caused by security or rd latency). + //bit 5. test MRR/MPR rd latency error. write 1 clear + //bit 4, sha done. write 1 to clean. + //bit 3, write done. write 1 to clean. + //bit 2, read done. write 1 to clean + //bit 1, write watchdog triggered. write 1 to clean + //bit 0, read watchdog triggered. write 1 to clean. +#define DMC_TEST_COMP_MASK ((0x0033 << 2) + 0xfd021400) + //32bits for DMC TEST COMPARE bit enable. + //1 : to MASK this bit. 0: compare this bit. +#define DMC_TEST_RDBI0 ((0x0034 << 2) + 0xfd021400) + //MPC RD FIFO command DBI read back data + //bit 31:16 the second cycle. + //bit 15:0 the first cycle. +#define DMC_TEST_RDBI1 ((0x0035 << 2) + 0xfd021400) + //MPC RD FIFO command DBI read back data + //bit 31:16. the Forth cycle. + //bit 15:0. the third cycle. +#define DMC_TEST_WSTRB0 ((0x0036 << 2) + 0xfd021400) + //MPC WR FIFO command DM bit write data + //bit 31:16 the second cycle. + //bit 15:0 the first cycle. +#define DMC_TEST_DRAM_CMD ((0x0038 << 2) + 0xfd021400) + //bit 31. cmd done. write 0 to clean. + //bit 30. data done. write 0 to clean. + //bit 4:0. only one bit can be 1. read data stored in DMC_TEST_RD* write data from DMC_TEST_W + //bit 4. LPDDR4 MPC write data command( MPC WR FIFO). Not support LPDDR4 in A1. + //bit 3. LPDDR4 MPC read data command (MPC RD Calibration and RD FIFO).Not support LPDDR4 in A1. + //bit 2. LPDDR4 MPC-1 command ( NOP, Start DQS interval ....)Not support LPDDR4 in A1. + //bit 1. mrr comand. + //bit 0. mrw command. +#define DMC_TEST_DRAM_CMD_CODE ((0x0039 << 2) + 0xfd021400) + //bit 27:26. 128bits data cycles . 0: 1 clock cycles; 1: 2 clock cycles; 2: 3 clock cycles; 3:4 clock cycles. + // LPDDR4 32bits: 4 clock cycles; LPDDR4 16bits: 2 clock cycles; + // DDR3/4/LPDDR3 32 bits : 2 clock cycles. DDR3/4 16bits: 1 cycles. + //bit 25 MRW/MRR/MPC command rank 1 select. 1: select. 0: not select. In A1, only rank0 supported. + //bit 24. MRW/MRR/MPC command rank 0 select. 1: select. 0: not select.In A1, only rank0 supported. + //bit 23:16 MR addr. DDR4 case : 18:16 ba[2:0]. 20:19 BG[1:0]. + //bit 15:0 opcode. +#define DMC_TEST_DRAM_CMD_TIME ((0x003a << 2) + 0xfd021400) +//bit 31:16 PRE CMD timer. //delay how many cycle to start the command. +//bit 15:0 POST CMD timer //delay how many cycle after the command execute. +//`endif +// +// Closing file: ../mmc_lp4/dmc/rtl/dmc_sec.vh +// +// +// Reading file: ../mmc_lp4/dmc/rtl/dmc_reg.vh +// +//`ifdef DMC_REG_DEFINE +//`else +//`define DMC_REG_DEFINE +// ----------------------------------------------- +// APB_BASE: APB1_BASE_ADDR = 0xfd020000 +// ----------------------------------------------- +//`define DMC_REG_BASE 32'hfd020000 +#define DMC_SOFT_RST2 ((0x0003 << 2) + 0xfd020000) + //bit 31~11. reserved for future. + //bit 10 DMC DFI cmd soft reset_n + //bit 9 DMC DFI MISC soft reset_n + //bit 8 DMC DFI data soft reset_n + //bit 7 DMC DFI dcu soft reset_n + //bit 6 DMC siu soft reset_n + //bit 5. DMC test soft reset_n. 0 : reset. 1 : normal working mode. + //bit 4. DMC low power control moudle soft reset_n. 0 : reset. 1 : normal working mode. + //bit 3. DMC QOS monitor module soft reset_n. 0 : reset. 1 : normal working mode. + //bit 2. DMC register modle soft reset_n. 0 : reset. 1 : normal working mode. + //bit 1. DMC canvas transfer module soft reset_n. 0 : reset. 1 : normal working mode. + //bit 0. DMC command buffers and command generation modules soft reset. 0 = reset. 1: +#define DMC_VERSION ((0x0005 << 2) + 0xfd020000) + //read only 32'h000b0000. for A1 +#define DMC_MON_CTRL0 ((0x0020 << 2) + 0xfd020000) + //bit 31. qos_mon_en. write 1 to trigger the enable. polling this bit 0, means finished. or use interrupt to check finish. + //bit 30. qos_mon interrupt clear. clear the qos monitor result. read 1 = qos mon finish interrupt. + //bit 1. qos monitor 1 enable. + //bit 0. qos monitor 0 enable. +#define DMC_MON_CTRL1 ((0x0021 << 2) + 0xfd020000) + //bit 8:0. qos monitor 0 channel select. + //bit 8 to select DMC TEST + //bit 7:0 each bit enable one AXI subID. +#define DMC_MON_CTRL2 ((0x0022 << 2) + 0xfd020000) + //bit 8. to enabe monitor 0 second level subID selection for example device. + //bit 7:0 each bit to enable one second level subID inside device. +#define DMC_MON_CTRL3 ((0x0023 << 2) + 0xfd020000) + //bit 8:0. qos monitor 1 channel select. + //bit 8 to select DMC TEST + //bit 7:0 each bit enable one AXI subID. +#define DMC_MON_CTRL4 ((0x0024 << 2) + 0xfd020000) + //bit 8. to enabe monitor 1 second level subID selection for example device. + //bit 7:0 each bit to enable one second level subID inside device. +#define DMC_MON_ALL_REQ_CNT ((0x0029 << 2) + 0xfd020000) + // at the test period, the whole MMC request time. +#define DMC_MON_ALL_GRANT_CNT ((0x002a << 2) + 0xfd020000) + // at the test period, the whole MMC granted data cycles. 64bits unit. +#define DMC_MON_ONE_GRANT_CNT ((0x002b << 2) + 0xfd020000) + // at the test period, the granted data cycles for the selected channel and ports. +#define DMC_MON_SEC_GRANT_CNT ((0x002c << 2) + 0xfd020000) + // at the test period, the granted data cycles for the selected channel and ports. +#define DMC_MON_TIMER ((0x002f << 2) + 0xfd020000) + // timer for the monitor period. +#define DMC_CLKG_CTRL2 ((0x0032 << 2) + 0xfd020000) + //bit 10 enable auto clock gating for dfi command generation + //bit 9 enable auto clock gating for dram cntroller + //bit 8 enable auto clock gating for dfi data path. + //bit 7. enalbe auto clock gating for write rsp generation. + //bit 6. enalbe auto clock gating for read rsp generation. + //bit 5. enalbe auto clock gating for ddr0 command filter. + //bit 4. enalbe auto clock gating for ddr0 write reorder buffer. + //bit 3. enalbe auto clock gating for ddr0 write data buffer. + //bit 2. enalbe auto clock gating for ddr0 read reorder buffer. + //bit 1. reserved + //bit 0. reserved +#define DMC_CLKG_CTRL3 ((0x0033 << 2) + 0xfd020000) + //bit 10 force to disable the clock of dfi command generation + //bit 9 force to disable the clock of dram cntroller + //bit 8 force to disable the clock of dfi data path. + //bit 7. force to disalbe the clock of write rsp generation. + //bit 6. force to disalbe the clock of read rsp generation. + //bit 5. force to disalbe the clock of command filter. + //bit 4. force to disalbe the clock of write reorder buffer. + //bit 3. force to disalbe the clock of write data buffer. + //bit 2. force to disalbe the clock of read reorder buffer. + //bit 1. reserved. + //bit 0. reserved. +#define DMC_CHAN_STS ((0x0036 << 2) + 0xfd020000) + //bit 4 always 1 + //bit 3 ddr0 write data buffer idle. 1 : idle 0: busy. + //bit 2 always 1. + //bit 1 ddr0 wbuf idle. 1 : idle 0: busy. + //bit 0. axi0 channel idle. 1 : idle 0: busy. +#define DMC_CMD_FILTER_CTRL3 ((0x0042 << 2) + 0xfd020000) + //bit 31. force wbuf empty. + //bit 30:26 wbuf high level number + //bit 25:21 wbuf mid level number + //bit 20:16 wbuf low level number + //bit 14:10 rbuf high level number + //bit 9:5 rbuf middle level number + //bit 4:0 rbuf low level number +#define DMC_CMD_FILTER_CTRL4 ((0x0043 << 2) + 0xfd020000) + //bit 29:25. tITW.long + //bit 24:20. tITW. short + //bit 19:12 tAP auto precharge the bank not used if idle that long time. + //bit 11:6 write to read accesses if there write hit request. + //bit 5:0 read to write accesses if there write hit request. +#define DMC_CMD_FILTER_CTRL5 ((0x0044 << 2) + 0xfd020000) + //bit 31:24 Once ddr data bus switch to read, the maxmum read command number to give up the bus when there's write request pending for write buffer. + //bit 23:16 Once ddr data bus switch to write, the maxmum write command number to give up the bus when there's read request pending too long. + //bit 15:8. Once ddr data bus switch to read, the minimum read command number to transfer back to write stage if there's still pending read request. + //bit 7:0. Once ddr data bus switch to write, the minimum write command number to transfer back to read stage if there's still pending write request. +#define DMC_CMD_FILTER_CTRL6 ((0x0045 << 2) + 0xfd020000) + //bit 31:24 write urgent 3 request pending hold num. + //bit 23:16 write urgent 2 request pending hold num. + //bit 15:8. write urgent 1 request pending hold num. + //bit 7:0. write urgent 0 request pending hold num. +#define DMC_CMD_FILTER_CTRL7 ((0x0046 << 2) + 0xfd020000) + //bit 15:8 write to read waiting cycles if there write hit request. + //bit 7:0 read to write waiting cycles if there write hit request. +#define DMC_CMD_BUFFER_CTRL ((0x0047 << 2) + 0xfd020000) + //bit 31:26 total write buffer number. default 32. + //bit 25:20 total read buffer number. default 32. + //bit 19:8 reserved. + //bit 7:0 aw_pending_inc_num. incease write ugent level 1 when write command waiting to in write buffer that long. +#define DMC_CMD_BUFFER_CTRL1 ((0x0048 << 2) + 0xfd020000) + //bit 29:24 read buffer number in non-urgent request. + //bit 23:16 read buffer bank miss watch dog threshold. + //bit 15:12 read buffer urgent level 3 counter inc weight. + //bit 11:8 read buffer urgent level 2 counter inc weight. + //bit 7:4 read buffer urgent level 1 counter inc weight. + //bit 3:0 read buffer urgent level 0 counter inc weight. +#define DMC_AXI0_CHAN_CTRL ((0x0080 << 2) + 0xfd020000) + //bit 31 AXI interface request enable. + //bit 19 AXI interface auto clock gating enable. 1: enable; 0 disable. + //bit 18 AXI interface clock disable. 1 : disable clock. 0 enable clock. + //bit 17 AXI interface dmc clock domain soft reset. 0 : reset. 1 : normal working mode. + //bit 16 AXI interface s0 clock domain soft reset. 0 : reset. 1 : normal working mode. + //bit 15:12 ugt3 QOS level. + //bit 11:8 ugt2 QOS level. + //bit 7:4 ugt1 QOS level. + //bit 3:0 not used. +#define DMC_AXI0_HOLD_CTRL ((0x0081 << 2) + 0xfd020000) + //31:24 write hold num. max outstanding request number. + //23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request. + //15:8 read hold num. max outstanding request number. + //7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request. +#define DMC_AXI5_HOLD_CTRL ((0x0095 << 2) + 0xfd020000) + //31:24 write hold num. max outstanding request number. + //23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request. + //15:8 read hold num. max outstanding request number. + //7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request. +//`endif +// +// Closing file: ../mmc_lp4/dmc/rtl/dmc_reg.vh +// +// +// Reading file: ../mmc_lp4/dmc/rtl/dmc_siu_reg.vh +// +//`ifdef DMC_SIU_REG_DEFINE +//`else +//`define DMC_SIU_REG_DEFINE +// ----------------------------------------------- +// APB_BASE: APB1_BASE_ADDR = 0xfd020400 +// ----------------------------------------------- +//`define DMC_DRAM_REG_BASE 32'hfd020400 +//in A1 project, don't support hardware controlled frequency change. +#define DMC_DRAM_TMRD ((0x0000 << 2) + 0xfd020400) + //bit 3:0. tMRD. +#define DMC_DRAM_TRFC ((0x0001 << 2) + 0xfd020400) + //bit 9:0 tRFC +#define DMC_DRAM_TRP ((0x0002 << 2) + 0xfd020400) + //bit 21:16. tRP for precharge all banks. + //bit 5:0. tRP for precharge one bank. +#define DMC_DRAM_TRTW ((0x0003 << 2) + 0xfd020400) + //bit 5:0 tRTW +#define DMC_DRAM_TCL ((0x0004 << 2) + 0xfd020400) + //bit 5:0 tCL/tRL. read latency. +#define DMC_DRAM_TCWL ((0x0005 << 2) + 0xfd020400) + //bit 5:0. CWL: write latency. +#define DMC_DRAM_TRAS ((0x0006 << 2) + 0xfd020400) + //bit 7:0. tRAS. minimum active to precharge time for same bank. +#define DMC_DRAM_TRC ((0x0007 << 2) + 0xfd020400) + //bit 7:0. tRC. minimum active to active time for same bank. +#define DMC_DRAM_TRCD ((0x0008 << 2) + 0xfd020400) + //bit 7:0 tRCD active to read/write timing for same bank. +#define DMC_DRAM_TRRD ((0x0009 << 2) + 0xfd020400) + //bit 21:16. tRRD_l active bank A to active B in same band group for DDR4. + //bit 5:0. tRRD/tRRD_s active bank A to active bank b time. + //tRRD_s: active bank A to active bank b in different bank grousp for DDR4. +#define DMC_DRAM_TFAW ((0x000a << 2) + 0xfd020400) + //bit 8:0 tFAW. four active command windows +#define DMC_DRAM_TRTP ((0x000b << 2) + 0xfd020400) + //bit 5:0 tRTP. +#define DMC_DRAM_TWR ((0x000c << 2) + 0xfd020400) + //bit 5:0 tWR. +#define DMC_DRAM_TWTR ((0x000d << 2) + 0xfd020400) + //bit 5:0 tWTR. +#define DMC_DRAM_TCCD ((0x000e << 2) + 0xfd020400) + //bit 19:16. tCCD/tCCD_l. + //bit 3:0 tCCD/tCCD_s read to read command time or write to write command time. +#define DMC_DRAM_TEXSR ((0x000f << 2) + 0xfd020400) + //bit 9:0. tEXSR. EXIT SELF-REFRESH to read/write command. +#define DMC_DRAM_TXS ((0x0010 << 2) + 0xfd020400) + //bit 9:0 tXS. EXIT SELF_REFRESH to other command time +#define DMC_DRAM_TXP ((0x0011 << 2) + 0xfd020400) + //bit 3:0. tXP. EXIT power down to other command time +#define DMC_DRAM_TXPDLL ((0x0012 << 2) + 0xfd020400) + //bit 9:0. tXPDLL, EXIT power down to read/write command time(need to relock PLL). +#define DMC_DRAM_TZQCS ((0x0013 << 2) + 0xfd020400) + //bit 11:0. ZQCS command to other command time. +#define DMC_DRAM_TCKSRE ((0x0014 << 2) + 0xfd020400) + //bit 4:0. enter self refresh to disable clock time. +#define DMC_DRAM_TCKSRX ((0x0015 << 2) + 0xfd020400) + //bit 4:0. enable clock to exit self refresh time. +#define DMC_DRAM_TCKE ((0x0016 << 2) + 0xfd020400) + //bit 4:0. CKE high or low minimum time. +#define DMC_DRAM_TMOD ((0x0017 << 2) + 0xfd020400) + //bit 4:0 tMOD. MRR/MRW to other command time. +#define DMC_DRAM_TDQS ((0x0018 << 2) + 0xfd020400) + //bit 3:0 tDQS. the delay to access different rank. +#define DMC_DRAM_TRSTL ((0x0019 << 2) + 0xfd020400) + //not used. +#define DMC_DRAM_TZQLAT ((0x001a << 2) + 0xfd020400) + //bit 5:0 ZQ LATCH command to other comand timing in LPDDR4 mode. +#define DMC_DRAM_TMRR ((0x001b << 2) + 0xfd020400) + //bit 7:0 tMRR not used in DMC. not support MR READ. +#define DMC_DRAM_TCKESR ((0x001c << 2) + 0xfd020400) + //bit 9:0 tCKESR. CKE low minimum pulse in self refresh mode. +#define DMC_DRAM_TDPD ((0x001d << 2) + 0xfd020400) + //not support. +#define DMC_DRAM_DFITCTRLDELAY ((0x001e << 2) + 0xfd020400) + //bit 3:0. DFI_t_ctrldealy +#define DMC_DRAM_DFITPHYWRDATA ((0x001f << 2) + 0xfd020400) + //bit 5:0. dfi_t_phy_wrdata. +#define DMC_DRAM_DFITPHYWRLAT ((0x0020 << 2) + 0xfd020400) + //bit 5:0. dfi_t_phy_wrlat. in DDR3/4/LPDDR3 mode: WL -5. in LPDDR4 mode: WL -5 + 2. +#define DMC_DRAM_DFITRDDATAEN ((0x0021 << 2) + 0xfd020400) + //bit 5:0. dfi_t_rddata_en. in DDR3/4/LPDDR3 mode: RL -5. in LPDDR4 mode : RL -5 + 1. +#define DMC_DRAM_DFITPHYRDLAT ((0x0022 << 2) + 0xfd020400) + //bit 5:0. dfi_t_rdlat. +#define DMC_DRAM_DFITCTRLUPDMIN ((0x0023 << 2) + 0xfd020400) + //bit 7:0. CTRLUPD_MIN minimux clock cycle to maintain CTRLUPD_REQ. +#define DMC_DRAM_DFITCTRLUPDMAX ((0x0024 << 2) + 0xfd020400) + //bit 7:0 CTRLUPD_MAX. maxmum clock cycle to maintain CTRLUPD_REQ if no CTRLUPD_ACK response. +#define DMC_DRAM_DFITMSTRRESP ((0x0025 << 2) + 0xfd020400) + //not used. +#define DMC_DRAM_DFITREFMSKI ((0x0026 << 2) + 0xfd020400) + //not used. +#define DMC_DRAM_DFITCTRLUPDI ((0x0027 << 2) + 0xfd020400) + //not used. +#define DMC_DRAM_DFITDRAMCLK ((0x0028 << 2) + 0xfd020400) +//bit 17 dram clk1 enable. +//bit 16 dram clk0 enable. +//bit 15:8 DRAM CLK disable waiting time +//bit 7:0 DRAM CLK enable enable timer +#define DMC_DRAM_DFITLPRESP ((0x002a << 2) + 0xfd020400) + //bit 3:0. dfi_lp_ctrl_req response time. after dfi_lp_ctrl_req asserted, and after response time if there's still no dfi_lp_ack respone, then drop the dfi_lp_ctrl_req. +#define DMC_DRAM_DFITPHYMSTR ((0x002b << 2) + 0xfd020400) + //bit 15 1: enable DFIPHYMASTER INTERFACE 0 disable DFIPHYMSTR en response. + // always 0 we would use DFI_RETRAIN function for PHY retrain required from LPDDR4. +#define DMC_DRAM_TCKECK ((0x002c << 2) + 0xfd020400) + //bit 4:0. tCKECK from CKE low to assert dfi_dram_clk_disable time. this time + dfi_t_ctrl_delay +#define DMC_DRAM_TREFI ((0x002d << 2) + 0xfd020400) + //write this register will update the auto refresh related register to the auto refresh control logic. + //bit 31:24: tZQCI dmc send zqci period. unit is how much auto refresh period. + //bit 23:16 pvti dmc send dfi_ctrlupd_req period. unit is one auto refresh period. + //bit 15:8. tREFI.dmc send auto refresh command period. unit is 100ns. + //bit 7:0. t100ns period. unit is dmc clock cycles +#define DMC_DRAM_TSR ((0x002e << 2) + 0xfd020400) + //bit 5:0 tSR. self resfresh enter to exit time. +#define DMC_DRAM_TCCDMW ((0x002f << 2) + 0xfd020400) + //bit 5:0. 4*tCCD in LPDDR4 mask write. +#define DMC_DRAM_TESCKE ((0x0030 << 2) + 0xfd020400) + //bit 5:0 tESCKE. enter self refresh to power time for LPDDR4. +#define DMC_DRAM_TREFI_DDR3 ((0x0031 << 2) + 0xfd020400) + //7:0. 8*DDR3 SDRAM tREFI time . the unit is t100ns. use this to check in 8*tREFI time, the DMC should sent more than 16 auto REFRESH command. +#define DMC_DRAM_TZQCAL ((0x0032 << 2) + 0xfd020400) + //7:0. ZQCAL for LPDDR4. +#define DMC_DRAM_T10US ((0x0033 << 2) + 0xfd020400) + //10us clock cycle number used for LP2 mode. +#define DMC_DRAM_TMRRI ((0x0034 << 2) + 0xfd020400) +//bit 7:0 tMRRI for MRR +#define DMC_DRAM_DFITPHYUPDTYPE0 ((0x0080 << 2) + 0xfd020400) + //dfi_phyupd_ack hold time for dfi_phyupd_req type = 0. +#define DMC_DRAM_DFITPHYUPDTYPE1 ((0x0081 << 2) + 0xfd020400) + //dfi_phyupd_ack hold time for dfi_phyupd_req type = 1. +#define DMC_DRAM_DFITPHYUPDTYPE2 ((0x0082 << 2) + 0xfd020400) + //dfi_phyupd_ack hold time for dfi_phyupd_req type = 2. +#define DMC_DRAM_DFITPHYUPDTYPE3 ((0x0083 << 2) + 0xfd020400) + //dfi_phyupd_ack hold time for dfi_phyupd_req type = 3. +#define DMC_DRAM_DFIODTCFG ((0x0084 << 2) + 0xfd020400) + //bit 12. rank1 ODT default. default vulue for ODT[1] pins if theres no read/write activity. + //bit 11. rank1 ODT write sel. enable ODT[1] if there's write occur in rank1. + //bit 10. rank1 ODT write nsel. enable ODT[1] if theres's write occur in rank0. + //bit 9. rank1 odt read sel. enable ODT[1] if there's read occur in rank1. + //bit 8. rank1 odt read nsel. enable ODT[1] if there's read occure in rank0. + //bit 4. rank0 ODT default. default vulue for ODT[0] pins if theres no read/write activity. + //bit 3. rank0 ODT write sel. enable ODT[0] if there's write occur in rank0. + //bit 2. rank0 ODT write nsel. enable ODT[0] if theres's write occur in rank1. + //bit 1. rank0 odt read sel. enable ODT[0] if there's read occur in rank0. + //bit 0. rank0 odt read nsel. enable ODT[0] if there's read occure in rank1. +#define DMC_DRAM_DFIODTCFG1 ((0x0085 << 2) + 0xfd020400) + //bit 27:24 ODT length for BL8 read transfer. + //bit 19:16. ODT length for BL8 write transfer. + //bit 12:8. ODT latency for reads. suppose to be 0. + //bit 4:0. ODT latency for writes. suppose to be 0. +#define DMC_DRAM_MCFG ((0x0086 << 2) + 0xfd020400) + //bit 14. 1: cke init low. 0 : cke init high. + //bit 13 1: dbi write enable only for LPDDR4. + //bit 12. 1: dbi read inversion. 0: dbi read high inversion. + //bit 11. 1: dbi read enable. 0: dbi not enabled. + //bit 10 1: enable staggered chip select for 2 ranks DRAM. + //bit 9 1: enable send auto refresh command to DDR SDRAM when PCTL is in CFG/STOP state. + //bit 8 send auto refr cmd before enter register triggered self refresh + //bit 7 send auto refr cmd after exit regsiter triggered self refresh mode. + //bit 6 disable dram clock after enter register triggered self refresh. + //bit 5 send DFI_LP_REQ to PHY after enter register triggered elf refresh mode. + //bit 4 send DRAM to power down mode after enter self refresh. ONLY for LPDDR4. + //bit 3 send DFI_CTRLUPD_REQ after exit register triggered self refresh. + //bit 2 send ZQCS command after exit register triggered self refresh. + //bit 1 enable PHY triggered DFI_PHYUPD_REQ. + //bit 0 2T mode. always 1 in DDR3/4 mode. +#define DMC_DRAM_DFI_CTRL ((0x0089 << 2) + 0xfd020400) + //bit 31 siu_dfi_lat err generation enable. 1: if dfi read latency violation, generate data error. 0 : disable. + //bit 30:0. not used. +#define DMC_DRAM_DFIINITCFG ((0x008a << 2) + 0xfd020400) + //bit 31. dfi_init_complete status. read only. + //bit 15:14. Frequency set 1 dfi_freq_ratio value. Not used in A1 + //bit 12:8 Frequency set 1 dfi_freq value. Not used in A1 + //bit 7:6 Frequency set 0 dfi_freq_ratio value. + //bit 5:1 Frequency set 0 dfi_freq value. + //bit 0. dfi_init_start value can be use manually config dfi_init_start signal. +#define DMC_DRAM_ZQ_CTRL ((0x008b << 2) + 0xfd020400) + // only bit 0 can be enable in A1. + //bit 2 send ZQCS command to RANK0 then send comand to RANK1. + //bit 1. send ZQCS command to both RANK0 and RANK1 together. + //bit 0. send ZQCS command to only rank0. +#define DMC_DRAM_APD_CTRL ((0x008c << 2) + 0xfd020400) + //bit 19:16 DFI_LP_WAKEUP value in APD DFI_LP_REQ mode + //bit 12 1: exit power down slow mode(waiting PLL LOCK). 0 : fast mode. + //bit 11 enable DFI_LP_REQ when enter Auto power down mode. + //bit 10 disable DFI_clk_disable when enter auto power down mode. + //bit 9:0 0 disable auto power down mode. + //non zero value to enable auto power down when DMC is in idle state for this number of clock cycles. +#define DMC_DRAM_ASR_CTRL ((0x008d << 2) + 0xfd020400) + //bit [25] LP2 mode PHYCLK enable. 1 : keep PHY clock enable after enter LP2 mode. 0 : shutdown PHY clock after enter LP2 mode. + //bit [24] LP2 mode SRX waiting enable. if Self refresh too long, waiting 10us for the PHY stable before DDR SDRAM exit from self refresh state. + //bit [23:20] DFI_LP_WAKEUP value in self refresh DFI_LP_REQ mode. + //bit 17 : send REFRESH command after exit from auto self refersh mode(ASR). + //bit 16 : send REFERSH command before enter to Auto self refresh mode(ASR). + //bit 15 : send ZQCS command after exit from Auto self refresh mode(ASR). + //bit 14 : send dfi_ctrl_upd after exit from ASR mode + //bit 13 : send power down command when enter ASR mode. //for LPDDR4 only. + //bit 12 : set the PHY enter LP2 mode after enter ASR mode. + //bit 11 : send DFI_LP_REQ after enter ASR mode. + //bit 10 : set DFI_CLK_DISABLE after enter ASR mode. + //bit 9:0. 0 disable auto ASR mode. + // Non-zero valule enable ASR mode. when DMC is in idle state for this number of clock cycles, the DMC will enter ASR mode. +#define DMC_DRAM_PHYMSTR_CTRL ((0x0090 << 2) + 0xfd020400) + //not used in A1. should be all 0. +#define DMC_DRAM_DFIODTRANKMAP ((0x0091 << 2) + 0xfd020400) + //not used in A1. +#define DMC_DRAM_REFR_CTRL ((0x0092 << 2) + 0xfd020400) + //bit 17:8 auto refresh request pending cnt if there's page hit request. + //bit 6 Disabled auto refresh command if over 16 auto refresh command sent in 2 TREFI_DDR3 period + //bit 5 enable dmc send ZQCS command . + //bit 4. enable dmc send DFI_CTRUPD_REQ. + //bit 3:1. how many refresh command send for one period. = this number + 1 + //bit 0. enable dmc send auto refresh command. +#define DMC_DRAM_FREQ_CTRL ((0x0093 << 2) + 0xfd020400) +//bit 31 . wiret 1 to change freqency read 0: finished. +//bit 30:9. not used. +//bit 9. 1 : FREQ MRW done. let FREQ change machine continue. +//bit 8 FREQ WAIT. 1 when freq change finishes, state machine stop at self refresh state in case there's something need to handle. + // 0 after freq change finishes the state machine go back to access state. +//bit 7 when change PLL setting, disable dmc clock +//bit 6 when change PLL setting, disable PHY DfiClk and DfiCtlClk. +//bit 5 check vpu_sleep_en ==1 when do FREQ change. if vpu_sleep_en == 0, just wait. +//bit 4 nxt frequency selection. 1 = freq1. 0 = freq0. +//bit 3:1. not used. +//bit 0. current frequency selection. +#define DMC_DRAM_SCFG ((0x0094 << 2) + 0xfd020400) + // bit 2:0 only one bit can be high at same time. + // bit 2 1 : to ask PCTL enter ACCESS STATE. 0 : deassert the request. + // bit 1 1 : to ask PCTL enter SELF REFRESH STATE. 0 : deassert the request. + // bit 0 1 : to ask PCTL enter STOP/CONFIG STATE . 0 : deassert the request. +#define DMC_DRAM_STAT ((0x0095 << 2) + 0xfd020400) + //bit 31 rd latency error. 1: means after dfiphytrdlat cycles, the read data still not back. + //bit 28:24 dram_sr_state + //bit 23:20 stop_st + //bit 19:15 sleep_st + //bit 14:12 ACCESS STATUS 0 : ACCESS is in normal working mode. + //1 : ACCESS sending precharege command. + //2 : ACCESS sending AUTO REFESH command. + //3 : ACCESS sending DIF_CTRLUPD_REQ command. + //4 : ACCESS sending ZQCS command to DDR DRAM(ZQCAL for LPDDR4). + //5 : ACCESS sending ZQLATCH command to LPDDR4 only. + //bit 11:8 APD STATUS: 0 : APD_IDLE + //1 : APD sending PRECHARGE command + //2 : APD sending CKE low command + //3 : APD sending DISABLE DRAM CLOCK command + //4 : APD sending DFI_LP_CTRL_REQ + //5 : APD in Auto Power down mode. + //6 : APD deassert DFI_LP_CTRL_REQ + //7 : APD sending enable DRAM CLOCK command + //8 : APD sending out CKE high command. + //bit 7:4: DRAM_STATUS: 0 : DRAM IDLE + //1 : DRAM_STOP/DRAM_CFG + //2 : DRAM_ACCESS + //3 : DRAM_SLEEP + //4 : DRAM APD(AUTO POWER DOWN). + //5 : IDLE -> STOP/CONFIG + //6 : STOP -> SLEEP + //7 : STOP -> ACCESS + //8 : ACCESS -> SLEEP. + //9 : ACCESS -> STOP + //A : ACCESS -> APD + //B : SLEEP -> STOP + //C : SLEEP -> ACCESS + //D : APD -> ACCESS + //bit 3 reserved. + //bit 2 1 : DRAM enter normal working state. + //bit 1 1 : DRAM enter sleep state. self refresh state. + //bit 0 1 : dram enter cfg state. +#define DMC_DRAM_STAT1 ((0x0096 << 2) + 0xfd020400) + //bit 11:8 freq_st. + //bit 7:5 train_st + //bit 4:0 dram_phy_st +#define DMC_PHY_RETRAINING_CTRL ((0x0097 << 2) + 0xfd020400) + // A1 not support LPDDR4 so this register is not used in A1. + //bit 31 : phy_retraining enable. + //bit 30 : check vpu sleep_en. + //bit 25:24 : retraining dfi_freq[4:3], the [2:0] bit still use the dfi_freq bits to keep the frequency. + //bit 23:0: retraining period unit : 100ns. +#define DMC_DFI_ERR_STAT ((0x0098 << 2) + 0xfd020400) + //LPDDR4 PHY DFI error infomation. + //bit 31:20. not used. + //bit 9. ddr0_dfi_error + //bit 8:5 ddr0_dfi_error_info. + //bit 4. ddr1_dfi_error. + //bit 3:0. ddr1_dfi_error_info. +#define DMC_LP2_TIMER ((0x009a << 2) + 0xfd020400) +//bit 15:0. timer setting to measure how long the chip is entered LP2 mode. +//this timer is 40bits counter with DMC PCLK. +//we use the high 16bits to compare this register. if the counter is large than this number, that means the PHY need addition 10us after wakeup the PHY and before exit self_refresh mode. +#define DMC_DRAM_DFI_SWAP_0 ((0x00a0 << 2) + 0xfd020400) + //bit 5:0. dfi_act_n function select + // 6'h00 : the function itself. + // 6'h01 : act_n. + // 6'h02 : ras_n. + // 6'h03 : cas_n. + // 6'h04 : we_n. + // 6'h05 : bg[0]. + // 6'h06 : bg[1]. + // 6'h07 : ba[0]. + // 6'h08 : ba[1]. + // 6'h09 : ba[2]. + // 6'h0a : a[0]. + // 6'h0b : a[1]. + // 6'h0c : a[2]. + // 6'h0d : a[3]. + // 6'h0e : a[4]. + // 6'h0f : a[5]. + // 6'h10 : a[6]. + // 6'h11 : a[7]. + // 6'h12 : a[8]. + // 6'h13 : a[9]. + // 6'h14 : a[10]. + // 6'h15 : a[11]. + // 6'h16 : a[12]. + // 6'h17 : a[13]. + // 6'h18 : a[14]. + // 6'h19 : a[15]. + // 6'h1a : a[16]. + // 6'h1b : a[17]. +#define DMC_DRAM_DFI_SWAP_1 ((0x00a1 << 2) + 0xfd020400) + //bit 5:0. dfi_ras_n function select + // 6'h00 : the function itself. + // 6'h01 : act_n. + // 6'h02 : ras_n. + // 6'h03 : cas_n. + // 6'h04 : we_n. + // 6'h05 : bg[0]. + // 6'h06 : bg[1]. + // 6'h07 : ba[0]. + // 6'h08 : ba[1]. + // 6'h09 : ba[2]. + // 6'h0a : a[0]. + // 6'h0b : a[1]. + // 6'h0c : a[2]. + // 6'h0d : a[3]. + // 6'h0e : a[4]. + // 6'h0f : a[5]. + // 6'h10 : a[6]. + // 6'h11 : a[7]. + // 6'h12 : a[8]. + // 6'h13 : a[9]. + // 6'h14 : a[10]. + // 6'h15 : a[11]. + // 6'h16 : a[12]. + // 6'h17 : a[13]. + // 6'h18 : a[14]. + // 6'h19 : a[15]. + // 6'h1a : a[16]. + // 6'h1b : a[17]. +#define DMC_DRAM_DFI_SWAP_2 ((0x00a2 << 2) + 0xfd020400) + //bit 5:0. dfi_cas_n function select + // 6'h00 : the function itself. + // 6'h01 : act_n. + // 6'h02 : ras_n. + // 6'h03 : cas_n. + // 6'h04 : we_n. + // 6'h05 : bg[0]. + // 6'h06 : bg[1]. + // 6'h07 : ba[0]. + // 6'h08 : ba[1]. + // 6'h09 : ba[2]. + // 6'h0a : a[0]. + // 6'h0b : a[1]. + // 6'h0c : a[2]. + // 6'h0d : a[3]. + // 6'h0e : a[4]. + // 6'h0f : a[5]. + // 6'h10 : a[6]. + // 6'h11 : a[7]. + // 6'h12 : a[8]. + // 6'h13 : a[9]. + // 6'h14 : a[10]. + // 6'h15 : a[11]. + // 6'h16 : a[12]. + // 6'h17 : a[13]. + // 6'h18 : a[14]. + // 6'h19 : a[15]. + // 6'h1a : a[16]. + // 6'h1b : a[17]. +#define DMC_DRAM_DFI_SWAP_3 ((0x00a3 << 2) + 0xfd020400) + //bit 5:0. dfi_we_n function select + // 6'h00 : the function itself. + // 6'h01 : act_n. + // 6'h02 : ras_n. + // 6'h03 : cas_n. + // 6'h04 : we_n. + // 6'h05 : bg[0]. + // 6'h06 : bg[1]. + // 6'h07 : ba[0]. + // 6'h08 : ba[1]. + // 6'h09 : ba[2]. + // 6'h0a : a[0]. + // 6'h0b : a[1]. + // 6'h0c : a[2]. + // 6'h0d : a[3]. + // 6'h0e : a[4]. + // 6'h0f : a[5]. + // 6'h10 : a[6]. + // 6'h11 : a[7]. + // 6'h12 : a[8]. + // 6'h13 : a[9]. + // 6'h14 : a[10]. + // 6'h15 : a[11]. + // 6'h16 : a[12]. + // 6'h17 : a[13]. + // 6'h18 : a[14]. + // 6'h19 : a[15]. + // 6'h1a : a[16]. + // 6'h1b : a[17]. +#define DMC_DRAM_DFI_SWAP_4 ((0x00a4 << 2) + 0xfd020400) + //bit 5:0. dfi_bg0 function select + // 6'h00 : the function itself. + // 6'h01 : act_n. + // 6'h02 : ras_n. + // 6'h03 : cas_n. + // 6'h04 : we_n. + // 6'h05 : bg[0]. + // 6'h06 : bg[1]. + // 6'h07 : ba[0]. + // 6'h08 : ba[1]. + // 6'h09 : ba[2]. + // 6'h0a : a[0]. + // 6'h0b : a[1]. + // 6'h0c : a[2]. + // 6'h0d : a[3]. + // 6'h0e : a[4]. + // 6'h0f : a[5]. + // 6'h10 : a[6]. + // 6'h11 : a[7]. + // 6'h12 : a[8]. + // 6'h13 : a[9]. + // 6'h14 : a[10]. + // 6'h15 : a[11]. + // 6'h16 : a[12]. + // 6'h17 : a[13]. + // 6'h18 : a[14]. + // 6'h19 : a[15]. + // 6'h1a : a[16]. + // 6'h1b : a[17]. +#define DMC_DRAM_DFI_SWAP_5 ((0x00a5 << 2) + 0xfd020400) + //bit 5:0. dfi_bg[1] function select + // 6'h00 : the function itself. + // 6'h01 : act_n. + // 6'h02 : ras_n. + // 6'h03 : cas_n. + // 6'h04 : we_n. + // 6'h05 : bg[0]. + // 6'h06 : bg[1]. + // 6'h07 : ba[0]. + // 6'h08 : ba[1]. + // 6'h09 : ba[2]. + // 6'h0a : a[0]. + // 6'h0b : a[1]. + // 6'h0c : a[2]. + // 6'h0d : a[3]. + // 6'h0e : a[4]. + // 6'h0f : a[5]. + // 6'h10 : a[6]. + // 6'h11 : a[7]. + // 6'h12 : a[8]. + // 6'h13 : a[9]. + // 6'h14 : a[10]. + // 6'h15 : a[11]. + // 6'h16 : a[12]. + // 6'h17 : a[13]. + // 6'h18 : a[14]. + // 6'h19 : a[15]. + // 6'h1a : a[16]. + // 6'h1b : a[17]. +#define DMC_DRAM_DFI_SWAP_6 ((0x00a6 << 2) + 0xfd020400) + //bit 5:0. dfi_ba[0] function select + // 6'h00 : the function itself. + // 6'h01 : act_n. + // 6'h02 : ras_n. + // 6'h03 : cas_n. + // 6'h04 : we_n. + // 6'h05 : bg[0]. + // 6'h06 : bg[1]. + // 6'h07 : ba[0]. + // 6'h08 : ba[1]. + // 6'h09 : ba[2]. + // 6'h0a : a[0]. + // 6'h0b : a[1]. + // 6'h0c : a[2]. + // 6'h0d : a[3]. + // 6'h0e : a[4]. + // 6'h0f : a[5]. + // 6'h10 : a[6]. + // 6'h11 : a[7]. + // 6'h12 : a[8]. + // 6'h13 : a[9]. + // 6'h14 : a[10]. + // 6'h15 : a[11]. + // 6'h16 : a[12]. + // 6'h17 : a[13]. + // 6'h18 : a[14]. + // 6'h19 : a[15]. + // 6'h1a : a[16]. + // 6'h1b : a[17]. +#define DMC_DRAM_DFI_SWAP_7 ((0x00a7 << 2) + 0xfd020400) + //bit 5:0. dfi_ba[1] function select + // 6'h00 : the function itself. + // 6'h01 : act_n. + // 6'h02 : ras_n. + // 6'h03 : cas_n. + // 6'h04 : we_n. + // 6'h05 : bg[0]. + // 6'h06 : bg[1]. + // 6'h07 : ba[0]. + // 6'h08 : ba[1]. + // 6'h09 : ba[2]. + // 6'h0a : a[0]. + // 6'h0b : a[1]. + // 6'h0c : a[2]. + // 6'h0d : a[3]. + // 6'h0e : a[4]. + // 6'h0f : a[5]. + // 6'h10 : a[6]. + // 6'h11 : a[7]. + // 6'h12 : a[8]. + // 6'h13 : a[9]. + // 6'h14 : a[10]. + // 6'h15 : a[11]. + // 6'h16 : a[12]. + // 6'h17 : a[13]. + // 6'h18 : a[14]. + // 6'h19 : a[15]. + // 6'h1a : a[16]. + // 6'h1b : a[17]. +#define DMC_DRAM_DFI_SWAP_8 ((0x00a8 << 2) + 0xfd020400) + //bit 5:0. dfi_ba[2] function select + // 6'h00 : the function itself. + // 6'h01 : act_n. + // 6'h02 : ras_n. + // 6'h03 : cas_n. + // 6'h04 : we_n. + // 6'h05 : bg[0]. + // 6'h06 : bg[1]. + // 6'h07 : ba[0]. + // 6'h08 : ba[1]. + // 6'h09 : ba[2]. + // 6'h0a : a[0]. + // 6'h0b : a[1]. + // 6'h0c : a[2]. + // 6'h0d : a[3]. + // 6'h0e : a[4]. + // 6'h0f : a[5]. + // 6'h10 : a[6]. + // 6'h11 : a[7]. + // 6'h12 : a[8]. + // 6'h13 : a[9]. + // 6'h14 : a[10]. + // 6'h15 : a[11]. + // 6'h16 : a[12]. + // 6'h17 : a[13]. + // 6'h18 : a[14]. + // 6'h19 : a[15]. + // 6'h1a : a[16]. + // 6'h1b : a[17]. +#define DMC_DRAM_DFI_SWAP_9 ((0x00a9 << 2) + 0xfd020400) + //bit 5:0. dfi_a[0] function select + // 6'h00 : the function itself. + // 6'h01 : act_n. + // 6'h02 : ras_n. + // 6'h03 : cas_n. + // 6'h04 : we_n. + // 6'h05 : bg[0]. + // 6'h06 : bg[1]. + // 6'h07 : ba[0]. + // 6'h08 : ba[1]. + // 6'h09 : ba[2]. + // 6'h0a : a[0]. + // 6'h0b : a[1]. + // 6'h0c : a[2]. + // 6'h0d : a[3]. + // 6'h0e : a[4]. + // 6'h0f : a[5]. + // 6'h10 : a[6]. + // 6'h11 : a[7]. + // 6'h12 : a[8]. + // 6'h13 : a[9]. + // 6'h14 : a[10]. + // 6'h15 : a[11]. + // 6'h16 : a[12]. + // 6'h17 : a[13]. + // 6'h18 : a[14]. + // 6'h19 : a[15]. + // 6'h1a : a[16]. + // 6'h1b : a[17]. +#define DMC_DRAM_DFI_SWAP_10 ((0x00aa << 2) + 0xfd020400) + //bit 5:0. dfi_a[1] function select +#define DMC_DRAM_DFI_SWAP_11 ((0x00ab << 2) + 0xfd020400) + //bit 5:0. dfi_a[2] function select +#define DMC_DRAM_DFI_SWAP_12 ((0x00ac << 2) + 0xfd020400) + //bit 5:0. dfi_a[3] function select +#define DMC_DRAM_DFI_SWAP_13 ((0x00ad << 2) + 0xfd020400) + //bit 5:0. dfi_a[4] function select +#define DMC_DRAM_DFI_SWAP_14 ((0x00ae << 2) + 0xfd020400) + //bit 5:0. dfi_a[5] function select +#define DMC_DRAM_DFI_SWAP_15 ((0x00af << 2) + 0xfd020400) + //bit 5:0. dfi_a[6] function select +#define DMC_DRAM_DFI_SWAP_16 ((0x00b0 << 2) + 0xfd020400) + //bit 5:0. dfi_a[7] function select +#define DMC_DRAM_DFI_SWAP_17 ((0x00b1 << 2) + 0xfd020400) + //bit 5:0. dfi_a[8] function select +#define DMC_DRAM_DFI_SWAP_18 ((0x00b2 << 2) + 0xfd020400) + //bit 5:0. dfi_a[9] function select +#define DMC_DRAM_DFI_SWAP_19 ((0x00b3 << 2) + 0xfd020400) + //bit 5:0. dfi_a[10] function select +#define DMC_DRAM_DFI_SWAP_20 ((0x00b4 << 2) + 0xfd020400) + //bit 5:0. dfi_a[11] function select +#define DMC_DRAM_DFI_SWAP_21 ((0x00b5 << 2) + 0xfd020400) + //bit 5:0. dfi_a[12] function select +#define DMC_DRAM_DFI_SWAP_22 ((0x00b6 << 2) + 0xfd020400) + //bit 5:0. dfi_a[13] function select +#define DMC_DRAM_DFI_SWAP_23 ((0x00b7 << 2) + 0xfd020400) + //bit 5:0. dfi_a[14] function select +#define DMC_DRAM_DFI_SWAP_24 ((0x00b8 << 2) + 0xfd020400) + //bit 5:0. dfi_a[15] function select +#define DMC_DRAM_DFI_SWAP_25 ((0x00b9 << 2) + 0xfd020400) + //bit 5:0. dfi_a[16] function select +#define DMC_DRAM_DFI_SWAP_26 ((0x00bb << 2) + 0xfd020400) + //bit 5:0. dfi_a[17] function select +// +// Closing file: ../mmc_lp4/dmc/rtl/dmc_siu_reg.vh +// +// +// Reading file: ../mmc_lp4/dmc/rtl/dmc_sticky_reg.vh +// +//`ifdef DMC_STICKY_REG_DEFINE +//`else +//`define DMC_STICKY_REG_DEFINE +// ----------------------------------------------- +// APB_BASE: APB1_BASE_ADDR = 0xfd020800 +// ----------------------------------------------- +//`define DMC_STICKY_REG_BASE 32'hfd020800 +//those register is for software save some tempary value. and because it's in RAM. it won't lose if DMC get reseted. +#define DMC_STICKY_0 ((0x0000 << 2) + 0xfd020800) +#define DMC_STICKY_1 ((0x0001 << 2) + 0xfd020800) +#define DMC_STICKY_2 ((0x0002 << 2) + 0xfd020800) +#define DMC_STICKY_3 ((0x0003 << 2) + 0xfd020800) +#define DMC_STICKY_4 ((0x0004 << 2) + 0xfd020800) +#define DMC_STICKY_5 ((0x0005 << 2) + 0xfd020800) +#define DMC_STICKY_6 ((0x0006 << 2) + 0xfd020800) +#define DMC_STICKY_7 ((0x0007 << 2) + 0xfd020800) +#define DMC_STICKY_8 ((0x0008 << 2) + 0xfd020800) +#define DMC_STICKY_9 ((0x0009 << 2) + 0xfd020800) +#define DMC_STICKY_10 ((0x000a << 2) + 0xfd020800) +#define DMC_STICKY_11 ((0x000b << 2) + 0xfd020800) +#define DMC_STICKY_12 ((0x000c << 2) + 0xfd020800) +#define DMC_STICKY_13 ((0x000d << 2) + 0xfd020800) +#define DMC_STICKY_14 ((0x000e << 2) + 0xfd020800) +#define DMC_STICKY_15 ((0x000f << 2) + 0xfd020800) +#define DMC_STICKY_16 ((0x0010 << 2) + 0xfd020800) +#define DMC_STICKY_17 ((0x0011 << 2) + 0xfd020800) +#define DMC_STICKY_18 ((0x0012 << 2) + 0xfd020800) +#define DMC_STICKY_19 ((0x0013 << 2) + 0xfd020800) +#define DMC_STICKY_20 ((0x0014 << 2) + 0xfd020800) +#define DMC_STICKY_21 ((0x0015 << 2) + 0xfd020800) +#define DMC_STICKY_22 ((0x0016 << 2) + 0xfd020800) +#define DMC_STICKY_23 ((0x0017 << 2) + 0xfd020800) +#define DMC_STICKY_24 ((0x0018 << 2) + 0xfd020800) +#define DMC_STICKY_25 ((0x0019 << 2) + 0xfd020800) +#define DMC_STICKY_26 ((0x001a << 2) + 0xfd020800) +#define DMC_STICKY_27 ((0x001b << 2) + 0xfd020800) +#define DMC_STICKY_28 ((0x001c << 2) + 0xfd020800) +#define DMC_STICKY_29 ((0x001d << 2) + 0xfd020800) +#define DMC_STICKY_30 ((0x001e << 2) + 0xfd020800) +#define DMC_STICKY_31 ((0x001f << 2) + 0xfd020800) +#define DMC_STICKY_32 ((0x0020 << 2) + 0xfd020800) +#define DMC_STICKY_33 ((0x0021 << 2) + 0xfd020800) +#define DMC_STICKY_34 ((0x0022 << 2) + 0xfd020800) +#define DMC_STICKY_35 ((0x0023 << 2) + 0xfd020800) +#define DMC_STICKY_36 ((0x0024 << 2) + 0xfd020800) +#define DMC_STICKY_37 ((0x0025 << 2) + 0xfd020800) +#define DMC_STICKY_38 ((0x0026 << 2) + 0xfd020800) +#define DMC_STICKY_39 ((0x0027 << 2) + 0xfd020800) +#define DMC_STICKY_40 ((0x0028 << 2) + 0xfd020800) +#define DMC_STICKY_41 ((0x0029 << 2) + 0xfd020800) +#define DMC_STICKY_42 ((0x002a << 2) + 0xfd020800) +#define DMC_STICKY_43 ((0x002b << 2) + 0xfd020800) +#define DMC_STICKY_44 ((0x002c << 2) + 0xfd020800) +#define DMC_STICKY_45 ((0x002d << 2) + 0xfd020800) +#define DMC_STICKY_46 ((0x002e << 2) + 0xfd020800) +#define DMC_STICKY_47 ((0x002f << 2) + 0xfd020800) +#define DMC_STICKY_48 ((0x0030 << 2) + 0xfd020800) +#define DMC_STICKY_49 ((0x0031 << 2) + 0xfd020800) +#define DMC_STICKY_50 ((0x0032 << 2) + 0xfd020800) +#define DMC_STICKY_51 ((0x0033 << 2) + 0xfd020800) +#define DMC_STICKY_52 ((0x0034 << 2) + 0xfd020800) +#define DMC_STICKY_53 ((0x0035 << 2) + 0xfd020800) +#define DMC_STICKY_54 ((0x0036 << 2) + 0xfd020800) +#define DMC_STICKY_55 ((0x0037 << 2) + 0xfd020800) +#define DMC_STICKY_56 ((0x0038 << 2) + 0xfd020800) +#define DMC_STICKY_57 ((0x0039 << 2) + 0xfd020800) +#define DMC_STICKY_58 ((0x003a << 2) + 0xfd020800) +#define DMC_STICKY_59 ((0x003b << 2) + 0xfd020800) +#define DMC_STICKY_60 ((0x003c << 2) + 0xfd020800) +#define DMC_STICKY_61 ((0x003d << 2) + 0xfd020800) +#define DMC_STICKY_62 ((0x003e << 2) + 0xfd020800) +#define DMC_STICKY_63 ((0x003f << 2) + 0xfd020800) +//`endif +// +// Closing file: ../mmc_lp4/dmc/rtl/dmc_sticky_reg.vh +// +//======================================================================== +// APB0_RESET_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe000000 +// ----------------------------------------------- +#define RESETCTRL_RESET0 ((0x0000 << 2) + 0xfe000000) +#define RESETCTRL_RESET1 ((0x0001 << 2) + 0xfe000000) +#define RESETCTRL_RESET2 ((0x0002 << 2) + 0xfe000000) +#define RESETCTRL_RESET0_LEVEL ((0x0010 << 2) + 0xfe000000) +#define RESETCTRL_RESET1_LEVEL ((0x0011 << 2) + 0xfe000000) +#define RESETCTRL_RESET2_LEVEL ((0x0012 << 2) + 0xfe000000) +#define RESETCTRL_RESET0_MASK ((0x0020 << 2) + 0xfe000000) +#define RESETCTRL_RESET1_MASK ((0x0021 << 2) + 0xfe000000) +#define RESETCTRL_RESET2_MASK ((0x0022 << 2) + 0xfe000000) +#define RESETCTRL_RESET_HOLD_CYC ((0x0030 << 2) + 0xfe000000) +#define RESETCTRL_WATCHDOG_CTRL0 ((0x0040 << 2) + 0xfe000000) +#define RESETCTRL_WATCHDOG_CTRL1 ((0x0041 << 2) + 0xfe000000) +#define RESETCTRL_WATCHDOG_CNT ((0x0042 << 2) + 0xfe000000) +#define RESETCTRL_WATCHDOG_CLR ((0x0043 << 2) + 0xfe000000) +#define RESETCTRL_SEC_RESET0 ((0x0050 << 2) + 0xfe000000) +#define RESETCTRL_SEC_RESET0_LEVEL ((0x0051 << 2) + 0xfe000000) +#define RESETCTRL_SEC_RESET0_MASK ((0x0052 << 2) + 0xfe000000) +//======================================================================== +// APB0_PAD_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe000400 +// ----------------------------------------------- +#define PADCTRL_PIN_MUX_REG0 ((0x0000 << 2) + 0xfe000400) +#define PADCTRL_PIN_MUX_REG1 ((0x0001 << 2) + 0xfe000400) +#define PADCTRL_PIN_MUX_REG2 ((0x0002 << 2) + 0xfe000400) +#define PADCTRL_PIN_MUX_REG3 ((0x0003 << 2) + 0xfe000400) +#define PADCTRL_PIN_MUX_REG4 ((0x0004 << 2) + 0xfe000400) +#define PADCTRL_PIN_MUX_REG5 ((0x0005 << 2) + 0xfe000400) +#define PADCTRL_PIN_MUX_REG6 ((0x0006 << 2) + 0xfe000400) +#define PADCTRL_PIN_MUX_REG7 ((0x0007 << 2) + 0xfe000400) +#define PADCTRL_PIN_MUX_REG8 ((0x0008 << 2) + 0xfe000400) +#define PADCTRL_PIN_MUX_REG9 ((0x0009 << 2) + 0xfe000400) +#define PADCTRL_PIN_MUX_REGA ((0x000a << 2) + 0xfe000400) +#define PADCTRL_PIN_MUX_REGB ((0x000b << 2) + 0xfe000400) +#define PADCTRL_PIN_MUX_REGC ((0x000c << 2) + 0xfe000400) +#define PADCTRL_PIN_MUX_REGD ((0x000d << 2) + 0xfe000400) +#define PADCTRL_PIN_MUX_REGE ((0x000e << 2) + 0xfe000400) +#define PADCTRL_PIN_MUX_REGF ((0x000f << 2) + 0xfe000400) +#define PADCTRL_GPIO_IRQ_CTRL0 ((0x0010 << 2) + 0xfe000400) +#define PADCTRL_GPIO_IRQ_CTRL1 ((0x0011 << 2) + 0xfe000400) +#define PADCTRL_GPIO_IRQ_CTRL2 ((0x0012 << 2) + 0xfe000400) +#define PADCTRL_GPIO_IRQ_CTRL3 ((0x0013 << 2) + 0xfe000400) +#define PADCTRL_GPIO_IRQ_CTRL4 ((0x0014 << 2) + 0xfe000400) +#define PADCTRL_WORLDSYNC_CTRL0 ((0x0018 << 2) + 0xfe000400) +#define PADCTRL_GPIO_MSR_CTRL0 ((0x0019 << 2) + 0xfe000400) +#define PADCTRL_GPIOP_I ((0x0020 << 2) + 0xfe000400) +#define PADCTRL_GPIOP_O ((0x0021 << 2) + 0xfe000400) +#define PADCTRL_GPIOP_OEN ((0x0022 << 2) + 0xfe000400) +#define PADCTRL_GPIOP_PULL_EN ((0x0023 << 2) + 0xfe000400) +#define PADCTRL_GPIOP_PULL_UP ((0x0024 << 2) + 0xfe000400) +#define PADCTRL_GPIOP_DS ((0x0025 << 2) + 0xfe000400) +#define PADCTRL_GPIOB_I ((0x0030 << 2) + 0xfe000400) +#define PADCTRL_GPIOB_O ((0x0031 << 2) + 0xfe000400) +#define PADCTRL_GPIOB_OEN ((0x0032 << 2) + 0xfe000400) +#define PADCTRL_GPIOB_PULL_EN ((0x0033 << 2) + 0xfe000400) +#define PADCTRL_GPIOB_PULL_UP ((0x0034 << 2) + 0xfe000400) +#define PADCTRL_GPIOB_DS ((0x0035 << 2) + 0xfe000400) +#define PADCTRL_GPIOX_I ((0x0040 << 2) + 0xfe000400) +#define PADCTRL_GPIOX_O ((0x0041 << 2) + 0xfe000400) +#define PADCTRL_GPIOX_OEN ((0x0042 << 2) + 0xfe000400) +#define PADCTRL_GPIOX_PULL_EN ((0x0043 << 2) + 0xfe000400) +#define PADCTRL_GPIOX_PULL_UP ((0x0044 << 2) + 0xfe000400) +#define PADCTRL_GPIOX_DS ((0x0045 << 2) + 0xfe000400) +#define PADCTRL_GPIOX_DS_EXT ((0x0046 << 2) + 0xfe000400) +#define PADCTRL_GPIOF_I ((0x0050 << 2) + 0xfe000400) +#define PADCTRL_GPIOF_O ((0x0051 << 2) + 0xfe000400) +#define PADCTRL_GPIOF_OEN ((0x0052 << 2) + 0xfe000400) +#define PADCTRL_GPIOF_PULL_EN ((0x0053 << 2) + 0xfe000400) +#define PADCTRL_GPIOF_PULL_UP ((0x0054 << 2) + 0xfe000400) +#define PADCTRL_GPIOF_DS ((0x0055 << 2) + 0xfe000400) +#define PADCTRL_GPIOA_I ((0x0060 << 2) + 0xfe000400) +#define PADCTRL_GPIOA_O ((0x0061 << 2) + 0xfe000400) +#define PADCTRL_GPIOA_OEN ((0x0062 << 2) + 0xfe000400) +#define PADCTRL_GPIOA_PULL_EN ((0x0063 << 2) + 0xfe000400) +#define PADCTRL_GPIOA_PULL_UP ((0x0064 << 2) + 0xfe000400) +#define PADCTRL_GPIOA_DS ((0x0065 << 2) + 0xfe000400) +#define PADCTRL_TESTN_I ((0x0070 << 2) + 0xfe000400) +#define PADCTRL_TESTN_O ((0x0071 << 2) + 0xfe000400) +#define PADCTRL_TESTN_OEN ((0x0072 << 2) + 0xfe000400) +#define PADCTRL_TESTN_PULL_EN ((0x0073 << 2) + 0xfe000400) +#define PADCTRL_TESTN_PULL_UP ((0x0074 << 2) + 0xfe000400) +#define PADCTRL_TESTN_DS ((0x0075 << 2) + 0xfe000400) +#define PADCTRL_MUTE_CTRL ((0x0080 << 2) + 0xfe000400) +//======================================================================== +// APB0_CLK_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe000800 +// ----------------------------------------------- +#define CLKTREE_SYS_OSCIN_CTRL ((0x0000 << 2) + 0xfe000800) +#define CLKTREE_RTC_BY_OSCIN_CTRL0 ((0x0001 << 2) + 0xfe000800) +#define CLKTREE_RTC_BY_OSCIN_CTRL1 ((0x0002 << 2) + 0xfe000800) +#define CLKTREE_RTC_CTRL ((0x0003 << 2) + 0xfe000800) +#define CLKTREE_SYS_CLK_CTRL0 ((0x0004 << 2) + 0xfe000800) +#define CLKTREE_AXI_CLK_CTRL0 ((0x0005 << 2) + 0xfe000800) +#define CLKTREE_SYS_CLK_EN0 ((0x0007 << 2) + 0xfe000800) +#define CLKTREE_SYS_CLK_EN1 ((0x0008 << 2) + 0xfe000800) +#define CLKTREE_AXI_CLK_EN ((0x0009 << 2) + 0xfe000800) +#define CLKTREE_DSPA_CLK_EN ((0x000a << 2) + 0xfe000800) +#define CLKTREE_DSPB_CLK_EN ((0x000b << 2) + 0xfe000800) +#define CLKTREE_DSPA_CLK_CTRL0 ((0x000c << 2) + 0xfe000800) +#define CLKTREE_DSPB_CLK_CTRL0 ((0x000d << 2) + 0xfe000800) +#define CLKTREE_CLK12_24_CTRL ((0x000e << 2) + 0xfe000800) +#define CLKTREE_GEN_CLK_CTRL ((0x000f << 2) + 0xfe000800) +#define CLKTREE_TIMESTAMP_CTRL0 ((0x0010 << 2) + 0xfe000800) +#define CLKTREE_TIMESTAMP_CTRL1 ((0x0011 << 2) + 0xfe000800) +#define CLKTREE_TIMESTAMP_CTRL2 ((0x0012 << 2) + 0xfe000800) +#define CLKTREE_TIMESTAMP_VAL0 ((0x0013 << 2) + 0xfe000800) +#define CLKTREE_TIMESTAMP_VAL1 ((0x0014 << 2) + 0xfe000800) +#define CLKTREE_TIMEBASE_CTRL0 ((0x0015 << 2) + 0xfe000800) +#define CLKTREE_TIMEBASE_CTRL1 ((0x0016 << 2) + 0xfe000800) +#define CLKTREE_SAR_ADC_CLK_CTRL ((0x0030 << 2) + 0xfe000800) +#define CLKTREE_PWM_CLK_AB_CTRL ((0x0031 << 2) + 0xfe000800) +#define CLKTREE_PWM_CLK_CD_CTRL ((0x0032 << 2) + 0xfe000800) +#define CLKTREE_PWM_CLK_EF_CTRL ((0x0033 << 2) + 0xfe000800) +#define CLKTREE_SPICC_CLK_CTRL ((0x0034 << 2) + 0xfe000800) +#define CLKTREE_TS_CLK_CTRL ((0x0035 << 2) + 0xfe000800) +#define CLKTREE_SPIFC_CLK_CTRL ((0x0036 << 2) + 0xfe000800) +#define CLKTREE_USB_BUSCLK_CTRL ((0x0037 << 2) + 0xfe000800) +#define CLKTREE_SD_EMMC_CLK_CTRL ((0x0038 << 2) + 0xfe000800) +#define CLKTREE_CECA_CLK_CTRL0 ((0x0039 << 2) + 0xfe000800) +#define CLKTREE_CECA_CLK_CTRL1 ((0x003a << 2) + 0xfe000800) +#define CLKTREE_CECB_CLK_CTRL0 ((0x003b << 2) + 0xfe000800) +#define CLKTREE_CECB_CLK_CTRL1 ((0x003c << 2) + 0xfe000800) +#define CLKTREE_PSRAM_CLK_CTRL ((0x003d << 2) + 0xfe000800) +#define CLKTREE_DMC_CLK_CTRL ((0x003e << 2) + 0xfe000800) +#define CLKTREE_FCLK_DIV1_SEL ((0x003f << 2) + 0xfe000800) +#define CLKTREE_TST_CTRL0 ((0x0040 << 2) + 0xfe000800) +//======================================================================== +// APB0_CEC - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe000c00 +// ----------------------------------------------- +#define CECA_GEN_CNTL ((0x0000 << 2) + 0xfe000c00) +#define CECA_RW_REG ((0x0001 << 2) + 0xfe000c00) +#define CECA_INTR_MASKN ((0x0002 << 2) + 0xfe000c00) +#define CECA_INTR_CLR ((0x0003 << 2) + 0xfe000c00) +#define CECA_INTR_STAT ((0x0004 << 2) + 0xfe000c00) +#define CECB_GEN_CNTL ((0x0010 << 2) + 0xfe000c00) +#define CECB_RW_REG ((0x0011 << 2) + 0xfe000c00) +#define CECB_INTR_MASKN ((0x0012 << 2) + 0xfe000c00) +#define CECB_INTR_CLR ((0x0013 << 2) + 0xfe000c00) +#define CECB_INTR_STAT ((0x0014 << 2) + 0xfe000c00) +//======================================================================== +// APB0_IR_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe001000 +// ----------------------------------------------- +#define IRCTRL_IR_DEC_LDR_ACTIVE ((0x0000 << 2) + 0xfe001000) +#define IRCTRL_IR_DEC_LDR_IDLE ((0x0001 << 2) + 0xfe001000) +#define IRCTRL_IR_DEC_LDR_REPEAT ((0x0002 << 2) + 0xfe001000) +#define IRCTRL_IR_DEC_BIT_0 ((0x0003 << 2) + 0xfe001000) +#define IRCTRL_IR_DEC_REG0 ((0x0004 << 2) + 0xfe001000) +#define IRCTRL_IR_DEC_FRAME ((0x0005 << 2) + 0xfe001000) +#define IRCTRL_IR_DEC_STATUS ((0x0006 << 2) + 0xfe001000) +#define IRCTRL_IR_DEC_REG1 ((0x0007 << 2) + 0xfe001000) +#define IRCTRL_MF_IR_DEC_LDR_ACTIVE ((0x0010 << 2) + 0xfe001000) +#define IRCTRL_MF_IR_DEC_LDR_IDLE ((0x0011 << 2) + 0xfe001000) +#define IRCTRL_MF_IR_DEC_LDR_REPEAT ((0x0012 << 2) + 0xfe001000) +#define IRCTRL_MF_IR_DEC_BIT_0 ((0x0013 << 2) + 0xfe001000) +#define IRCTRL_MF_IR_DEC_REG0 ((0x0014 << 2) + 0xfe001000) +#define IRCTRL_MF_IR_DEC_FRAME ((0x0015 << 2) + 0xfe001000) +#define IRCTRL_MF_IR_DEC_STATUS ((0x0016 << 2) + 0xfe001000) +#define IRCTRL_MF_IR_DEC_REG1 ((0x0017 << 2) + 0xfe001000) +#define IRCTRL_MF_IR_DEC_REG2 ((0x0018 << 2) + 0xfe001000) +#define IRCTRL_MF_IR_DEC_DURATN2 ((0x0019 << 2) + 0xfe001000) +#define IRCTRL_MF_IR_DEC_DURATN3 ((0x001a << 2) + 0xfe001000) +#define IRCTRL_MF_IR_DEC_FRAME1 ((0x001b << 2) + 0xfe001000) +#define IRCTRL_MF_IR_DEC_STATUS1 ((0x001c << 2) + 0xfe001000) +#define IRCTRL_MF_IR_DEC_STATUS2 ((0x001d << 2) + 0xfe001000) +#define IRCTRL_MF_IR_DEC_REG3 ((0x001e << 2) + 0xfe001000) +#define IRCTRL_MF_IR_DEC_FRAME_RSV0 ((0x001f << 2) + 0xfe001000) +#define IRCTRL_MF_IR_DEC_FRAME_RSV1 ((0x0020 << 2) + 0xfe001000) +#define IRCTRL_MF_IR_DEC_FILTE ((0x0021 << 2) + 0xfe001000) +#define IRCTRL_MF_IR_DEC_IRQ_CTL ((0x0022 << 2) + 0xfe001000) +#define IRCTRL_MF_IR_DEC_FIFO_CTL ((0x0023 << 2) + 0xfe001000) +#define IRCTRL_MF_IR_DEC_WIDTH_NEW ((0x0024 << 2) + 0xfe001000) +#define IRCTRL_MF_IR_DEC_REPEAT_DET ((0x0025 << 2) + 0xfe001000) +#define IRCTRL_IR_DEC_DEMOD_CNTL0 ((0x0030 << 2) + 0xfe001000) +#define IRCTRL_IR_DEC_DEMOD_CNTL1 ((0x0031 << 2) + 0xfe001000) +#define IRCTRL_IR_DEC_DEMOD_IIR_THD ((0x0032 << 2) + 0xfe001000) +#define IRCTRL_IR_DEC_DEMOD_THD0 ((0x0033 << 2) + 0xfe001000) +#define IRCTRL_IR_DEC_DEMOD_THD1 ((0x0034 << 2) + 0xfe001000) +#define IRCTRL_IR_DEC_DEMOD_SUM_CNT0 ((0x0035 << 2) + 0xfe001000) +#define IRCTRL_IR_DEC_DEMOD_SUM_CNT1 ((0x0036 << 2) + 0xfe001000) +#define IRCTRL_IR_DEC_DEMOD_CNT0 ((0x0037 << 2) + 0xfe001000) +#define IRCTRL_IR_DEC_DEMOD_CNT1 ((0x0038 << 2) + 0xfe001000) +#define IRCTRL_IR_BLASTER_ADDR0 ((0x0043 << 2) + 0xfe001000) +#define IRCTRL_IR_BLASTER_ADDR1 ((0x0044 << 2) + 0xfe001000) +#define IRCTRL_IR_BLASTER_ADDR2 ((0x0045 << 2) + 0xfe001000) +#define IRCTRL_IR_BLASTER_ADDR3 ((0x0046 << 2) + 0xfe001000) +//======================================================================== +// APB0_I2C_M - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe001400 +// ----------------------------------------------- +#define I2C_M_A_CONTROL_REG ((0x0000 << 2) + 0xfe001400) +#define I2C_M_A_SLAVE_ADDR ((0x0001 << 2) + 0xfe001400) +#define I2C_M_A_TOKEN_LIST0 ((0x0002 << 2) + 0xfe001400) +#define I2C_M_A_TOKEN_LIST1 ((0x0003 << 2) + 0xfe001400) +#define I2C_M_A_WDATA_REG0 ((0x0004 << 2) + 0xfe001400) +#define I2C_M_A_WDATA_REG1 ((0x0005 << 2) + 0xfe001400) +#define I2C_M_A_RDATA_REG0 ((0x0006 << 2) + 0xfe001400) +#define I2C_M_A_RDATA_REG1 ((0x0007 << 2) + 0xfe001400) +#define I2C_M_A_TIMEOUT_TH ((0x0008 << 2) + 0xfe001400) +//======================================================================== +// APB0_I2C_S - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe001800 +// ----------------------------------------------- +#define I2C_S_A_CONTROL_REG ((0x0000 << 2) + 0xfe001800) +#define I2C_S_A_SEND_REG ((0x0001 << 2) + 0xfe001800) +#define I2C_S_A_RECV_REG ((0x0002 << 2) + 0xfe001800) +#define I2C_S_A_CNTL1_REG ((0x0003 << 2) + 0xfe001800) +//======================================================================== +// APB0_UART_A - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe001c00 +// ----------------------------------------------- +#define UART_A_WFIFO ((0x0000 << 2) + 0xfe001c00) +#define UART_A_RFIFO ((0x0001 << 2) + 0xfe001c00) +#define UART_A_CONTROL ((0x0002 << 2) + 0xfe001c00) +#define UART_A_STATUS ((0x0003 << 2) + 0xfe001c00) +#define UART_A_MISC ((0x0004 << 2) + 0xfe001c00) +#define UART_A_REG5 ((0x0005 << 2) + 0xfe001c00) +//======================================================================== +// APB0_UART_B - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe002000 +// ----------------------------------------------- +#define UART_B_WFIFO ((0x0000 << 2) + 0xfe002000) +#define UART_B_RFIFO ((0x0001 << 2) + 0xfe002000) +#define UART_B_CONTROL ((0x0002 << 2) + 0xfe002000) +#define UART_B_STATUS ((0x0003 << 2) + 0xfe002000) +#define UART_B_MISC ((0x0004 << 2) + 0xfe002000) +#define UART_B_REG5 ((0x0005 << 2) + 0xfe002000) +//======================================================================== +// APB0_PWM_AB - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe002400 +// ----------------------------------------------- +#define PWMAB_PWM_A ((0x0000 << 2) + 0xfe002400) +#define PWMAB_PWM_B ((0x0001 << 2) + 0xfe002400) +#define PWMAB_MISC_REG_AB ((0x0002 << 2) + 0xfe002400) +#define PWMAB_DELTA_SIGMA_AB ((0x0003 << 2) + 0xfe002400) +#define PWMAB_TIME_AB ((0x0004 << 2) + 0xfe002400) +#define PWMAB_A2 ((0x0005 << 2) + 0xfe002400) +#define PWMAB_B2 ((0x0006 << 2) + 0xfe002400) +#define PWMAB_BLINK_AB ((0x0007 << 2) + 0xfe002400) +#define PWMAB_LOCK_AB ((0x0008 << 2) + 0xfe002400) +//======================================================================== +// APB0_PWM_CD - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe002800 +// ----------------------------------------------- +#define PWMCD_PWM_C ((0x0000 << 2) + 0xfe002800) +#define PWMCD_PWM_D ((0x0001 << 2) + 0xfe002800) +#define PWMCD_MISC_REG_CD ((0x0002 << 2) + 0xfe002800) +#define PWMCD_DELTA_SIGMA_CD ((0x0003 << 2) + 0xfe002800) +#define PWMCD_TIME_CD ((0x0004 << 2) + 0xfe002800) +#define PWMCD_C2 ((0x0005 << 2) + 0xfe002800) +#define PWMCD_D2 ((0x0006 << 2) + 0xfe002800) +#define PWMCD_BLINK_CD ((0x0007 << 2) + 0xfe002800) +#define PWMCD_LOCK_CD ((0x0008 << 2) + 0xfe002800) +//======================================================================== +// APB0_SARADC - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe002c00 +// ----------------------------------------------- +#define SAR_ADC_REG0 ((0x0000 << 2) + 0xfe002c00) +#define SAR_ADC_CHAN_LIST ((0x0001 << 2) + 0xfe002c00) +#define SAR_ADC_AVG_CNTL ((0x0002 << 2) + 0xfe002c00) +#define SAR_ADC_REG3 ((0x0003 << 2) + 0xfe002c00) +#define SAR_ADC_DELAY ((0x0004 << 2) + 0xfe002c00) +#define SAR_ADC_LAST_RD ((0x0005 << 2) + 0xfe002c00) +#define SAR_ADC_FIFO_RD ((0x0006 << 2) + 0xfe002c00) +#define SAR_ADC_AUX_SW ((0x0007 << 2) + 0xfe002c00) +#define SAR_ADC_CHAN_10_SW ((0x0008 << 2) + 0xfe002c00) +#define SAR_ADC_DETECT_IDLE_SW ((0x0009 << 2) + 0xfe002c00) +#define SAR_ADC_DELTA_10 ((0x000a << 2) + 0xfe002c00) +#define SAR_ADC_REG11 ((0x000b << 2) + 0xfe002c00) +#define SAR_ADC_REG12 ((0x000c << 2) + 0xfe002c00) +#define SAR_ADC_REG13 ((0x000d << 2) + 0xfe002c00) +#define SAR_ADC_CHNL01 ((0x000e << 2) + 0xfe002c00) +#define SAR_ADC_CHNL23 ((0x000f << 2) + 0xfe002c00) +#define SAR_ADC_CHNL45 ((0x0010 << 2) + 0xfe002c00) +#define SAR_ADC_CHNL67 ((0x0011 << 2) + 0xfe002c00) +//======================================================================== +// JTAGCTRL_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe003000 +// ----------------------------------------------- +#define JTAGCTRL_CTRL0 ((0x0000 << 2) + 0xfe003000) +#define JTAGCTRL_PWD_CTRL0 ((0x0001 << 2) + 0xfe003000) +#define JTAGCTRL_PWD_ADDR0 ((0x0002 << 2) + 0xfe003000) +#define JTAGCTRL_PWD_ADDR1 ((0x0003 << 2) + 0xfe003000) +#define JTAGCTRL_PWD_ADDR2 ((0x0004 << 2) + 0xfe003000) +#define JTAGCTRL_PWD_ADDR3 ((0x0005 << 2) + 0xfe003000) +#define JTAGCTRL_PWD_VALUE0 ((0x0006 << 2) + 0xfe003000) +#define JTAGCTRL_PWD_VALUE1 ((0x0007 << 2) + 0xfe003000) +#define JTAGCTRL_PWD_VALUE2 ((0x0008 << 2) + 0xfe003000) +#define JTAGCTRL_PWD_VALUE3 ((0x0009 << 2) + 0xfe003000) +#define JTAGCTRL_PWD_STS ((0x000a << 2) + 0xfe003000) +//======================================================================== +// APB0_MSR_CLK - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe003400 +// ----------------------------------------------- +#define MSR_CLK_REG0 ((0x0000 << 2) + 0xfe003400) +#define MSR_CLK_REG1 ((0x0001 << 2) + 0xfe003400) +#define MSR_CLK_REG2 ((0x0002 << 2) + 0xfe003400) +#define MSR_CLK_REG3 ((0x0003 << 2) + 0xfe003400) +#define MSR_CLK_REG4 ((0x0004 << 2) + 0xfe003400) +#define MSR_CLK_REG5 ((0x0005 << 2) + 0xfe003400) +#define MSR_CLK_DUTY ((0x0006 << 2) + 0xfe003400) +//======================================================================== +// APB0_SPICCA_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe003800 +// ----------------------------------------------- +#define SPICC_A_RXDATA ((0x0000 << 2) + 0xfe003800) +#define SPICC_A_TXDATA ((0x0001 << 2) + 0xfe003800) +#define SPICC_A_CONREG ((0x0002 << 2) + 0xfe003800) +#define SPICC_A_INTREG ((0x0003 << 2) + 0xfe003800) +#define SPICC_A_DMAREG ((0x0004 << 2) + 0xfe003800) +#define SPICC_A_STATREG ((0x0005 << 2) + 0xfe003800) +#define SPICC_A_PERIODREG ((0x0006 << 2) + 0xfe003800) +#define SPICC_A_TESTREG ((0x0007 << 2) + 0xfe003800) +#define SPICC_A_DRADDR ((0x0008 << 2) + 0xfe003800) +#define SPICC_A_DWADDR ((0x0009 << 2) + 0xfe003800) +#define SPICC_A_LD_CNTL0 ((0x000a << 2) + 0xfe003800) +#define SPICC_A_LD_CNTL1 ((0x000b << 2) + 0xfe003800) +#define SPICC_A_LD_RADDR ((0x000c << 2) + 0xfe003800) +#define SPICC_A_LD_WADDR ((0x000d << 2) + 0xfe003800) +#define SPICC_A_ENHANCE_CNTL ((0x000e << 2) + 0xfe003800) +#define SPICC_A_ENHANCE_CNTL1 ((0x000f << 2) + 0xfe003800) +#define SPICC_A_ENHANCE_CNTL2 ((0x0010 << 2) + 0xfe003800) +//======================================================================== +// APB0_SPICCB_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe003c00 +// ----------------------------------------------- +#define SPICC_B_RXDATA ((0x0000 << 2) + 0xfe003c00) +#define SPICC_B_TXDATA ((0x0001 << 2) + 0xfe003c00) +#define SPICC_B_CONREG ((0x0002 << 2) + 0xfe003c00) +#define SPICC_B_INTREG ((0x0003 << 2) + 0xfe003c00) +#define SPICC_B_DMAREG ((0x0004 << 2) + 0xfe003c00) +#define SPICC_B_STATREG ((0x0005 << 2) + 0xfe003c00) +#define SPICC_B_PERIODREG ((0x0006 << 2) + 0xfe003c00) +#define SPICC_B_TESTREG ((0x0007 << 2) + 0xfe003c00) +#define SPICC_B_DRADDR ((0x0008 << 2) + 0xfe003c00) +#define SPICC_B_DWADDR ((0x0009 << 2) + 0xfe003c00) +#define SPICC_B_LD_CNTL0 ((0x000a << 2) + 0xfe003c00) +#define SPICC_B_LD_CNTL1 ((0x000b << 2) + 0xfe003c00) +#define SPICC_B_LD_RADDR ((0x000c << 2) + 0xfe003c00) +#define SPICC_B_LD_WADDR ((0x000d << 2) + 0xfe003c00) +#define SPICC_B_ENHANCE_CNTL ((0x000e << 2) + 0xfe003c00) +#define SPICC_B_ENHANCE_CNTL1 ((0x000f << 2) + 0xfe003c00) +#define SPICC_B_ENHANCE_CNTL2 ((0x0010 << 2) + 0xfe003c00) +//======================================================================== +// USBCTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe004000 +// ----------------------------------------------- +#define USB_CTRL0 ((0x0000 << 2) + 0xfe004000) +#define USB_CTRL1 ((0x0001 << 2) + 0xfe004000) +#define USB_CTRL2 ((0x0002 << 2) + 0xfe004000) +#define USB_CTRL3 ((0x0003 << 2) + 0xfe004000) +#define USB_CTRL4 ((0x0004 << 2) + 0xfe004000) +#define USB_CTRL5 ((0x0005 << 2) + 0xfe004000) +#define USB_CTRL6 ((0x0006 << 2) + 0xfe004000) +#define USB_CTRL7 ((0x0007 << 2) + 0xfe004000) +#define USB_CTRL8 ((0x0008 << 2) + 0xfe004000) +#define USB_CTRL9 ((0x0009 << 2) + 0xfe004000) +#define USB_CTRL10 ((0x000a << 2) + 0xfe004000) +#define USB_CTRL11 ((0x000b << 2) + 0xfe004000) +#define USB_CTRL12 ((0x000c << 2) + 0xfe004000) +#define USB_CTRL13 ((0x000d << 2) + 0xfe004000) +#define USB_CTRL14 ((0x000e << 2) + 0xfe004000) +#define USB_CTRL15 ((0x000f << 2) + 0xfe004000) +#define USB_CTRL16 ((0x0010 << 2) + 0xfe004000) +#define USB_CTRL17 ((0x0011 << 2) + 0xfe004000) +#define USB_CTRL18 ((0x0012 << 2) + 0xfe004000) +#define USB_CTRL19 ((0x0013 << 2) + 0xfe004000) +#define USB_CTRL20 ((0x0014 << 2) + 0xfe004000) +#define USB_CTRL21 ((0x0015 << 2) + 0xfe004000) +#define USB_CTRL22 ((0x0016 << 2) + 0xfe004000) +#define USB_CTRL23 ((0x0017 << 2) + 0xfe004000) +#define USB_CTRL24 ((0x0018 << 2) + 0xfe004000) +#define USB_CTRL25 ((0x0019 << 2) + 0xfe004000) +#define USB_CTRL26 ((0x001a << 2) + 0xfe004000) +#define USB_CTRL27 ((0x001b << 2) + 0xfe004000) +#define USB_CTRL28 ((0x001c << 2) + 0xfe004000) +#define USB_CTRL29 ((0x001d << 2) + 0xfe004000) +#define USB_CTRL30 ((0x001e << 2) + 0xfe004000) +#define USB_CTRL31 ((0x001f << 2) + 0xfe004000) +//======================================================================== +// APB0_ACODEC_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe004800 +// ----------------------------------------------- +#define ACODEC_0 ((0x0000 << 2) + 0xfe004800) +#define ACODEC_1 ((0x0001 << 2) + 0xfe004800) +#define ACODEC_2 ((0x0002 << 2) + 0xfe004800) +#define ACODEC_3 ((0x0003 << 2) + 0xfe004800) +#define ACODEC_4 ((0x0004 << 2) + 0xfe004800) +#define ACODEC_5 ((0x0005 << 2) + 0xfe004800) +#define ACODEC_6 ((0x0006 << 2) + 0xfe004800) +#define ACODEC_7 ((0x0007 << 2) + 0xfe004800) +#define ACODEC_8 ((0x0008 << 2) + 0xfe004800) +#define ACODEC_9 ((0x0009 << 2) + 0xfe004800) +#define ACODEC_STS0 ((0x0010 << 2) + 0xfe004800) +//======================================================================== +// APB0_TEMP_SENSOR - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe004c00 +// ----------------------------------------------- +#define TS_CFG_REG1 ((0x0001 << 2) + 0xfe004c00) +#define TS_CFG_REG2 ((0x0002 << 2) + 0xfe004c00) +#define TS_CFG_REG3 ((0x0003 << 2) + 0xfe004c00) +#define TS_CFG_REG4 ((0x0004 << 2) + 0xfe004c00) +#define TS_CFG_REG5 ((0x0005 << 2) + 0xfe004c00) +#define TS_CFG_REG6 ((0x0006 << 2) + 0xfe004c00) +#define TS_CFG_REG7 ((0x0007 << 2) + 0xfe004c00) +#define TS_STAT0 ((0x0010 << 2) + 0xfe004c00) +#define TS_STAT1 ((0x0011 << 2) + 0xfe004c00) +#define TS_STAT2 ((0x0012 << 2) + 0xfe004c00) +#define TS_STAT3 ((0x0013 << 2) + 0xfe004c00) +#define TS_STAT4 ((0x0014 << 2) + 0xfe004c00) +#define TS_STAT5 ((0x0015 << 2) + 0xfe004c00) +#define TS_STAT6 ((0x0016 << 2) + 0xfe004c00) +#define TS_STAT7 ((0x0017 << 2) + 0xfe004c00) +#define TS_STAT8 ((0x0018 << 2) + 0xfe004c00) +#define TS_STAT9 ((0x0019 << 2) + 0xfe004c00) +//======================================================================== +// APB0_KL_EFUSE_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe005000 +// ----------------------------------------------- +// +// Reading file: ../crypto/crypto_reg.h +// +#define OTP_TEE_RDY ((0x0000 << 2) + 0xfe005000) +#define OTP_TEE_CHK ((0x0001 << 2) + 0xfe005000) +#define OTP_TEE_CFG ((0x0002 << 2) + 0xfe005000) +#define OTP_TEE_WR_DAT0 ((0x0004 << 2) + 0xfe005000) +#define OTP_TEE_WR_DAT1 ((0x0005 << 2) + 0xfe005000) +#define OTP_TEE_WR_DAT2 ((0x0006 << 2) + 0xfe005000) +#define OTP_TEE_WR_DAT3 ((0x0007 << 2) + 0xfe005000) +#define OTP_TEE_RD_DAT0 ((0x0008 << 2) + 0xfe005000) +#define OTP_TEE_RD_DAT1 ((0x0009 << 2) + 0xfe005000) +#define OTP_TEE_RD_DAT2 ((0x000a << 2) + 0xfe005000) +#define OTP_TEE_RD_DAT3 ((0x000b << 2) + 0xfe005000) +#define OTP_RMA_PW0 ((0x000c << 2) + 0xfe005000) +#define OTP_RMA_PW1 ((0x000d << 2) + 0xfe005000) +#define OTP_RMA_PW2 ((0x000e << 2) + 0xfe005000) +#define OTP_RMA_PW3 ((0x000f << 2) + 0xfe005000) +#define OTP_REE_RDY ((0x0010 << 2) + 0xfe005000) +#define OTP_REE_CHK ((0x0011 << 2) + 0xfe005000) +#define OTP_REE_CFG ((0x0012 << 2) + 0xfe005000) +#define OTP_REE_RD_DAT0 ((0x0014 << 2) + 0xfe005000) +#define OTP_REE_RD_DAT1 ((0x0015 << 2) + 0xfe005000) +#define OTP_REE_RD_DAT2 ((0x0016 << 2) + 0xfe005000) +#define OTP_REE_RD_DAT3 ((0x0017 << 2) + 0xfe005000) +#define OTP_LIC0 ((0x0018 << 2) + 0xfe005000) +#define OTP_LIC1 ((0x0019 << 2) + 0xfe005000) +#define OTP_LIC2 ((0x001a << 2) + 0xfe005000) +#define OTP_LIC3 ((0x001b << 2) + 0xfe005000) +#define RNG_SEC_CONFIG_REG1 ((0x0041 << 2) + 0xfe005000) +#define RNG_SEC_CONFIG_REG2 ((0x0042 << 2) + 0xfe005000) +#define RNG_SEC_DATA ((0x0044 << 2) + 0xfe005000) +#define RNG_SEC_STS ((0x0045 << 2) + 0xfe005000) +#define RNG_USR_DATA ((0x0046 << 2) + 0xfe005000) +#define RNG_USR_STS ((0x0047 << 2) + 0xfe005000) +#define KTE_SLOT0 ((0x0060 << 2) + 0xfe005000) +#define KTE_SLOT1 ((0x0061 << 2) + 0xfe005000) +#define KTE_SLOT2 ((0x0062 << 2) + 0xfe005000) +#define KTE_SLOT3 ((0x0063 << 2) + 0xfe005000) +#define KTE_SLOT4 ((0x0064 << 2) + 0xfe005000) +#define KTE_SLOT5 ((0x0065 << 2) + 0xfe005000) +#define KTE_SLOT6 ((0x0066 << 2) + 0xfe005000) +#define KTE_SLOT7 ((0x0067 << 2) + 0xfe005000) +#define MKL_TEE_RDY ((0x0080 << 2) + 0xfe005000) +#define MKL_TEE_CHK ((0x0081 << 2) + 0xfe005000) +#define MKL_TEE_CFG ((0x0082 << 2) + 0xfe005000) +#define MKL_TEE_EK ((0x0084 << 2) + 0xfe005000) +#define MKL_REE_RDY ((0x00a0 << 2) + 0xfe005000) +#define MKL_REE_CHK ((0x00a1 << 2) + 0xfe005000) +#define MKL_REE_CFG ((0x00a2 << 2) + 0xfe005000) +#define MKL_REE_EK ((0x00a4 << 2) + 0xfe005000) +// +// Closing file: ../crypto/crypto_reg.h +// +//======================================================================== +// APB0_PWM_EF - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe005400 +// ----------------------------------------------- +#define PWMEF_PWM_E ((0x0000 << 2) + 0xfe005400) +#define PWMEF_PWM_F ((0x0001 << 2) + 0xfe005400) +#define PWMEF_MISC_REG_EF ((0x0002 << 2) + 0xfe005400) +#define PWMEF_DELTA_SIGMA_EF ((0x0003 << 2) + 0xfe005400) +#define PWMEF_TIME_EF ((0x0004 << 2) + 0xfe005400) +#define PWMEF_E2 ((0x0005 << 2) + 0xfe005400) +#define PWMEF_F2 ((0x0006 << 2) + 0xfe005400) +#define PWMEF_BLINK_EF ((0x0007 << 2) + 0xfe005400) +#define PWMEF_LOCK_EF ((0x0008 << 2) + 0xfe005400) +//======================================================================== +// APB0_SYS_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe005800 +// ----------------------------------------------- +#define SYSCTRL_METAL_REV0 ((0x0000 << 2) + 0xfe005800) +#define SYSCTRL_METAL_REV1 ((0x0001 << 2) + 0xfe005800) +//`define SYSCTRL_PROD_ENABLE 8'h0a +#define SYSCTRL_CHIP_ID ((0x000b << 2) + 0xfe005800) +#define SYSCTRL_WRITEONCE1_REG0 ((0x0010 << 2) + 0xfe005800) +#define SYSCTRL_WRITEONCE1_STICKY_REG0 ((0x0011 << 2) + 0xfe005800) +#define SYSCTRL_WRITEONCE1_SEC_REG0 ((0x0012 << 2) + 0xfe005800) +#define SYSCTRL_WRITEONCE1_STICKY_SEC_REG0 ((0x0013 << 2) + 0xfe005800) +#define SYSCTRL_WRITEONCE_REG0 ((0x0014 << 2) + 0xfe005800) +#define SYSCTRL_WRITEONCE_REG1 ((0x0015 << 2) + 0xfe005800) +#define SYSCTRL_WRITEONCE_SEC_REG0 ((0x0016 << 2) + 0xfe005800) +#define SYSCTRL_WRITEONCE_STICKY_REG0 ((0x0017 << 2) + 0xfe005800) +#define SYSCTRL_WRITEONCE_STICKY_REG1 ((0x0018 << 2) + 0xfe005800) +#define SYSCTRL_WRITEONCE_STICKY_SEC_REG0 ((0x0019 << 2) + 0xfe005800) +#define SYSCTRL_TIMERA_CTRL ((0x0030 << 2) + 0xfe005800) +#define SYSCTRL_TIMERA ((0x0031 << 2) + 0xfe005800) +#define SYSCTRL_TIMERB_CTRL ((0x0032 << 2) + 0xfe005800) +#define SYSCTRL_TIMERB ((0x0033 << 2) + 0xfe005800) +#define SYSCTRL_TIMERC_CTRL ((0x0034 << 2) + 0xfe005800) +#define SYSCTRL_TIMERC ((0x0035 << 2) + 0xfe005800) +#define SYSCTRL_TIMERD_CTRL ((0x0036 << 2) + 0xfe005800) +#define SYSCTRL_TIMERD ((0x0037 << 2) + 0xfe005800) +#define SYSCTRL_SEC_TIMERA_CTRL ((0x0038 << 2) + 0xfe005800) +#define SYSCTRL_SEC_TIMERA ((0x0039 << 2) + 0xfe005800) +#define SYSCTRL_TIMERE_CTRL ((0x0040 << 2) + 0xfe005800) +#define SYSCTRL_TIMERE ((0x0041 << 2) + 0xfe005800) +#define SYSCTRL_TIMERE_HI ((0x0042 << 2) + 0xfe005800) +#define SYSCTRL_TIMERF_CTRL ((0x0043 << 2) + 0xfe005800) +#define SYSCTRL_TIMERF ((0x0044 << 2) + 0xfe005800) +#define SYSCTRL_TIMERF_HI ((0x0045 << 2) + 0xfe005800) +#define SYSCTRL_SEC_TIMERE_CTRL ((0x0046 << 2) + 0xfe005800) +#define SYSCTRL_SEC_TIMERE ((0x0047 << 2) + 0xfe005800) +#define SYSCTRL_SEC_TIMERE_HI ((0x0048 << 2) + 0xfe005800) +#define SYSCTRL_OSC_RING_CTRL0 ((0x0050 << 2) + 0xfe005800) +#define SYSCTRL_SEC_DDR_AXI_SEL ((0x0051 << 2) + 0xfe005800) +#define SYSCTRL_AM2AXI_CTRL0 ((0x0052 << 2) + 0xfe005800) +#define SYSCTRL_AM2AXI_STS ((0x0053 << 2) + 0xfe005800) +#define SYSCTRL_POC ((0x0060 << 2) + 0xfe005800) +//`define SYSCTRL_PROD_PWD_VALUE0 8'h80 +//`define SYSCTRL_PROD_PWD_VALUE1 8'h81 +//`define SYSCTRL_PROD_PWD_VALUE2 8'h82 +//`define SYSCTRL_PROD_PWD_VALUE3 8'h83 +//`define SYSCTRL_PROD_STATUS 8'h84 +#define SYSCTRL_DEBUG_REG0 ((0x0090 << 2) + 0xfe005800) +#define SYSCTRL_DEBUG_REG1 ((0x0091 << 2) + 0xfe005800) +#define SYSCTRL_DEBUG_REG2 ((0x0092 << 2) + 0xfe005800) +#define SYSCTRL_DEBUG_REG3 ((0x0093 << 2) + 0xfe005800) +#define SYSCTRL_DEBUG_REG4 ((0x0094 << 2) + 0xfe005800) +#define SYSCTRL_DEBUG_REG5 ((0x0095 << 2) + 0xfe005800) +#define SYSCTRL_DEBUG_REG6 ((0x0096 << 2) + 0xfe005800) +#define SYSCTRL_DEBUG_REG7 ((0x0097 << 2) + 0xfe005800) +#define SYSCTRL_STATUS_REG0 ((0x00a0 << 2) + 0xfe005800) +#define SYSCTRL_STATUS_REG1 ((0x00a1 << 2) + 0xfe005800) +#define SYSCTRL_STATUS_REG2 ((0x00a2 << 2) + 0xfe005800) +#define SYSCTRL_STATUS_REG3 ((0x00a3 << 2) + 0xfe005800) +#define SYSCTRL_STATUS_REG4 ((0x00a4 << 2) + 0xfe005800) +#define SYSCTRL_STATUS_REG5 ((0x00a5 << 2) + 0xfe005800) +#define SYSCTRL_STATUS_REG6 ((0x00a6 << 2) + 0xfe005800) +#define SYSCTRL_STATUS_REG7 ((0x00a7 << 2) + 0xfe005800) +#define SYSCTRL_STICKY_REG0 ((0x00b0 << 2) + 0xfe005800) +#define SYSCTRL_STICKY_REG1 ((0x00b1 << 2) + 0xfe005800) +#define SYSCTRL_STICKY_REG2 ((0x00b2 << 2) + 0xfe005800) +#define SYSCTRL_STICKY_REG3 ((0x00b3 << 2) + 0xfe005800) +#define SYSCTRL_STICKY_REG4 ((0x00b4 << 2) + 0xfe005800) +#define SYSCTRL_STICKY_REG5 ((0x00b5 << 2) + 0xfe005800) +#define SYSCTRL_STICKY_REG6 ((0x00b6 << 2) + 0xfe005800) +#define SYSCTRL_STICKY_REG7 ((0x00b7 << 2) + 0xfe005800) +#define SYSCTRL_SEC_STATUS_REG0 ((0x00c0 << 2) + 0xfe005800) +#define SYSCTRL_SEC_STATUS_REG1 ((0x00c1 << 2) + 0xfe005800) +#define SYSCTRL_SEC_STATUS_REG2 ((0x00c2 << 2) + 0xfe005800) +#define SYSCTRL_SEC_STATUS_REG3 ((0x00c3 << 2) + 0xfe005800) +#define SYSCTRL_SEC_STATUS_REG4 ((0x00c4 << 2) + 0xfe005800) +#define SYSCTRL_SEC_STATUS_REG5 ((0x00c5 << 2) + 0xfe005800) +#define SYSCTRL_SEC_STATUS_REG6 ((0x00c6 << 2) + 0xfe005800) +#define SYSCTRL_SEC_STATUS_REG7 ((0x00c7 << 2) + 0xfe005800) +#define SYSCTRL_SEC_STATUS_REG8 ((0x00c8 << 2) + 0xfe005800) +#define SYSCTRL_SEC_STATUS_REG9 ((0x00c9 << 2) + 0xfe005800) +#define SYSCTRL_SEC_STATUS_REG10 ((0x00ca << 2) + 0xfe005800) +#define SYSCTRL_SEC_STATUS_REG11 ((0x00cb << 2) + 0xfe005800) +#define SYSCTRL_SEC_STATUS_REG12 ((0x00cc << 2) + 0xfe005800) +#define SYSCTRL_SEC_STATUS_REG13 ((0x00cd << 2) + 0xfe005800) +#define SYSCTRL_SEC_STATUS_REG14 ((0x00ce << 2) + 0xfe005800) +#define SYSCTRL_SEC_STATUS_REG15 ((0x00cf << 2) + 0xfe005800) +#define SYSCTRL_SEC_STATUS_REG16 ((0x00d0 << 2) + 0xfe005800) +#define SYSCTRL_SEC_STATUS_REG17 ((0x00d1 << 2) + 0xfe005800) +#define SYSCTRL_SEC_STATUS_REG18 ((0x00d2 << 2) + 0xfe005800) +#define SYSCTRL_SEC_STATUS_REG19 ((0x00d3 << 2) + 0xfe005800) +#define SYSCTRL_SEC_STATUS_REG20 ((0x00d4 << 2) + 0xfe005800) +#define SYSCTRL_SEC_STATUS_REG21 ((0x00d5 << 2) + 0xfe005800) +#define SYSCTRL_SEC_STATUS_REG22 ((0x00d6 << 2) + 0xfe005800) +#define SYSCTRL_SEC_STATUS_REG23 ((0x00d7 << 2) + 0xfe005800) +#define SYSCTRL_SEC_STICKY_REG0 ((0x00e0 << 2) + 0xfe005800) +#define SYSCTRL_SEC_STICKY_REG1 ((0x00e1 << 2) + 0xfe005800) +#define SYSCTRL_SEC_STICKY_REG2 ((0x00e2 << 2) + 0xfe005800) +#define SYSCTRL_SEC_STICKY_REG3 ((0x00e3 << 2) + 0xfe005800) +#define SYSCTRL_SEC_STICKY_REG4 ((0x00e4 << 2) + 0xfe005800) +#define SYSCTRL_SEC_STICKY_REG5 ((0x00e5 << 2) + 0xfe005800) +#define SYSCTRL_SEC_STICKY_REG6 ((0x00e6 << 2) + 0xfe005800) +#define SYSCTRL_SEC_STICKY_REG7 ((0x00e7 << 2) + 0xfe005800) +#define SYSCTRL_MSG_INDEX0_STICKY ((0x00f0 << 2) + 0xfe005800) +#define SYSCTRL_MSG_INDEX1_STICKY ((0x00f1 << 2) + 0xfe005800) +#define SYSCTRL_MSG_INDEX2_STICKY ((0x00f2 << 2) + 0xfe005800) +#define SYSCTRL_MSG_INDEX3_STICKY ((0x00f3 << 2) + 0xfe005800) +//======================================================================== +// APB0_I2C_M_B - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe005c00 +// ----------------------------------------------- +#define I2C_M_B_CONTROL_REG ((0x0000 << 2) + 0xfe005c00) +#define I2C_M_B_SLAVE_ADDR ((0x0001 << 2) + 0xfe005c00) +#define I2C_M_B_TOKEN_LIST0 ((0x0002 << 2) + 0xfe005c00) +#define I2C_M_B_TOKEN_LIST1 ((0x0003 << 2) + 0xfe005c00) +#define I2C_M_B_WDATA_REG0 ((0x0004 << 2) + 0xfe005c00) +#define I2C_M_B_WDATA_REG1 ((0x0005 << 2) + 0xfe005c00) +#define I2C_M_B_RDATA_REG0 ((0x0006 << 2) + 0xfe005c00) +#define I2C_M_B_RDATA_REG1 ((0x0007 << 2) + 0xfe005c00) +#define I2C_M_B_TIMEOUT_TH ((0x0008 << 2) + 0xfe005c00) +//======================================================================== +// APB0_DMA - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe006000 +// ----------------------------------------------- +//TODO +//======================================================================== +// APB0_IRQ_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe006400 +// ----------------------------------------------- +#define IRQCTRL_IRQOUT_MASK0 ((0x0000 << 2) + 0xfe006400) +#define IRQCTRL_IRQOUT_MASK1 ((0x0001 << 2) + 0xfe006400) +#define IRQCTRL_IRQOUT_MASK2 ((0x0002 << 2) + 0xfe006400) +#define IRQCTRL_IRQOUT_MASK3 ((0x0003 << 2) + 0xfe006400) +#define IRQCTRL_IRQOUT_INV0 ((0x0010 << 2) + 0xfe006400) +#define IRQCTRL_IRQOUT_INV1 ((0x0011 << 2) + 0xfe006400) +#define IRQCTRL_IRQOUT_INV2 ((0x0012 << 2) + 0xfe006400) +#define IRQCTRL_IRQOUT_INV3 ((0x0013 << 2) + 0xfe006400) +//`define APB0_IRQIN_MASK0_CLK_USB 8'h00 +//`define APB0_IRQIN_MASK0_CLK_CPU 8'h01 +//`define APB0_IRQIN_MASK0_CLK_SYS 8'h02 +//`define APB0_IRQIN_MASK1_CLK_SYS 8'h03 +//`define APB0_IRQIN_MASK0_CLK_DSPA 8'h04 +//`define APB0_IRQIN_MASK0_CLK_DSPB 8'h05 +//`define APB0_IRQIN_CLRLVL_CLK_USB 8'h10 +//`define APB0_IRQIN_CLRLVL_CLK_DSPA 8'h11 +//`define APB0_IRQIN_CLRLVL_CLK_DSPB 8'h12 +//======================================================================== +// APB0_I2C_M - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe006800 +// ----------------------------------------------- +#define I2C_M_C_CONTROL_REG ((0x0000 << 2) + 0xfe006800) +#define I2C_M_C_SLAVE_ADDR ((0x0001 << 2) + 0xfe006800) +#define I2C_M_C_TOKEN_LIST0 ((0x0002 << 2) + 0xfe006800) +#define I2C_M_C_TOKEN_LIST1 ((0x0003 << 2) + 0xfe006800) +#define I2C_M_C_WDATA_REG0 ((0x0004 << 2) + 0xfe006800) +#define I2C_M_C_WDATA_REG1 ((0x0005 << 2) + 0xfe006800) +#define I2C_M_C_RDATA_REG0 ((0x0006 << 2) + 0xfe006800) +#define I2C_M_C_RDATA_REG1 ((0x0007 << 2) + 0xfe006800) +#define I2C_M_C_TIMEOUT_TH ((0x0008 << 2) + 0xfe006800) +//======================================================================== +// APB0_I2C_M - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe006c00 +// ----------------------------------------------- +#define I2C_M_D_CONTROL_REG ((0x0000 << 2) + 0xfe006c00) +#define I2C_M_D_SLAVE_ADDR ((0x0001 << 2) + 0xfe006c00) +#define I2C_M_D_TOKEN_LIST0 ((0x0002 << 2) + 0xfe006c00) +#define I2C_M_D_TOKEN_LIST1 ((0x0003 << 2) + 0xfe006c00) +#define I2C_M_D_WDATA_REG0 ((0x0004 << 2) + 0xfe006c00) +#define I2C_M_D_WDATA_REG1 ((0x0005 << 2) + 0xfe006c00) +#define I2C_M_D_RDATA_REG0 ((0x0006 << 2) + 0xfe006c00) +#define I2C_M_D_RDATA_REG1 ((0x0007 << 2) + 0xfe006c00) +#define I2C_M_D_TIMEOUT_TH ((0x0008 << 2) + 0xfe006c00) +//======================================================================== +// APB0_UART_C - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe007000 +// ----------------------------------------------- +#define UART_C_WFIFO ((0x0000 << 2) + 0xfe007000) +#define UART_C_RFIFO ((0x0001 << 2) + 0xfe007000) +#define UART_C_CONTROL ((0x0002 << 2) + 0xfe007000) +#define UART_C_STATUS ((0x0003 << 2) + 0xfe007000) +#define UART_C_MISC ((0x0004 << 2) + 0xfe007000) +#define UART_C_REG5 ((0x0005 << 2) + 0xfe007000) +//======================================================================== +// APB0_PWR_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe007800 +// ----------------------------------------------- +#define PWRCTRL_PWR_ACK0 ((0x0000 << 2) + 0xfe007800) +#define PWRCTRL_ISO_EN0 ((0x0001 << 2) + 0xfe007800) +#define PWRCTRL_PWR_OFF0 ((0x0002 << 2) + 0xfe007800) +#define PWRCTRL_SAVE_EN0 ((0x0003 << 2) + 0xfe007800) +#define PWRCTRL_RESTORE_EN0 ((0x0004 << 2) + 0xfe007800) +#define PWRCTRL_MEM_PD0 ((0x0010 << 2) + 0xfe007800) +#define PWRCTRL_MEM_PD1 ((0x0011 << 2) + 0xfe007800) +#define PWRCTRL_MEM_PD2 ((0x0012 << 2) + 0xfe007800) +#define PWRCTRL_MEM_PD3 ((0x0013 << 2) + 0xfe007800) +#define PWRCTRL_MEM_PD4 ((0x0014 << 2) + 0xfe007800) +#define PWRCTRL_R_ISO_EN0 ((0x0020 << 2) + 0xfe007800) +#define PWRCTRL_R_PWR_OFF0 ((0x0021 << 2) + 0xfe007800) +#define PWRCTRL_R_MEM_PD0 ((0x0022 << 2) + 0xfe007800) +#define PWRCTRL_R_MEM_PD1 ((0x0023 << 2) + 0xfe007800) +#define PWRCTRL_R_MEM_PD2 ((0x0024 << 2) + 0xfe007800) +#define PWRCTRL_R_MEM_PD3 ((0x0025 << 2) + 0xfe007800) +#define PWRCTRL_R_MEM_PD4 ((0x0026 << 2) + 0xfe007800) +//`define PWRCTRL_MEM_PD_DSPA 8'h10 +//`define PWRCTRL_MEM_PD_DSPB 8'h11 +//`define PWRCTRL_MEM_PD_RAMA 8'h12 +//`define PWRCTRL_MEM_PD_RAMB 8'h13 +//`define PWRCTRL_MEM_PD_CPU 8'h14 +//`define PWRCTRL_MEM_PD_AUDIO 8'h20 +//`define PWRCTRL_MEM_PD_USBCTRL 8'h21 +//`define PWRCTRL_MEM_PD_SPICC 8'h22 +//`define PWRCTRL_MEM_PD_SPIFC 8'h23 +//`define PWRCTRL_MEM_PD_IR 8'h24 +//`define PWRCTRL_MEM_PD_SDIO 8'h25 +//`define PWRCTRL_MEM_PD_KLEFUSE 8'h26 +//`define PWRCTRL_MEM_PD_PSRAM 8'h27 +//`define PWRCTRL_MEM_PD_DDR 8'h28 +//`define PWRCTRL_MEM_PD_DMC 8'h29 +#define PWRCTRL_AUTO_OFF_CTRL ((0x0030 << 2) + 0xfe007800) +#define PWRCTRL_AUTO_OFF ((0x0031 << 2) + 0xfe007800) +#define PWRCTRL_AUTO_OFF_STS ((0x0032 << 2) + 0xfe007800) +#define PWRCTRL_TIMER_TH_01 ((0x0033 << 2) + 0xfe007800) +#define PWRCTRL_TIMER_TH_23 ((0x0034 << 2) + 0xfe007800) +#define PWRCTRL_TIMER_TH_45 ((0x0035 << 2) + 0xfe007800) +#define PWRCTRL_TIMER_TH_67 ((0x0036 << 2) + 0xfe007800) +#define PWRCTRL_MASK_PWR_ACK0 ((0x0040 << 2) + 0xfe007800) +#define PWRCTRL_MASK_RSTN_OFF0 ((0x0041 << 2) + 0xfe007800) +#define PWRCTRL_MASK_RSTN_ON0 ((0x0042 << 2) + 0xfe007800) +#define PWRCTRL_MASK_PWR_OFF0 ((0x0043 << 2) + 0xfe007800) +#define PWRCTRL_MASK_PWR_ON0 ((0x0044 << 2) + 0xfe007800) +#define PWRCTRL_MASK_ISO_OFF0 ((0x0045 << 2) + 0xfe007800) +#define PWRCTRL_MASK_ISO_ON0 ((0x0046 << 2) + 0xfe007800) +#define PWRCTRL_MASK_MEM_OFF0 ((0x0050 << 2) + 0xfe007800) +#define PWRCTRL_MASK_MEM_OFF1 ((0x0051 << 2) + 0xfe007800) +#define PWRCTRL_MASK_MEM_OFF2 ((0x0052 << 2) + 0xfe007800) +#define PWRCTRL_MASK_MEM_OFF3 ((0x0053 << 2) + 0xfe007800) +#define PWRCTRL_MASK_MEM_OFF4 ((0x0054 << 2) + 0xfe007800) +#define PWRCTRL_MASK_MEM_ON0 ((0x0058 << 2) + 0xfe007800) +#define PWRCTRL_MASK_MEM_ON1 ((0x0059 << 2) + 0xfe007800) +#define PWRCTRL_MASK_MEM_ON2 ((0x005a << 2) + 0xfe007800) +#define PWRCTRL_MASK_MEM_ON3 ((0x005b << 2) + 0xfe007800) +#define PWRCTRL_MASK_MEM_ON4 ((0x005c << 2) + 0xfe007800) +//======================================================================== +// APB0_ANA_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe007c00 +// ----------------------------------------------- +#define ANACTRL_FIXPLL_CTRL0 ((0x0020 << 2) + 0xfe007c00) +#define ANACTRL_FIXPLL_CTRL1 ((0x0021 << 2) + 0xfe007c00) +#define ANACTRL_FIXPLL_CTRL2 ((0x0022 << 2) + 0xfe007c00) +#define ANACTRL_FIXPLL_CTRL3 ((0x0023 << 2) + 0xfe007c00) +#define ANACTRL_FIXPLL_CTRL4 ((0x0024 << 2) + 0xfe007c00) +#define ANACTRL_FIXPLL_STS ((0x0025 << 2) + 0xfe007c00) +#define ANACTRL_SYSPLL_CTRL0 ((0x0040 << 2) + 0xfe007c00) +#define ANACTRL_SYSPLL_CTRL1 ((0x0041 << 2) + 0xfe007c00) +#define ANACTRL_SYSPLL_CTRL2 ((0x0042 << 2) + 0xfe007c00) +#define ANACTRL_SYSPLL_CTRL3 ((0x0043 << 2) + 0xfe007c00) +#define ANACTRL_SYSPLL_CTRL4 ((0x0044 << 2) + 0xfe007c00) +#define ANACTRL_SYSPLL_STS ((0x0045 << 2) + 0xfe007c00) +#define ANACTRL_HIFIPLL_CTRL0 ((0x0050 << 2) + 0xfe007c00) +#define ANACTRL_HIFIPLL_CTRL1 ((0x0051 << 2) + 0xfe007c00) +#define ANACTRL_HIFIPLL_CTRL2 ((0x0052 << 2) + 0xfe007c00) +#define ANACTRL_HIFIPLL_CTRL3 ((0x0053 << 2) + 0xfe007c00) +#define ANACTRL_HIFIPLL_CTRL4 ((0x0054 << 2) + 0xfe007c00) +#define ANACTRL_HIFIPLL_STS ((0x0055 << 2) + 0xfe007c00) +#define ANACTRL_AUDDDS_CTRL0 ((0x0060 << 2) + 0xfe007c00) +#define ANACTRL_AUDDDS_CTRL1 ((0x0061 << 2) + 0xfe007c00) +#define ANACTRL_AUDDDS_CTRL2 ((0x0062 << 2) + 0xfe007c00) +#define ANACTRL_AUDDDS_CTRL3 ((0x0063 << 2) + 0xfe007c00) +#define ANACTRL_AUDDDS_CTRL4 ((0x0064 << 2) + 0xfe007c00) +#define ANACTRL_AUDDDS_STS ((0x0065 << 2) + 0xfe007c00) +#define ANACTRL_MISCTOP_CTRL0 ((0x0070 << 2) + 0xfe007c00) +#define ANACTRL_POR_CNTL ((0x0082 << 2) + 0xfe007c00) +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe020000 +// ----------------------------------------------- +#define RSA_BASE ((0x0000 << 2) + 0xfe020000) +//======================================================================== +// CPUCTRL_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB1_BASE_ADDR = 0xfd000000 +// ----------------------------------------------- +#define CPUCTRL_CTRL0 ((0x0000 << 2) + 0xfd000000) +#define CPUCTRL_CTRL1 ((0x0001 << 2) + 0xfd000000) +#define CPUCTRL_CTRL2 ((0x0002 << 2) + 0xfd000000) +#define CPUCTRL_CTRL3 ((0x0003 << 2) + 0xfd000000) +#define CPUCTRL_CTRL4 ((0x0004 << 2) + 0xfd000000) +#define CPUCTRL_CTRL5 ((0x0005 << 2) + 0xfd000000) +#define CPUCTRL_CTRL6 ((0x0006 << 2) + 0xfd000000) +#define CPUCTRL_CTRL7 ((0x0007 << 2) + 0xfd000000) +#define CPUCTRL_CTRL8 ((0x0008 << 2) + 0xfd000000) +#define CPUCTRL_CTRL9 ((0x0009 << 2) + 0xfd000000) +#define CPUCTRL_CTRL10 ((0x000a << 2) + 0xfd000000) +#define CPUCTRL_CTRL11 ((0x000b << 2) + 0xfd000000) +#define CPUCTRL_CTRL12 ((0x000c << 2) + 0xfd000000) +#define CPUCTRL_CTRL13 ((0x000d << 2) + 0xfd000000) +#define CPUCTRL_CTRL14 ((0x000e << 2) + 0xfd000000) +#define CPUCTRL_CTRL15 ((0x000f << 2) + 0xfd000000) +#define CPUCTRL_STS0 ((0x0010 << 2) + 0xfd000000) +#define CPUCTRL_STS1 ((0x0011 << 2) + 0xfd000000) +#define CPUCTRL_STS2 ((0x0012 << 2) + 0xfd000000) +#define CPUCTRL_STS3 ((0x0013 << 2) + 0xfd000000) +#define CPUCTRL_STS4 ((0x0014 << 2) + 0xfd000000) +#define CPUCTRL_STS5 ((0x0015 << 2) + 0xfd000000) +#define CPUCTRL_STS6 ((0x0016 << 2) + 0xfd000000) +#define CPUCTRL_STS7 ((0x0017 << 2) + 0xfd000000) +#define CPUCTRL_STS8 ((0x0018 << 2) + 0xfd000000) +#define CPUCTRL_STS9 ((0x0019 << 2) + 0xfd000000) +#define CPUCTRL_CLK_CTRL0 ((0x0020 << 2) + 0xfd000000) +#define CPUCTRL_CLK_CTRL1 ((0x0021 << 2) + 0xfd000000) +#define CPUCTRL_CLK_CTRL2 ((0x0022 << 2) + 0xfd000000) +#define CPUCTRL_CLK_CTRL3 ((0x0023 << 2) + 0xfd000000) +#define CPUCTRL_CLK_CTRL4 ((0x0024 << 2) + 0xfd000000) +#define CPUCTRL_CLK_CTRL5 ((0x0025 << 2) + 0xfd000000) +#define CPUCTRL_CLK_CTRL6 ((0x0026 << 2) + 0xfd000000) +#define CPUCTRL_CLK_CTRL7 ((0x0027 << 2) + 0xfd000000) +#define CPUCTRL_RESET_CTRL ((0x0030 << 2) + 0xfd000000) +#define CPUCTRL_ROM_DISABLE ((0x0031 << 2) + 0xfd000000) +//======================================================================== +// RAMA_SEC_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB1_BASE_ADDR = 0xfd000800 +// ----------------------------------------------- +#define SRAM_RANGE0_STA ((0x0000 << 2) + 0xfd000800) +#define SRAM_RANGE1_STA ((0x0001 << 2) + 0xfd000800) +#define SRAM_RANGE2_STA ((0x0002 << 2) + 0xfd000800) +#define SRAM_RANGE3_STA ((0x0003 << 2) + 0xfd000800) +#define SRAM_RANGE4_STA ((0x0004 << 2) + 0xfd000800) +#define SRAM_RANGE5_STA ((0x0005 << 2) + 0xfd000800) +#define SRAM_RANGE6_STA ((0x0006 << 2) + 0xfd000800) +#define SRAM_RANGE0_EDA ((0x0007 << 2) + 0xfd000800) +#define SRAM_RANGE1_EDA ((0x0008 << 2) + 0xfd000800) +#define SRAM_RANGE2_EDA ((0x0009 << 2) + 0xfd000800) +#define SRAM_RANGE3_EDA ((0x000a << 2) + 0xfd000800) +#define SRAM_RANGE4_EDA ((0x000b << 2) + 0xfd000800) +#define SRAM_RANGE5_EDA ((0x000c << 2) + 0xfd000800) +#define SRAM_RANGE6_EDA ((0x000d << 2) + 0xfd000800) +#define SRAM_RANGE0_CTRL0 ((0x000e << 2) + 0xfd000800) +#define SRAM_RANGE1_CTRL0 ((0x000f << 2) + 0xfd000800) +#define SRAM_RANGE2_CTRL0 ((0x0010 << 2) + 0xfd000800) +#define SRAM_RANGE3_CTRL0 ((0x0011 << 2) + 0xfd000800) +#define SRAM_RANGE4_CTRL0 ((0x0012 << 2) + 0xfd000800) +#define SRAM_RANGE5_CTRL0 ((0x0013 << 2) + 0xfd000800) +#define SRAM_RANGE6_CTRL0 ((0x0014 << 2) + 0xfd000800) +#define SRAM_RANGE7_CTRL0 ((0x0015 << 2) + 0xfd000800) +#define SRAM_RANGE0_CTRL1 ((0x0016 << 2) + 0xfd000800) +#define SRAM_RANGE1_CTRL1 ((0x0017 << 2) + 0xfd000800) +#define SRAM_RANGE2_CTRL1 ((0x0018 << 2) + 0xfd000800) +#define SRAM_RANGE3_CTRL1 ((0x0019 << 2) + 0xfd000800) +#define SRAM_RANGE4_CTRL1 ((0x001a << 2) + 0xfd000800) +#define SRAM_RANGE5_CTRL1 ((0x001b << 2) + 0xfd000800) +#define SRAM_RANGE6_CTRL1 ((0x001c << 2) + 0xfd000800) +#define SRAM_RANGE7_CTRL1 ((0x001d << 2) + 0xfd000800) +#define SRAM_SEC_CTRL0 ((0x001e << 2) + 0xfd000800) +#define SRAM_REG_LOCK ((0x001f << 2) + 0xfd000800) +//======================================================================== +// RAMB_SEC_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB1_BASE_ADDR = 0xfd000c00 +// ----------------------------------------------- +#define SRAM_RANGE0_STA_B ((0x0000 << 2) + 0xfd000c00) +#define SRAM_RANGE1_STA_B ((0x0001 << 2) + 0xfd000c00) +#define SRAM_RANGE2_STA_B ((0x0002 << 2) + 0xfd000c00) +#define SRAM_RANGE3_STA_B ((0x0003 << 2) + 0xfd000c00) +#define SRAM_RANGE4_STA_B ((0x0004 << 2) + 0xfd000c00) +#define SRAM_RANGE5_STA_B ((0x0005 << 2) + 0xfd000c00) +#define SRAM_RANGE6_STA_B ((0x0006 << 2) + 0xfd000c00) +#define SRAM_RANGE0_EDA_B ((0x0007 << 2) + 0xfd000c00) +#define SRAM_RANGE1_EDA_B ((0x0008 << 2) + 0xfd000c00) +#define SRAM_RANGE2_EDA_B ((0x0009 << 2) + 0xfd000c00) +#define SRAM_RANGE3_EDA_B ((0x000a << 2) + 0xfd000c00) +#define SRAM_RANGE4_EDA_B ((0x000b << 2) + 0xfd000c00) +#define SRAM_RANGE5_EDA_B ((0x000c << 2) + 0xfd000c00) +#define SRAM_RANGE6_EDA_B ((0x000d << 2) + 0xfd000c00) +#define SRAM_RANGE0_CTRL0_B ((0x000e << 2) + 0xfd000c00) +#define SRAM_RANGE1_CTRL0_B ((0x000f << 2) + 0xfd000c00) +#define SRAM_RANGE2_CTRL0_B ((0x0010 << 2) + 0xfd000c00) +#define SRAM_RANGE3_CTRL0_B ((0x0011 << 2) + 0xfd000c00) +#define SRAM_RANGE4_CTRL0_B ((0x0012 << 2) + 0xfd000c00) +#define SRAM_RANGE5_CTRL0_B ((0x0013 << 2) + 0xfd000c00) +#define SRAM_RANGE6_CTRL0_B ((0x0014 << 2) + 0xfd000c00) +#define SRAM_RANGE7_CTRL0_B ((0x0015 << 2) + 0xfd000c00) +#define SRAM_RANGE0_CTRL1_B ((0x0016 << 2) + 0xfd000c00) +#define SRAM_RANGE1_CTRL1_B ((0x0017 << 2) + 0xfd000c00) +#define SRAM_RANGE2_CTRL1_B ((0x0018 << 2) + 0xfd000c00) +#define SRAM_RANGE3_CTRL1_B ((0x0019 << 2) + 0xfd000c00) +#define SRAM_RANGE4_CTRL1_B ((0x001a << 2) + 0xfd000c00) +#define SRAM_RANGE5_CTRL1_B ((0x001b << 2) + 0xfd000c00) +#define SRAM_RANGE6_CTRL1_B ((0x001c << 2) + 0xfd000c00) +#define SRAM_RANGE7_CTRL1_B ((0x001d << 2) + 0xfd000c00) +#define SRAM_SEC_CTRL0_B ((0x001e << 2) + 0xfd000c00) +#define SRAM_REG_LOCK_B ((0x001f << 2) + 0xfd000c00) +// +// Reading file: REG_LIST_DSP_RTL.h +// +// synopsys translate_off +// synopsys translate_on +//======================================================================== +// DSPA - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe030000 +// ----------------------------------------------- +#define DSP_CFG0 ((0x0000 << 2) + 0xfe030000) +#define DSP_CFG1 ((0x0001 << 2) + 0xfe030000) +#define DSP_CFG2 ((0x0002 << 2) + 0xfe030000) +#define DSP_IMPWIRE ((0x0003 << 2) + 0xfe030000) +#define DSP_RESET_VEC ((0x0004 << 2) + 0xfe030000) +#define DSP_SEC_CFG0 ((0x0006 << 2) + 0xfe030000) +#define DSP_SEC_CFG1 ((0x0007 << 2) + 0xfe030000) +#define DSP_IRQ_CTRL0 ((0x0010 << 2) + 0xfe030000) +#define DSP_IRQ_CTRL1 ((0x0011 << 2) + 0xfe030000) +#define DSP_IRQ_CTRL2 ((0x0012 << 2) + 0xfe030000) +#define DSP_IRQ_CTRL3 ((0x0013 << 2) + 0xfe030000) +#define DSP_IRQ_CTRL4 ((0x0014 << 2) + 0xfe030000) +#define DSP_IRQ_CTRL5 ((0x0015 << 2) + 0xfe030000) +#define DSP_IRQ_CTRL6 ((0x0016 << 2) + 0xfe030000) +#define DSP_IRQ_CTRL7 ((0x0017 << 2) + 0xfe030000) +#define DSP_IRQ_CTRL8 ((0x0018 << 2) + 0xfe030000) +#define DSP_IRQ_STS ((0x001f << 2) + 0xfe030000) +#define DSP_REMAP0 ((0x0020 << 2) + 0xfe030000) +#define DSP_REMAP1 ((0x0021 << 2) + 0xfe030000) +#define DSP_REMAP2 ((0x0022 << 2) + 0xfe030000) +#define DSP_STS0 ((0x0040 << 2) + 0xfe030000) +#define DSP_STS1 ((0x0041 << 2) + 0xfe030000) +#define DSP_STS2 ((0x0042 << 2) + 0xfe030000) +#define DSP_STS3 ((0x0043 << 2) + 0xfe030000) +#define DSP_STS4 ((0x0044 << 2) + 0xfe030000) +#define DSP_STS5 ((0x0045 << 2) + 0xfe030000) +#define DSP_MAILBOX_SET_0 ((0x0050 << 2) + 0xfe030000) +#define DSP_MAILBOX_SET_1 ((0x0051 << 2) + 0xfe030000) +#define DSP_MAILBOX_SET_2 ((0x0052 << 2) + 0xfe030000) +#define DSP_MAILBOX_SET_3 ((0x0053 << 2) + 0xfe030000) +#define DSP_MAILBOX_SET_4 ((0x0054 << 2) + 0xfe030000) +#define DSP_MAILBOX_SET_5 ((0x0055 << 2) + 0xfe030000) +#define DSP_MAILBOX_SET_6 ((0x0056 << 2) + 0xfe030000) +#define DSP_MAILBOX_SET_7 ((0x0057 << 2) + 0xfe030000) +#define DSP_MAILBOX_SET_8 ((0x0058 << 2) + 0xfe030000) +#define DSP_MAILBOX_SET_9 ((0x0059 << 2) + 0xfe030000) +#define DSP_MAILBOX_SET_10 ((0x005a << 2) + 0xfe030000) +#define DSP_MAILBOX_SET_11 ((0x005b << 2) + 0xfe030000) +#define DSP_MAILBOX_CLR_0 ((0x0060 << 2) + 0xfe030000) +#define DSP_MAILBOX_CLR_1 ((0x0061 << 2) + 0xfe030000) +#define DSP_MAILBOX_CLR_2 ((0x0062 << 2) + 0xfe030000) +#define DSP_MAILBOX_CLR_3 ((0x0063 << 2) + 0xfe030000) +#define DSP_MAILBOX_CLR_4 ((0x0064 << 2) + 0xfe030000) +#define DSP_MAILBOX_CLR_5 ((0x0065 << 2) + 0xfe030000) +#define DSP_MAILBOX_CLR_6 ((0x0066 << 2) + 0xfe030000) +#define DSP_MAILBOX_CLR_7 ((0x0067 << 2) + 0xfe030000) +#define DSP_MAILBOX_CLR_8 ((0x0068 << 2) + 0xfe030000) +#define DSP_MAILBOX_CLR_9 ((0x0069 << 2) + 0xfe030000) +#define DSP_MAILBOX_CLR_10 ((0x006a << 2) + 0xfe030000) +#define DSP_MAILBOX_CLR_11 ((0x006b << 2) + 0xfe030000) +#define DSP_MAILBOX_STAT_0 ((0x0070 << 2) + 0xfe030000) +#define DSP_MAILBOX_STAT_1 ((0x0071 << 2) + 0xfe030000) +#define DSP_MAILBOX_STAT_2 ((0x0072 << 2) + 0xfe030000) +#define DSP_MAILBOX_STAT_3 ((0x0073 << 2) + 0xfe030000) +#define DSP_MAILBOX_STAT_4 ((0x0074 << 2) + 0xfe030000) +#define DSP_MAILBOX_STAT_5 ((0x0075 << 2) + 0xfe030000) +#define DSP_MAILBOX_STAT_6 ((0x0076 << 2) + 0xfe030000) +#define DSP_MAILBOX_STAT_7 ((0x0077 << 2) + 0xfe030000) +#define DSP_MAILBOX_STAT_8 ((0x0078 << 2) + 0xfe030000) +#define DSP_MAILBOX_STAT_9 ((0x0079 << 2) + 0xfe030000) +#define DSP_MAILBOX_STAT_10 ((0x007a << 2) + 0xfe030000) +#define DSP_MAILBOX_STAT_11 ((0x007b << 2) + 0xfe030000) +#define DSP_QIF_CTRL ((0x0080 << 2) + 0xfe030000) +#define DSP_QIF_STS ((0x0081 << 2) + 0xfe030000) +#define DSP_WRFIFO_TOCPUA ((0x0082 << 2) + 0xfe030000) +#define DSP_WRFIFO_TOCPUB ((0x0083 << 2) + 0xfe030000) +#define DSP_WRFIFO_TODSP ((0x0084 << 2) + 0xfe030000) +#define DSP_RDFIFO_FRCPUA ((0x0088 << 2) + 0xfe030000) +#define DSP_RDFIFO_FRCPUB ((0x0089 << 2) + 0xfe030000) +#define DSP_RDFIFO_FRDSP ((0x008a << 2) + 0xfe030000) +//======================================================================== +// DSPB - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe040000 +// ----------------------------------------------- +#define DSPB_CFG0 ((0x0000 << 2) + 0xfe040000) +#define DSPB_CFG1 ((0x0001 << 2) + 0xfe040000) +#define DSPB_CFG2 ((0x0002 << 2) + 0xfe040000) +#define DSPB_IMPWIRE ((0x0003 << 2) + 0xfe040000) +#define DSPB_RESET_VEC ((0x0004 << 2) + 0xfe040000) +#define DSPB_SEC_CFG0 ((0x0006 << 2) + 0xfe040000) +#define DSPB_SEC_CFG1 ((0x0007 << 2) + 0xfe040000) +#define DSPB_IRQ_CTRL0 ((0x0010 << 2) + 0xfe040000) +#define DSPB_IRQ_CTRL1 ((0x0011 << 2) + 0xfe040000) +#define DSPB_IRQ_CTRL2 ((0x0012 << 2) + 0xfe040000) +#define DSPB_IRQ_CTRL3 ((0x0013 << 2) + 0xfe040000) +#define DSPB_IRQ_CTRL4 ((0x0014 << 2) + 0xfe040000) +#define DSPB_IRQ_CTRL5 ((0x0015 << 2) + 0xfe040000) +#define DSPB_IRQ_CTRL6 ((0x0016 << 2) + 0xfe040000) +#define DSPB_IRQ_CTRL7 ((0x0017 << 2) + 0xfe040000) +#define DSPB_IRQ_CTRL8 ((0x0018 << 2) + 0xfe040000) +#define DSPB_IRQ_STS ((0x001f << 2) + 0xfe040000) +#define DSPB_REMAP0 ((0x0020 << 2) + 0xfe040000) +#define DSPB_REMAP1 ((0x0021 << 2) + 0xfe040000) +#define DSPB_REMAP2 ((0x0022 << 2) + 0xfe040000) +#define DSPB_STS0 ((0x0040 << 2) + 0xfe040000) +#define DSPB_STS1 ((0x0041 << 2) + 0xfe040000) +#define DSPB_STS2 ((0x0042 << 2) + 0xfe040000) +#define DSPB_STS3 ((0x0043 << 2) + 0xfe040000) +#define DSPB_STS4 ((0x0044 << 2) + 0xfe040000) +#define DSPB_STS5 ((0x0045 << 2) + 0xfe040000) +#define DSPB_MAILBOX_SET_0 ((0x0050 << 2) + 0xfe040000) +#define DSPB_MAILBOX_SET_1 ((0x0051 << 2) + 0xfe040000) +#define DSPB_MAILBOX_SET_2 ((0x0052 << 2) + 0xfe040000) +#define DSPB_MAILBOX_SET_3 ((0x0053 << 2) + 0xfe040000) +#define DSPB_MAILBOX_SET_4 ((0x0054 << 2) + 0xfe040000) +#define DSPB_MAILBOX_SET_5 ((0x0055 << 2) + 0xfe040000) +#define DSPB_MAILBOX_SET_6 ((0x0056 << 2) + 0xfe040000) +#define DSPB_MAILBOX_SET_7 ((0x0057 << 2) + 0xfe040000) +#define DSPB_MAILBOX_SET_8 ((0x0058 << 2) + 0xfe040000) +#define DSPB_MAILBOX_SET_9 ((0x0059 << 2) + 0xfe040000) +#define DSPB_MAILBOX_SET_10 ((0x005a << 2) + 0xfe040000) +#define DSPB_MAILBOX_SET_11 ((0x005b << 2) + 0xfe040000) +#define DSPB_MAILBOX_CLR_0 ((0x0060 << 2) + 0xfe040000) +#define DSPB_MAILBOX_CLR_1 ((0x0061 << 2) + 0xfe040000) +#define DSPB_MAILBOX_CLR_2 ((0x0062 << 2) + 0xfe040000) +#define DSPB_MAILBOX_CLR_3 ((0x0063 << 2) + 0xfe040000) +#define DSPB_MAILBOX_CLR_4 ((0x0064 << 2) + 0xfe040000) +#define DSPB_MAILBOX_CLR_5 ((0x0065 << 2) + 0xfe040000) +#define DSPB_MAILBOX_CLR_6 ((0x0066 << 2) + 0xfe040000) +#define DSPB_MAILBOX_CLR_7 ((0x0067 << 2) + 0xfe040000) +#define DSPB_MAILBOX_CLR_8 ((0x0068 << 2) + 0xfe040000) +#define DSPB_MAILBOX_CLR_9 ((0x0069 << 2) + 0xfe040000) +#define DSPB_MAILBOX_CLR_10 ((0x006a << 2) + 0xfe040000) +#define DSPB_MAILBOX_CLR_11 ((0x006b << 2) + 0xfe040000) +#define DSPB_MAILBOX_STAT_0 ((0x0070 << 2) + 0xfe040000) +#define DSPB_MAILBOX_STAT_1 ((0x0071 << 2) + 0xfe040000) +#define DSPB_MAILBOX_STAT_2 ((0x0072 << 2) + 0xfe040000) +#define DSPB_MAILBOX_STAT_3 ((0x0073 << 2) + 0xfe040000) +#define DSPB_MAILBOX_STAT_4 ((0x0074 << 2) + 0xfe040000) +#define DSPB_MAILBOX_STAT_5 ((0x0075 << 2) + 0xfe040000) +#define DSPB_MAILBOX_STAT_6 ((0x0076 << 2) + 0xfe040000) +#define DSPB_MAILBOX_STAT_7 ((0x0077 << 2) + 0xfe040000) +#define DSPB_MAILBOX_STAT_8 ((0x0078 << 2) + 0xfe040000) +#define DSPB_MAILBOX_STAT_9 ((0x0079 << 2) + 0xfe040000) +#define DSPB_MAILBOX_STAT_10 ((0x007a << 2) + 0xfe040000) +#define DSPB_MAILBOX_STAT_11 ((0x007b << 2) + 0xfe040000) +#define DSPB_QIF_CTRL ((0x0080 << 2) + 0xfe040000) +#define DSPB_QIF_STS ((0x0081 << 2) + 0xfe040000) +#define DSPB_WRFIFO_TOCPUA ((0x0082 << 2) + 0xfe040000) +#define DSPB_WRFIFO_TOCPUB ((0x0083 << 2) + 0xfe040000) +#define DSPB_WRFIFO_TODSP ((0x0084 << 2) + 0xfe040000) +#define DSPB_RDFIFO_FRCPUA ((0x0088 << 2) + 0xfe040000) +#define DSPB_RDFIFO_FRCPUB ((0x0089 << 2) + 0xfe040000) +#define DSPB_RDFIFO_FRDSP ((0x008a << 2) + 0xfe040000) +// synopsys translate_off +// synopsys translate_on +// +// Closing file: REG_LIST_DSP_RTL.h +// +// synopsys translate_off +// synopsys translate_on +// +// Closing file: ./REG_LIST_RTL.h +// +#include "soc_def.h" +#endif // REGISTER_H +
diff --git a/arch/arm/include/asm/arch-a1/regs.h b/arch/arm/include/asm/arch-a1/regs.h new file mode 100644 index 0000000..5c23c59 --- /dev/null +++ b/arch/arm/include/asm/arch-a1/regs.h
@@ -0,0 +1,5 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ +
diff --git a/arch/arm/include/asm/arch-a1/romboot.h b/arch/arm/include/asm/arch-a1/romboot.h new file mode 100644 index 0000000..2967fbb --- /dev/null +++ b/arch/arm/include/asm/arch-a1/romboot.h
@@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __BOOT_ROM_H_ +#define __BOOT_ROM_H_ +#ifndef __ASSEMBLY__ +//#include <stdint.h> +//uint8_t simple_i2c(uint8_t adr); +//void spi_pin_mux(void); +//void spi_init(void); +//uint32_t spi_read(uint32_t src, uint32_t mem, uint32_t size); +//void udelay(uint32_t usec); +//void boot_des_decrypt(uint8_t *ct, uint8_t *pt, uint32_t size); + +#endif /* ! __ASSEMBLY__ */ +#include "config.h" + +/* Magic number to "boot" up A53 */ +#define AO_SEC_SD_CFG10_CB 0x80000000 + +/*BOOT device and ddr size*/ +/*31-28: boot device id, 27-24: boot device para, 23-20: reserved*/ +/*19-8: ddr size, 7-0: board revision*/ +//#define P_AO_SEC_GP_CFG0 0xDA100240 //defined in secure_apb.h +#define AO_SEC_GP_CFG7_W0_BIT 8 +#define AO_SEC_GP_CFG7_W0 0x100 + +#define BOOT_ID_RESERVED 0 +#define BOOT_ID_EMMC 1 +#define BOOT_ID_NAND 2 +#define BOOT_ID_SPI 3 +#define BOOT_ID_SDCARD 4 +#define BOOT_ID_USB 5 + +#endif /* __BOOT_ROM_H_ */
diff --git a/arch/arm/include/asm/arch-a1/sd_emmc.h b/arch/arm/include/asm/arch-a1/sd_emmc.h new file mode 100644 index 0000000..501b590 --- /dev/null +++ b/arch/arm/include/asm/arch-a1/sd_emmc.h
@@ -0,0 +1,89 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __SD_EMMC_H__ +#define __SD_EMMC_H__ + +#include <mmc.h> + +#define SDIO_PORT_A 0 +#define SDIO_PORT_B 1 +#define SDIO_PORT_C 2 + +#define SD_EMMC_CLKSRC_24M 24000000 /* 24 MHz */ +#define SD_EMMC_CLKSRC_DIV2 1000000000 /* 1 GHz */ + + +#define MESON_SD_EMMC_CLOCK 0x00 +#define CLK_MAX_DIV 63 +#define Cfg_div 0 +#define Cfg_src 6 +#define Cfg_co_phase 8 +#define Cfg_tx_phase 10 +#define Cfg_rx_phase 12 +#define Cfg_sram_pd 14 +#define Cfg_tx_delay 16 +#define Cfg_rx_delay 22 +#define Cfg_always_on 28 +#define Cfg_irq_sdio_sleep 29 +#define Cfg_irq_sdio_sleep_ds 30 + +#define MESON_SD_EMMC_CFG 0x44 +#define CFG_BUS_WIDTH_MASK GENMASK(1, 0) +#define CFG_BUS_WIDTH_1 0 +#define CFG_BUS_WIDTH_4 1 +#define CFG_BUS_WIDTH_8 2 +#define CFG_BL_LEN_MASK GENMASK(7, 4) +#define CFG_BL_LEN_SHIFT 4 +#define CFG_BL_LEN_512 (9 << 4) +#define CFG_RESP_TIMEOUT_MASK GENMASK(11, 8) +#define CFG_RESP_TIMEOUT_256 (8 << 8) +#define CFG_RC_CC_MASK GENMASK(15, 12) +#define CFG_RC_CC_16 (4 << 12) +#define CFG_SDCLK_ALWAYS_ON BIT(18) +#define CFG_AUTO_CLK BIT(23) + +#define MESON_SD_EMMC_STATUS 0x48 +#define STATUS_MASK GENMASK(15, 0) +#define STATUS_ERR_MASK GENMASK(12, 0) +#define STATUS_RXD_ERR_MASK GENMASK(7, 0) +#define STATUS_TXD_ERR BIT(8) +#define STATUS_DESC_ERR BIT(9) +#define STATUS_RESP_ERR BIT(10) +#define STATUS_RESP_TIMEOUT BIT(11) +#define STATUS_DESC_TIMEOUT BIT(12) +#define STATUS_END_OF_CHAIN BIT(13) + +#define MESON_SD_EMMC_IRQ_EN 0x4c + +#define MESON_SD_EMMC_CMD_CFG 0x50 +#define CMD_CFG_LENGTH_MASK GENMASK(8, 0) +#define CMD_CFG_BLOCK_MODE BIT(9) +#define CMD_CFG_R1B BIT(10) +#define CMD_CFG_END_OF_CHAIN BIT(11) +#define CMD_CFG_TIMEOUT_4S (12 << 12) +#define CMD_CFG_NO_RESP BIT(16) +#define CMD_CFG_DATA_IO BIT(18) +#define CMD_CFG_DATA_WR BIT(19) +#define CMD_CFG_RESP_NOCRC BIT(20) +#define CMD_CFG_RESP_128 BIT(21) +#define CMD_CFG_CMD_INDEX_SHIFT 24 +#define CMD_CFG_OWNER BIT(31) + +#define MESON_SD_EMMC_CMD_ARG 0x54 +#define MESON_SD_EMMC_CMD_DAT 0x58 +#define MESON_SD_EMMC_CMD_RSP 0x5c +#define MESON_SD_EMMC_CMD_RSP1 0x60 +#define MESON_SD_EMMC_CMD_RSP2 0x64 +#define MESON_SD_EMMC_CMD_RSP3 0x68 + +struct meson_mmc_platdata { + struct mmc_config cfg; + struct mmc mmc; + void *regbase; + void *w_buf; +}; + +#endif
diff --git a/arch/arm/include/asm/arch-a1/secure_apb.h b/arch/arm/include/asm/arch-a1/secure_apb.h new file mode 100644 index 0000000..428610a --- /dev/null +++ b/arch/arm/include/asm/arch-a1/secure_apb.h
@@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <asm/arch/regs.h> +#include <asm/arch/register.h>
diff --git a/arch/arm/include/asm/arch-a1/soc_def.h b/arch/arm/include/asm/arch-a1/soc_def.h new file mode 100644 index 0000000..f0a0b1a --- /dev/null +++ b/arch/arm/include/asm/arch-a1/soc_def.h
@@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __A1_DEF_H__ +#define __A1_DEF_H__ + +#define SEC_AO_SEC_GP_CFG2 (SYSCTRL_SEC_STATUS_REG6) + +#endif /* __A1_DEF_H__ */
diff --git a/arch/arm/include/asm/arch-a1/timer.h b/arch/arm/include/asm/arch-a1/timer.h new file mode 100644 index 0000000..492cc8d --- /dev/null +++ b/arch/arm/include/asm/arch-a1/timer.h
@@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __TIMER_H +#define __TIMER_H + +#include <asm/arch/romboot.h> +#include <asm/arch/timer.h> +#include <asm/arch/io.h> + +/** + * Get the current timestamp from the system timer. + */ +uint32_t get_time(void); + +/** + * Busy-wait. + * + * @param us Number of microseconds to delay. + */ +void _udelay(unsigned int us); + +#endif /* __TIMER_H */
diff --git a/arch/arm/include/asm/arch-a1/timing.h b/arch/arm/include/asm/arch-a1/timing.h new file mode 100644 index 0000000..a431d1b --- /dev/null +++ b/arch/arm/include/asm/arch-a1/timing.h
@@ -0,0 +1,528 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __AML_TIMING_H_ +#define __AML_TIMING_H_ + +#include <asm/arch/ddr_define.h> +#include <asm/arch/types.h> +#include <asm/arch/mnPmuSramMsgBlock_ddr3.h> +#include <asm/arch/mnPmuSramMsgBlock_ddr4.h> +#include <asm/arch/mnPmuSramMsgBlock_ddr4_2d.h> +#include <asm/arch/mnPmuSramMsgBlock_lpddr3.h> +#include <asm/arch/mnPmuSramMsgBlock_lpddr4.h> +#include <asm/arch/mnPmuSramMsgBlock_lpddr4_2d.h> + +#define BL2_INIT_STAGE_0 0 +#define BL2_INIT_STAGE_1 1 +#define BL2_INIT_STAGE_2 2 +#define BL2_INIT_STAGE_3 3 +#define BL2_INIT_STAGE_4 4 +#define BL2_INIT_STAGE_5 5 +#define BL2_INIT_STAGE_6 6 +#define BL2_INIT_STAGE_7 7 +#define BL2_INIT_STAGE_8 8 +#define BL2_INIT_STAGE_9 9 + +#define BL2_INIT_STAGE_POWERKEY_PRE_INIT 0x81 +#define BL2_INIT_STAGE_POWERKEY_CHK_HW 0x82 +#define BL2_INIT_STAGE_POWERKEY_CFG_GROUP 0x83 +#define BL2_INIT_STAGE_POWERKEY_INIT 0xC0 + +#define POWERKEY_CFG0 0 +#define POWERKEY_CFG1 1 +#define POWERKEY_CFG2 2 +#define POWERKEY_CFG3 3 + +/* Share vddcore parameters with bl2 */ +#define BL2_INIT_STAGE_VDDCORE_TABLE 0x84 +#define BL2_INIT_STAGE_VDDCORE_CONFIG 0x85 +#define BL2_INIT_STAGE_VDDCORE_CONFIG_1 0x86 + +typedef struct bl2_reg { + unsigned int reg; + unsigned int value; + unsigned int mask; + unsigned short udelay; + unsigned char flag; + unsigned char rsv_0; +}__attribute__ ((packed)) bl2_reg_t; + +typedef struct ddr_reg { + unsigned int reg; + unsigned int value; + unsigned int mask; + unsigned short udelay; + unsigned char flag; + unsigned char rsv_0; +}__attribute__ ((packed)) ddr_reg_t; + +typedef struct training_delay_set_ps{ + unsigned char ac_trace_delay[10]; + unsigned char ac_trace_delay_rev[2]; + unsigned char read_dqs_delay[16]; + unsigned char read_dq_bit_delay[72]; + unsigned short write_dqs_delay[16]; +// */ + unsigned short write_dq_bit_delay[72]; + unsigned short read_dqs_gate_delay[16]; + unsigned char soc_bit_vref[36]; + unsigned char dram_bit_vref[32]; + ///* + unsigned char rever1;//read_dqs read_dq,write_dqs, write_dq + unsigned char dfi_mrl; + unsigned char dfi_hwtmrl; + unsigned char ARdPtrInitVal; + unsigned short csr_vrefinglobal; + unsigned short csr_dqsrcvcntrl[4]; + unsigned short csr_pptdqscntinvtrntg0[4]; + unsigned short csr_pptdqscntinvtrntg1[4]; + unsigned short csr_seq0bgpr[9]; + unsigned short csr_dllgainctl; + unsigned short csr_dlllockpara; +// unsigned short rever2; +}__attribute__ ((packed)) training_delay_set_ps_t; + +typedef struct ddr_mrs_reg { + unsigned int cfg_ddr_mr[8]; + unsigned int cfg_ddr_mr11; + unsigned int cfg_ddr_mr12; + unsigned int cfg_ddr_mr13; + unsigned int cfg_ddr_mr14; + unsigned int cfg_ddr_mr16; + unsigned int cfg_ddr_mr17; + unsigned int cfg_ddr_mr22; + unsigned int cfg_ddr_mr24; +}__attribute__ ((packed)) ddr_mrs_reg_t; + +typedef struct ddr_timing{ + unsigned int identifier; + unsigned int cfg_ddr_mrd; + unsigned int cfg_ddr_rfcab; + unsigned int cfg_ddr_rfcpb; + unsigned int cfg_ddr_rpab; + unsigned int cfg_ddr_rppb; + unsigned int cfg_ddr_rtw; + unsigned int cfg_ddr_rl; + unsigned int cfg_ddr_wl; + unsigned int cfg_ddr_ras; + unsigned int cfg_ddr_rc; + unsigned int cfg_ddr_rcd; + unsigned int cfg_ddr_rrds; + unsigned int cfg_ddr_rrdl; + unsigned int cfg_ddr_faw; + unsigned int cfg_ddr_rtp; + unsigned int cfg_ddr_wr; + unsigned int cfg_ddr_wtrs; + unsigned int cfg_ddr_wtrl; + unsigned int cfg_ddr_ccds; + unsigned int cfg_ddr_ccdl; + unsigned int cfg_ddr_exsr; + unsigned int cfg_ddr_xs; + unsigned int cfg_ddr_xp; + unsigned int cfg_ddr_xpdll; + unsigned int cfg_ddr_zqcs; + unsigned int cfg_ddr_cksre; + unsigned int cfg_ddr_cksrx; + unsigned int cfg_ddr_cke; + unsigned int cfg_ddr_mod; + unsigned int cfg_ddr_dqs; + unsigned int cfg_ddr_rstl; + unsigned int cfg_ddr_zqlat; + unsigned int cfg_ddr_mrr; + unsigned int cfg_ddr_ckesr; + unsigned int cfg_ddr_dpd; + unsigned int cfg_ddr_ckeck; + unsigned int cfg_ddr_refi; + unsigned int cfg_ddr_sr; + unsigned int cfg_ddr_ccdmw; + unsigned int cfg_ddr_escke; + unsigned int cfg_ddr_refi_ddr3; + unsigned int cfg_ddr_dfictrldelay; + unsigned int cfg_ddr_dfiphywrdata; + unsigned int cfg_ddr_dfiphywrlat; + unsigned int cfg_ddr_dfiphyrddataen; + unsigned int cfg_ddr_dfiphyrdlat; + unsigned int cfg_ddr_dfictrlupdmin; + unsigned int cfg_ddr_dfictrlupdmax; + unsigned int cfg_ddr_dfimstrresp; + unsigned int cfg_ddr_dfirefmski; + unsigned int cfg_ddr_dfictrlupdi; + unsigned int cfg_ddr_dfidramclk; + unsigned int cfg_ddr_dfilpresp; + unsigned int cfg_ddr_dfiphymstr; + unsigned int cfg_ddr_rtodt; + unsigned int cfg_ddr_wlmrd; + unsigned int cfg_ddr_wlo; + unsigned int cfg_ddr_al; + unsigned int cfg_ddr_zqcl; + unsigned int cfg_ddr_zqcsi; + unsigned int cfg_ddr_zqreset; + unsigned int cfg_ddr_tdqsck_min; + unsigned int cfg_ddr_tdqsck_max; + //training_delay_set_ps_t cfg_ddr_training_delay_ps; + ddr_mrs_reg_t cfg_ddr_mrs_reg_ps[2]; + unsigned int dfi_odt1_config_ps[2]; + //ddr_mrs_reg_t cfg_ddr_mrs_reg_ps1; + #if 0 + unsigned int cfg_ddr_mr[8]; + unsigned int cfg_ddr_mr11; + unsigned int cfg_ddr_mr12; + unsigned int cfg_ddr_mr13; + unsigned int cfg_ddr_mr14; + unsigned int cfg_ddr_mr16; + unsigned int cfg_ddr_mr17; + unsigned int cfg_ddr_mr22; + unsigned int cfg_ddr_mr24; + unsigned int cfg_ddr_reserve[5]; + #endif +}__attribute__ ((packed)) ddr_timing_t; + +typedef struct ddr_phy_common_extra_set{ + unsigned short csr_pllctrl3; + unsigned short csr_pptctlstatic[4]; + unsigned short csr_trainingincdecdtsmen[4]; + unsigned short csr_tsmbyte0[4]; + unsigned short csr_hwtcamode; + unsigned short csr_hwtlpcsena; + unsigned short csr_hwtlpcsenb; + unsigned short csr_acsmctrl13; + unsigned short csr_acsmctrl23; + unsigned char csr_soc_vref_dac1_dfe[36]; +}__attribute__ ((packed)) ddr_phy_common_extra_set_t; + +typedef struct retraining_set{ + ddr_phy_common_extra_set_t cfg_ddr_phy_common_extra_set_t; + training_delay_set_ps_t cfg_ddr_training_delay_ps; +}__attribute__ ((packed)) retraining_set_t; + +typedef struct ddr_set{ + unsigned int magic; + unsigned char fast_boot[4];// 0 fastboot enable 1 window test margin 2 auto offset after window test 3 auto window test + //unsigned int rsv_int0; + unsigned int ddr_func; + unsigned char board_id; + //board id reserve,,do not modify + unsigned char version; + // firmware reserve version,,do not modify + unsigned char DramType; + //support DramType should confirm with amlogic + //#define CONFIG_DDR_TYPE_DDR3 0 + //#define CONFIG_DDR_TYPE_DDR4 1 + //#define CONFIG_DDR_TYPE_LPDDR4 2 + //#define CONFIG_DDR_TYPE_LPDDR3 3 + //#define CONFIG_DDR_TYPE_LPDDR2 4 + unsigned char DisabledDbyte; + //use for dram bus 16bit or 32bit,if use 16bit mode ,should disable bit 2,3 + //bit 0 ---use byte 0 ,1 disable byte 0, + //bit 1 ---use byte 1 ,1 disable byte 1, + //bit 2 ---use byte 2 ,1 disable byte 2, + //bit 3 ---use byte 3 ,1 disable byte 3, + unsigned char Is2Ttiming; + //ddr3/ddr3 use 2t timing,now only support 2t timming + unsigned char HdtCtrl; + //training information control,do not modify + unsigned char dram_rank_config; + //support Dram connection type should confirm with amlogic + //#define CONFIG_DDR0_16BIT_CH0 0x1 //dram total bus width 16bit only use cs0 + //#define CONFIG_DDR0_16BIT_RANK01_CH0 0x4 //dram total bus width 16bit use cs0 cs1 + //#define CONFIG_DDR0_32BIT_RANK0_CH0 0x2 //dram total bus width 32bit use cs0 + //#define CONFIG_DDR0_32BIT_RANK01_CH01 0x3 //only for lpddr4,dram total bus width 32bit use chanel a cs0 cs1 chanel b cs0 cs1 + //#define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5 //dram total bus width 32bit only use cs0,but high address use 16bit mode + //#define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6 //dram total bus width 32bit use cs0 cs1,but cs1 use 16bit mode ,current phy not support reserve + //#define CONFIG_DDR0_32BIT_RANK01_CH0 0x7 //dram total bus width 32bit use cs0 cs1 + //#define CONFIG_DDR0_32BIT_RANK0_CH01 0x8 //only for lpddr4,dram total bus width 32bit use chanel a cs0 chanel b cs0 + + /* rsv_char0. update for diagnose type define */ + unsigned char diagnose; + + unsigned short soc_data_drv_ohm_ps1; + unsigned short dram_data_drv_ohm_ps1; + unsigned short soc_data_odt_ohm_ps1; + unsigned short dram_data_odt_ohm_ps1; + unsigned short dram_data_wr_odt_ohm_ps1; + #if 0 + /* imem/dmem define */ + unsigned int imem_load_addr; + //system reserve,do not modify + unsigned int dmem_load_addr; + //system reserve,do not modify + unsigned short imem_load_size; + #endif + //system reserve,do not modify + unsigned short dmem_load_size; + //system reserve,do not modify + unsigned int ddr_base_addr; + //system reserve,do not modify + unsigned int ddr_start_offset; + //system reserve,do not modify + + unsigned short dram_cs0_size_MB; + //config cs0 dram size ,like 1G DRAM ,setting 1024 + unsigned short dram_cs1_size_MB; + //config cs1 dram size,like 512M DRAM ,setting 512 + /* align8 */ + + unsigned short training_SequenceCtrl[2]; + //system reserve,do not modify + unsigned char phy_odt_config_rank[2]; + //unsigned char rever1; + //unsigned char rever2; + unsigned short rank1_ca_vref_permil; + //training odt config ,only use for training + // [0]Odt pattern for accesses targeting rank 0. [3:0] is used for write ODT [7:4] is used for read ODT + // [1]Odt pattern for accesses targeting rank 1. [3:0] is used for write ODT [7:4] is used for read ODT + unsigned int dfi_odt_config; + //normal go status od config,use for normal status + //bit 12. rank1 ODT default. default vulue for ODT[1] pins if theres no read/write activity. + //bit 11. rank1 ODT write sel. enable ODT[1] if there's write occur in rank1. + //bit 10. rank1 ODT write nsel. enable ODT[1] if theres's write occur in rank0. + //bit 9. rank1 odt read sel. enable ODT[1] if there's read occur in rank1. + //bit 8. rank1 odt read nsel. enable ODT[1] if there's read occure in rank0. + //bit 4. rank0 ODT default. default vulue for ODT[0] pins if theres no read/write activity. + //bit 3. rank0 ODT write sel. enable ODT[0] if there's write occur in rank0. + //bit 2. rank0 ODT write nsel. enable ODT[0] if theres's write occur in rank1. + //bit 1. rank0 odt read sel. enable ODT[0] if there's read occur in rank0. + //bit 0. rank0 odt read nsel. enable ODT[0] if there's read occure in rank1. + unsigned short DRAMFreq[4]; + //config dram frequency,use DRAMFreq[0],ohter reserve + unsigned char PllBypassEn; + //system reserve,do not modify + unsigned char ddr_rdbi_wr_enable; + //system reserve,do not modify + unsigned char ddr_rfc_type; + //config dram rfc type,according dram type,also can use same dram type max config + //#define DDR_RFC_TYPE_DDR3_512Mbx1 0 + //#define DDR_RFC_TYPE_DDR3_512Mbx2 1 + //#define DDR_RFC_TYPE_DDR3_512Mbx4 2 + //#define DDR_RFC_TYPE_DDR3_512Mbx8 3 + //#define DDR_RFC_TYPE_DDR3_512Mbx16 4 + //#define DDR_RFC_TYPE_DDR4_2Gbx1 5 + //#define DDR_RFC_TYPE_DDR4_2Gbx2 6 + //#define DDR_RFC_TYPE_DDR4_2Gbx4 7 + //#define DDR_RFC_TYPE_DDR4_2Gbx8 8 + //#define DDR_RFC_TYPE_LPDDR4_2Gbx1 9 + //#define DDR_RFC_TYPE_LPDDR4_3Gbx1 10 + //#define DDR_RFC_TYPE_LPDDR4_4Gbx1 11 + unsigned char enable_lpddr4x_mode; + //system reserve,do not modify + /* align8 */ + + unsigned int pll_ssc_mode; + // + /* pll ssc config: + * + * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode], + * ppm = strength * 500 + * mode: 0=center, 1=up, 2=down + * + * eg: + * 1. config 1000ppm center ss. then mode=0, strength=2 + * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0, + * 2. config 3000ppm down ss. then mode=2, strength=6 + * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2, + */ + unsigned short clk_drv_ohm; + //config soc clk pin signal driver stength ,select 20,30,40,60ohm + unsigned short cs_drv_ohm; + //config soc cs0 cs1 pin signal driver stength ,select 20,30,40,60ohm + unsigned short ac_drv_ohm; + //config soc normal address command pin driver stength ,select 20,30,40,60ohm + unsigned short soc_data_drv_ohm_p; + //config soc data pin pull up driver stength,select 0,28,30,32,34,37,40,43,48,53,60,68,80,96,120ohm + unsigned short soc_data_drv_ohm_n; + //config soc data pin pull down driver stength,select 0,28,30,32,34,37,40,43,48,53,60,68,80,96,120ohm + unsigned short soc_data_odt_ohm_p; + //config soc data pin odt pull up stength,select 0,28,30,32,34,37,40,43,48,53,60,68,80,96,120ohm + unsigned short soc_data_odt_ohm_n; + //config soc data pin odt pull down stength,select 0,28,30,32,34,37,40,43,48,53,60,68,80,96,120ohm + unsigned short dram_data_drv_ohm; + //config dram data pin pull up pull down driver stength,ddr3 select 34,40ohm,ddr4 select 34,48ohm,lpddr4 select 40,48,60,80,120,240ohm + unsigned short dram_data_odt_ohm; + //config dram data pin odt pull up down stength,ddr3 select 40,60,120ohm,ddr4 select 34,40,48,60,120,240ohm,lpddr4 select 40,48,60,80,120,240ohm + unsigned short dram_ac_odt_ohm; + //config dram ac pin odt pull up down stength,use for lpddr4, select 40,48,60,80,120,240ohm + unsigned short soc_clk_slew_rate; + //system reserve,do not modify + unsigned short soc_cs_slew_rate; + //system reserve,do not modify + unsigned short soc_ac_slew_rate; + //system reserve,do not modify + unsigned short soc_data_slew_rate; + //system reserve,do not modify + unsigned short vref_output_permil; //phy + //setting same with vref_dram_permil + unsigned short vref_receiver_permil; //soc + //soc init SOC receiver vref ,config like 500 means 0.5VDDQ,take care ,please follow SI + unsigned short vref_dram_permil; + //soc init DRAM receiver vref ,config like 500 means 0.5VDDQ,take care ,please follow SI + unsigned short max_core_timmming_frequency; + //use for limited ddr speed core timmming parameter,for some old dram maybe have no over speed register + /* align8 */ + + unsigned char ac_trace_delay[10]; + unsigned char lpddr4_dram_vout_voltage_1_3_2_5_setting; + //use for lpddr4 read vout voltage setting 0 --->2/5VDDQ ,1--->1/3VDDQ + unsigned char lpddr4_x8_mode; + unsigned char slt_test_function[2]; //[0] slt test function enable,bit 0 enable 4 frequency scan,bit 1 enable force delay line offset ,bit 7 enable skip training function + //[1],slt test parameter ,use for force delay line offset + //system reserve,do not modify + unsigned short tdqs2dq; + unsigned char dram_data_wr_odt_ohm; + unsigned char bitTimeControl_2d; + //system reserve,do not modify + /* align8 */ + unsigned char char_rev1; + unsigned char training_offset;//char_rev2; + unsigned int ddr_dmc_remap[5]; + unsigned int dram_rtt_nom_wr_park[2]; + //system reserve,do not modify + /* align8 */ + unsigned char ddr_lpddr34_ca_remap[4]; + ////use for lpddr3 /lpddr4 ca training data byte lane remap + unsigned char ddr_lpddr34_dq_remap[32]; + ////use for lpddr3 /lpddr4 ca pinmux remap + unsigned char ac_pinmux[DWC_AC_PINMUX_TOTAL]; + //use for lpddr3 /lpddr4 ca pinmux remap + unsigned char dfi_pinmux[DWC_DFI_PINMUX_TOTAL]; + unsigned char char_rev3; + unsigned char char_rev4; + ddr_phy_common_extra_set_t cfg_ddr_phy_common_extra_set_t; + training_delay_set_ps_t cfg_ddr_training_delay_ps[2]; + + //override read bit delay +}__attribute__ ((packed)) ddr_set_t; + +typedef struct psram_set { + unsigned int magic; + unsigned int board_id; + /* align8 */ + unsigned int version; + unsigned char psram_mr[12]; + /* align8 */ + unsigned char psram_board_mask; + unsigned char psram_amlogic_protocol_id; + unsigned char psram_test_function[2]; + unsigned char psram_vendor_id; + unsigned char psram_device_id; + unsigned char psram_soc_drv; + unsigned char psram_dram_drv; + /* align8 */ + unsigned int psram_ac_timing0; + unsigned int psram_ac_timing1; + unsigned int psram_ac_timing2; + unsigned int psram_mode_crtl; + /* align8 */ + unsigned short psram_frequency; + unsigned short psram_size; + unsigned int psram_mode_crtl_bl33; + unsigned int psram_pin_crtl; + unsigned int psram_lcd_ctrl; + /* align8 */ + unsigned char psram_pin_dq_in_delay[8]; + unsigned char psram_pin_dq_out_delay[8]; + unsigned char psram_pin_dq_out_oe_delay[8]; + /* align8 */ + unsigned char psram_pin_dm_out_delay; + unsigned char psram_pin_dm_out_oe_delay; + unsigned char psram_pin_cs_out_delay; + unsigned char psram_pin_dqsp_in_delay; + unsigned char psram_pin_dqsn_in_delay; + unsigned char psram_pin_ckp_out_delay; + unsigned char psram_pin_ckn_out_delay; + /* align8 */ + unsigned char psram_pin_rden_delay; + unsigned char psram_bdlr_delay; + unsigned char psram_reserve[6]; + + /* pls check alignment of each variable */ +}__attribute__ ((packed)) psram_set_t; + +typedef struct psram_bl2_set{ + uint16_t psram_mr[12]; + uint32_t psram_ac_timing0; + uint32_t psram_ac_timing1; + uint32_t psram_ac_timing2; + uint32_t psram_mode_crtl; + uint32_t psram_cur_clk_frequeny; + char psram_cur_amlogic_protocol_id; + char psram_use_hifi_pll; + char psram_fixed_latency_enable; + char psram_initial_latency; + char psram_cmd_cycle; + char psram_enable_data_mask; + char psram_user_cmd_code_read_register; + char psram_user_cmd_code_write_register; + char psram_user_cmd_code_read_memory; + char psram_user_cmd_code_write_memory; + uint32_t axi_req_ctrl0; + uint32_t axi_req_ctrl1; + uint32_t axi_req_ctrl2; + uint32_t user_ctrl0; + uint32_t user_ctrl1; + uint32_t user_ctrl2; + uint32_t user_ctrl3; + uint32_t psram_ctrl; +}psram_bl2_set_t; + +typedef struct psram_bl33_set{ + char psram_board_mask; + char psram_amlogic_protocol_id; + char psram_test_function[2]; + char psram_vendor_id; + char psram_device_id; + uint16_t psram_frequency; + uint16_t psram_dram_size; + char psram_soc_drv; + char psram_dram_drv; + uint32_t psram_mode_crtl_bl33; + uint32_t psram_pin_crtl; + uint32_t psram_lcd_ctrl; + char psram_pin_dq_in_delay[8]; + char psram_pin_dq_out_delay[8]; + char psram_pin_dq_out_oe_delay[8]; + char psram_pin_dm_out_delay; + char psram_pin_dm_out_oe_delay; + char psram_pin_cs_out_delay; + char psram_pin_dqsp_in_delay; + char psram_pin_dqsn_in_delay; + char psram_pin_ckp_out_delay; + char psram_pin_ckn_out_delay; + char psram_pin_rden_delay; + char psram_bdlr_delay; + char psram_reserver[7]; +}psram_psram_dev_t; + +typedef struct pll_set{ + unsigned short cpu_clk; + unsigned short pxp; + unsigned int spi_ctrl; + unsigned short vddee; + unsigned short vcck; + unsigned char szPad[4]; + + unsigned long lCustomerID; + unsigned char debug_mode; + unsigned char log_chl; + unsigned char log_ctrl; + unsigned char ddr_timming_save_mode; + unsigned int nCFGTAddr; + /* align 8Byte */ + + unsigned int sys_pll_cntl[8]; + unsigned int ddr_pll_cntl[8]; + unsigned int fix_pll_cntl[8]; +}__attribute__ ((packed)) pll_set_t; + +typedef struct dmem_cfg { + PMU_SMB_DDR3U_1D_t ddr3u; + PMU_SMB_DDR4U_1D_t ddr4u; + PMU_SMB_DDR4U_2D_t ddr4u_2d; + PMU_SMB_LPDDR3_1D_t lpddr3u; + PMU_SMB_LPDDR4_1D_t lpddr4u; + PMU_SMB_LPDDR4_2D_t lpddr4u_2d; +} dmem_cfg_t; + +#endif //__AML_TIMING_H_
diff --git a/arch/arm/include/asm/arch-a1/tsensor.h b/arch/arm/include/asm/arch-a1/tsensor.h new file mode 100644 index 0000000..cce98d6 --- /dev/null +++ b/arch/arm/include/asm/arch-a1/tsensor.h
@@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __TSENSOR_H__ +#define __TSENSOR_H__ + + +struct tsensor_cali_data { + unsigned int cmd; /* R/W */ + unsigned int offset; + unsigned int size; + unsigned long buffer_phy; + unsigned long retcnt_phy; +}; + + +#define CONFIG_HIGH_TEMP_COOL 90 + +#define T_AVG_NUM 16 /*trim temp cnt*/ +#define T_READ_NUM 2 /*trim temp cnt*/ +#define T_VER_MASK 0x80 +#define T_VALUE_MIN 0x1500 +#define T_VALUE_MAX 0x3500 +#define T_DLY_TIME 4500 /*update sensor register need 4.2ms*/ + +#define T_CONTROL_DATA 0x62b +#define T_TSCLK_DATA 0x130 + +#define ts_b 3159 +#define ts_a 9411 +#define ts_m 424 +#define ts_n 324 + +#ifdef CONFIG_AML_TSENSOR +int temp_read_entry(void); +int temp_trim_entry(int tempbase, int tempver); +int temp_cooling_entry(void); +#else +int temp_read_entry(void) +{ + return -1; +} +int temp_trim_entry(int tempbase, int tempver) +{ + return -1; +} +int temp_cooling_entry(void) +{ + return 0; +} +#endif +#endif
diff --git a/arch/arm/include/asm/arch-a1/types.h b/arch/arm/include/asm/arch-a1/types.h new file mode 100644 index 0000000..2d362b1 --- /dev/null +++ b/arch/arm/include/asm/arch-a1/types.h
@@ -0,0 +1,89 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __TYPES_H +#define __TYPES_H + +#ifndef _INT8_T_DECLARED +typedef char int8_t; +#define _INT8_T_DECLARED +#endif + +#ifndef _INT16_T_DECLARED +typedef short int16_t; +#define _INT16_T_DECLARED +#endif + +#ifndef _INT32_T_DECLARED +typedef int int32_t; +#define _INT32_T_DECLARED +#endif + +#ifndef _INT64_T_DECLARED +typedef long int64_t; +#define _INT64_T_DECLARED +#endif + +#ifndef _UINT8_T_DECLARED +typedef unsigned char uint8_t; +#define _UINT8_T_DECLARED +#endif + +#ifndef _UINT16_T_DECLARED +typedef unsigned short uint16_t; +#define _UINT16_T_DECLARED +#endif + +#ifndef _UINT32_T_DECLARED +typedef unsigned int uint32_t; +#define _UINT32_T_DECLARED +#endif + +#ifndef _UINT64_T_DECLARED +typedef unsigned long uint64_t; +#define _UINT64_T_DECLARED +#endif + +#ifndef _INT8PTR_T_DECLARED +typedef char * int8ptr_t; +#define _INT8PTR_T_DECLARED +#endif + +#ifndef _INT16PTR_T_DECLARED +typedef short * int16ptr_t; +#define _INT16PTR_T_DECLARED +#endif + +#ifndef _INT32PTR_T_DECLARED +typedef int * int32ptr_t; +#define _INT32PTR_T_DECLARED +#endif + +#ifndef _INT64PTR_T_DECLARED +typedef long * int64ptr_t; +#define _INT64PTR_T_DECLARED +#endif + +#ifndef _UINT8PTR_T_DECLARED +typedef unsigned char * uint8ptr_t; +#define _UINT8PTR_T_DECLARED +#endif + +#ifndef _UINT16PTR_T_DECLARED +typedef unsigned short * uint16ptr_t; +#define _UINT16PTR_T_DECLARED +#endif + +#ifndef _UINT32PTR_T_DECLARED +typedef unsigned int * uint32ptr_t; +#define _UINT32PTR_T_DECLARED +#endif + +#ifndef _UINT64PTR_T_DECLARED +typedef unsigned long * uint64ptr_t; +#define _UINT64PTR_T_DECLARED +#endif + +#endif \ No newline at end of file
diff --git a/arch/arm/include/asm/arch-a1/uart.h b/arch/arm/include/asm/arch-a1/uart.h new file mode 100644 index 0000000..757dc91 --- /dev/null +++ b/arch/arm/include/asm/arch-a1/uart.h
@@ -0,0 +1,152 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __MESON_FIRM_UART_H_ +#define __MESON_FIRM_UART_H_ +#include <config.h> +#include <common.h> +#include "register.h" +//#include "io.h" +#include <asm/arch/secure_apb.h> + +#ifndef CONFIG_CONS_INDEX +#error Please define CONFIG_CONS_INDEX==[0|1] +#endif + +#if CONFIG_CONS_INDEX==0 +#define UART_PORT_CONS UART_PORT_0 +#elif CONFIG_CONS_INDEX==1 +#define UART_PORT_CONS UART_PORT_1 +#elif CONFIG_CONS_INDEX==2 +#define UART_PORT_CONS UART_PORT_AO +#define USE_AO_UART 1 +#else +#error Please define CONFIG_CONS_INDEX==[0|1] +#endif +/* +#define UART_PORT_0 CBUS_REG_ADDR(UART0_WFIFO) +#define UART_PORT_1 CBUS_REG_ADDR(UART1_WFIFO) +#define UART_PORT_2 CBUS_REG_ADDR(UART2_WFIFO) +#define UART_PORT_AO P_AO_UART_WFIFO + +#define UART_WFIFO (0<<2) +#define UART_RFIFO (1<<2) +#define UART_CONTROL (2<<2) +#define UART_STATUS (3<<2) +#define UART_MISC (4<<2) +*/ + +#include "clock.h" + +#define UART_CLK_SRC CLK81 +#define UART_PORT_0 0xfe001c00 +#define UART_PORT_1 0xfe001c00 +#define UART_PORT_AO 0xfe001c00 +#define UART_WFIFO 0 +#define UART_RFIFO 1 +#define UART_CONTROL 2 +#define UART_STATUS 3 +#define UART_MISC 4 + +#if USE_AO_UART == 1 +#define P_UART(uart_base,reg) (uart_base + (reg<<2)) +#else +#define P_UART(uart_base,reg) CBUS_REG_ADDR(uart_base+reg) +#endif +#define P_UART_WFIFO(uart_base) P_UART(uart_base,UART_WFIFO) +#define P_UART_RFIFO(uart_base) P_UART(uart_base,UART_RFIFO) + +#define P_UART_CONTROL(uart_base) P_UART(uart_base,UART_CONTROL) + #define UART_CNTL_MASK_BAUD_RATE (0xfff) + #define UART_CNTL_MASK_TX_EN (1<<12) + #define UART_CNTL_MASK_RX_EN (1<<13) + #define UART_CNTL_MASK_2WIRE (1<<15) + #define UART_CNTL_MASK_STP_BITS (3<<16) + #define UART_CNTL_MASK_STP_1BIT (0<<16) + #define UART_CNTL_MASK_STP_2BIT (1<<16) + #define UART_CNTL_MASK_PRTY_EVEN (0<<18) + #define UART_CNTL_MASK_PRTY_ODD (1<<18) + #define UART_CNTL_MASK_PRTY_TYPE (1<<18) + #define UART_CNTL_MASK_PRTY_EN (1<<19) + #define UART_CNTL_MASK_CHAR_LEN (3<<20) + #define UART_CNTL_MASK_CHAR_8BIT (0<<20) + #define UART_CNTL_MASK_CHAR_7BIT (1<<20) + #define UART_CNTL_MASK_CHAR_6BIT (2<<20) + #define UART_CNTL_MASK_CHAR_5BIT (3<<20) + #define UART_CNTL_MASK_RST_TX (1<<22) + #define UART_CNTL_MASK_RST_RX (1<<23) + #define UART_CNTL_MASK_CLR_ERR (1<<24) + #define UART_CNTL_MASK_INV_RX (1<<25) + #define UART_CNTL_MASK_INV_TX (1<<26) + #define UART_CNTL_MASK_RINT_EN (1<<27) + #define UART_CNTL_MASK_TINT_EN (1<<28) + #define UART_CNTL_MASK_INV_CTS (1<<29) + #define UART_CNTL_MASK_MASK_ERR (1<<30) + #define UART_CNTL_MASK_INV_RTS (1<<31) +#define P_UART_STATUS(uart_base) P_UART(uart_base,UART_STATUS ) + #define UART_STAT_MASK_RFIFO_CNT (0x7f<<0) + #define UART_STAT_MASK_TFIFO_CNT (0x7f<<8) + #define UART_STAT_MASK_PRTY_ERR (1<<16) + #define UART_STAT_MASK_FRAM_ERR (1<<17) + #define UART_STAT_MASK_WFULL_ERR (1<<18) + #define UART_STAT_MASK_RFIFO_FULL (1<<19) + #define UART_STAT_MASK_RFIFO_EMPTY (1<<20) + #define UART_STAT_MASK_TFIFO_FULL (1<<21) + #define UART_STAT_MASK_TFIFO_EMPTY (1<<22) + #define UART_STAT_MASK_XMIT_BUSY (1<<25) + #define UART_STAT_MASK_RECV_BUSY (1<<26) +#define P_UART_MISC(uart_base) P_UART(uart_base,UART_MISC ) + + +#ifndef CONFIG_SERIAL_STP_BITS +#define CONFIG_SERIAL_STP_BITS 1 // 1 , 2 +#endif +#if CONFIG_SERIAL_STP_BITS==1 +#define UART_STP_BIT UART_CNTL_MASK_STP_1BIT +#elif CONFIG_SERIAL_STP_BITS==2 +#define UART_STP_BIT UART_CNTL_MASK_STP_2BIT +#else +#error CONFIG_SERIAL_STP_BITS wrong +#endif + + +#ifndef CONFIG_SERIAL_PRTY_TYPE +#define CONFIG_SERIAL_PRTY_TYPE 0 //0 ,2 ,3 +#endif +#if CONFIG_SERIAL_PRTY_TYPE==0 +#define UART_PRTY_BIT 0 +#elif CONFIG_SERIAL_PRTY_TYPE==2 +#define UART_PRTY_BIT (UART_CNTL_MASK_PRTY_EN|UART_CNTL_MASK_PRTY_EVEN) +#elif CONFIG_SERIAL_PRTY_TYPE==3 +#define UART_PRTY_BIT (UART_CNTL_MASK_PRTY_EN|UART_CNTL_MASK_PRTY_ODD) +#else +#error CONFIG_SERIAL_PRTY_TYPE wrong +#endif + +#ifndef CONFIG_SERIAL_CHAR_LEN +#define CONFIG_SERIAL_CHAR_LEN 8 //5,6,7,8 +#endif +#if CONFIG_SERIAL_CHAR_LEN==5 +#define UART_CHAR_LEN UART_CNTL_MASK_CHAR_5BIT +#elif CONFIG_SERIAL_CHAR_LEN==6 +#define UART_CHAR_LEN UART_CNTL_MASK_CHAR_6BIT +#elif CONFIG_SERIAL_CHAR_LEN==7 +#define UART_CHAR_LEN UART_CNTL_MASK_CHAR_7BIT +#elif CONFIG_SERIAL_CHAR_LEN==8 +#define UART_CHAR_LEN UART_CNTL_MASK_CHAR_8BIT +#else +#error CONFIG_SERIAL_CHAR_LEN wrong +#endif +#define UART_CONTROL_SET(baud,clk81) \ + (((clk81)/(baud*4) -1) \ + | UART_STP_BIT \ + | UART_PRTY_BIT \ + | UART_CHAR_LEN \ + | UART_CNTL_MASK_TX_EN \ + | UART_CNTL_MASK_RX_EN \ + | UART_CNTL_MASK_RST_TX \ + | UART_CNTL_MASK_RST_RX \ + | UART_CNTL_MASK_CLR_ERR ) +#endif
diff --git a/arch/arm/include/asm/arch-a1/usb.h b/arch/arm/include/asm/arch-a1/usb.h new file mode 100644 index 0000000..0efea92 --- /dev/null +++ b/arch/arm/include/asm/arch-a1/usb.h
@@ -0,0 +1,247 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __ARCH_ARM_MESON_USB_H_U_BOOT__ +#define __ARCH_ARM_MESON_USB_H_U_BOOT__ + +#include <common.h> +#include <asm/types.h> +#include <asm/arch/io.h> +#include <asm/arch/secure_apb.h> +#include <generic-phy.h> +#include <asm-generic/gpio.h> + +#define USB_PHY_PORT_MAX 1 +/* Phy register MACRO definitions */ + +#define LINKSYSTEM_FLADJ_MASK (0x3f << 1) +#define LINKSYSTEM_FLADJ(_x) ((_x) << 1) +#define LINKSYSTEM_XHCI_VERSION_CONTROL (0x1 << 27) + +#define PHYUTMI_OTGDISABLE (1 << 6) +#define PHYUTMI_FORCESUSPEND (1 << 1) +#define PHYUTMI_FORCESLEEP (1 << 0) + +#define PHYCLKRST_SSC_REFCLKSEL_MASK (0xff << 23) +#define PHYCLKRST_SSC_REFCLKSEL(_x) ((_x) << 23) + +#define PHYCLKRST_SSC_RANGE_MASK (0x03 << 21) +#define PHYCLKRST_SSC_RANGE(_x) ((_x) << 21) + +#define PHYCLKRST_SSC_EN (0x1 << 20) +#define PHYCLKRST_REF_SSP_EN (0x1 << 19) +#define PHYCLKRST_REF_CLKDIV2 (0x1 << 18) + +#define PHYCLKRST_MPLL_MULTIPLIER_MASK (0x7f << 11) +#define PHYCLKRST_MPLL_MULTIPLIER_100MHZ_REF (0x19 << 11) +#define PHYCLKRST_MPLL_MULTIPLIER_50M_REF (0x02 << 11) +#define PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF (0x68 << 11) +#define PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF (0x7d << 11) +#define PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF (0x02 << 11) + +#define PHYCLKRST_FSEL_MASK (0x3f << 5) +#define PHYCLKRST_FSEL(_x) ((_x) << 5) +#define PHYCLKRST_FSEL_PAD_100MHZ (0x27 << 5) +#define PHYCLKRST_FSEL_PAD_24MHZ (0x2a << 5) +#define PHYCLKRST_FSEL_PAD_20MHZ (0x31 << 5) +#define PHYCLKRST_FSEL_PAD_19_2MHZ (0x38 << 5) + +#define PHYCLKRST_RETENABLEN (0x1 << 4) + +#define PHYCLKRST_REFCLKSEL_MASK (0x03 << 2) +#define PHYCLKRST_REFCLKSEL_PAD_REFCLK (0x2 << 2) +#define PHYCLKRST_REFCLKSEL_EXT_REFCLK (0x3 << 2) + +#define PHYCLKRST_PORTRESET (0x1 << 1) +#define PHYCLKRST_COMMONONN (0x1 << 0) + +#define PHYPARAM0_REF_USE_PAD (0x1 << 31) +#define PHYPARAM0_REF_LOSLEVEL_MASK (0x1f << 26) +#define PHYPARAM0_REF_LOSLEVEL (0x9 << 26) + +#define PHYPARAM1_PCS_TXDEEMPH_MASK (0x1f << 0) +#define PHYPARAM1_PCS_TXDEEMPH (0x1c) + +#define PHYTEST_POWERDOWN_SSP (0x1 << 3) +#define PHYTEST_POWERDOWN_HSP (0x1 << 2) + +#define PHYBATCHG_UTMI_CLKSEL (0x1 << 2) + +#define FSEL_CLKSEL_24M (0x5) + +#define USB_PHY2_ENABLE 0x10000000 +#define USB_PHY2_RESET 0x20000000 + +/* XHCI PHY register structure */ +#define PHY_REGISTER_SIZE 0x20 + +struct phy_aml_usb2_priv { + unsigned int base_addr; + unsigned int reset_addr; + unsigned int dwc2_a_addr; + unsigned int u2_port_num; + unsigned int usbphy_reset_bit[8]; + unsigned int clktree_usb_bus_ctrl_addr; + unsigned int usb_phy2_pll_base_addr[4]; +}; + +struct phy_aml_usb3_priv { + unsigned int base_addr; + unsigned int usb3_port_num; + struct gpio_desc desc; +}; + +/* Register definitions */ +typedef struct u2p_aml_regs { + volatile uint32_t u2p_r0; + volatile uint32_t u2p_r1; +} u2p_aml_regs_t; + +typedef union u2p_r0 { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned host_device:1; + unsigned power_ok:1; + unsigned hast_mode:1; + unsigned POR:1; + unsigned IDPULLUP0:1; + unsigned DRVVBUS0:1; + unsigned reserved:26; + } b; +} u2p_r0_t; + +typedef union u2p_r1 { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned phy_rdy:1; + unsigned IDDIG0:1; + unsigned OTGSESSVLD0:1; + unsigned VBUSVALID0:1; + unsigned reserved:28; + } b; +} u2p_r1_t; + + +typedef struct usb_aml_regs { + volatile uint32_t usb_r0; + volatile uint32_t usb_r1; + volatile uint32_t usb_r2; + volatile uint32_t usb_r3; + volatile uint32_t usb_r4; + volatile uint32_t usb_r5; +} usb_aml_regs_t; + +typedef union usb_r0 { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned reserved:17; + unsigned p30_lane0_tx2rx_loopback:1; + unsigned p30_lane0_ext_pclk_reg:1; + unsigned p30_pcs_rx_los_mask_val:10; + unsigned u2d_ss_scaledown_mode:2; + unsigned u2d_act:1; + } b; +} usb_r0_t; + +typedef union usb_r1 { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned u3h_bigendian_gs:1; + unsigned u3h_pme_en:1; + unsigned u3h_hub_port_overcurrent:3; + unsigned reserved_1:2; + unsigned u3h_hub_port_perm_attach:3; + unsigned reserved_2:2; + unsigned u3h_host_u2_port_disable:2; + unsigned reserved_3:2; + unsigned u3h_host_u3_port_disable:1; + unsigned u3h_host_port_power_control_present:1; + unsigned u3h_host_msi_enable:1; + unsigned u3h_fladj_30mhz_reg:6; + unsigned p30_pcs_tx_swing_full:7; + } b; +} usb_r1_t; + +typedef union usb_r2 { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned reserved:20; + unsigned p30_pcs_tx_deemph_3p5db:6; + unsigned p30_pcs_tx_deemph_6db:6; + } b; +} usb_r2_t; + +typedef union usb_r3 { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned p30_ssc_en:1; + unsigned p30_ssc_range:3; + unsigned p30_ssc_ref_clk_sel:9; + unsigned p30_ref_ssp_en:1; + unsigned reserved:18; + } b; +} usb_r3_t; + +typedef union usb_r4 { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned p21_PORTRESET0:1; + unsigned p21_SLEEPM0:1; + unsigned mem_pd:2; + unsigned p21_only:1; + unsigned reserved:27; + } b; +} usb_r4_t; + +typedef union usb_r5 { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned iddig_sync:1; + unsigned iddig_reg:1; + unsigned iddig_cfg:2; + unsigned iddig_en0:1; + unsigned iddig_en1:1; + unsigned iddig_curr:1; + unsigned usb_iddig_irq:1; + unsigned iddig_th:8; + unsigned iddig_cnt:8; + unsigned reserved:8; + } b; +} usb_r5_t; + +/* usb id mode, only after M2 + mode = 0 : HARDWARE + mode = 1 : SW_HOST + mode = 2 : SW_DEVICE + */ +#define USB_ID_MODE_HARDWARE (1) +#define USB_ID_MODE_SW_HOST (2) +#define USB_ID_MODE_SW_DEVICE (3) +int usb2_phy_tuning(uint32_t phy2_pll_base, int port); +void set_usb_pll(uint32_t phy2_pll_base); +int usb_save_phy_dev (unsigned int number, struct phy *phy); +int usb2_phy_init (struct phy *phy); +unsigned int usb_get_dwc_a_base_addr(void); +unsigned int usb_get_device_mode_phy_base(void); +void usb_phy_tuning_reset(void); +void usb_device_mode_init(void); + +#endif
diff --git a/arch/arm/include/asm/arch-c1/acs.h b/arch/arm/include/asm/arch-c1/acs.h new file mode 100644 index 0000000..65de6df --- /dev/null +++ b/arch/arm/include/asm/arch-c1/acs.h
@@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __ACS_H +#define __ACS_H + +#ifndef __ASSEMBLY__ +typedef struct acs_setting{ + char acs_magic[5]; //acs setting magic word, make sure this piece of data was right. + unsigned char chip_type; //chip type + unsigned short version; //version of acs_setting struct, for PC tool use. + unsigned long acs_set_length; //length of current struct. + + //ddr setting part, 16 bytes + char ddr_magic[5]; //magic word to indicate that following 12 bytes was ddr setting. + unsigned char ddr_set_version; //struct version, for PC tool use. + unsigned short ddr_set_length; //length of ddr struct. + unsigned long ddr_set_addr; //address of ddr setting. + + char ddr_reg_magic[5]; + unsigned char ddr_reg_version; + unsigned short ddr_reg_length; + unsigned long ddr_reg_addr; + + char pll_magic[5]; + unsigned char pll_set_version; + unsigned short pll_set_length; + unsigned long pll_set_addr; + + char sto_magic[5]; + unsigned char sto_set_version; + unsigned short sto_set_length; + unsigned long sto_set_addr; + + char bl2_regs_magic[5]; + unsigned char bl2_regs_version; + unsigned short bl2_regs_length; + unsigned long bl2_regs_addr; + + char rsv_magic[5]; + unsigned char rsv_set_version; + unsigned short rsv_set_length; + unsigned long rsv_set_addr; + char board_id[12]; + unsigned short ddr_struct_size[12]; + unsigned long ddr_struct_org_size; + char revision[40]; +}__attribute__ ((packed)) acs_set_t; + +#endif +#endif
diff --git a/arch/arm/include/asm/arch-c1/bl31_apis.h b/arch/arm/include/asm/arch-c1/bl31_apis.h new file mode 100644 index 0000000..a0c78a5 --- /dev/null +++ b/arch/arm/include/asm/arch-c1/bl31_apis.h
@@ -0,0 +1,164 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +/* + * Trustzone API + * + * Copyright (C) 2012 Amlogic, Inc. + * + * Author: Platform-SH@amlogic.com + * + */ + +#ifndef __GXBB_BL31_APIS_H +#define __GXBB_BL31_APIS_H + +#include <asm/arch/io.h> + +/*#define SRAM_READ 0x82000010 +#define CORE_RD_REV1 0x82000011 +#define SRAM_ACS_READ 0x82000012 +#define SRAM_ACS_INDIRECT_READ 0x82000013*/ + +#define GET_SHARE_MEM_INPUT_BASE 0x82000020 +#define GET_SHARE_MEM_OUTPUT_BASE 0x82000021 +#define GET_REBOOT_REASON 0x82000022 +#define GET_SHARE_STORAGE_IN_BASE 0x82000023 +#define GET_SHARE_STORAGE_OUT_BASE 0x82000024 +#define GET_SHARE_STORAGE_BLOCK_BASE 0x82000025 +#define GET_SHARE_STORAGE_MESSAGE_BASE 0x82000026 +#define GET_SHARE_STORAGE_BLOCK_SIZE 0x82000027 +#define SET_STORAGE_INFO 0x82000028 +#define SET_REBOOT_REASON 0x82000049 + +/* Set Reboot Reason then Reboot*/ +#define PSCI_SYS_REBOOT 0x84000009 + +/* SECUREOS DEFINITION*/ +/* SMC Identifiers for non-secure world functions */ +#define CALL_TRUSTZONE_HAL_API 0x5 + +/* EFUSE */ +#define EFUSE_READ 0x82000030 +#define EFUSE_WRITE 0x82000031 +#define EFUSE_WRITE_PATTERN 0x82000032 +#define EFUSE_USER_MAX 0x82000033 + +#define DEBUG_EFUSE_WRITE_PATTERN 0x820000F0 +#define DEBUG_EFUSE_READ_PATTERN 0x820000F1 + +/* JTAG*/ +#define JTAG_ON 0x82000040 +#define JTAG_OFF 0x82000041 + +#define SET_USB_BOOT_FUNC 0x82000043 + /* USB BOOT FUNC sub command list*/ + #define CLEAR_USB_BOOT 1 + #define FORCE_USB_BOOT 2 + #define RUN_COMD_USB_BOOT 3 + #define PANIC_DUMP_USB_BOOT 4 + +#define GET_CHIP_ID 0x82000044 + +/* tsensor calibration data */ +#define TSENSOR_CALI_SET 0x8200004C + +/*oscring efuse value get */ +#define OSCRING_EFUSE_GET 0x8200004D +/* Security Key*/ +#define SECURITY_KEY_QUERY 0x82000060 +#define SECURITY_KEY_READ 0x82000061 +#define SECURITY_KEY_WRITE 0x82000062 +#define SECURITY_KEY_TELL 0x82000063 +#define SECURITY_KEY_VERIFY 0x82000064 +#define SECURITY_KEY_STATUS 0x82000065 +#define SECURITY_KEY_NOTIFY 0x82000066 +#define SECURITY_KEY_LIST 0x82000067 +#define SECURITY_KEY_REMOVE 0x82000068 +#define SECURITY_KEY_NOTIFY_EX 0x82000069 +#define SECURITY_KEY_SET_ENCTYPE 0x8200006A +#define SECURITY_KEY_GET_ENCTYPE 0x8200006B +#define SECURITY_KEY_VERSION 0x8200006C + +/*viu probe en*/ +#define VIU_PREOBE_EN 0x82000080 +/*set boot first timeout*/ +#define SET_BOOT_FIRST 0x82000087 + +/* KEYMASTER */ +#define SET_BOOT_PARAMS 0x82000072 +#define SHA256_DIGEST_SIZE 32 +typedef struct { + uint32_t device_locked; + uint32_t verified_boot_state; + uint8_t verified_boot_key[SHA256_DIGEST_SIZE]; + uint8_t verified_boot_hash[SHA256_DIGEST_SIZE]; +} keymaster_boot_params; + +/* Secure HAL APIs */ +#define TRUSTZONE_HAL_API_SRAM 0x400 + +/*start hifi4 */ +#define START_HIFI4 0x82000090 +#define DSP_SEC_POWERSET 0x82000092 + + +#define SRAM_HAL_API_CHECK_EFUSE 0x403 +struct sram_hal_api_arg { + unsigned int cmd; + unsigned int req_len; + unsigned int res_len; + unsigned long req_phy_addr; + unsigned long res_phy_addr; + unsigned long ret_phy_addr; +}; + +#define JTAG_STATE_ON 0 +#define JTAG_STATE_OFF 1 +#define JTAG_M3_AO 0 +#define JTAG_M3_EE 1 +#define JTAG_A53_AO 2 +#define JTAG_A53_EE 3 +#define CLUSTER_BIT 2 + + +///////////////////////////////////////////////////////////////////////////////// +#define AML_DATA_PROCESS (0x820000FF) + #define AML_D_P_W_EFUSE_SECURE_BOOT (0x10) + #define AML_D_P_W_EFUSE_PASSWORD (0x11) + #define AML_D_P_W_EFUSE_CUSTOMER_ID (0x12) + #define AML_D_P_W_EFUSE_AMLOGIC (0x20) + #define AML_D_P_IMG_DECRYPT (0x40) + #define AML_D_P_UPGRADE_CHECK (0x80) + +#define GXB_EFUSE_PATTERN_SIZE (0x500) +#define GXB_IMG_SIZE (24<<20) +#define GXB_IMG_LOAD_ADDR (0x1080000) + #define GXB_IMG_DEC_KNL (1<<0) + #define GXB_IMG_DEC_RMD (1<<1) + #define GXB_IMG_DEC_DTB (1<<2) + #define GXB_IMG_DEC_ALL (GXB_IMG_DEC_KNL|GXB_IMG_DEC_RMD|GXB_IMG_DEC_DTB) + +#define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t" + +void aml_set_jtag_state(unsigned state, unsigned select); +unsigned aml_get_reboot_reason(void); +unsigned aml_reboot(uint64_t function_id, uint64_t arg0, uint64_t arg1, uint64_t arg2); +void aml_set_reboot_reason(uint64_t function_id, uint64_t arg0, uint64_t arg1, uint64_t arg2); +unsigned long aml_sec_boot_check(unsigned long ,unsigned long ,unsigned long,unsigned long ); +long get_sharemem_info(unsigned long); +void set_usb_boot_function(unsigned long command); +void aml_system_off(void); + +void bl31_get_chipid(unsigned int *, unsigned int *, + unsigned int *, unsigned int *); +void set_viu_probe_enable(void); +void wdt_send_cmd_to_bl31(uint64_t cmd, uint64_t value); +void power_set_dsp(unsigned int id, unsigned int powerflag); +void init_dsp(unsigned int id,unsigned int addr,unsigned int cfg0); +void set_boot_first_timeout(uint64_t arg0); +int bl31_get_cornerinfo(uint8_t *outbuf, int size); +int32_t set_boot_params(const keymaster_boot_params*); +#endif
diff --git a/arch/arm/include/asm/arch-c1/board_id.h b/arch/arm/include/asm/arch-c1/board_id.h new file mode 100644 index 0000000..6488771 --- /dev/null +++ b/arch/arm/include/asm/arch-c1/board_id.h
@@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +unsigned int get_board_id(void); \ No newline at end of file
diff --git a/arch/arm/include/asm/arch-c1/clk_measure_tab.h b/arch/arm/include/asm/arch-c1/clk_measure_tab.h new file mode 100644 index 0000000..7e9162c --- /dev/null +++ b/arch/arm/include/asm/arch-c1/clk_measure_tab.h
@@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef _ARCH_MESON_A1_MEASURE_H_ +#define _ARCH_MESON_A1_MEASURE_H_ + +static const char* clk_msr_table[] = { + [0] = "tdmout_b_sclk", + [1] = "tdmout_a_sclk", + [2] = "tdmin_lb_sclk", + [3] = "tdmin_b_sclk", + [4] = "tdmin_a_sclk", + [5] = "vad_clk", + [6] = "resampleA_clk", + [7] = "pdm_sysclk", + [8] = "pdm_dclk", + [9] = "locker_out_clk", + [10] = "locker_in_clk", + [12] = "tdmin_vad_clk", + [13] = "au_adc_clk", + [14] = "au_dac_clk", + [16] = "spicc_a_clk", + [17] = "spifc_clk", + [18] = "sd_emmc_a_clk", + [19] = "spicc_b_clk", + [24] = "ts_clk", + [25] = "pwm_f_clk", + [26] = "pwm_e_clk", + [27] = "pwm_d_clk", + [28] = "pwm_c_clk", + [29] = "pwm_b_clk", + [30] = "pwm_a_clk", + [31] = "saradc_clk", + [32] = "usb_bus", + [33] = "dsp_b_clk", + [34] = "dsp_a_clk", + [35] = "axi_clk", + [36] = "sys_clk", + [39] = "gpio_msr", + [40] = "rng_ring_osc0", + [41] = "rng_ring_osc1", + [42] = "rng_ring_osc2", + [43] = "rng_ring_osc3", + [44] = "dds_out", + [45] = "cpu_clk_div16", + [46] = "osc_ring_cpu0", + [47] = "osc_ring_cpu1", + [48] = "osc_ring_cpu2", + [49] = "osc_ring_cpu3", + [50] = "osc_ring_ddr", + [51] = "osc_ring_dmc", + [52] = "osc_ring_dspa", + [53] = "osc_ring_dspb", + [54] = "osc_ring_rama", + [55] = "osc_ring_ramb", + [56] = "osc_ring_ramc", + [57] = "osc_ring_dos0", + [58] = "osc_ring_dos1", + [59] = "osc_ring_dos2", + [60] = "osc_ring_dos3", + [62] = "eth_mppll_50m", + [63] = "co_clkin_to_mac", + [64] = "eth_phy_plltxclk", + [65] = "eth_phy_rxclk", + [66] = "co_tx_clk", + [67] = "co_rx_clk", + [68] = "cts_mipi_isp_clk", + [69] = "cts_mipi_csi_phy_clk", + [70] = "cts_nna_axi_clk", + [71] = "cts_nna_core_clk", + [72] = "cts_eth_clk_rmii", + [73] = "cts_eth_clk125Mhz", + [74] = "cts_jpeg_enc_clk ", + [75] = "cts_rtc_clk", + [76] = "cts_ge2d_clk", + [77] = "cts_gdc_axi_clk", + [78] = "cts_gdc_core_clk", + [79] = "cts_pwm_j_clk", + [80] = "cts_pwm_i_clk", + [81] = "cts_pwm_h_clk", + [82] = "cts_pwm_g_clk", + [83] = "cts_wave_cclk", + [84] = "cts_wave_bclk", + [85] = "cts_wave_aclk", + [86] = "cts_sd_emmc_C_clk", + [87] = "cts_sd_emmc_B_clk", + [88] = "ephy_test_clk", + [89] = "mipi_csi_phy0_clk", + [90] = "mipi_csi_phy1_clk", + [91] = "mod_eth_phy_ref_clk", + [92] = "ddr_dpll_pt_clk", +}; + +#endif
diff --git a/arch/arm/include/asm/arch-c1/clock.h b/arch/arm/include/asm/arch-c1/clock.h new file mode 100644 index 0000000..9955501 --- /dev/null +++ b/arch/arm/include/asm/arch-c1/clock.h
@@ -0,0 +1,121 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __C1_H +#define __C1_H + +/* + * Clock controller register address + * APB_BASE: APB0_BASE_ADDR = 0xfe000800 + */ +#define C1_SYS_OSCIN_CTRL 0x0 +#define C1_RTC_BY_OSCIN_CTRL0 0x4 +#define C1_RTC_BY_OSCIN_CTRL1 0x8 +#define C1_RTC_CTRL 0xc +#define C1_SYS_CLK_CTRL0 0x10 +#define C1_AXI_CLK_CTRL0 0x14 +#define C1_SYS_CLK_EN0 0x18 +#define C1_SYS_CLK_EN1 0x1c +#define C1_SYS_CLK_EN2 0x20 +#define C1_AXI_CLK_EN 0x24 +#define C1_DSPA_CLK_EN 0x28 +#define C1_DSPB_CLK_EN 0x2c +#define C1_DSPA_CLK_CTRL0 0x30 +#define C1_DSPB_CLK_CTRL0 0x34 +#define C1_CLK12_24_CTRL 0x38 +#define C1_GEN_CLK_CTRL 0x3c +#define C1_TIMESTAMP_CTRL0 0x40 +#define C1_TIMESTAMP_CTRL1 0x44 +#define C1_TIMESTAMP_CTRL2 0x48 +#define C1_TIMESTAMP_VAL0 0x4c +#define C1_TIMESTAMP_VAL1 0x50 +#define C1_TIMEBASE_CTRL0 0x54 +#define C1_TIMEBASE_CTRL1 0x58 +#define C1_SAR_ADC_CLK_CTRL 0xc0 +#define C1_PWM_CLK_AB_CTRL 0xc4 +#define C1_PWM_CLK_CD_CTRL 0xc8 +#define C1_PWM_CLK_EF_CTRL 0xcc +#define C1_SPICC_CLK_CTRL 0xd0 +#define C1_TS_CLK_CTRL 0xd4 +#define C1_SPIFC_CLK_CTRL 0xd8 +#define C1_USB_BUSCLK_CTRL 0xdc +#define C1_SD_EMMC_CLK_CTRL 0xe0 +#define C1_CECA_CLK_CTRL0 0xe4 +#define C1_CECA_CLK_CTRL1 0xe8 +#define C1_CECB_CLK_CTRL0 0xec +#define C1_CECB_CLK_CTRL1 0xf0 +#define C1_PSRAM_CLK_CTRL 0xf4 +#define C1_DMC_CLK_CTRL 0xf8 +#define C1_FCLK_DIV1_SEL 0xfc +#define C1_TST_CTRL 0x100 +#define C1_WAVE_CLK_CTRL0 0x104 +#define C1_WAVE_CLK_CTRL1 0x108 +#define C1_JPEG_CLK_CTRL 0x10C +#define C1_MIPI_ISP_CLK_CTRL 0x110 +#define C1_NNA_CLK_CTRL 0x114 +#define C1_GDC_CLK_CTRL 0x118 +#define C1_GE2D_CLK_CTRL 0x11C +#define C1_SD_EMMC_CLK_CTRL1 0x120 +#define C1_ETH_CLK_CTRL 0x124 +#define C1_PWM_CLK_GH_CTRL 0x128 +#define C1_PWM_CLK_IJ_CTRL 0x12C +#define C1_MBIST_ATSPEED_CTRL 0x130 + +/* + * For PLl register offset + * APB_BASE: APB0_BASE_ADDR = 0xfe007c00 + */ +#define C1_ANACTRL_FIXPLL_GATE_DIS 0x40 + 0x7400 +#define C1_ANACTRL_FIXPLL_CTRL0 0x80 + 0x7400 +#define C1_ANACTRL_FIXPLL_CTRL1 0x84 + 0x7400 +#define C1_ANACTRL_FIXPLL_CTRL2 0x88 + 0x7400 +#define C1_ANACTRL_FIXPLL_CTRL3 0x8c + 0x7400 +#define C1_ANACTRL_FIXPLL_CTRL4 0x90 + 0x7400 +#define C1_ANACTRL_FIXPLL_CTRL5 0x94 + 0x7400 +#define C1_ANACTRL_FIXPLL_CTRL6 0x98 + 0x7400 +#define C1_ANACTRL_FIXPLL_STS 0x9c + 0x7400 +#define C1_ANACTRL_GPPLL_CTRL0 0xc0 + 0x7400 +#define C1_ANACTRL_GPPLL_CTRL1 0xc4 + 0x7400 +#define C1_ANACTRL_GPPLL_CTRL2 0xc8 + 0x7400 +#define C1_ANACTRL_GPPLL_CTRL3 0xcc + 0x7400 +#define C1_ANACTRL_GPPLL_CTRL4 0xd0 + 0x7400 +#define C1_ANACTRL_GPPLL_CTRL5 0xd4 + 0x7400 +#define C1_ANACTRL_GPPLL_STS 0xd8 + 0x7400 +#define C1_ANACTRL_SYSPLL_CTRL0 0x100 + 0x7400 +#define C1_ANACTRL_SYSPLL_CTRL1 0x104 + 0x7400 +#define C1_ANACTRL_SYSPLL_CTRL2 0x108 + 0x7400 +#define C1_ANACTRL_SYSPLL_CTRL3 0x10c + 0x7400 +#define C1_ANACTRL_SYSPLL_CTRL4 0x110 + 0x7400 +#define C1_ANACTRL_SYSPLL_STS 0x114 + 0x7400 +#define C1_ANACTRL_HIFIPLL_CTRL0 0x140 + 0x7400 +#define C1_ANACTRL_HIFIPLL_CTRL1 0x144 + 0x7400 +#define C1_ANACTRL_HIFIPLL_CTRL2 0x148 + 0x7400 +#define C1_ANACTRL_HIFIPLL_CTRL3 0x14c + 0x7400 +#define C1_ANACTRL_HIFIPLL_CTRL4 0x150 + 0x7400 +#define C1_ANACTRL_HIFIPLL_STS 0x154 + 0x7400 +#define C1_ANACTRL_AUDDDS_CTRL0 0x180 + 0x7400 +#define C1_ANACTRL_AUDDDS_CTRL1 0x184 + 0x7400 +#define C1_ANACTRL_AUDDDS_CTRL2 0x188 + 0x7400 +#define C1_ANACTRL_AUDDDS_CTRL3 0x18c + 0x7400 +#define C1_ANACTRL_AUDDDS_CTRL4 0x190 + 0x7400 +#define C1_ANACTRL_AUDDDS_STS 0x194 + 0x7400 +#define C1_ANACTRL_MISCTOP_CTRL0 0x1c0 + 0x7400 +#define C1_ANACTRL_POR_CNTL 0x208 + 0x7400 + +/* + * CPU clok register offset + * APB_BASE: APB1_BASE_ADDR = 0xfe007400 + */ +/* + *#define C1_CPUCTRL_CLK_CTRL0 0x0 + 0x7400 + *#define C1_CPUCTRL_CLK_CTRL1 0x4 + 0x7400 + *#define C1_CPUCTRL_CLK_CTRL5 0x14 + 0x7400 + *#define C1_CPUCTRL_CLK_CTRL6 0x18 + 0x7400 + */ + +#include <dt-bindings/clock/c1-clkc.h> +#define NR_CLKS (CLKID_END_BASE) + +#endif /* __C1_H */
diff --git a/arch/arm/include/asm/arch-c1/core.h b/arch/arm/include/asm/arch-c1/core.h new file mode 100644 index 0000000..97fd220 --- /dev/null +++ b/arch/arm/include/asm/arch-c1/core.h
@@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __CORE_H__ +#define __CORE_H__ + +int get_core_mpidr(unsigned int cpuid); +int get_core_idx(unsigned int mpidr); +int get_core_max(void); + +#endif
diff --git a/arch/arm/include/asm/arch-c1/cpu.h b/arch/arm/include/asm/arch-c1/cpu.h new file mode 100644 index 0000000..478eb38 --- /dev/null +++ b/arch/arm/include/asm/arch-c1/cpu.h
@@ -0,0 +1,80 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef _CPU_H +#define _CPU_H +/* #include <config.h> */ +/* #include <asm/plat-cpu.h> */ +/* #include <asm/arch/ddr.h> */ + +#if 0 +#define CONFIG_AML_MESON 1 +#define CONFIG_AML_MESON_GX 1 +#define CONFIG_AML_MESON_G12A 1 +#endif + +/*enable viu probe*/ +#if 0 +#define CONFIG_CMD_VIU_PROBE 1 +#endif + +/* for uboot envrionment use */ +#define CONFIG_DDR_SIZE 256 + +/* dram */ +#define PHYS_SDRAM_1_BASE 0x00000000UL +#define PHYS_SDRAM_1_SIZE 0x10000000UL +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1_BASE + +#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1_BASE + CONFIG_SYS_TEXT_BASE) + +/* console/print buffer */ +#define CONFIG_SYS_CBSIZE 512 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY (0x1800000) /* 24MHz */ + +/* use "hush" command parser */ +#if 0 +#define CONFIG_SYS_HUSH_PARSER +#endif + +#if 0 +#define CONFIG_DTB_MEM_ADDR 0x1000000 +#endif + +#if 0 +#define CONFIG_AML_CUSTOMER_ID (0) +#endif + +#define AML_CUSTOMER_ID (0) + +//#define CONFIG_SILENT_CONSOLE +//#define CONFIG_SILENT_CONSOLE_UPDATE_ON_RELOC +//#define CONFIG_SILENT_U_BOOT_ONLY + +/* 2018.03.19 new compress solution, only support BL33 LZ4 compress */ +#define CONFIG_AML_BL33_COMPRESS_ENABLE 1 + +/* 2018.03.19 G12A only support v3 format for normal & secure boot */ +#define CONFIG_AML_SECURE_BOOT_V3 1 + +#define NR_CPUS 4 + +#define CPU_ID_REG SYSCTRL_SEC_STATUS_REG0 +#define PACKAGE_ID_MASK 0xFF + +/*C1 SoC secure boot solution default not support AES algorithm*/ +//#define CONFIG_AML_CRYPTO_AES 1 + + +/*Flag for enable AES key generate to EFUSE pattern, with this flag only +AES key will be generated to EFUSE pattern, it can be used for use case +like the AES key not ready when secure boot enabled for the first time. +*/ +//#define CONFIG_AML_EFUSE_GEN_AES_ONLY 1 + +#endif /* _CPU_H */
diff --git a/arch/arm/include/asm/arch-c1/cpu_config.h b/arch/arm/include/asm/arch-c1/cpu_config.h new file mode 100644 index 0000000..45e7e80 --- /dev/null +++ b/arch/arm/include/asm/arch-c1/cpu_config.h
@@ -0,0 +1,85 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef _BOOT_ROM_CONFIG_H_ +#define _BOOT_ROM_CONFIG_H_ + +/*********************************************************** + * The following constants are GXBB definition + **********************************************************/ +#define ROMBOOT_START 0xD9040000 +#define ROM_SIZE (64*1024) +#define ROMBOOT_END (ROMBOOT_START+ROM_SIZE) + +/*********************************************************** + * AHB-SRAM Total Size 80KB, layout shown as below + * + * ROMCODE use the top 32KB + * + * [ 128] 0xD901_3F80 - 0xD901_3FFF Reserved + * [ 128] 0xD901_3F00 - 0xD901_3F7F CPUs Boot Entry + * [ 256] 0xD901_3E00 - 0xD901_3EFF Debug Info + * [ 512] 0xD901_3C00 - 0xD901_3DFF eFuse mirror + * [ 1K] 0xD901_3800 - 0xD901_3BFF Secure Mailbox (3) + * [ 1K] 0xD901_3400 - 0xD901_37FF High Mailbox (2) * + * [ 1K] 0xD901_3000 - 0xD901_33FF High Mailbox (1) * + * [ 26K] 0xD900_C800 - 0xD901_2FFF BL1 Stack, BSS + * [ 1K] 0xD900_C400 - 0xD900_C7FF NAND, USB Buffer + * [ 1K] 0xD900_C000 - 0xD900_C3FF Reserved + * + **********************************************************/ +#define RAM_START 0xD9000000 +#define RAM_SIZE (80 * 1024) +#define BL1_RAM_START (RAM_START + 0xC000) +#define BL1_RAM_SIZE (32 * 1024) +#define BL1_RAM_END (BL1_RAM_START + BL1_RAM_SIZE) +#define BSS_START (BL1_RAM_START + (2 * 1024)) +#define BSS_SIZE (18 * 1024) +#define _STACK_END (BSS_START + BSS_SIZE + 8*1024) +#define BL1_EFUSE_MIRROR (BL1_RAM_END - 1024) +#define P_SHARED_EFUSE_MIRROR (volatile uint32_t *)(BL1_EFUSE_MIRROR) +#define BL1_DEBUG_BUFFER (BL1_RAM_END - 512) +#define CPU_BOOT_ENTRY (BL1_DEBUG_BUFFER + 256) +#define P_SHARED_DEBUG_BUFF (volatile uint32_t *)(BL1_DEBUG_BUFFER) +#define BL1_SEC_MBX (BL1_RAM_END - 2*1024) +#define BL1_NAND_BUFF (BL1_RAM_START + 1024) +#define BL1_USB_BUFF (BL1_NAND_BUFF) + +#define MEMORY_LOC RAM_START + +#define SRAM_DEBUG_BUFF_SIZE 256 + +/* BL2 SPL size */ +#define BL2_SIZE (64 * 1024) + +//for signature test +//#define CONFIG_AML_SIG_TEST_BUILD + +/* Software SHA2 */ +#define CONFIG_SHA2_SW + +/* Hardware SHA2 */ +#define CONFIG_SHA2_HW +#define SHA2_HW_UPDATE_API + +/* Keep timer config in conf.h */ +#define CONFIG_TIMER + +/* Bootrom debug info */ +#define CONFIG_DEBUG_INFO + +/* Mincrypt RSA library */ +//#define CONFIG_MINCRYPT + +/* PolarSSL RSA library */ +#define CONFIG_POLARSSL_RSA + +#ifdef CONFIG_POLARSSL_RSA +#ifndef CONFIG_MALLOC +#define CONFIG_MALLOC +#endif /* ! CONFIG_MALLOC */ +#endif /* CONFIG_POLARSSL_RSA */ + +#endif /* _BOOT_ROM_CONFIG_H_ */
diff --git a/arch/arm/include/asm/arch-c1/cpu_reset.h b/arch/arm/include/asm/arch-c1/cpu_reset.h new file mode 100644 index 0000000..46f9abf --- /dev/null +++ b/arch/arm/include/asm/arch-c1/cpu_reset.h
@@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef _BOOT_ROM_WATCHDOG_H +#define _BOOT_ROM_WATCHDOG_H +#include <asm/arch/secure_apb.h> + +void reset_system(void); + +/* uboot reset interface */ +void reset_cpu(unsigned long flag); + +#endif /* _BOOT_ROM_WATCHDOG_H */
diff --git a/arch/arm/include/asm/arch-c1/cpu_sdio.h b/arch/arm/include/asm/arch-c1/cpu_sdio.h new file mode 100644 index 0000000..46f366a --- /dev/null +++ b/arch/arm/include/asm/arch-c1/cpu_sdio.h
@@ -0,0 +1,239 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __CPU_SDIO_H__ +#define __CPU_SDIO_H__ + +#define SD_EMMC_BASE_A 0xFFE03000 +#define SD_EMMC_BASE_B 0xFFE05000 +#define SD_EMMC_BASE_C 0xFFE07000 + +#define SDIO_PORT_A 0 +#define SDIO_PORT_B 1 +#define SDIO_PORT_C 2 + +struct sd_emmc_global_regs { + volatile uint32_t gclock; // 0x00 + volatile uint32_t gdelay; // 0x04 + volatile uint32_t gdelay1; //0x08 + volatile uint32_t gadjust; // 0x0c + volatile uint32_t gcalout; // 0x10 + volatile uint32_t reserved_14[11]; // 0x14~0x3c + volatile uint32_t gstart; // 0x40 + volatile uint32_t gcfg; // 0x44 + volatile uint32_t gstatus; // 0x48 + volatile uint32_t girq_en; // 0x4c + volatile uint32_t gcmd_cfg; // 0x50 + volatile uint32_t gcmd_arg; // 0x54 + volatile uint32_t gcmd_dat; // 0x58 + volatile uint32_t gcmd_rsp0; // 0x5c + volatile uint32_t gcmd_rsp1; // 0x60 + volatile uint32_t gcmd_rsp2; // 0x64 + volatile uint32_t gcmd_rsp3; // 0x68 + volatile uint32_t reserved_6c; // 0x6c + volatile uint32_t gcurr_cfg; // 0x70 + volatile uint32_t gcurr_arg; // 0x74 + volatile uint32_t gcurr_dat; // 0x78 + volatile uint32_t gcurr_rsp; // 0x7c + volatile uint32_t gnext_cfg; // 0x80 + volatile uint32_t gnext_arg; // 0x84 + volatile uint32_t gnext_dat; // 0x88 + volatile uint32_t gnext_rsp; // 0x8c + volatile uint32_t grxd; // 0x90 + volatile uint32_t gtxd; // 0x94 + volatile uint32_t reserved_98[90]; // 0x98~0x1fc + volatile uint32_t gdesc[128]; // 0x200 + volatile uint32_t gping[128]; // 0x400 + volatile uint32_t gpong[128]; // 0x800 +}; + +union sd_emmc_setup { + uint32_t d32; + struct { + unsigned bw:3; + unsigned fast:1; + unsigned par:3; + unsigned hcs:1; + unsigned sd:1; + unsigned sdhc:1; + unsigned type:6; + unsigned rca:16; + } b; +}; + +struct sd_emmc_desc_info{ + uint32_t cmd_info; + uint32_t cmd_arg; + uint32_t data_addr; + uint32_t resp_addr; +}; + +struct cmd_cfg{ + uint32_t length:9; + uint32_t block_mode:1; + uint32_t r1b:1; + uint32_t end_of_chain:1; + uint32_t timeout:4; + uint32_t no_resp:1; + uint32_t no_cmd:1; + uint32_t data_io:1; + uint32_t data_wr:1; + uint32_t resp_nocrc:1; + uint32_t resp_128:1; + uint32_t resp_num:1; + uint32_t data_num:1; + uint32_t cmd_index:6; + uint32_t error:1; + uint32_t owner:1; +}; + +struct sd_emmc_status{ + uint32_t rxd_err:8; /*[7:0] RX data CRC error per wire, for multiple block read, the CRC errors are ORed together.*/ + uint32_t txd_err:1; /*[8] TX data CRC error, for multiple block write, any one of blocks CRC error. */ + uint32_t desc_err:1; /*[9] SD/eMMC controller doesn¡¯t own descriptor. The owner bit is ¡°0¡±, set cfg_ignore_owner to ignore this error.*/ + uint32_t resp_err:1; /*[10] Response CRC error.*/ + uint32_t resp_timeout:1; /*[11] No response received before time limit. The timeout limit is set by cfg_resp_timeout.*/ + uint32_t desc_timeout:1; /*[12] Descriptor execution time over time limit. The timeout limit is set by descriptor itself.*/ + /* Consider the multiple block read/write, set the proper timeout limits.*/ + uint32_t end_of_chain:1; /*[13] End of Chain IRQ, Normal IRQ. */ + uint32_t desc_irq:1; /*[14] This descriptor requests an IRQ, Normal IRQ, the descriptor chain execution keeps going on.*/ + uint32_t irq_sdio:1; /*[15] SDIO device uses DAT[1] to request IRQ. */ + uint32_t dat_i:8; /*[23:16] Input data signals. */ + uint32_t cmd_i:1; /*[24] nput response signal. */ + uint32_t ds:1; /*[25] Input data strobe. */ + uint32_t bus_fsm:4; /*[29:26] BUS fsm */ + uint32_t desc_wr_rdy:1; /*[30] Descriptor write back process is done and it is ready for CPU to read.*/ + uint32_t core_rdy:1; /*[31] desc_busy or sd_emmc_irq or bus_fsm is not idle.*/ +};//__attribute__((__may_alias__)); + + +struct sd_emmc_clock{ + uint32_t div:6; /*[5:0] Clock divider. Frequency = clock source/cfg_div, Maximum divider 63. */ + /*Clock off: cfg_div==0, the clock is disabled */ + /*Divider bypass: cfg_div==1, clock source is used as core clock without divider. */ + uint32_t src:2; /*[7:6] Clock source, 0: Crystal 24MHz, 1: Fix PLL, 850MHz*/ + /* 2: MPLL, <637MHz, used for 400MHz exactly. 3: different PLL */ + uint32_t core_phase:2; /*[9:8] Core clock phase. 0: 0 phase, 1: 90 phase, 2: 180 phase, 3: 270 phase.*/ + uint32_t tx_phase:2; /*[11:10] TX clock phase. 0: 0 phase, 1: 90 phase, 2: 180 phase, 3: 270 phase.*/ + uint32_t rx_phase:2; /*[13:12] RX clock phase. 0: 0 phase, 1: 90 phase, 2: 180 phase, 3: 270 phase.*/ + uint32_t reserved14:2; + uint32_t tx_delay:6; /*[21:16] TX clock delay line. 0: no delay, n: delay n*200ps. Maximum delay 3ns.*/ + uint32_t rx_delay:6; /*[27:22] RX clock delay line. 0: no delay, n: delay n*200ps. Maximum delay 3ns.*/ + uint32_t always_on:1; /*[28] 1: Keep clock always on. 0: Clock on/off controlled by activities. */ + /*Any APB3 access or descriptor execution will keep clock on.*/ + uint32_t irq_sdio_sleep:1; /*[29] 1: enable IRQ sdio when in sleep mode. */ + uint32_t irq_sdio_sleep_ds:1;/*[30] 1:enable ds as irq*/ + uint32_t reserved26:1; +}; + +struct sd_emmc_delay{ + uint32_t dat0:6; /*[3:0] Data 0 delay line. */ + uint32_t dat1:6; /*[7:4] Data 1 delay line. */ + uint32_t dat2:6; /*[11:8] Data 2 delay line. */ + uint32_t dat3:6; /*[15:12] Data 3 delay line. */ + uint32_t dat4:6; /*[19:16] Data 4 delay line. */ + uint32_t spare:2; +}; + +struct sd_emmc_delay1{ + uint32_t dat5:6; /*[23:20] Data 5 delay line. */ + uint32_t dat6:6; /*[27:24] Data 6 delay line. */ + uint32_t dat7:6; /*[31:28] Data 7 delay line. */ + uint32_t dat8:6; /*[31:28] Data 7 delay line. */ + uint32_t dat9:6; /*[31:28] Data 7 delay line. */ + uint32_t spare:2; +}; + +struct sd_emmc_adjust{ + uint32_t cmd_delay:4; /*[3:0] Command delay line. */ + uint32_t ds_delay:4; /*[7:4] DS delay line. */ + uint32_t cali_sel:4; /*[11:8] Select one signal to be tested.*/ + /*Signals are labeled from 0 to 9 the same as delay lines. */ + uint32_t cali_enable:1; /*[12] Enable calibration. */ + uint32_t adj_enable:1; /*[13] Adjust interface timing by resampling the input signals. */ + uint32_t cali_rise:1; /*[14] 1: test the rising edge. 0: test the falling edge. */ + uint32_t ds_enable:1; /*[15] Sampling the DAT based on DS in HS400 mode*/ + uint32_t adj_delay:6; /*[21:16] Resample the input signals when clock index==adj_delay. */ + uint32_t adj_auto:1; /*[22] Use cali_dut first falling edge to adjust the timing */ + /*set cali_enable to 1 to use this function*/ + uint32_t reserved23:9; +}; + + +struct sd_emmc_calout{ + uint32_t cali_idx:6; /*[5:0] Calibration reading. The event happens at this index. */ + uint32_t reserved6:1; + uint32_t cali_vld:1; /*[7] The reading is valid. */ + uint32_t cali_setup:8; /*[15:8] Copied from BASE+0x8 [15:8] include cali_sel, cali_enable, adj_enable, cali_rise. */ + uint32_t reserved16:16; +}; + + +struct sd_emmc_start{ + uint32_t init:1; /*[0] 1: Read descriptor from internal SRAM, limited to 32 descriptors. */ + /* 0: Read descriptor from external DDR */ + uint32_t busy:1; /*[1] 1: Start command chain execution process. 0: Stop */ + uint32_t addr:30; /*[31:2] Descriptor address, the last 2 bits are 0, 4 bytes aligned. */ + /* When internal SRAM is used, the valid address range is from 0x200~0x3ff */ + /* When external DDR is used, the valid address is anywhere in DDR, the length of chain is unlimited.*/ +};//__attribute__((__may_alias__)); + + +struct sd_emmc_config{ + uint32_t bus_width:2; /*[1:0] 0: 1 bit, 1: 4 bits, 2: 8 bits, 3: 2 bits (not supported)*/ + uint32_t ddr:1; /*[2] 1: DDR mode, 0: SDR mode */ + uint32_t dc_ugt:1; /*[3] 1: DDR access urgent, 0: DDR access normal. */ + uint32_t bl_len:4; /*[7:4] Block length 2^cfg_bl_len, because internal buffer size is limited to 512 bytes, the cfg_bl_len <=9. */ + uint32_t resp_timeout:4; /*[11:8] Wait response till 2^cfg_resp_timeout core clock cycles. Maximum 32768 core cycles. */ + uint32_t rc_cc:4; /*[15:12] Wait response-command, command-command gap before next command, 2^cfg_rc_cc core clock cycles. */ + uint32_t out_fall:1; /*[16] DDR mode only. The command and TXD start from rising edge. Set 1 to start from falling edge. */ + uint32_t blk_gap_ip:1; /*[17] 1: Enable SDIO data block gap interrupt period. 0: Disabled.*/ + uint32_t spare:1; /*[18] Spare, ??? need check*/ + uint32_t ignore_owner:1; /*[19] Use this descriptor even if its owner bit is ¡°0¡±.*/ + uint32_t chk_ds:1; /*[20] Check data strobe in HS400.*/ + uint32_t cmd_low:1; /*[21] Hold CMD as output Low, eMMC boot mode.*/ + uint32_t stop_clk:1; /*[22] 1: stop clock. 0: normal clock.*/ + /*In normal mode, the clock is automatically on/off during reading mode to back off reading in case of*/ + /*DDR slow response, stop clock is used in voltage switch.*/ + uint32_t auto_clk:1; /*[23] 1: when BUS is idle and no descriptor is available, turn off clock, to save power.*/ + /* 0: core clock is always on.*/ + uint32_t txd_add_err:1; /*[24] TXD add error test*/ + /*Test feature, should not be used in normal condition.*/ + /*It will inverted the first CRC bits of the 3rd block.*/ + /*Block index starts from 0, 1, 2, ¡*/ + uint32_t txd_retry:1; /*[25] When TXD CRC error, host sends the block again.*/ + /*The total number of retries of one descriptor is limited to 15, */ + /*after 15 retries, the TXD_err is set to high.*/ + uint32_t revd:8; /*[31:26] reved*/ +};//__attribute__((__may_alias__)); + + +struct sd_emmc_irq_en{ + uint32_t rxd_err:8; /*[7:0] RX data CRC error per wire.*/ + uint32_t txd_err:1; /*[8] TX data CRC error. */ + uint32_t desc_err:1; /*[9] SD/eMMC controller doesn¡¯t own descriptor. */ + uint32_t resp_err:1; /*[10] Response CRC error.*/ + uint32_t resp_timeout:1; /*[11] No response received before time limit. */ + uint32_t desc_timeout:1; /*[12] Descriptor execution time over time limit. */ + uint32_t end_of_chain:1; /*[13] End of Chain IRQ. */ + uint32_t desc_irq:1; /*[14] This descriptor requests an IRQ. */ + uint32_t irq_sdio:1; /*[15] Enable sdio interrupt. */ + uint32_t revd:16; /*[31:16] reved*/ +}; + +struct sd_emmc_data_info{ + uint32_t cnt:10; /*[9:0] Rxd words received from BUS. Txd words received from DDR.*/ + uint32_t blk:9; /*[24:16] Rxd Blocks received from BUS. Txd blocks received from DDR.*/ + uint32_t revd:30; /*[31:17] Reved. */ +}; + + +struct sd_emmc_card_info{ + uint32_t txd_cnt:10; /*[9:0] Txd BUS cycle counter. */ + uint32_t txd_blk:9; /*[24:16] Txd BUS block counter.*/ + uint32_t revd:30; /*[31:17] Reved. */ +}; + +#endif
diff --git a/arch/arm/include/asm/arch-c1/ddr.h b/arch/arm/include/asm/arch-c1/ddr.h new file mode 100644 index 0000000..ad27855 --- /dev/null +++ b/arch/arm/include/asm/arch-c1/ddr.h
@@ -0,0 +1,100 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <config.h> +#include <io.h> +#include <stdint.h> +#include <asm/arch/ddr_define.h> + +/* io defines */ +//#define wr_reg(addr, data) (*((volatile uint32_t *)addr))=(uint32_t)(uint64_t)(data) +//#define rd_reg(addr) (*((volatile uint32_t *)(addr))) +#define wr_reg(addr, data) writel(data, addr) +#define rd_reg(addr) readl(addr) +/*clear [mask] 0 bits in [addr], set these 0 bits with [value] corresponding bits*/ +#define modify_reg(addr, value, mask) wr_reg(addr, ((rd_reg(addr) & (mask)) | (value))) +#define wait_set(addr, loc) do{}while(0 == (rd_reg(addr) & (1<<loc))); +#define wait_clr(addr, loc) do{}while(1 == (rd_reg(addr) & (1<<loc))); +#define wait_equal(addr, data) do{}while(data != (rd_reg(addr))); + +/* function defines */ +unsigned int ddr_init(void); +unsigned int ddr_init_pll(void); +unsigned int ddr_init_dmc(void); +unsigned int ddr_init_pctl(void); +unsigned int hot_boot(void); +void ddr_print_info(void); +void ddr_test(void); +void ddr_pre_init(void); +void ddr_debug(void); + +/* pctl status */ +#define UPCTL_STAT_MASK (7) +#define UPCTL_STAT_INIT (0) +#define UPCTL_STAT_CONFIG (1) +#define UPCTL_STAT_ACCESS (3) +#define UPCTL_STAT_LOW_POWER (5) + +/* pctl cmds */ +#define UPCTL_CMD_INIT (0) +#define UPCTL_CMD_CONFIG (1) +#define UPCTL_CMD_GO (2) +#define UPCTL_CMD_SLEEP (3) +#define UPCTL_CMD_WAKEUP (4) + +/* PUB PIR setting */ +#define PUB_PIR_INIT (1<<0) +#define PUB_PIR_ZCAL (1<<1) +#define PUB_PIR_CA (1<<2) +#define PUB_PIR_PLLINIT (1<<4) +#define PUB_PIR_DCAL (1<<5) +#define PUB_PIR_PHYRST (1<<6) +#define PUB_PIR_DRAMRST (1<<7) +#define PUB_PIR_DRAMINIT (1<<8) +#define PUB_PIR_WL (1<<9) +#define PUB_PIR_QSGATE (1<<10) +#define PUB_PIR_WLADJ (1<<11) +#define PUB_PIR_RDDSKW (1<<12) +#define PUB_PIR_WRDSKW (1<<13) +#define PUB_PIR_RDEYE (1<<14) +#define PUB_PIR_WREYE (1<<15) +#define PUB_PIR_ICPC (1<<16) +#define PUB_PIR_PLLBYP (1<<17) +#define PUB_PIR_CTLDINIT (1<<18) +#define PUB_PIR_RDIMMINIT (1<<19) +#define PUB_PIR_CLRSR (1<<27) +#define PUB_PIR_LOCKBYP (1<<28) +#define PUB_PIR_DCALBYP (1<<29) +#define PUB_PIR_ZCALBYP (1<<30) +#define PUB_PIR_INITBYP (1<<31) + +/* PHY initialize register (PIR) */ +#define DDR_PIR ((PUB_PIR_ZCAL) |\ + (PUB_PIR_PLLINIT) |\ + (PUB_PIR_DCAL) |\ + (PUB_PIR_PHYRST) |\ + (PUB_PIR_DRAMRST) |\ + (PUB_PIR_DRAMINIT) |\ + (PUB_PIR_WL) |\ + (PUB_PIR_QSGATE) |\ + (PUB_PIR_WLADJ) |\ + (PUB_PIR_RDDSKW) |\ + (PUB_PIR_WRDSKW) |\ + (PUB_PIR_RDEYE) |\ + (PUB_PIR_WREYE) \ + ) + +/* PHY general status register (PGSR0) */ +#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3) +#define DDR_PGSR0_CHECK() ((rd_reg(DDR0_PUB_PGSR0) != 0xC0000fff) && \ + (rd_reg(DDR0_PUB_PGSR0) != 0x80000fff)) +#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR2) +#define DDR_PGSR0_CHECK() +#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3) +#define DDR_PGSR0_CHECK() +#endif + +/* other regs */ +#define SCRATCH0 0xC1107D3C
diff --git a/arch/arm/include/asm/arch-c1/ddr_define.h b/arch/arm/include/asm/arch-c1/ddr_define.h new file mode 100644 index 0000000..2d2697e --- /dev/null +++ b/arch/arm/include/asm/arch-c1/ddr_define.h
@@ -0,0 +1,305 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#define CONFIG_BOARD_ID_MASK 0xFF +#define CONFIG_DDR_TYPE_DDR3 0 +#define CONFIG_DDR_TYPE_DDR4 1 +#define CONFIG_DDR_TYPE_LPDDR4 2 +#define CONFIG_DDR_TYPE_LPDDR3 3 +#define CONFIG_DDR_TYPE_LPDDR2 4 +#define CONFIG_DDR_TYPE_AUTO 0xf + +/* ddr channel defines */ +#define CONFIG_DDR0_16BIT 1 +#define CONFIG_DDR0_RANK0 2 +#define CONFIG_DDR0_RANK01 3 +#define CONFIG_DDR0_16BIT_2 4 +/* CONFIG_DDR_CHL_AUTO mode support RANK0 and RANK0+1 mode auto detect */ +#define CONFIG_DDR_CHL_AUTO 0xF +#define CONFIG_DDR0_16BIT_CH0 0x1 +#define CONFIG_DDR0_16BIT_RANK01_CH0 0x4 +#define CONFIG_DDR0_32BIT_RANK0_CH0 0x2 +#define CONFIG_DDR0_32BIT_RANK01_CH01 0x3 +#define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5 +#define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6 +#define CONFIG_DDR0_32BIT_RANK01_CH0 0x7 +#define CONFIG_DDR0_32BIT_RANK0_CH01 0x8 + +#define CFG_DDR_BASE_ADDR 0X0 +#define CFG_DDR_START_OFFSET 0X00000000 //TXLX SKIP 0MB + +/* ddr type identifier */ +#define CONFIG_DDR_TIMMING_LPDDR2 0x02 +#define CONFIG_DDR_TIMMING_LPDDR3 0x03 +#define CONFIG_DDR_TIMMING_DDR3_7 0x07 +#define CONFIG_DDR_TIMMING_DDR3_9 0x09 +#define CONFIG_DDR_TIMMING_DDR3_11 0x0B +#define CONFIG_DDR_TIMMING_DDR3_12 0x0C +#define CONFIG_DDR_TIMMING_DDR3_13 0x0D +#define CONFIG_DDR_TIMMING_DDR3_14 0x0E + +#define CONFIG_DDR_TIMMING_DDR4_1600 0x0F +#define CONFIG_DDR_TIMMING_DDR4_1866 0x10 +#define CONFIG_DDR_TIMMING_DDR4_2133 0x11 +#define CONFIG_DDR_TIMMING_DDR4_2400 0x12 +#define CONFIG_DDR_TIMMING_DDR4_2666 0x13 +#define CONFIG_DDR_TIMMING_DDR4_3200 0x14 + +#define LPDDR_DIE_ROW_COL_R13_C9 0 +#define LPDDR_DIE_ROW_COL_R14_C9 1 +#define LPDDR_DIE_ROW_COL_R14_C10 2 +#define LPDDR_DIE_ROW_COL_R13_C10 3 +#define LPDDR_DIE_ROW_COL_R14_C11 4 + +#define CONFIG_LPDDR3_CA_TRAINING_USE_LANE0 0 +#define CONFIG_LPDDR3_CA_TRAINING_USE_LANE1 1 +#define CONFIG_LPDDR3_CA_TRAINING_USE_LANE2 2 +#define CONFIG_LPDDR3_CA_TRAINING_USE_LANE3 3 + +#define CONFIG_DDR_FUNC_TEST (1<<0) + +#define CONFIG_DDR_INIT_RETRY_TOTAL (10) +#define CONFIG_DDR_PCTL_RETRY_TOTAL (100) + +#define DDR_USE_1_RANK(chl_set) ((chl_set == CONFIG_DDR0_RANK0) || \ + (chl_set == CONFIG_DDR0_16BIT)) +#define DDR_USE_2_RANK(chl_set) ((chl_set == CONFIG_DDR0_RANK01)) + +#define DMC_TEST_SLT_ENABLE_DDR_AUTO_FAST_BOOT 1<<5 +#define DMC_TEST_SLT_ENABLE_DDR_AUTO_WINDOW_TEST 1<<4 +/* DMC_DDR_CTRL defines */ +#define DDR_DDR4_ENABLE (1<<22) +#define DDR_RANK1_ENABLE (1<<21) +#define DDR_DDR4_BG_ENABLE (1<<20) +#define DDR_16BIT_ENABLE (1<<16) + +#define DDR_RANK1_SIZE_CTRL (3) +#define DDR_RANK0_SIZE_CTRL (0) + +/* dram cfg magic */ +#define DRAM_CFG_MAGIC 0x2e676663 + +#define DMC_TEST_SLT_SCAN_FREQUENCY 1 +#define DMC_TEST_SLT_OFFSET_DELAY (1<<1) +#define DMC_TEST_SLT_ENABLE_DDR_SKIP_TRAINING (1<<6) +#define DMC_TEST_SLT_ENABLE_DDR_DVFS (1<<7) + +/* ddr configs */ +#define DDR_RFC_TYPE_DDR3_512Mbx1 0 +#define DDR_RFC_TYPE_DDR3_512Mbx2 1 +#define DDR_RFC_TYPE_DDR3_512Mbx4 2 +#define DDR_RFC_TYPE_DDR3_512Mbx8 3 +#define DDR_RFC_TYPE_DDR3_512Mbx16 4 +#define DDR_RFC_TYPE_DDR4_2Gbx1 5 +#define DDR_RFC_TYPE_DDR4_2Gbx2 6 +#define DDR_RFC_TYPE_DDR4_2Gbx4 7 +#define DDR_RFC_TYPE_DDR4_2Gbx8 8 + +#define DDR_RFC_TYPE_LPDDR4_2Gbx1 9 +#define DDR_RFC_TYPE_LPDDR4_3Gbx1 10 +#define DDR_RFC_TYPE_LPDDR4_4Gbx1 11 +#define DDR_RFC_TYPE_LPDDR4_6Gbx1 12 +#define DDR_RFC_TYPE_LPDDR4_8Gbx1 13 + +#define DDR_ENABLE_FINE_TUNE_FLAG_AC_DELAY (1<<0) +#define DDR_ENABLE_FINE_TUNE_FLAG_WRITE_DQS (1<<1) +#define DDR_ENABLE_FINE_TUNE_FLAG_READ_DQS (1<<2) +#define DDR_ENABLE_FINE_TUNE_FLAG_WRITE_DQ (1<<3) +#define DDR_ENABLE_FINE_TUNE_FLAG_READ_DQ (1<<4) + +/* lpddr3 defines */ +#ifndef CONFIG_LPDDR_REMAP_SET +#define CONFIG_LPDDR_REMAP_SET LPDDR_DIE_ROW_COL_R14_C9 +#endif + +/* how to add a new ddr function? + 1. add CONFIG_DDR_FUNC_XXX in (config).h file + 2. add define in this file. + 2.1 add + #ifndef CONFIG_DDR_FUNC_XXX + #define CONFIG_DDR_FUNC_XXX 0 + #endif + 2.2 add + #define DDR_FUNC_XXX (CONFIG_FUNC_XXX<<X) + 2.3 add DDR_FUNC_XXX |\ in DDR_FUNC + 3. add same define and parser in bl2 code + */ +/* 2.1, 2,2, 2,3 example */ +/* +#ifndef CONFIG_CMD_DDR_D2PLL +#define CONFIG_CMD_DDR_D2PLL 0 +#endif +#define DDR_FUNC_D2PLL (CONFIG_CMD_DDR_D2PLL<<0) +#define DDR_FUNC (EXISTING_FUNCTIONS) |\ + (DDR_FUNC_D2PLL) +*/ + +/* d2pll support */ +#ifndef CONFIG_CMD_DDR_D2PLL +#define CONFIG_CMD_DDR_D2PLL 0 +#endif +#define DDR_FUNC_D2PLL (CONFIG_CMD_DDR_D2PLL<<0) + +/* ddr low power function support */ +#ifndef CONFIG_DDR_LOW_POWER +#define CONFIG_DDR_LOW_POWER 0 +#endif +#define DDR_FUNC_LP (CONFIG_DDR_LOW_POWER<<1) + +/* ddr zq power down support */ +#ifndef CONFIG_DDR_ZQ_PD +#define CONFIG_DDR_ZQ_PD 0 +#endif +#define DDR_FUNC_ZQ_PD (CONFIG_DDR_ZQ_PD<<2) + +/* ddr vref function */ +#ifndef CONFIG_DDR_USE_EXT_VREF +#define CONFIG_DDR_USE_EXT_VREF 0 +#endif +#define DDR_FUNC_EXT_VREF (CONFIG_DDR_USE_EXT_VREF<<3) + +/* ddr4 timing test function */ +#ifndef CONFIG_DDR4_TIMING_TEST +#define CONFIG_DDR4_TIMING_TEST 0 +#endif +#define DDR_FUNC_DDR4_TIMING_TEST (CONFIG_DDR4_TIMING_TEST<<4) + +/* ddr pll bypass */ +#ifndef CONFIG_DDR_PLL_BYPASS +#define CONFIG_DDR_PLL_BYPASS 0 +#endif +#define DDR_FUNC_DDR_PLL_BYPASS (CONFIG_DDR_PLL_BYPASS<<5) + +/* ddr rdbi function */ +#ifndef CONFIG_DDR_FUNC_RDBI +#define CONFIG_DDR_FUNC_RDBI 0 +#endif +#define DDR_FUNC_RDBI (CONFIG_DDR_FUNC_RDBI<<6) + +/* lpddr3 ca trainingi function */ +#ifndef CONFIG_DDR_FUNC_LPDDR3_CA +#define CONFIG_DDR_FUNC_LPDDR3_CA 0 +#endif +#define DDR_FUNC_LPDDR3_CA (CONFIG_DDR_FUNC_LPDDR3_CA<<7) + +/* print ddr training window */ +#ifndef CONFIG_DDR_FUNC_PRINT_WINDOW +#define CONFIG_DDR_FUNC_PRINT_WINDOW 0 +#endif +#define DDR_FUNC_PRINT_WINDOW (CONFIG_DDR_FUNC_PRINT_WINDOW<<8) + + +/* print ddr training window */ +//#ifndef CONFIG_DDR_FULL_TEST +//#define CONFIG_DDR_FULL_TEST 0 +//#endif +//#define DDR_FULL_TEST (CONFIG_DDR_FULL_TEST<<10) + +/* non-sec region scramble function */ +#ifndef CONFIG_DDR_NONSEC_SCRAMBLE +#define CONFIG_DDR_NONSEC_SCRAMBLE 0 +#endif +#define DDR_NONSEC_SCRAMBLE (CONFIG_DDR_NONSEC_SCRAMBLE<<11) + +#if(CONFIG_DDR_FUNC_LPDDR3_CA==1) +#if (CONFIG_LPDDR3_CA_TRAINING_CA0==CONFIG_LPDDR3_CA_TRAINING_USE_LANE0) +#define DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT0 (0<<20) +#define DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT1 (0<<21) +#elif (CONFIG_LPDDR3_CA_TRAINING_CA0==CONFIG_LPDDR3_CA_TRAINING_USE_LANE1) +#define DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT0 (1<<20) +#define DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT1 (0<<21) +#elif (CONFIG_LPDDR3_CA_TRAINING_CA0==CONFIG_LPDDR3_CA_TRAINING_USE_LANE2) +#define DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT0 (0<<20) +#define DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT1 (1<<21) +#elif (CONFIG_LPDDR3_CA_TRAINING_CA0==CONFIG_LPDDR3_CA_TRAINING_USE_LANE3) +#define DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT0 (1<<20) +#define DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT1 (1<<21) +#endif +#if (CONFIG_LPDDR3_CA_TRAINING_CA1==CONFIG_LPDDR3_CA_TRAINING_USE_LANE0) +#define DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT0 (0<<22) +#define DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT1 (0<<23) +#elif (CONFIG_LPDDR3_CA_TRAINING_CA1==CONFIG_LPDDR3_CA_TRAINING_USE_LANE1) +#define DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT0 (1<<22) +#define DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT1 (0<<23) +#elif (CONFIG_LPDDR3_CA_TRAINING_CA1==CONFIG_LPDDR3_CA_TRAINING_USE_LANE2) +#define DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT0 (0<<22) +#define DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT1 (1<<23) +#elif (CONFIG_LPDDR3_CA_TRAINING_CA1==CONFIG_LPDDR3_CA_TRAINING_USE_LANE3) +#define DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT0 (1<<22) +#define DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT1 (1<<23) +#endif +#else /* CONFIG_DDR_FUNC_LPDDR3_CA != 1 */ +#define DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT0 (0<<20) +#define DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT1 (0<<21) +#define DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT0 (0<<22) +#define DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT1 (0<<23) +#endif /* CONFIG_DDR_FUNC_LPDDR3_CA */ + +#if(CONFIG_DDR_FUNC_LPDDR3_SOC_ODT_ONLY_UP==1) +#define DDR_FUNC_LPDDR3_SOC_ODT_ONLY_UP (1<<25) +#else +#define DDR_FUNC_LPDDR3_SOC_ODT_ONLY_UP (0<<25) +#endif +#define DDR_FUNC_FAST_BOOT_CHECK_CHIP_ID (1<<30) +#define DDR_FUNC_CONFIG_DFE_FUNCTION (1<<29) +#define DDR_FUNC_CONFIG_DDR_DVFS_FUNCTION (1<<28) +#define DDR_FUNC (DDR_FUNC_D2PLL | \ + DDR_FUNC_LP | \ + DDR_FUNC_ZQ_PD | \ + DDR_FUNC_EXT_VREF | \ + DDR_FUNC_DDR4_TIMING_TEST | \ + DDR_FUNC_DDR_PLL_BYPASS | \ + DDR_FUNC_RDBI | \ + DDR_FUNC_LPDDR3_CA | \ + DDR_FUNC_PRINT_WINDOW | \ + DDR_FULL_TEST | \ + DDR_NONSEC_SCRAMBLE | \ + DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT0| \ + DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT1| \ + DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT0| \ + DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT1| \ + DDR_FUNC_LPDDR3_SOC_ODT_ONLY_UP | \ + (1 << 31) \ + ) + + + + +/* bl2 reg override stages define */ +#define BL2_INIT_STAGE_0 0 +#define BL2_INIT_STAGE_1 1 +#define BL2_INIT_STAGE_2 2 +#define BL2_INIT_STAGE_3 3 +#define BL2_INIT_STAGE_4 4 +#define BL2_INIT_STAGE_5 5 +#define BL2_INIT_STAGE_6 6 +#define BL2_INIT_STAGE_7 7 +#define BL2_INIT_STAGE_8 8 +#define BL2_INIT_STAGE_9 9 + + +/* ddr reg override stages define */ +#define DDR_OVERRIDE_STAGE_DDR3_PRE_INIT 0x10 +#define DDR_OVERRIDE_STAGE_DDR3_DMC_INIT 0x11 + +#define DDR_OVERRIDE_STAGE_DDR4_PRE_INIT 0x20 +#define DDR_OVERRIDE_STAGE_DDR4_DMC_INIT 0x21 + +#define DDR_OVERRIDE_STAGE_LPDDR3_PRE_INIT 0x30 +#define DDR_OVERRIDE_STAGE_LPDDR3_DMC_INIT 0x31 + +#define DDR_OVERRIDE_STAGE_LPDDR4_PRE_INIT 0x40 +#define DDR_OVERRIDE_STAGE_LPDDR4_DMC_INIT 0x41 + + +#define DWC_AC_PINMUX_TOTAL 28 +#define DWC_DFI_PINMUX_TOTAL 26 +#define DWC_DQ_PINMUX_TOTAL 32 + +/* diagnose function defines */ +#define CONFIG_DIAGNOSE_DISABLE 0x0 +#define CONFIG_DIAGNOSE_1D 0x1 +#define CONFIG_DIAGNOSE_2D 0x2 +#define CONFIG_DIAGNOSE_1D_2D 0x3
diff --git a/arch/arm/include/asm/arch-c1/efuse.h b/arch/arm/include/asm/arch-c1/efuse.h new file mode 100644 index 0000000..4a68e88 --- /dev/null +++ b/arch/arm/include/asm/arch-c1/efuse.h
@@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __EFUSE_H +#define __EFUSE_H + +#include <config.h> +#include <common.h> + +/* efuse HAL_API arg */ +struct efuse_hal_api_arg { + unsigned int cmd; /* R/W */ + unsigned int offset; + unsigned int size; + unsigned long buffer_phy; + unsigned long retcnt_phy; +}; + + +#define EFUSE_BYTES 512 /* (EFUSE_BITS/8) */ + +#define EFUSE_HAL_API_READ 0 +#define EFUSE_HAL_API_WRITE 1 +#define EFUSE_HAL_API_WRITE_PATTERN 2 +#define EFUSE_HAL_API_USER_MAX 3 + +#define EFUSE_USER_MASK (0x1 << 16) +#define EFUSE_THERMAL_MASK (0x1 << 17) +#define EFUSE_THERMAL_VERFLAG_MASK (0x1 << 18) +#define EFUSE_ENCRYPT_MASK (0x1 << 19) + +//#define ASSIST_HW_REV 0x1f53 + +int efuse_read_usr(char *buf, size_t count, loff_t *ppos); +int efuse_write_usr(char *buf, size_t count, loff_t *ppos); +uint32_t efuse_get_max(void); +ssize_t efuse_read(char *buf, size_t count, loff_t *ppos); +ssize_t efuse_write(const char *buf, size_t count, loff_t *ppos); + +int32_t meson_trustzone_efuse(struct efuse_hal_api_arg *arg); +int32_t meson_trustzone_efuse_get_max(struct efuse_hal_api_arg *arg); + +#endif +
diff --git a/arch/arm/include/asm/arch-c1/eth_setup.h b/arch/arm/include/asm/arch-c1/eth_setup.h new file mode 100644 index 0000000..6e643f6 --- /dev/null +++ b/arch/arm/include/asm/arch-c1/eth_setup.h
@@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <asm/arch/io.h> + +/* + *board configuration interface. + * */ +struct eth_clock_conf{ + int enable; + int clock_50MHZ_phase; + //add ... as you need. +}; + +struct eth_board_socket{ +char *name ; +int (*eth_clock_configure)(struct eth_clock_conf); +int (*eth_pinmux_setup)(void); +int (*eth_hw_reset)(void); + +}; + + + +/* + *clock define part + */ + +#define ETH_BASE (0xff3f0000) +#define ETH_PLL_CNTL CBUS_REG_ADDR(0x2050) + /* Ethernet ctrl */ +#define ETH_PLL_CNTL_DIVEN (1<<0) +#define ETH_PLL_CNTL_MACSPD (1<<1) +#define ETH_PLL_CNTL_DATEND (1<<2) +#define ETH_PLL_CNTL_DESEND (1<<3) + + +/* + please refer following doc for detail + @AppNote-M3-ClockTrees.docx + + select clk: -> CBUS_REG(0x1076) + + 7-sys_pll_div2 + 6-vid2_pll_clk + 5-vid_pll_clk + 4-aud_pll_clk + 3-ddr_pll_clk + 2-misc_pll_clk + 1-sys_pll_clk + 0-XTAL + + clk_freq:800MHz + output_clk:50MHz + aways,maybe changed for others? +*/ + +#define ETH_CLKSRC_XTAL (0) +#define ETH_CLKSRC_SYS_PLL_CLK (1) +#define ETH_CLKSRC_MISC_PLL_CLK (2) +#define ETH_CLKSRC_DDR_PLL_CLK (3) +#define ETH_CLKSRC_AUD_PLL_CLK ( +#define ETH_CLKSRC_VID_PLL_CLK (5) +#define ETH_CLKSRC_VID2_PLL_CLK (6) +#define ETH_CLKSRC_SYS_PLL_DIV2_CLK (7) +#define CLK_1M (1000000) + +typedef union eth_aml_reg0 { + /** raw register data */ + unsigned int d32; + /** register bits */ + struct { + unsigned phy_intf_sel:3; + unsigned rx_clk_rmii_invert:1; + unsigned rgmii_tx_clk_src:1; + unsigned rgmii_tx_clk_phase:2; + unsigned rgmii_tx_clk_ratio:3; + unsigned phy_ref_clk_enable:1; + unsigned clk_rmii_i_invert:1; + unsigned clk_en:1; + unsigned adj_enable:1; + unsigned adj_setup:1; + unsigned adj_delay:5; + unsigned adj_skew:5; + unsigned cali_start:1; + unsigned cali_rise:1; + unsigned cali_sel:3; + unsigned rgmii_rx_reuse:1; + unsigned eth_urgent:1; + } b; +} eth_aml_reg0_t; + +#define ETH_VALIDE_CLKSRC(clk,out_clk) ((clk%out_clk)==0) + +int eth_clk_set(int selectclk,unsigned long clk_freq,unsigned long out_clk); +
diff --git a/arch/arm/include/asm/arch-c1/gpio.h b/arch/arm/include/asm/arch-c1/gpio.h new file mode 100644 index 0000000..2467368 --- /dev/null +++ b/arch/arm/include/asm/arch-c1/gpio.h
@@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __ASM_ARCH_MESON_GPIO_H +#define __ASM_ARCH_MESON_GPIO_H + + +#endif /* __ASM_ARCH_MESON_GPIO_H */
diff --git a/arch/arm/include/asm/arch-c1/i2c.h b/arch/arm/include/asm/arch-c1/i2c.h new file mode 100644 index 0000000..a93a09d --- /dev/null +++ b/arch/arm/include/asm/arch-c1/i2c.h
@@ -0,0 +1,280 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __AML_MACH_I2C__ +#define __AML_MACH_I2C__ + +#include <asm/io.h> +#include <asm/arch/secure_apb.h> + +/** + * struct i2c_msg - an I2C transaction segment beginning with START + * @addr: Slave address, either seven or ten bits. When this is a ten + * bit address, I2C_M_TEN must be set in @flags and the adapter + * must support I2C_FUNC_10BIT_ADDR. + * @flags: I2C_M_RD is handled by all adapters. No other flags may be + * provided unless the adapter exported the relevant I2C_FUNC_* + * flags through i2c_check_functionality(). + * @len: Number of data bytes in @buf being read from or written to the + * I2C slave address. For read transactions where I2C_M_RECV_LEN + * is set, the caller guarantees that this buffer can hold up to + * 32 bytes in addition to the initial length byte sent by the + * slave (plus, if used, the SMBus PEC); and this value will be + * incremented by the number of block data bytes received. + * @buf: The buffer into which data is read, or from which it's written. + * + * An i2c_msg is the low level representation of one segment of an I2C + * transaction. It is visible to drivers in the @i2c_transfer() procedure, + * to userspace from i2c-dev, and to I2C adapter drivers through the + * @i2c_adapter.@master_xfer() method. + * + * Except when I2C "protocol mangling" is used, all I2C adapters implement + * the standard rules for I2C transactions. Each transaction begins with a + * START. That is followed by the slave address, and a bit encoding read + * versus write. Then follow all the data bytes, possibly including a byte + * with SMBus PEC. The transfer terminates with a NAK, or when all those + * bytes have been transferred and ACKed. If this is the last message in a + * group, it is followed by a STOP. Otherwise it is followed by the next + * @i2c_msg transaction segment, beginning with a (repeated) START. + * + * Alternatively, when the adapter supports I2C_FUNC_PROTOCOL_MANGLING then + * passing certain @flags may have changed those standard protocol behaviors. + * Those flags are only for use with broken/nonconforming slaves, and with + * adapters which are known to support the specific mangling options they + * need (one or more of IGNORE_NAK, NO_RD_ACK, NOSTART, and REV_DIR_ADDR). + */ +struct i2c_msg { + __u16 addr; /* slave address */ + __u16 flags; +#define I2C_M_TEN 0x0010 /* this is a ten bit chip address */ +#define I2C_M_RD 0x0001 /* read data, from slave to master */ +#define I2C_M_NOSTART 0x4000 /* if I2C_FUNC_PROTOCOL_MANGLING */ +#define I2C_M_REV_DIR_ADDR 0x2000 /* if I2C_FUNC_PROTOCOL_MANGLING */ +#define I2C_M_IGNORE_NAK 0x1000 /* if I2C_FUNC_PROTOCOL_MANGLING */ +#define I2C_M_NO_RD_ACK 0x0800 /* if I2C_FUNC_PROTOCOL_MANGLING */ +#define I2C_M_RECV_LEN 0x0400 /* length will be first received byte */ + __u16 len; /* msg length */ + __u8 *buf; /* pointer to msg data */ +}; + +#define MESON_I2C_MASTER_AO_START (AO_I2C_M_0_CONTROL_REG) +//#define MESON_I2C_MASTER_AO_END (0xc810051c+5) + +#define MESON_I2C_MASTER_A_START CBUS_REG_ADDR(I2C_M_0_CONTROL_REG) +#define MESON_I2C_MASTER_A_END (CBUS_REG_ADDR(I2C_M_0_RDATA_REG1+1)-1) + +#define MESON_I2C_MASTER_B_START CBUS_REG_ADDR(I2C_M_1_CONTROL_REG) +#define MESON_I2C_MASTER_B_END (CBUS_REG_ADDR(I2C_M_1_RDATA_REG1+1)-1) + +#define MESON_I2C_MASTER_C_START CBUS_REG_ADDR(I2C_M_2_CONTROL_REG) +#define MESON_I2C_MASTER_C_END (CBUS_REG_ADDR(I2C_M_2_RDATA_REG1+1)-1) + +#define MESON_I2C_MASTER_D_START CBUS_REG_ADDR(I2C_M_3_CONTROL_REG) +#define MESON_I2C_MASTER_D_END (CBUS_REG_ADDR(I2C_M_3_RDATA_REG1+1)-1) + +#define MESON_I2C_SLAVE_START CBUS_REG_ADDR(I2C_S_CONTROL_REG) +#define MESON_I2C_SLAVE_END (CBUS_REG_ADDR(I2C_S_CNTL1_REG+1)-1) + + +#define AML_I2C_MASTER_AO 0 +#define AML_I2C_MASTER_A 1 +#define AML_I2C_MASTER_B 2 +#define AML_I2C_MASTER_C 3 +#define AML_I2C_MASTER_D 4 + + +#define AML_I2C_SLAVE_ADDR 0x6c + +/*M1 i2c pinmux + * I/O I2C_MASTER_A I2C_MASTER_B I2C_SLAVE + * GPIO_JTAG_TMS SCK_A REG1[12] SCK_A REG1[13] + * GPIO_JTAG_TDI SDA_A REG1[12] SDA_A REG1[13] + * GPIO_JTAG_TCK SCK_B REG1[16] SCK_A REG1[17] + * GPIO_JTAG_TDO SDA_B REG1[20] SDA_A REG1[21] + * GPIOB_0 SCK_B REG2[5] SCK_A REG2[6] + * GPIOB_1 SDA_B REG2[2] SDA_A REG2[3] + * GPIOB_2 SCK_A REGS[13] SCK_A REG2[14] + * GPIOB_3 SDA_A REG2[9] SDA_A REG2[10] + * GPIOC_13 SCK_B REG3[28] SCK_A REG3[29] + * GPIOC_14 SDA_B REG3[25] SDA_A REG3[26] + * GPIOC_21 SCK_A REG7[9] SCK_A REG7[10] + * GPIOC_22 SDA_A REG7[6] SDA_A REG7[7] + * GPIOE_16 SCK_B REG5[27] SCK_A REG5[28] + * GPIOE_17 SDA_B REG5[25] SDA_A REG5[26] +*/ + +/*i2c master a*/ + + +#define MESON_I2C_MASTER_A_GPIOZ_17_REG (PERIPHS_PIN_MUX_9) +#define MESON_I2C_MASTER_A_GPIOZ_17_BIT (1<<7) +#define MESON_I2C_MASTER_A_GPIOZ_18_REG (PERIPHS_PIN_MUX_9) +#define MESON_I2C_MASTER_A_GPIOZ_18_BIT (1<<8) + +#define MESON_I2C_MASTER_A_GPIOW_0_REG (PERIPHS_PIN_MUX_5) +#define MESON_I2C_MASTER_A_GPIOW_0_BIT (1<<22) +#define MESON_I2C_MASTER_A_GPIOW_1_REG (PERIPHS_PIN_MUX_5) +#define MESON_I2C_MASTER_A_GPIOW_1_BIT (1<<23) + +/*i2c master b*/ + + +#define MESON_I2C_MASTER_B_GPIOH_3_REG (PERIPHS_PIN_MUX_7) +#define MESON_I2C_MASTER_B_GPIOH_3_BIT (1<<6) +#define MESON_I2C_MASTER_B_GPIOH_4_REG (PERIPHS_PIN_MUX_7) +#define MESON_I2C_MASTER_B_GPIOH_4_BIT (1<<7) + +#define MESON_I2C_MASTER_B_GPIOY_12_REG (PERIPHS_PIN_MUX_10) +#define MESON_I2C_MASTER_B_GPIOY_12_BIT (1<<14) +#define MESON_I2C_MASTER_B_GPIOY_13_REG (PERIPHS_PIN_MUX_10) +#define MESON_I2C_MASTER_B_GPIOY_13_BIT (1<<15) + +/*i2c master c*/ +#define MESON_I2C_MASTER_C_GPIOY_7_REG (PERIPHS_PIN_MUX_4) +#define MESON_I2C_MASTER_C_GPIOY_7_BIT (1<<28) +#define MESON_I2C_MASTER_C_GPIOY_8_REG (PERIPHS_PIN_MUX_4) +#define MESON_I2C_MASTER_C_GPIOY_8_BIT (1<<29) + +#define MESON_I2C_MASTER_C_GPIOX_0_REG (PERIPHS_PIN_MUX_1) +#define MESON_I2C_MASTER_C_GPIOX_0_BIT (1<<22) +#define MESON_I2C_MASTER_C_GPIOX_1_REG (PERIPHS_PIN_MUX_1) +#define MESON_I2C_MASTER_C_GPIOX_1_BIT (1<<23) + +/*i2c master d*/ + + +#define MESON_I2C_MASTER_D_GPIOY_10_REG (PERIPHS_PIN_MUX_10) +#define MESON_I2C_MASTER_D_GPIOY_10_BIT (1<<10) +#define MESON_I2C_MASTER_D_GPIOY_11_REG (PERIPHS_PIN_MUX_10) +#define MESON_I2C_MASTER_D_GPIOY_11_BIT (1<<11) + +#define MESON_I2C_MASTER_D_GPIOH_5_REG (PERIPHS_PIN_MUX_7) +#define MESON_I2C_MASTER_D_GPIOH_5_BIT (1<<23) +#define MESON_I2C_MASTER_D_GPIOH_6_REG (PERIPHS_PIN_MUX_7) +#define MESON_I2C_MASTER_D_GPIOH_6_BIT (1<<24) + +/*i2c master AO*/ + + +#define MESON_I2C_MASTER_AO_GPIOAO_4_REG (P_AO_RTI_PINMUX_REG0) /* P_AO_RTI_PIN_MUX_REG */ +#define MESON_I2C_MASTER_AO_GPIOAO_4_BIT (1<<8) +#define MESON_I2C_MASTER_AO_GPIOAO_5_REG (P_AO_RTI_PINMUX_REG0) /* P_AO_RTI_PIN_MUX_REG */ +#define MESON_I2C_MASTER_AO_GPIOAO_5_BIT (1<<9) + +/*i2c slave*/ +#define MESON_I2C_SLAVE_JTAG_TMS_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_1) +#define MESON_I2C_SLAVE_JTAG_TMS_BIT (1<<13) +#define MESON_I2C_SLAVE_JTAG_TDI_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_1) +#define MESON_I2C_SLAVE_JTAG_TDI_BIT (1<<13) + +#define MESON_I2C_SLAVE_GPIOB_2_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_2) +#define MESON_I2C_SLAVE_GPIOB_2_BIT (1<<14) +#define MESON_I2C_SLAVE_GPIOB_3_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_2) +#define MESON_I2C_SLAVE_GPIOB_3_BIT (1<<10) + +#define MESON_I2C_SLAVE_GPIOC_21_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_7) +#define MESON_I2C_SLAVE_GPIOC_21_BIT (1<<10) +#define MESON_I2C_SLAVE_GPIOC_22_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_7) +#define MESON_I2C_SLAVE_GPIOC_22_BIT (1<<7) + +#define MESON_I2C_SLAVE_JTAG_TCK_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_1) +#define MESON_I2C_SLAVE_JTAG_TCK_BIT (1<<17) +#define MESON_I2C_SLAVE_JTAG_TDO_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_1) +#define MESON_I2C_SLAVE_JTAG_TDO_BIT (1<<21) + +#define MESON_I2C_SLAVE_GPIOB_0_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_2) +#define MESON_I2C_SLAVE_GPIOB_0_BIT (1<<6) +#define MESON_I2C_SLAVE_GPIOB_1_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_2) +#define MESON_I2C_SLAVE_GPIOB_1_BIT (1<<3) + +#define MESON_I2C_SLAVE_GPIOC_13_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_3) +#define MESON_I2C_SLAVE_GPIOC_13_BIT (1<<29) +#define MESON_I2C_SLAVE_GPIOC_14_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_3) +#define MESON_I2C_SLAVE_GPIOC_14_BIT (1<<26) + +#define MESON_I2C_SLAVE_GPIOC_16_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_5) +#define MESON_I2C_SLAVE_GPIOC_16_BIT (1<<28) +#define MESON_I2C_SLAVE_GPIOC_17_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_5) +#define MESON_I2C_SLAVE_GPIOC_17_BIT (1<<26) + + +#define AML_I2C_SPPED_50K 50000 +#define AML_I2C_SPPED_100K 100000 +#define AML_I2C_SPPED_200K 200000 +#define AML_I2C_SPPED_300K 300000 +#define AML_I2C_SPPED_400K 400000 + +struct aml_pinmux_reg_bit { + unsigned long scl_reg; + unsigned long sda_reg; + unsigned int scl_bit; + unsigned int sda_bit; +}; + +struct aml_i2c_platform{ + unsigned int slave_addr;/*7bit addr*/ + unsigned int wait_count;/*i2c wait ack timeout = + wait_count * wait_ack_interval */ + unsigned int wait_ack_interval; + unsigned int wait_read_interval; + unsigned int wait_xfer_interval; + unsigned int master_no; + unsigned int use_pio;/*0: hardware i2c, 1: manual pio i2c*/ + unsigned int master_i2c_speed; + + /* only need 1 i2c master to comunicate with several devices, + * should I prepare 2 master interface to use simultaneously?*/ + struct resource * resource; + struct aml_pinmux_reg_bit master_ao_pinmux; + struct aml_pinmux_reg_bit master_a_pinmux; + struct aml_pinmux_reg_bit master_b_pinmux; + struct aml_pinmux_reg_bit master_c_pinmux; + struct aml_pinmux_reg_bit master_d_pinmux; + + struct aml_pinmux_reg_bit slave_reg_bit; +}; + +/**************i2c software gpio***************/ + +#define MESON_I2C_PREG_GPIOC_OE CBUS_REG_ADDR(PREG_FGPIO_EN_N) +#define MESON_I2C_PREG_GPIOC_OUTLVL CBUS_REG_ADDR(PREG_FGPIO_O) +#define MESON_I2C_PREG_GPIOC_INLVL CBUS_REG_ADDR(PREG_FGPIO_I) + +#define MESON_I2C_PREG_GPIOE_OE CBUS_REG_ADDR(PREG_HGPIO_EN_N) +#define MESON_I2C_PREG_GPIOE_OUTLVL CBUS_REG_ADDR(PREG_HGPIO_O) +#define MESON_I2C_PREG_GPIOE_INLVL CBUS_REG_ADDR(PREG_HGPIO_I) + +#define MESON_I2C_PREG_GPIOA_OE CBUS_REG_ADDR(PREG_EGPIO_EN_N) +#define MESON_I2C_PREG_GPIOA_OUTLVL CBUS_REG_ADDR(PREG_EGPIO_O) +#define MESON_I2C_PREG_GPIOA_INLVL CBUS_REG_ADDR(PREG_EGPIO_I) + +struct aml_sw_i2c_pins +{ + unsigned int scl_reg_out; + unsigned int scl_reg_in; + unsigned int scl_bit; + unsigned int scl_oe; + unsigned int sda_reg_out; + unsigned int sda_reg_in; + unsigned int sda_bit; + unsigned int sda_oe; +}; + + +struct aml_sw_i2c_platform { + struct aml_sw_i2c_pins sw_pins; + + /* local settings */ + int udelay; /* half clock cycle time in us, + minimum 2 us for fast-mode I2C, + minimum 5 us for standard-mode I2C and SMBus, + maximum 50 us for SMBus */ + int timeout; /* in jiffies */ +}; + + +#endif //__AML_MACH_I2C__ + +
diff --git a/arch/arm/include/asm/arch-c1/io.h b/arch/arm/include/asm/arch-c1/io.h new file mode 100644 index 0000000..fd3981a --- /dev/null +++ b/arch/arm/include/asm/arch-c1/io.h
@@ -0,0 +1,102 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __MACH_MESSON_REGS_IO_H +#define __MACH_MESSON_REGS_IO_H + +#ifndef __ASSEMBLY__ + +#include <asm/io.h> +#define IO_CBUS_BASE (0xFFD00000L) +#define IO_AXI_BUS_BASE (0xFFB00000L) /* gpv */ +#define IO_AHB_BUS_BASE (0xFF500000L) /* usb0 */ +#define IO_APB_BUS_BASE (0xFFFC0000L) /* AHB SRAM, sec/sys ahb? txlx_mem_map.xlsx */ +#define IO_APB_HDMI_BUS_BASE (0xFFE00000L) /* */ +#define IO_VPU_BUS_BASE (0xFF900000L) /* VPU */ + +#define CBUS_REG_OFFSET(reg) ((reg) << 2) +#define CBUS_REG_ADDR(reg) (IO_CBUS_BASE + CBUS_REG_OFFSET(reg)) + +#define AXI_REG_OFFSET(reg) ((reg) << 2) +#define AXI_REG_ADDR(reg) (IO_AXI_BUS_BASE + AXI_REG_OFFSET(reg)) + +#define AHB_REG_OFFSET(reg) ((reg) << 2) +#define AHB_REG_ADDR(reg) (IO_AHB_BUS_BASE + AHB_REG_OFFSET(reg)) + +#define VPU_REG_OFFSET(reg) ((reg) << 2) +#define VPU_REG_ADDR(reg) (IO_VPU_BUS_BASE + VPU_REG_OFFSET(reg)) + + +#define APB_REG_OFFSET(reg) (reg) +#define APB_REG_ADDR(reg) (IO_APB_BUS_BASE + APB_REG_OFFSET(reg)) +#define APB_REG_ADDR_VALID(reg) (((unsigned long)(reg) & 3) == 0) + +#define APB_HDMI_REG_OFFSET(reg) (reg) +#define APB_HDMI_REG_ADDR(reg) (IO_APB_HDMI_BUS_BASE + APB_HDMI_REG_OFFSET(reg)) +#define APB_HDMI_REG_ADDR_VALID(reg) (((unsigned long)(reg) & 3) == 0) + + +#define WRITE_CBUS_REG(reg, val) __raw_writel(val, CBUS_REG_ADDR(reg)) +#define READ_CBUS_REG(reg) (__raw_readl(CBUS_REG_ADDR(reg))) +#define WRITE_CBUS_REG_BITS(reg, val, start, len) \ + WRITE_CBUS_REG(reg, (READ_CBUS_REG(reg) & ~(((1L<<(len))-1)<<(start)) )| ((unsigned)((val)&((1L<<(len))-1)) << (start))) +#define READ_CBUS_REG_BITS(reg, start, len) \ + ((READ_CBUS_REG(reg) >> (start)) & ((1L<<(len))-1)) +#define CLEAR_CBUS_REG_MASK(reg, mask) WRITE_CBUS_REG(reg, (READ_CBUS_REG(reg)&(~(mask)))) +#define SET_CBUS_REG_MASK(reg, mask) WRITE_CBUS_REG(reg, (READ_CBUS_REG(reg)|(mask))) + +#define WRITE_AXI_REG(reg, val) __raw_writel(val, AXI_REG_ADDR(reg)) +#define READ_AXI_REG(reg) (__raw_readl(AXI_REG_ADDR(reg))) +#define WRITE_AXI_REG_BITS(reg, val, start, len) \ + WRITE_AXI_REG(reg, (READ_AXI_REG(reg) & ~(((1L<<(len))-1)<<(start)) )| ((unsigned)((val)&((1L<<(len))-1)) << (start))) +#define READ_AXI_REG_BITS(reg, start, len) \ + ((READ_AXI_REG(reg) >> (start)) & ((1L<<(len))-1)) +#define CLEAR_AXI_REG_MASK(reg, mask) WRITE_AXI_REG(reg, (READ_AXI_REG(reg)&(~(mask)))) +#define SET_AXI_REG_MASK(reg, mask) WRITE_AXI_REG(reg, (READ_AXI_REG(reg)|(mask))) + +#define WRITE_AHB_REG(reg, val) __raw_writel(val, AHB_REG_ADDR(reg)) +#define READ_AHB_REG(reg) (__raw_readl(AHB_REG_ADDR(reg))) +#define WRITE_AHB_REG_BITS(reg, val, start, len) \ + WRITE_AHB_REG(reg, (READ_AHB_REG(reg) & ~(((1L<<(len))-1)<<(start)) )| ((unsigned)((val)&((1L<<(len))-1)) << (start))) +#define READ_AHB_REG_BITS(reg, start, len) \ + ((READ_AHB_REG(reg) >> (start)) & ((1L<<(len))-1)) +#define CLEAR_AHB_REG_MASK(reg, mask) WRITE_AHB_REG(reg, (READ_AHB_REG(reg)&(~(mask)))) +#define SET_AHB_REG_MASK(reg, mask) WRITE_AHB_REG(reg, (READ_AHB_REG(reg)|(mask))) + +#define WRITE_APB_REG(reg, val) __raw_writel(val, APB_REG_ADDR(reg)) +#define READ_APB_REG(reg) (__raw_readl(APB_REG_ADDR(reg))) +#define WRITE_APB_REG_BITS(reg, val, start, len) \ + WRITE_APB_REG(reg, (READ_APB_REG(reg) & ~(((1L<<(len))-1)<<(start)) )| ((unsigned)((val)&((1L<<(len))-1)) << (start))) +#define READ_APB_REG_BITS(reg, start, len) \ + ((READ_APB_REG(reg) >> (start)) & ((1L<<(len))-1)) +#define CLEAR_APB_REG_MASK(reg, mask) WRITE_APB_REG(reg, (READ_APB_REG(reg)&(~(mask)))) +#define SET_APB_REG_MASK(reg, mask) WRITE_APB_REG(reg, (READ_APB_REG(reg)|(mask))) + +#define WRITE_APB_HDMI_REG(reg, val) __raw_writel(val, APB_HDMI_REG_ADDR(reg)) +#define READ_APB_HDMI_REG(reg) (__raw_readl(APB_HDMI_REG_ADDR(reg))) +#define WRITE_APB_HDMI_REG_BITS(reg, val, start, len) \ + WRITE_APB_HDMI_REG(reg, (READ_APB_HDMI_REG(reg) & ~(((1L<<(len))-1)<<(start)) )| ((unsigned)((val)&((1L<<(len))-1)) << (start))) +#define READ_APB_HDMI_REG_BITS(reg, start, len) \ + ((READ_APB_HDMI_REG(reg) >> (start)) & ((1L<<(len))-1)) +#define CLEAR_APB_HDMI_REG_MASK(reg, mask) WRITE_APB_HDMI_REG(reg, (READ_APB_HDMI_REG(reg)&(~(mask)))) +#define SET_APB_HDMI_REG_MASK(reg, mask) WRITE_APB_HDMI_REG(reg, (READ_APB_HDMI_REG(reg)|(mask))) + +/* for back compatible alias */ +#define WRITE_MPEG_REG(reg, val) \ + WRITE_CBUS_REG(reg, val) +#define READ_MPEG_REG(reg) \ + READ_CBUS_REG(reg) +#define WRITE_MPEG_REG_BITS(reg, val, start, len) \ + WRITE_CBUS_REG_BITS(reg, val, start, len) +#define READ_MPEG_REG_BITS(reg, start, len) \ + READ_CBUS_REG_BITS(reg, start, len) +#define CLEAR_MPEG_REG_MASK(reg, mask) \ + CLEAR_CBUS_REG_MASK(reg, mask) +#define SET_MPEG_REG_MASK(reg, mask) \ + SET_CBUS_REG_MASK(reg, mask) +#endif + + +#endif
diff --git a/arch/arm/include/asm/arch-c1/mailbox.h b/arch/arm/include/asm/arch-c1/mailbox.h new file mode 100644 index 0000000..04ae20f --- /dev/null +++ b/arch/arm/include/asm/arch-c1/mailbox.h
@@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + + /* + * + * Copyright (C) 2012 Amlogic, Inc. + * + * Author: Platform-SH@amlogic.com + * + */ + +#ifndef __GXBB_MAILBOX_H_ +#define __GXBB_MAILBOX_H_ + +#define SCPI_CMD_SENSOR_VALUE 0x1C +#define SCPI_CMD_SET_USR_DATA 0x20 +#define SCPI_CMD_OPEN_SCP_LOG 0xC4 +#define SCPI_CMD_THERMAL_CALIB 0xC5 + +#define SCPI_CMD_USB_BOOT 0xB0 +#define SCPI_CMD_USB_UNBOOT 0xB1 +#define SCPI_CMD_SDCARD_BOOT 0xB2 +#define SCPI_CMD_CLEAR_BOOT 0xB3 + +#define SCPI_CMD_REV_PWM_DELT 0x42 + +#define LOW_PRIORITY 0 +#define HIGH_PRIORITY 1 + +#define P_SHARE_SRAM_BASE 0xfffa0000 +#define SRAM_SIZE 0x48000 +#define MHU_HIGH_SCP_TO_AP_PAYLOAD (SRAM_SIZE - 0xc00) +#define MHU_HIGH_AP_TO_SCP_PAYLOAD (MHU_HIGH_SCP_TO_AP_PAYLOAD + 0x200) +#define MHU_LOW_SCP_TO_AP_PAYLOAD (SRAM_SIZE - 0x1000) +#define MHU_LOW_AP_TO_SCP_PAYLOAD (MHU_LOW_SCP_TO_AP_PAYLOAD + 0x200) + +enum scpi_client_id { + SCPI_CL_NONE, + SCPI_CL_CLOCKS, + SCPI_CL_DVFS, + SCPI_CL_POWER, + SCPI_CL_THERMAL, + SCPI_CL_REMOTE, + SCPI_CL_LED_TIMER, + SCPI_MAX = 0xff, +}; + +enum scpi_error_codes { + SCPI_SUCCESS = 0, /* Success */ + SCPI_ERR_PARAM = 1, /* Invalid parameter(s) */ + SCPI_ERR_ALIGN = 2, /* Invalid alignment */ + SCPI_ERR_SIZE = 3, /* Invalid size */ + SCPI_ERR_HANDLER = 4, /* Invalid handler/callback */ + SCPI_ERR_ACCESS = 5, /* Invalid access/permission denied */ + SCPI_ERR_RANGE = 6, /* Value out of range */ + SCPI_ERR_TIMEOUT = 7, /* Timeout has occurred */ + SCPI_ERR_NOMEM = 8, /* Invalid memory area or pointer */ + SCPI_ERR_PWRSTATE = 9, /* Invalid power state */ + SCPI_ERR_SUPPORT = 10, /* Not supported or disabled */ + SCPI_ERR_DEVICE = 11, /* Device error */ + SCPI_ERR_MAX +}; + +void open_scp_log(unsigned int channel); +int thermal_calibration(unsigned int type, unsigned int data); +int thermal_get_value(unsigned int sensor_id, unsigned int *value); +int send_usr_data(unsigned int clinet_id, unsigned int *val, unsigned int size); +void send_pwm_delt(int32_t vcck_delt, int32_t ee_delt); + #endif
diff --git a/arch/arm/include/asm/arch-c1/mnPmuSramMsgBlock_ddr3.h b/arch/arm/include/asm/arch-c1/mnPmuSramMsgBlock_ddr3.h new file mode 100644 index 0000000..c067367 --- /dev/null +++ b/arch/arm/include/asm/arch-c1/mnPmuSramMsgBlock_ddr3.h
@@ -0,0 +1,637 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +/** \brief DDR3U_1D training firmware message block structure + * + * Please refer to the Training Firmware App Note for futher information about + * the usage for Message Block. + */ +typedef struct _PMU_SMB_DDR3U_1D_t { + uint8_t Reserved00; // Byte offset 0x00, CSR Addr 0x54000, Direction=In + // Reserved00[0:4] RFU, must be zero + // + // Reserved00[5] = Train vrefDAC0 During Read Deskew + // 0x1 = Read Deskew will begin by enabling and roughly training the phy’s per-lane reference voltages. Training the vrefDACs CSRs will increase the maximum 1D training time by around half a millisecond, but will improve 1D training accuracy on systems with significant voltage-offsets between lane read eyes. + // 0X0 = Read Deskew will assume the messageblock’s phyVref setting will work for all lanes. + // + // Reserved00[6] = Enable High Effort WrDQ1D + // 0x1 = WrDQ1D will conditionally retry training at several extra RxClkDly Timings. This will increase the maximum 1D training time by up to 4 extra iterations of WrDQ1D. This is only required in systems that suffer from very large, asymmetric eye-collapse when receiving PRBS patterns. + // 0x0 = WrDQ1D assume rxClkDly values found by SI Friendly RdDqs1D will work for receiving PRBS patterns + // + // Reserved00[7] = Optimize for the special hard macros in TSMC28. + // 0x1 = set if the phy being trained was manufactured in any TSMC28 process node. + // 0x0 = otherwise, when not training a TSMC28 phy, leave this field as 0. + uint8_t MsgMisc; // Byte offset 0x01, CSR Addr 0x54000, Direction=In + // Contains various global options for training. + // + // Bit fields: + // + // MsgMisc[0] = MTESTEnable + // 0x1 = Pulse primary digital test output bump at the end of each major training stage. This enables observation of training stage completion by observing the digital test output. + // 0x0 = Do not pulse primary digital test output bump + // + // MsgMisc[1] = SimulationOnlyReset + // 0x1 = Verilog only simulation option to shorten duration of DRAM reset pulse length to 1ns. + // Must never be set to 1 in silicon. + // 0x0 = Use reset pulse length specifed by JEDEC standard + // + // MsgMisc[2] = SimulationOnlyTraining + // 0x1 = Verilog only simulation option to shorten the duration of the training steps by performing fewer iterations. + // Must never be set to 1 in silicon. + // 0x0 = Use standard training duration. + // + // MsgMisc[3] = RFU, must be zero (DDR4 UDIMM and RDIMM only, otherwise RFU, must be zero) + // + // + // + // MsgMisc[4] = Suppress streaming messages, including assertions, regardless of HdtCtrl setting. + // Stage Completion messages, as well as training completion and error messages are + // Still sent depending on HdtCtrl setting. + // + // MsgMisc[5] = PerByteMaxRdLat + // 0x1 = Each DBYTE will return dfi_rddata_valid at the lowest possible latency. This may result in unaligned data between bytes to be returned to the DFI. + // 0x0 = Every DBYTE will return dfi_rddata_valid simultaneously. This will ensure that data bytes will return aligned accesses to the DFI. + // + // MsgMisc[6] = PartialRank (DDR3 UDIMM and DDR4 UDIMM only, otherwise RFU, must be zero) + // 0x1 = Support rank populated with a subset of byte, but where even-odd pair of rank support all the byte + // 0x0 = All rank populated with all the byte (tyical configuration) + // + // MsgMisc[7] RFU, must be zero + // + // Notes: + // + // - SimulationOnlyReset and SimulationOnlyTraining can be used to speed up simulation run times, and must never be used in real silicon. Some VIPs may have checks on DRAM reset parameters that may need to be disabled when using SimulationOnlyReset. + uint16_t PmuRevision; // Byte offset 0x02, CSR Addr 0x54001, Direction=Out + // PMU firmware revision ID + // After training is run, this address will contain the revision ID of the firmware. + // Please reference this revision ID when filing support cases with Synopsys. + uint8_t Pstate; // Byte offset 0x04, CSR Addr 0x54002, Direction=In + // Must be set to the target Pstate to be trained + // 0x0 = Pstate 0 + // 0x1 = Pstate 1 + // 0x2 = Pstate 2 + // 0x3 = Pstate 3 + // All other encodings are reserved + uint8_t PllBypassEn; // Byte offset 0x05, CSR Addr 0x54002, Direction=In + // Set according to whether target Pstate uses PHY PLL bypass + // 0x0 = PHY PLL is enabled for target Pstate + // 0x1 = PHY PLL is bypassed for target Pstate + uint16_t DRAMFreq; // Byte offset 0x06, CSR Addr 0x54003, Direction=In + // DDR data rate for the target Pstate in units of MT/s. + // For example enter 0x0640 for DDR1600. + uint8_t DfiFreqRatio; // Byte offset 0x08, CSR Addr 0x54004, Direction=In + // Frequency ratio betwen DfiCtlClk and SDRAM memclk. + // 0x1 = 1:1 + // 0x2 = 1:2 + // 0x4 = 1:4 + uint8_t BPZNResVal ; // Byte offset 0x09, CSR Addr 0x54004, Direction=In + // Must be programmed to match the precision resistor connected to Phy BP_ZN + // 0x00 = Do not program. Use current CSR value. + // 0xf0 = 240 Ohm (recommended value) + // 0x78 = 120 Ohm + // 0x28 = 40 Ohm + // All other values are reserved. + // + uint8_t PhyOdtImpedance; // Byte offset 0x0a, CSR Addr 0x54005, Direction=In + // Must be programmed to the termination impedance in ohms used by PHY during reads. + // + // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start) + // + // See PHY databook for legal termination impedance values. + // + // For digital simulation, any legal value can be used. For silicon, the users must determine the correct value through SI simulation or other methods. + uint8_t PhyDrvImpedance; // Byte offset 0x0b, CSR Addr 0x54005, Direction=In + // Must be programmed to the driver impedance in ohms used by PHY during writes for all DBYTE drivers (DQ/DM/DBI/DQS). + // + // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start) + // + // See PHY databook for legal R_on driver impedance values. + // + // For digital simulation, any value can be used that is not Hi-Z. For silicon, the users must determine the correct value through SI simulation or other methods. + uint8_t PhyVref; // Byte offset 0x0c, CSR Addr 0x54006, Direction=In + // Must be programmed with the Vref level to be used by the PHY during reads + // + // The units of this field are a percentage of VDDQ according to the following equation: + // + // Receiver Vref = VDDQ*PhyVref[6:0]/128 + // + // For example to set Vref at 0.75*VDDQ, set this field to 0x60. + // + // For digital simulation, any legal value can be used. For silicon, the users must calculate the analytical Vref by using the impedances, terminations, and series resistance present in the system. + uint8_t DramType; // Byte offset 0x0d, CSR Addr 0x54006, Direction=In + // Module Type: + // 0x01 = DDR3 unbuffered + // 0x02 = Reserved + // 0x03 = Reserved + // 0x04 = Reserved + // 0x05 = Reserved + // + uint8_t DisabledDbyte; // Byte offset 0x0e, CSR Addr 0x54007, Direction=In + // Bitmap to indicate which Dbyte are not connected (for DByte 0 to 7): + // Set DisabledDbyte[i] to 1 only to specify that DByte i not need to be trained (DByte 8 can be disabled via EnabledDQs setting) + uint8_t EnabledDQs; // Byte offset 0x0f, CSR Addr 0x54007, Direction=In + // Total number of DQ bits enabled in PHY + uint8_t CsPresent; // Byte offset 0x10, CSR Addr 0x54008, Direction=In + // Indicates presence of DRAM at each chip select for PHY. Each bit corresponds to a logical CS. + // + // If the bit is set to 1, the CS is connected to DRAM. + // If the bit is set to 0, the CS is not connected to DRAM. + // + // CsPresent[0] = CS0 is populated with DRAM + // CsPresent[1] = CS1 is populated with DRAM + // CsPresent[2] = CS2 is populated with DRAM + // CsPresent[3] = CS3 is populated with DRAM + // CsPresent[7:4] = Reserved (must be programmed to 0) + // + // + uint8_t CsPresentD0; // Byte offset 0x11, CSR Addr 0x54008, Direction=In + // The CS signals from field CsPresent that are routed to DIMM connector 0 + uint8_t CsPresentD1; // Byte offset 0x12, CSR Addr 0x54009, Direction=In + // The CS signals from field CsPresent that are routed to DIMM connector 1 + uint8_t AddrMirror; // Byte offset 0x13, CSR Addr 0x54009, Direction=In + // Corresponds to CS[3:0] + // 1 = Address Mirror. + // 0 = No Address Mirror. + uint8_t CsTestFail; // Byte offset 0x14, CSR Addr 0x5400a, Direction=Out + // This field will be set if training fails on any rank. + // 0x0 = No failures + // non-zero = one or more ranks failed training + uint8_t PhyCfg; // Byte offset 0x15, CSR Addr 0x5400a, Direction=In + // Additional mode bits. + // + // Bit fields: + // [0] SlowAccessMode : + // 1 = 2T Address Timing. + // 0 = 1T Address Timing. + // [7-1] RFU, must be zero + uint16_t SequenceCtrl; // Byte offset 0x16, CSR Addr 0x5400b, Direction=In + // Controls the training steps to be run. Each bit corresponds to a training step. + // + // If the bit is set to 1, the training step will run. + // If the bit is set to 0, the training step will be skipped. + // + // Training step to bit mapping: + // SequenceCtrl[0] = Run DevInit - Device/phy initialization. Should always be set. + // SequenceCtrl[1] = Run WrLvl - Write leveling + // SequenceCtrl[2] = Run RxEn - Read gate training + // SequenceCtrl[3] = Run RdDQS1D - 1d read dqs training + // SequenceCtrl[4] = Run WrDQ1D - 1d write dq training + // SequenceCtrl[5] = RFU, must be zero + // SequenceCtrl[6] = RFU, must be zero + // SequenceCtrl[7] = RFU, must be zero + // SequenceCtrl[8] = Run RdDeskew - Per lane read dq deskew training + // SequenceCtrl[9] = Run MxRdLat - Max read latency training + // SequenceCtrl[10] = RFU, must be zero + // SequenceCtrl[11] = RFU, must be zero + // SequenceCtrl[12] = RFU, must be zero + // SequenceCtrl[13] = RFU, must be zero + // SequenceCtrl[15-14] = RFU, must be zero + uint8_t HdtCtrl; // Byte offset 0x18, CSR Addr 0x5400c, Direction=In + // To control the total number of debug messages, a verbosity subfield (HdtCtrl, Hardware Debug Trace Control) exists in the message block. Every message has a verbosity level associated with it, and as the HdtCtrl value is increased, less important s messages stop being sent through the mailboxes. The meanings of several major HdtCtrl thresholds are explained below: + // + // 0x05 = Detailed debug messages (e.g. Eye delays) + // 0x0A = Coarse debug messages (e.g. rank information) + // 0xC8 = Stage completion + // 0xC9 = Assertion messages + // 0xFF = Firmware completion messages only + // + // See Training App Note for more detailed information on what messages are included for each threshold. + // + uint8_t Reserved19; // Byte offset 0x19, CSR Addr 0x5400c, Direction=N/A + + + + + + + + + + + + + + + + + uint8_t Reserved1A; // Byte offset 0x1a, CSR Addr 0x5400d, Direction=N/A + + + + + + + + + + + + + + + + + + + + uint8_t Reserved1B; // Byte offset 0x1b, CSR Addr 0x5400d, Direction=N/A + + + + uint8_t Reserved1C; // Byte offset 0x1c, CSR Addr 0x5400e, Direction=N/A + + uint8_t Reserved1D; // Byte offset 0x1d, CSR Addr 0x5400e, Direction=N/A + + uint8_t Reserved1E; // Byte offset 0x1e, CSR Addr 0x5400f, Direction=In + // Input for constraining the range of vref(DQ) values training will collect data for, usually reducing training time. However, too large of a voltage range may cause longer 2D training times while too small of a voltage range may truncate passing regions. When in doubt, leave this field set to 0. + // Used by 2D training in: Rd2D, Wr2D + // + // Reserved1E[0-3]: Rd2D Voltage Range + // 0 = Training will search all phy vref(DQ) settings + // 1 = limit to +/-2 %VDDQ from phyVref + // 2 = limit to +/-4 %VDDQ from phyVref + // … + // 15 = limit to +/-30% VDDQ from phyVref + // + // Reserved1E[4-7]: Wr2D Voltage Range + // 0 = Training will search all dram vref(DQ) settings + // 1 = limit to +/-2 %VDDQ from MR6 + // 2 = limit to +/-4 %VDDQ from MR6 + // … + // 15 = limit to +/-30% VDDQ from MR6 + uint8_t Reserved1F; // Byte offset 0x1f, CSR Addr 0x5400f, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved20; // Byte offset 0x20, CSR Addr 0x54010, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved21; // Byte offset 0x21, CSR Addr 0x54010, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint16_t PhyConfigOverride; // Byte offset 0x22, CSR Addr 0x54011, Direction=In + // Override PhyConfig csr. + // 0x0: Use hardware csr value for PhyConfing (recommended) + // Other values: Use value for PhyConfig instead of Hardware value. + // + uint8_t DFIMRLMargin; // Byte offset 0x24, CSR Addr 0x54012, Direction=In + // Margin added to smallest passing trained DFI Max Read Latency value, in units of DFI clocks. Recommended to be >= 1. See the Training App Note for more details on the training process and the use of this value. + int8_t CDD_RR_3_2; // Byte offset 0x25, CSR Addr 0x54012, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 3 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_3_1; // Byte offset 0x26, CSR Addr 0x54013, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 3 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_3_0; // Byte offset 0x27, CSR Addr 0x54013, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 3 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_2_3; // Byte offset 0x28, CSR Addr 0x54014, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 2 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_2_1; // Byte offset 0x29, CSR Addr 0x54014, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 2 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_2_0; // Byte offset 0x2a, CSR Addr 0x54015, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 2 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_1_3; // Byte offset 0x2b, CSR Addr 0x54015, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 1 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_1_2; // Byte offset 0x2c, CSR Addr 0x54016, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 1 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_1_0; // Byte offset 0x2d, CSR Addr 0x54016, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 1 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_0_3; // Byte offset 0x2e, CSR Addr 0x54017, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 0 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_0_2; // Byte offset 0x2f, CSR Addr 0x54017, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 0 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_0_1; // Byte offset 0x30, CSR Addr 0x54018, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 0 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_3_2; // Byte offset 0x31, CSR Addr 0x54018, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 3 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_3_1; // Byte offset 0x32, CSR Addr 0x54019, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 3 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_3_0; // Byte offset 0x33, CSR Addr 0x54019, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 3 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_2_3; // Byte offset 0x34, CSR Addr 0x5401a, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 2 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_2_1; // Byte offset 0x35, CSR Addr 0x5401a, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 2 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_2_0; // Byte offset 0x36, CSR Addr 0x5401b, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 2 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_1_3; // Byte offset 0x37, CSR Addr 0x5401b, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 1 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_1_2; // Byte offset 0x38, CSR Addr 0x5401c, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 1 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_1_0; // Byte offset 0x39, CSR Addr 0x5401c, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 1 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_0_3; // Byte offset 0x3a, CSR Addr 0x5401d, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 0 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_0_2; // Byte offset 0x3b, CSR Addr 0x5401d, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 0 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_0_1; // Byte offset 0x3c, CSR Addr 0x5401e, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 0 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_3_3; // Byte offset 0x3d, CSR Addr 0x5401e, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 3 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_3_2; // Byte offset 0x3e, CSR Addr 0x5401f, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 3 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_3_1; // Byte offset 0x3f, CSR Addr 0x5401f, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 3 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_3_0; // Byte offset 0x40, CSR Addr 0x54020, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 3 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_2_3; // Byte offset 0x41, CSR Addr 0x54020, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 2 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_2_2; // Byte offset 0x42, CSR Addr 0x54021, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 2 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_2_1; // Byte offset 0x43, CSR Addr 0x54021, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 2 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_2_0; // Byte offset 0x44, CSR Addr 0x54022, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 2 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_1_3; // Byte offset 0x45, CSR Addr 0x54022, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_1_2; // Byte offset 0x46, CSR Addr 0x54023, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_1_1; // Byte offset 0x47, CSR Addr 0x54023, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_1_0; // Byte offset 0x48, CSR Addr 0x54024, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_0_3; // Byte offset 0x49, CSR Addr 0x54024, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 0 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_0_2; // Byte offset 0x4a, CSR Addr 0x54025, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 0 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_0_1; // Byte offset 0x4b, CSR Addr 0x54025, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 0 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_0_0; // Byte offset 0x4c, CSR Addr 0x54026, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 0 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_3_3; // Byte offset 0x4d, CSR Addr 0x54026, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 3 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_3_2; // Byte offset 0x4e, CSR Addr 0x54027, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 3 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_3_1; // Byte offset 0x4f, CSR Addr 0x54027, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 3 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_3_0; // Byte offset 0x50, CSR Addr 0x54028, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 3 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_2_3; // Byte offset 0x51, CSR Addr 0x54028, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 2 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_2_2; // Byte offset 0x52, CSR Addr 0x54029, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 2 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_2_1; // Byte offset 0x53, CSR Addr 0x54029, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 2 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_2_0; // Byte offset 0x54, CSR Addr 0x5402a, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 2 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_1_3; // Byte offset 0x55, CSR Addr 0x5402a, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_1_2; // Byte offset 0x56, CSR Addr 0x5402b, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_1_1; // Byte offset 0x57, CSR Addr 0x5402b, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_1_0; // Byte offset 0x58, CSR Addr 0x5402c, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_0_3; // Byte offset 0x59, CSR Addr 0x5402c, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_0_2; // Byte offset 0x5a, CSR Addr 0x5402d, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_0_1; // Byte offset 0x5b, CSR Addr 0x5402d, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_0_0; // Byte offset 0x5c, CSR Addr 0x5402e, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + uint8_t Reserved5D; // Byte offset 0x5d, CSR Addr 0x5402e, Direction=N/A + // This field is ignored if 0. If larger than 0, this value is used as is as the offset in fine-step applied at the end of DDR4 RxEnable training, instead of the default offset. + uint16_t MR0; // Byte offset 0x5e, CSR Addr 0x5402f, Direction=In + // Value of DDR mode register MR0 for all ranks for current pstate + uint16_t MR1; // Byte offset 0x60, CSR Addr 0x54030, Direction=In + // Value of DDR mode register MR1 for all ranks for current pstate + uint16_t MR2; // Byte offset 0x62, CSR Addr 0x54031, Direction=In + // Value of DDR mode register MR2 for all ranks for current pstate + uint8_t Reserved64; // Byte offset 0x64, CSR Addr 0x54032, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved65; // Byte offset 0x65, CSR Addr 0x54032, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved66; // Byte offset 0x66, CSR Addr 0x54033, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved67; // Byte offset 0x67, CSR Addr 0x54033, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved68; // Byte offset 0x68, CSR Addr 0x54034, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved69; // Byte offset 0x69, CSR Addr 0x54034, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved6A; // Byte offset 0x6a, CSR Addr 0x54035, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved6B; // Byte offset 0x6b, CSR Addr 0x54035, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved6C; // Byte offset 0x6c, CSR Addr 0x54036, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved6D; // Byte offset 0x6d, CSR Addr 0x54036, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved6E; // Byte offset 0x6e, CSR Addr 0x54037, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved6F; // Byte offset 0x6f, CSR Addr 0x54037, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved70; // Byte offset 0x70, CSR Addr 0x54038, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved71; // Byte offset 0x71, CSR Addr 0x54038, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved72; // Byte offset 0x72, CSR Addr 0x54039, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved73; // Byte offset 0x73, CSR Addr 0x54039, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t AcsmOdtCtrl0; // Byte offset 0x74, CSR Addr 0x5403a, Direction=In + // Odt pattern for accesses targeting rank 0. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl1; // Byte offset 0x75, CSR Addr 0x5403a, Direction=In + // Odt pattern for accesses targeting rank 1. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl2; // Byte offset 0x76, CSR Addr 0x5403b, Direction=In + // Odt pattern for accesses targeting rank 2. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl3; // Byte offset 0x77, CSR Addr 0x5403b, Direction=In + // Odt pattern for accesses targeting rank 3. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl4; // Byte offset 0x78, CSR Addr 0x5403c, Direction=In + // This field is reserved and must be programmed to 0x00. + uint8_t AcsmOdtCtrl5; // Byte offset 0x79, CSR Addr 0x5403c, Direction=In + // This field is reserved and must be programmed to 0x00. + uint8_t AcsmOdtCtrl6; // Byte offset 0x7a, CSR Addr 0x5403d, Direction=In + // This field is reserved and must be programmed to 0x00. + uint8_t AcsmOdtCtrl7; // Byte offset 0x7b, CSR Addr 0x5403d, Direction=In + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved7C; // Byte offset 0x7c, CSR Addr 0x5403e, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved7D; // Byte offset 0x7d, CSR Addr 0x5403e, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved7E; // Byte offset 0x7e, CSR Addr 0x5403f, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved7F; // Byte offset 0x7f, CSR Addr 0x5403f, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved80; // Byte offset 0x80, CSR Addr 0x54040, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved81; // Byte offset 0x81, CSR Addr 0x54040, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved82; // Byte offset 0x82, CSR Addr 0x54041, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved83; // Byte offset 0x83, CSR Addr 0x54041, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved84; // Byte offset 0x84, CSR Addr 0x54042, Direction=N/A + + uint8_t Reserved85; // Byte offset 0x85, CSR Addr 0x54042, Direction=N/A + + uint8_t Reserved86; // Byte offset 0x86, CSR Addr 0x54043, Direction=N/A + + uint8_t Reserved87; // Byte offset 0x87, CSR Addr 0x54043, Direction=N/A + + uint8_t Reserved88; // Byte offset 0x88, CSR Addr 0x54044, Direction=N/A + + uint8_t Reserved89; // Byte offset 0x89, CSR Addr 0x54044, Direction=N/A + + uint8_t Reserved8A; // Byte offset 0x8a, CSR Addr 0x54045, Direction=N/A + + uint8_t Reserved8B; // Byte offset 0x8b, CSR Addr 0x54045, Direction=N/A + + uint8_t Reserved8C; // Byte offset 0x8c, CSR Addr 0x54046, Direction=N/A + + uint8_t Reserved8D; // Byte offset 0x8d, CSR Addr 0x54046, Direction=N/A + + uint8_t Reserved8E; // Byte offset 0x8e, CSR Addr 0x54047, Direction=N/A + + uint8_t Reserved8F; // Byte offset 0x8f, CSR Addr 0x54047, Direction=N/A + + uint8_t Reserved90; // Byte offset 0x90, CSR Addr 0x54048, Direction=N/A + + uint8_t Reserved91; // Byte offset 0x91, CSR Addr 0x54048, Direction=N/A + + uint8_t Reserved92; // Byte offset 0x92, CSR Addr 0x54049, Direction=N/A + + uint8_t Reserved93; // Byte offset 0x93, CSR Addr 0x54049, Direction=N/A + + uint8_t Reserved94; // Byte offset 0x94, CSR Addr 0x5404a, Direction=N/A + + uint8_t Reserved95; // Byte offset 0x95, CSR Addr 0x5404a, Direction=N/A + + uint8_t Reserved96; // Byte offset 0x96, CSR Addr 0x5404b, Direction=N/A + + uint8_t Reserved97; // Byte offset 0x97, CSR Addr 0x5404b, Direction=N/A + + uint8_t Reserved98; // Byte offset 0x98, CSR Addr 0x5404c, Direction=N/A + + uint8_t Reserved99; // Byte offset 0x99, CSR Addr 0x5404c, Direction=N/A + + uint8_t Reserved9A; // Byte offset 0x9a, CSR Addr 0x5404d, Direction=N/A + + uint8_t Reserved9B; // Byte offset 0x9b, CSR Addr 0x5404d, Direction=N/A + + uint8_t Reserved9C; // Byte offset 0x9c, CSR Addr 0x5404e, Direction=N/A + + uint8_t Reserved9D; // Byte offset 0x9d, CSR Addr 0x5404e, Direction=N/A + + uint8_t Reserved9E; // Byte offset 0x9e, CSR Addr 0x5404f, Direction=N/A + + uint8_t Reserved9F; // Byte offset 0x9f, CSR Addr 0x5404f, Direction=N/A + + uint8_t ReservedA0; // Byte offset 0xa0, CSR Addr 0x54050, Direction=N/A + + uint8_t ReservedA1; // Byte offset 0xa1, CSR Addr 0x54050, Direction=N/A + + uint8_t ReservedA2; // Byte offset 0xa2, CSR Addr 0x54051, Direction=N/A + + uint8_t ReservedA3; // Byte offset 0xa3, CSR Addr 0x54051, Direction=N/A + +} __attribute__ ((packed)) PMU_SMB_DDR3U_1D_t;
diff --git a/arch/arm/include/asm/arch-c1/mnPmuSramMsgBlock_ddr4.h b/arch/arm/include/asm/arch-c1/mnPmuSramMsgBlock_ddr4.h new file mode 100644 index 0000000..6dfd4d0 --- /dev/null +++ b/arch/arm/include/asm/arch-c1/mnPmuSramMsgBlock_ddr4.h
@@ -0,0 +1,2380 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +/** \brief DDR4U_1D training firmware message block structure + * + * Please refer to the Training Firmware App Note for futher information about + * the usage for Message Block. + */ +typedef struct _PMU_SMB_DDR4U_1D_t { + uint8_t Reserved00; // Byte offset 0x00, CSR Addr 0x54000, Direction=In + // Reserved00[0:4] RFU, must be zero + // + // Reserved00[5] = Train vrefDAC0 During Read Deskew + // 0x1 = Read Deskew will begin by enabling and roughly training the phy’s per-lane reference voltages. Training the vrefDACs CSRs will increase the maximum 1D training time by around half a millisecond, but will improve 1D training accuracy on systems with significant voltage-offsets between lane read eyes. + // 0X0 = Read Deskew will assume the messageblock’s phyVref setting will work for all lanes. + // + // Reserved00[6] = Enable High Effort WrDQ1D + // 0x1 = WrDQ1D will conditionally retry training at several extra RxClkDly Timings. This will increase the maximum 1D training time by up to 4 extra iterations of WrDQ1D. This is only required in systems that suffer from very large, asymmetric eye-collapse when receiving PRBS patterns. + // 0x0 = WrDQ1D assume rxClkDly values found by SI Friendly RdDqs1D will work for receiving PRBS patterns + // + // Reserved00[7] = Optimize for the special hard macros in TSMC28. + // 0x1 = set if the phy being trained was manufactured in any TSMC28 process node. + // 0x0 = otherwise, when not training a TSMC28 phy, leave this field as 0. + uint8_t MsgMisc; // Byte offset 0x01, CSR Addr 0x54000, Direction=In + // Contains various global options for training. + // + // Bit fields: + // + // MsgMisc[0] = MTESTEnable + // 0x1 = Pulse primary digital test output bump at the end of each major training stage. This enables observation of training stage completion by observing the digital test output. + // 0x0 = Do not pulse primary digital test output bump + // + // MsgMisc[1] = SimulationOnlyReset + // 0x1 = Verilog only simulation option to shorten duration of DRAM reset pulse length to 1ns. + // Must never be set to 1 in silicon. + // 0x0 = Use reset pulse length specifed by JEDEC standard + // + // MsgMisc[2] = SimulationOnlyTraining + // 0x1 = Verilog only simulation option to shorten the duration of the training steps by performing fewer iterations. + // Must never be set to 1 in silicon. + // 0x0 = Use standard training duration. + // + // MsgMisc[3] = UseDdr4PerDeviceVrefDq (DDR4 UDIMM and RDIMM only, otherwise RFU, must be zero) + // 0x1 = Program user characterized Vref DQ values per DDR4 DRAM device. The message block VrefDqR*Nib* fields must be populated with the desired per device Vref DQs when using this option. Note: this option is not applicable in 2D training because these values are explicitly trained in 2D. + // 0x0 = Program Vref DQ for all DDR4 devices with the single value provided in MR6 message block field + // + // MsgMisc[4] = Suppress streaming messages, including assertions, regardless of HdtCtrl setting. + // Stage Completion messages, as well as training completion and error messages are + // Still sent depending on HdtCtrl setting. + // + // MsgMisc[5] = PerByteMaxRdLat + // 0x1 = Each DBYTE will return dfi_rddata_valid at the lowest possible latency. This may result in unaligned data between bytes to be returned to the DFI. + // 0x0 = Every DBYTE will return dfi_rddata_valid simultaneously. This will ensure that data bytes will return aligned accesses to the DFI. + // + // MsgMisc[6] = PartialRank (DDR3 UDIMM and DDR4 UDIMM only, otherwise RFU, must be zero) + // 0x1 = Support rank populated with a subset of byte, but where even-odd pair of rank support all the byte + // 0x0 = All rank populated with all the byte (tyical configuration) + // + // MsgMisc[7] RFU, must be zero + // + // Notes: + // + // - SimulationOnlyReset and SimulationOnlyTraining can be used to speed up simulation run times, and must never be used in real silicon. Some VIPs may have checks on DRAM reset parameters that may need to be disabled when using SimulationOnlyReset. + uint16_t PmuRevision; // Byte offset 0x02, CSR Addr 0x54001, Direction=Out + // PMU firmware revision ID + // After training is run, this address will contain the revision ID of the firmware. + // Please reference this revision ID when filing support cases with Synopsys. + uint8_t Pstate; // Byte offset 0x04, CSR Addr 0x54002, Direction=In + // Must be set to the target Pstate to be trained + // 0x0 = Pstate 0 + // 0x1 = Pstate 1 + // 0x2 = Pstate 2 + // 0x3 = Pstate 3 + // All other encodings are reserved + uint8_t PllBypassEn; // Byte offset 0x05, CSR Addr 0x54002, Direction=In + // Set according to whether target Pstate uses PHY PLL bypass + // 0x0 = PHY PLL is enabled for target Pstate + // 0x1 = PHY PLL is bypassed for target Pstate + uint16_t DRAMFreq; // Byte offset 0x06, CSR Addr 0x54003, Direction=In + // DDR data rate for the target Pstate in units of MT/s. + // For example enter 0x0640 for DDR1600. + uint8_t DfiFreqRatio; // Byte offset 0x08, CSR Addr 0x54004, Direction=In + // Frequency ratio betwen DfiCtlClk and SDRAM memclk. + // 0x1 = 1:1 + // 0x2 = 1:2 + // 0x4 = 1:4 + uint8_t BPZNResVal ; // Byte offset 0x09, CSR Addr 0x54004, Direction=In + // Must be programmed to match the precision resistor connected to Phy BP_ZN + // 0x00 = Do not program. Use current CSR value. + // 0xf0 = 240 Ohm (recommended value) + // 0x78 = 120 Ohm + // 0x28 = 40 Ohm + // All other values are reserved. + // + uint8_t PhyOdtImpedance; // Byte offset 0x0a, CSR Addr 0x54005, Direction=In + // Must be programmed to the termination impedance in ohms used by PHY during reads. + // + // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start) + // + // See PHY databook for legal termination impedance values. + // + // For digital simulation, any legal value can be used. For silicon, the users must determine the correct value through SI simulation or other methods. + uint8_t PhyDrvImpedance; // Byte offset 0x0b, CSR Addr 0x54005, Direction=In + // Must be programmed to the driver impedance in ohms used by PHY during writes for all DBYTE drivers (DQ/DM/DBI/DQS). + // + // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start) + // + // See PHY databook for legal R_on driver impedance values. + // + // For digital simulation, any value can be used that is not Hi-Z. For silicon, the users must determine the correct value through SI simulation or other methods. + uint8_t PhyVref; // Byte offset 0x0c, CSR Addr 0x54006, Direction=In + // Must be programmed with the Vref level to be used by the PHY during reads + // + // The units of this field are a percentage of VDDQ according to the following equation: + // + // Receiver Vref = VDDQ*PhyVref[6:0]/128 + // + // For example to set Vref at 0.75*VDDQ, set this field to 0x60. + // + // For digital simulation, any legal value can be used. For silicon, the users must calculate the analytical Vref by using the impedances, terminations, and series resistance present in the system. + uint8_t DramType; // Byte offset 0x0d, CSR Addr 0x54006, Direction=In + // Module Type: + // 0x01 = Reserved + // 0x02 = DDR4 unbuffered + // 0x03 = Reserved + // 0x04 = Reserved + // 0x05 = Reserved + // + uint8_t DisabledDbyte; // Byte offset 0x0e, CSR Addr 0x54007, Direction=In + // Bitmap to indicate which Dbyte are not connected (for DByte 0 to 7): + // Set DisabledDbyte[i] to 1 only to specify that DByte i not need to be trained (DByte 8 can be disabled via EnabledDQs setting) + uint8_t EnabledDQs; // Byte offset 0x0f, CSR Addr 0x54007, Direction=In + // Total number of DQ bits enabled in PHY + uint8_t CsPresent; // Byte offset 0x10, CSR Addr 0x54008, Direction=In + // Indicates presence of DRAM at each chip select for PHY. Each bit corresponds to a logical CS. + // + // If the bit is set to 1, the CS is connected to DRAM. + // If the bit is set to 0, the CS is not connected to DRAM. + // + // CsPresent[0] = CS0 is populated with DRAM + // CsPresent[1] = CS1 is populated with DRAM + // CsPresent[2] = CS2 is populated with DRAM + // CsPresent[3] = CS3 is populated with DRAM + // CsPresent[7:4] = Reserved (must be programmed to 0) + // + // + uint8_t CsPresentD0; // Byte offset 0x11, CSR Addr 0x54008, Direction=In + // The CS signals from field CsPresent that are routed to DIMM connector 0 + uint8_t CsPresentD1; // Byte offset 0x12, CSR Addr 0x54009, Direction=In + // The CS signals from field CsPresent that are routed to DIMM connector 1 + uint8_t AddrMirror; // Byte offset 0x13, CSR Addr 0x54009, Direction=In + // Corresponds to CS[3:0] + // 1 = Address Mirror. + // 0 = No Address Mirror. + uint8_t CsTestFail; // Byte offset 0x14, CSR Addr 0x5400a, Direction=Out + // This field will be set if training fails on any rank. + // 0x0 = No failures + // non-zero = one or more ranks failed training + uint8_t PhyCfg; // Byte offset 0x15, CSR Addr 0x5400a, Direction=In + // Additional mode bits. + // + // Bit fields: + // [0] SlowAccessMode : + // 1 = 2T Address Timing. + // 0 = 1T Address Timing. + // [7-1] RFU, must be zero + uint16_t SequenceCtrl; // Byte offset 0x16, CSR Addr 0x5400b, Direction=In + // Controls the training steps to be run. Each bit corresponds to a training step. + // + // If the bit is set to 1, the training step will run. + // If the bit is set to 0, the training step will be skipped. + // + // Training step to bit mapping: + // SequenceCtrl[0] = Run DevInit - Device/phy initialization. Should always be set. + // SequenceCtrl[1] = Run WrLvl - Write leveling + // SequenceCtrl[2] = Run RxEn - Read gate training + // SequenceCtrl[3] = Run RdDQS1D - 1d read dqs training + // SequenceCtrl[4] = Run WrDQ1D - 1d write dq training + // SequenceCtrl[5] = RFU, must be zero + // SequenceCtrl[6] = RFU, must be zero + // SequenceCtrl[7] = RFU, must be zero + // SequenceCtrl[8] = Run RdDeskew - Per lane read dq deskew training + // SequenceCtrl[9] = Run MxRdLat - Max read latency training + // SequenceCtrl[10] = Run Reserved + // SequenceCtrl[11] = Run Reserved + // SequenceCtrl[12] = Run Reserved + // SequenceCtrl[13] = Run Reserved + // SequenceCtrl[15-14] = RFU, must be zero + uint8_t HdtCtrl; // Byte offset 0x18, CSR Addr 0x5400c, Direction=In + // To control the total number of debug messages, a verbosity subfield (HdtCtrl, Hardware Debug Trace Control) exists in the message block. Every message has a verbosity level associated with it, and as the HdtCtrl value is increased, less important s messages stop being sent through the mailboxes. The meanings of several major HdtCtrl thresholds are explained below: + // + // 0x05 = Detailed debug messages (e.g. Eye delays) + // 0x0A = Coarse debug messages (e.g. rank information) + // 0xC8 = Stage completion + // 0xC9 = Assertion messages + // 0xFF = Firmware completion messages only + // + // See Training App Note for more detailed information on what messages are included for each threshold. + // + uint8_t Reserved19; // Byte offset 0x19, CSR Addr 0x5400c, Direction=N/A + + + + + + + + + + + + + + + + + uint8_t Reserved1A; // Byte offset 0x1a, CSR Addr 0x5400d, Direction=N/A + + + + + + + + + + + + + + + + + + + + uint8_t Reserved1B; // Byte offset 0x1b, CSR Addr 0x5400d, Direction=N/A + + + + uint8_t Reserved1C; // Byte offset 0x1c, CSR Addr 0x5400e, Direction=N/A + + uint8_t Reserved1D; // Byte offset 0x1d, CSR Addr 0x5400e, Direction=N/A + + uint8_t Reserved1E; // Byte offset 0x1e, CSR Addr 0x5400f, Direction=In + // Input for constraining the range of vref(DQ) values training will collect data for, usually reducing training time. However, too large of a voltage range may cause longer 2D training times while too small of a voltage range may truncate passing regions. When in doubt, leave this field set to 0. + // Used by 2D training in: Rd2D, Wr2D + // + // Reserved1E[0-3]: Rd2D Voltage Range + // 0 = Training will search all phy vref(DQ) settings + // 1 = limit to +/-2 %VDDQ from phyVref + // 2 = limit to +/-4 %VDDQ from phyVref + // … + // 15 = limit to +/-30% VDDQ from phyVref + // + // Reserved1E[4-7]: Wr2D Voltage Range + // 0 = Training will search all dram vref(DQ) settings + // 1 = limit to +/-2 %VDDQ from MR6 + // 2 = limit to +/-4 %VDDQ from MR6 + // … + // 15 = limit to +/-30% VDDQ from MR6 + uint8_t Reserved1F; // Byte offset 0x1f, CSR Addr 0x5400f, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved20; // Byte offset 0x20, CSR Addr 0x54010, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved21; // Byte offset 0x21, CSR Addr 0x54010, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint16_t PhyConfigOverride; // Byte offset 0x22, CSR Addr 0x54011, Direction=In + // Override PhyConfig csr. + // 0x0: Use hardware csr value for PhyConfing (recommended) + // Other values: Use value for PhyConfig instead of Hardware value. + // + uint8_t DFIMRLMargin; // Byte offset 0x24, CSR Addr 0x54012, Direction=In + // Margin added to smallest passing trained DFI Max Read Latency value, in units of DFI clocks. Recommended to be >= 1. See the Training App Note for more details on the training process and the use of this value. + int8_t CDD_RR_3_2; // Byte offset 0x25, CSR Addr 0x54012, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 3 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_3_1; // Byte offset 0x26, CSR Addr 0x54013, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 3 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_3_0; // Byte offset 0x27, CSR Addr 0x54013, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 3 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_2_3; // Byte offset 0x28, CSR Addr 0x54014, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 2 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_2_1; // Byte offset 0x29, CSR Addr 0x54014, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 2 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_2_0; // Byte offset 0x2a, CSR Addr 0x54015, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 2 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_1_3; // Byte offset 0x2b, CSR Addr 0x54015, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 1 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_1_2; // Byte offset 0x2c, CSR Addr 0x54016, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 1 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_1_0; // Byte offset 0x2d, CSR Addr 0x54016, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 1 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_0_3; // Byte offset 0x2e, CSR Addr 0x54017, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 0 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_0_2; // Byte offset 0x2f, CSR Addr 0x54017, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 0 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_0_1; // Byte offset 0x30, CSR Addr 0x54018, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 0 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_3_2; // Byte offset 0x31, CSR Addr 0x54018, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 3 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_3_1; // Byte offset 0x32, CSR Addr 0x54019, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 3 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_3_0; // Byte offset 0x33, CSR Addr 0x54019, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 3 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_2_3; // Byte offset 0x34, CSR Addr 0x5401a, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 2 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_2_1; // Byte offset 0x35, CSR Addr 0x5401a, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 2 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_2_0; // Byte offset 0x36, CSR Addr 0x5401b, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 2 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_1_3; // Byte offset 0x37, CSR Addr 0x5401b, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 1 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_1_2; // Byte offset 0x38, CSR Addr 0x5401c, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 1 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_1_0; // Byte offset 0x39, CSR Addr 0x5401c, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 1 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_0_3; // Byte offset 0x3a, CSR Addr 0x5401d, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 0 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_0_2; // Byte offset 0x3b, CSR Addr 0x5401d, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 0 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_0_1; // Byte offset 0x3c, CSR Addr 0x5401e, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 0 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_3_3; // Byte offset 0x3d, CSR Addr 0x5401e, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 3 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_3_2; // Byte offset 0x3e, CSR Addr 0x5401f, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 3 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_3_1; // Byte offset 0x3f, CSR Addr 0x5401f, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 3 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_3_0; // Byte offset 0x40, CSR Addr 0x54020, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 3 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_2_3; // Byte offset 0x41, CSR Addr 0x54020, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 2 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_2_2; // Byte offset 0x42, CSR Addr 0x54021, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 2 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_2_1; // Byte offset 0x43, CSR Addr 0x54021, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 2 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_2_0; // Byte offset 0x44, CSR Addr 0x54022, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 2 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_1_3; // Byte offset 0x45, CSR Addr 0x54022, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_1_2; // Byte offset 0x46, CSR Addr 0x54023, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_1_1; // Byte offset 0x47, CSR Addr 0x54023, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_1_0; // Byte offset 0x48, CSR Addr 0x54024, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_0_3; // Byte offset 0x49, CSR Addr 0x54024, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 0 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_0_2; // Byte offset 0x4a, CSR Addr 0x54025, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 0 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_0_1; // Byte offset 0x4b, CSR Addr 0x54025, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 0 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_0_0; // Byte offset 0x4c, CSR Addr 0x54026, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 0 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_3_3; // Byte offset 0x4d, CSR Addr 0x54026, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 3 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_3_2; // Byte offset 0x4e, CSR Addr 0x54027, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 3 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_3_1; // Byte offset 0x4f, CSR Addr 0x54027, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 3 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_3_0; // Byte offset 0x50, CSR Addr 0x54028, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 3 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_2_3; // Byte offset 0x51, CSR Addr 0x54028, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 2 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_2_2; // Byte offset 0x52, CSR Addr 0x54029, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 2 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_2_1; // Byte offset 0x53, CSR Addr 0x54029, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 2 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_2_0; // Byte offset 0x54, CSR Addr 0x5402a, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 2 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_1_3; // Byte offset 0x55, CSR Addr 0x5402a, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_1_2; // Byte offset 0x56, CSR Addr 0x5402b, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_1_1; // Byte offset 0x57, CSR Addr 0x5402b, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_1_0; // Byte offset 0x58, CSR Addr 0x5402c, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_0_3; // Byte offset 0x59, CSR Addr 0x5402c, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_0_2; // Byte offset 0x5a, CSR Addr 0x5402d, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_0_1; // Byte offset 0x5b, CSR Addr 0x5402d, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_0_0; // Byte offset 0x5c, CSR Addr 0x5402e, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + uint8_t Reserved5D; // Byte offset 0x5d, CSR Addr 0x5402e, Direction=N/A + // This field is ignored if 0. If larger than 0, this value is used as is as the offset in fine-step applied at the end of DDR4 RxEnable training, instead of the default offset. + uint16_t MR0; // Byte offset 0x5e, CSR Addr 0x5402f, Direction=In + // Value of DDR mode register MR0 for all ranks for current pstate + uint16_t MR1; // Byte offset 0x60, CSR Addr 0x54030, Direction=In + // Value of DDR mode register MR1 for all ranks for current pstate + uint16_t MR2; // Byte offset 0x62, CSR Addr 0x54031, Direction=In + // Value of DDR mode register MR2 for all ranks for current pstate + uint16_t MR3; // Byte offset 0x64, CSR Addr 0x54032, Direction=In + // Value of DDR mode register MR3 for all ranks for current pstate + uint16_t MR4; // Byte offset 0x66, CSR Addr 0x54033, Direction=In + // Value of DDR mode register MR4 for all ranks for current pstate + uint16_t MR5; // Byte offset 0x68, CSR Addr 0x54034, Direction=In + // Value of DDR mode register MR5 for all ranks for current pstate + uint16_t MR6; // Byte offset 0x6a, CSR Addr 0x54035, Direction=In + // Value of DDR mode register MR6 for all ranks for current pstate. Note: The initial VrefDq value and range must be set in A6:A0. + uint8_t X16Present; // Byte offset 0x6c, CSR Addr 0x54036, Direction=In + // X16 device map. Corresponds to CS[3:0]. + // X16Present[0] = CS0 is populated with X16 devices + // X16Present[1] = CS1 is populated with X16 devices + // X16Present[2] = CS2 is populated with X16 devices + // X16Present[3] = CS3 is populated with X16 devices + // X16Present[7:4] = Reserved (must be programmed to 0) + // + // Ranks may not contain mixed device types. + uint8_t CsSetupGDDec; // Byte offset 0x6d, CSR Addr 0x54036, Direction=In + // controls timing of chip select signals when DDR4 gear-down mode is active + // 0 - Leave delay of chip select timing group signal the same both before and after gear-down sync occurs + // 1 - Add 1UI of delay to chip select timing group signals when geardown-mode is active. This allows CS signals to have equal setup and hold time in gear-down mode + uint16_t RTT_NOM_WR_PARK0; // Byte offset 0x6e, CSR Addr 0x54037, Direction=In + // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 0 DRAM: + // RTT_NOM_WR_PARK0[0] = 1: Option is enable (otherwise, remaining bit fields are don't care) + // RTT_NOM_WR_PARK0[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 0 + // RTT_NOM_WR_PARK0[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 0 + // RTT_NOM_WR_PARK0[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 0 + uint16_t RTT_NOM_WR_PARK1; // Byte offset 0x70, CSR Addr 0x54038, Direction=In + // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 1 DRAM: + // RTT_NOM_WR_PARK1[0] = 1: Option is enable (otherwise, remaining bit fields are don't care) + // RTT_NOM_WR_PARK1[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 1 + // RTT_NOM_WR_PARK1[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 1 + // RTT_NOM_WR_PARK1[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 1 + uint16_t RTT_NOM_WR_PARK2; // Byte offset 0x72, CSR Addr 0x54039, Direction=In + // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 2 DRAM: + // RTT_NOM_WR_PARK2[0] = 1: Option is enable (otherwise, remaining bit fields are don't care) + // RTT_NOM_WR_PARK2[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 2 + // RTT_NOM_WR_PARK2[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 2 + // RTT_NOM_WR_PARK2[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 2 + uint16_t RTT_NOM_WR_PARK3; // Byte offset 0x74, CSR Addr 0x5403a, Direction=In + // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 3 DRAM: + // RTT_NOM_WR_PARK3[0] = 1: Option is enable (otherwise, remaining bit fields are don't care) + // RTT_NOM_WR_PARK3[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 3 + // RTT_NOM_WR_PARK3[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 3 + // RTT_NOM_WR_PARK3[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 3 + uint16_t RTT_NOM_WR_PARK4; // Byte offset 0x76, CSR Addr 0x5403b, Direction=In + // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 4 DRAM: + // RTT_NOM_WR_PARK4[0] = 1: Option is enable (otherwise, remaining bit fields are don't care) + // RTT_NOM_WR_PARK4[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 4 + // RTT_NOM_WR_PARK4[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 4 + // RTT_NOM_WR_PARK4[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 4 + uint16_t RTT_NOM_WR_PARK5; // Byte offset 0x78, CSR Addr 0x5403c, Direction=In + // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 5 DRAM: + // RTT_NOM_WR_PARK5[0] = 1: Option is enable (otherwise, remaining bit fields are don't care) + // RTT_NOM_WR_PARK5[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 5 + // RTT_NOM_WR_PARK5[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 5 + // RTT_NOM_WR_PARK5[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 5 + uint16_t RTT_NOM_WR_PARK6; // Byte offset 0x7a, CSR Addr 0x5403d, Direction=In + // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 6 DRAM: + // RTT_NOM_WR_PARK6[0] = 1: Option is enable (otherwise, remaining bit fields are don't care) + // RTT_NOM_WR_PARK6[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 6 + // RTT_NOM_WR_PARK6[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 6 + // RTT_NOM_WR_PARK6[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 6 + uint16_t RTT_NOM_WR_PARK7; // Byte offset 0x7c, CSR Addr 0x5403e, Direction=In + // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 7 DRAM: + // RTT_NOM_WR_PARK7[0] = 1: Option is enable (otherwise, remaining bit fields are don't care) + // RTT_NOM_WR_PARK7[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 7 + // RTT_NOM_WR_PARK7[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 7 + // RTT_NOM_WR_PARK7[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 7 + uint8_t AcsmOdtCtrl0; // Byte offset 0x7e, CSR Addr 0x5403f, Direction=In + // Odt pattern for accesses targeting rank 0. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl1; // Byte offset 0x7f, CSR Addr 0x5403f, Direction=In + // Odt pattern for accesses targeting rank 1. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl2; // Byte offset 0x80, CSR Addr 0x54040, Direction=In + // Odt pattern for accesses targeting rank 2. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl3; // Byte offset 0x81, CSR Addr 0x54040, Direction=In + // Odt pattern for accesses targeting rank 3. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl4; // Byte offset 0x82, CSR Addr 0x54041, Direction=In + // Odt pattern for accesses targeting rank 4. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl5; // Byte offset 0x83, CSR Addr 0x54041, Direction=In + // Odt pattern for accesses targeting rank 5. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl6; // Byte offset 0x84, CSR Addr 0x54042, Direction=In + // Odt pattern for accesses targeting rank 6. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl7; // Byte offset 0x85, CSR Addr 0x54042, Direction=In + // Odt pattern for accesses targeting rank 7. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t VrefDqR0Nib0; // Byte offset 0x86, CSR Addr 0x54043, Direction=InOut + // VrefDq for rank 0 nibble 0. Specifies MR6[6:0] + uint8_t VrefDqR0Nib1; // Byte offset 0x87, CSR Addr 0x54043, Direction=InOut + // VrefDq for rank 0 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR0Nib0 for x8 or x16 devices. + uint8_t VrefDqR0Nib2; // Byte offset 0x88, CSR Addr 0x54044, Direction=InOut + // VrefDq for rank 0 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR0Nib0 for x16 devices. + uint8_t VrefDqR0Nib3; // Byte offset 0x89, CSR Addr 0x54044, Direction=InOut + // VrefDq for rank 0 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR0Nib0 for x16 devices, or VrefDqR0Nib2 for x8 devices. + uint8_t VrefDqR0Nib4; // Byte offset 0x8a, CSR Addr 0x54045, Direction=InOut + // VrefDq for rank 0 nibble 4. Specifies MR6[6:0] + uint8_t VrefDqR0Nib5; // Byte offset 0x8b, CSR Addr 0x54045, Direction=InOut + // VrefDq for rank 0 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR0Nib4 for x8 or x16 devices. + uint8_t VrefDqR0Nib6; // Byte offset 0x8c, CSR Addr 0x54046, Direction=InOut + // VrefDq for rank 0 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR0Nib4 for x16 devices. + uint8_t VrefDqR0Nib7; // Byte offset 0x8d, CSR Addr 0x54046, Direction=InOut + // VrefDq for rank 0 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR0Nib4 for x16 devices, or VrefDqR0Nib6 for x8 devices. + uint8_t VrefDqR0Nib8; // Byte offset 0x8e, CSR Addr 0x54047, Direction=InOut + // VrefDq for rank 0 nibble 8. Specifies MR6[6:0] + uint8_t VrefDqR0Nib9; // Byte offset 0x8f, CSR Addr 0x54047, Direction=InOut + // VrefDq for rank 0 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR0Nib8 for x8 or x16 devices. + uint8_t VrefDqR0Nib10; // Byte offset 0x90, CSR Addr 0x54048, Direction=InOut + // VrefDq for rank 0 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR0Nib8 for x16 devices. + uint8_t VrefDqR0Nib11; // Byte offset 0x91, CSR Addr 0x54048, Direction=InOut + // VrefDq for rank 0 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR0Nib8 for x16 devices, or VrefDqR0Nib10 for x8 devices. + uint8_t VrefDqR0Nib12; // Byte offset 0x92, CSR Addr 0x54049, Direction=InOut + // VrefDq for rank 0 nibble 12. Specifies MR6[6:0] + uint8_t VrefDqR0Nib13; // Byte offset 0x93, CSR Addr 0x54049, Direction=InOut + // VrefDq for rank 0 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR0Nib12 for x8 or x16 devices. + uint8_t VrefDqR0Nib14; // Byte offset 0x94, CSR Addr 0x5404a, Direction=InOut + // VrefDq for rank 0 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR0Nib12 for x16 devices. + uint8_t VrefDqR0Nib15; // Byte offset 0x95, CSR Addr 0x5404a, Direction=InOut + // VrefDq for rank 0 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR0Nib12 for x16 devices, or VrefDqR0Nib14 for x8 devices. + uint8_t VrefDqR0Nib16; // Byte offset 0x96, CSR Addr 0x5404b, Direction=InOut + // VrefDq for rank 0 nibble 16. Specifies MR6[6:0] + uint8_t VrefDqR0Nib17; // Byte offset 0x97, CSR Addr 0x5404b, Direction=InOut + // VrefDq for rank 0 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR0Nib16 for x8 or x16 devices. + uint8_t VrefDqR0Nib18; // Byte offset 0x98, CSR Addr 0x5404c, Direction=InOut + // VrefDq for rank 0 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR0Nib16 for x16 devices. + uint8_t VrefDqR0Nib19; // Byte offset 0x99, CSR Addr 0x5404c, Direction=InOut + // VrefDq for rank 0 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR0Nib16 for x16 devices, or VrefDqR0Nib18 for x8 devices. + uint8_t VrefDqR1Nib0; // Byte offset 0x9a, CSR Addr 0x5404d, Direction=InOut + // VrefDq for rank 1 nibble 0. Specifies MR6[6:0] + uint8_t VrefDqR1Nib1; // Byte offset 0x9b, CSR Addr 0x5404d, Direction=InOut + // VrefDq for rank 1 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR1Nib0 for x8 or x16 devices. + uint8_t VrefDqR1Nib2; // Byte offset 0x9c, CSR Addr 0x5404e, Direction=InOut + // VrefDq for rank 1 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR1Nib0 for x16 devices. + uint8_t VrefDqR1Nib3; // Byte offset 0x9d, CSR Addr 0x5404e, Direction=InOut + // VrefDq for rank 1 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR1Nib0 for x16 devices, or VrefDqR1Nib2 for x8 devices. + uint8_t VrefDqR1Nib4; // Byte offset 0x9e, CSR Addr 0x5404f, Direction=InOut + // VrefDq for rank 1 nibble 4. Specifies MR6[6:0] + uint8_t VrefDqR1Nib5; // Byte offset 0x9f, CSR Addr 0x5404f, Direction=InOut + // VrefDq for rank 1 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR1Nib4 for x8 or x16 devices. + uint8_t VrefDqR1Nib6; // Byte offset 0xa0, CSR Addr 0x54050, Direction=InOut + // VrefDq for rank 1 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR1Nib4 for x16 devices. + uint8_t VrefDqR1Nib7; // Byte offset 0xa1, CSR Addr 0x54050, Direction=InOut + // VrefDq for rank 1 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR1Nib4 for x16 devices, or VrefDqR1Nib6 for x8 devices. + uint8_t VrefDqR1Nib8; // Byte offset 0xa2, CSR Addr 0x54051, Direction=InOut + // VrefDq for rank 1 nibble 8. Specifies MR6[6:0] + uint8_t VrefDqR1Nib9; // Byte offset 0xa3, CSR Addr 0x54051, Direction=InOut + // VrefDq for rank 1 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR1Nib8 for x8 or x16 devices. + uint8_t VrefDqR1Nib10; // Byte offset 0xa4, CSR Addr 0x54052, Direction=InOut + // VrefDq for rank 1 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR1Nib8 for x16 devices. + uint8_t VrefDqR1Nib11; // Byte offset 0xa5, CSR Addr 0x54052, Direction=InOut + // VrefDq for rank 1 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR1Nib8 for x16 devices, or VrefDqR1Nib10 for x8 devices. + uint8_t VrefDqR1Nib12; // Byte offset 0xa6, CSR Addr 0x54053, Direction=InOut + // VrefDq for rank 1 nibble 12. Specifies MR6[6:0] + uint8_t VrefDqR1Nib13; // Byte offset 0xa7, CSR Addr 0x54053, Direction=InOut + // VrefDq for rank 1 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR1Nib12 for x8 or x16 devices. + uint8_t VrefDqR1Nib14; // Byte offset 0xa8, CSR Addr 0x54054, Direction=InOut + // VrefDq for rank 1 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR1Nib12 for x16 devices. + uint8_t VrefDqR1Nib15; // Byte offset 0xa9, CSR Addr 0x54054, Direction=InOut + // VrefDq for rank 1 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR1Nib12 for x16 devices, or VrefDqR1Nib14 for x8 devices. + uint8_t VrefDqR1Nib16; // Byte offset 0xaa, CSR Addr 0x54055, Direction=InOut + // VrefDq for rank 1 nibble 16. Specifies MR6[6:0] + uint8_t VrefDqR1Nib17; // Byte offset 0xab, CSR Addr 0x54055, Direction=InOut + // VrefDq for rank 1 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR1Nib16 for x8 or x16 devices. + uint8_t VrefDqR1Nib18; // Byte offset 0xac, CSR Addr 0x54056, Direction=InOut + // VrefDq for rank 1 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR1Nib16 for x16 devices. + uint8_t VrefDqR1Nib19; // Byte offset 0xad, CSR Addr 0x54056, Direction=InOut + // VrefDq for rank 1 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR1Nib16 for x16 devices, or VrefDqR1Nib18 for x8 devices. + uint8_t VrefDqR2Nib0; // Byte offset 0xae, CSR Addr 0x54057, Direction=InOut + // VrefDq for rank 2 nibble 0. Specifies MR6[6:0] + uint8_t VrefDqR2Nib1; // Byte offset 0xaf, CSR Addr 0x54057, Direction=InOut + // VrefDq for rank 2 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR2Nib0 for x8 or x16 devices. + uint8_t VrefDqR2Nib2; // Byte offset 0xb0, CSR Addr 0x54058, Direction=InOut + // VrefDq for rank 2 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR2Nib0 for x16 devices. + uint8_t VrefDqR2Nib3; // Byte offset 0xb1, CSR Addr 0x54058, Direction=InOut + // VrefDq for rank 2 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR2Nib0 for x16 devices, or VrefDqR2Nib2 for x8 devices. + uint8_t VrefDqR2Nib4; // Byte offset 0xb2, CSR Addr 0x54059, Direction=InOut + // VrefDq for rank 2 nibble 4. Specifies MR6[6:0] + uint8_t VrefDqR2Nib5; // Byte offset 0xb3, CSR Addr 0x54059, Direction=InOut + // VrefDq for rank 2 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR2Nib4 for x8 or x16 devices. + uint8_t VrefDqR2Nib6; // Byte offset 0xb4, CSR Addr 0x5405a, Direction=InOut + // VrefDq for rank 2 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR2Nib4 for x16 devices. + uint8_t VrefDqR2Nib7; // Byte offset 0xb5, CSR Addr 0x5405a, Direction=InOut + // VrefDq for rank 2 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR2Nib4 for x16 devices, or VrefDqR2Nib6 for x8 devices. + uint8_t VrefDqR2Nib8; // Byte offset 0xb6, CSR Addr 0x5405b, Direction=InOut + // VrefDq for rank 2 nibble 8. Specifies MR6[6:0] + uint8_t VrefDqR2Nib9; // Byte offset 0xb7, CSR Addr 0x5405b, Direction=InOut + // VrefDq for rank 2 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR2Nib8 for x8 or x16 devices. + uint8_t VrefDqR2Nib10; // Byte offset 0xb8, CSR Addr 0x5405c, Direction=InOut + // VrefDq for rank 2 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR2Nib8 for x16 devices. + uint8_t VrefDqR2Nib11; // Byte offset 0xb9, CSR Addr 0x5405c, Direction=InOut + // VrefDq for rank 2 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR2Nib8 for x16 devices, or VrefDqR2Nib10 for x8 devices. + uint8_t VrefDqR2Nib12; // Byte offset 0xba, CSR Addr 0x5405d, Direction=InOut + // VrefDq for rank 2 nibble 12. Specifies MR6[6:0] + uint8_t VrefDqR2Nib13; // Byte offset 0xbb, CSR Addr 0x5405d, Direction=InOut + // VrefDq for rank 2 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR2Nib12 for x8 or x16 devices. + uint8_t VrefDqR2Nib14; // Byte offset 0xbc, CSR Addr 0x5405e, Direction=InOut + // VrefDq for rank 2 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR2Nib12 for x16 devices. + uint8_t VrefDqR2Nib15; // Byte offset 0xbd, CSR Addr 0x5405e, Direction=InOut + // VrefDq for rank 2 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR2Nib12 for x16 devices, or VrefDqR2Nib14 for x8 devices. + uint8_t VrefDqR2Nib16; // Byte offset 0xbe, CSR Addr 0x5405f, Direction=InOut + // VrefDq for rank 2 nibble 16. Specifies MR6[6:0] + uint8_t VrefDqR2Nib17; // Byte offset 0xbf, CSR Addr 0x5405f, Direction=InOut + // VrefDq for rank 2 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR2Nib16 for x8 or x16 devices. + uint8_t VrefDqR2Nib18; // Byte offset 0xc0, CSR Addr 0x54060, Direction=InOut + // VrefDq for rank 2 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR2Nib16 for x16 devices. + uint8_t VrefDqR2Nib19; // Byte offset 0xc1, CSR Addr 0x54060, Direction=InOut + // VrefDq for rank 2 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR2Nib16 for x16 devices, or VrefDqR2Nib18 for x8 devices. + uint8_t VrefDqR3Nib0; // Byte offset 0xc2, CSR Addr 0x54061, Direction=InOut + // VrefDq for rank 3 nibble 0. Specifies MR6[6:0] + uint8_t VrefDqR3Nib1; // Byte offset 0xc3, CSR Addr 0x54061, Direction=InOut + // VrefDq for rank 3 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR3Nib0 for x8 or x16 devices. + uint8_t VrefDqR3Nib2; // Byte offset 0xc4, CSR Addr 0x54062, Direction=InOut + // VrefDq for rank 3 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR3Nib0 for x16 devices. + uint8_t VrefDqR3Nib3; // Byte offset 0xc5, CSR Addr 0x54062, Direction=InOut + // VrefDq for rank 3 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR3Nib0 for x16 devices, or VrefDqR3Nib2 for x8 devices. + uint8_t VrefDqR3Nib4; // Byte offset 0xc6, CSR Addr 0x54063, Direction=InOut + // VrefDq for rank 3 nibble 4. Specifies MR6[6:0] + uint8_t VrefDqR3Nib5; // Byte offset 0xc7, CSR Addr 0x54063, Direction=InOut + // VrefDq for rank 3 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR3Nib4 for x8 or x16 devices. + uint8_t VrefDqR3Nib6; // Byte offset 0xc8, CSR Addr 0x54064, Direction=InOut + // VrefDq for rank 3 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR3Nib4 for x16 devices. + uint8_t VrefDqR3Nib7; // Byte offset 0xc9, CSR Addr 0x54064, Direction=InOut + // VrefDq for rank 3 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR3Nib4 for x16 devices, or VrefDqR3Nib6 for x8 devices. + uint8_t VrefDqR3Nib8; // Byte offset 0xca, CSR Addr 0x54065, Direction=InOut + // VrefDq for rank 3 nibble 8. Specifies MR6[6:0] + uint8_t VrefDqR3Nib9; // Byte offset 0xcb, CSR Addr 0x54065, Direction=InOut + // VrefDq for rank 3 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR3Nib8 for x8 or x16 devices. + uint8_t VrefDqR3Nib10; // Byte offset 0xcc, CSR Addr 0x54066, Direction=InOut + // VrefDq for rank 3 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR3Nib8 for x16 devices. + uint8_t VrefDqR3Nib11; // Byte offset 0xcd, CSR Addr 0x54066, Direction=InOut + // VrefDq for rank 3 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR3Nib8 for x16 devices, or VrefDqR3Nib10 for x8 devices. + uint8_t VrefDqR3Nib12; // Byte offset 0xce, CSR Addr 0x54067, Direction=InOut + // VrefDq for rank 3 nibble 12. Specifies MR6[6:0] + uint8_t VrefDqR3Nib13; // Byte offset 0xcf, CSR Addr 0x54067, Direction=InOut + // VrefDq for rank 3 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR3Nib12 for x8 or x16 devices. + uint8_t VrefDqR3Nib14; // Byte offset 0xd0, CSR Addr 0x54068, Direction=InOut + // VrefDq for rank 3 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR3Nib12 for x16 devices. + uint8_t VrefDqR3Nib15; // Byte offset 0xd1, CSR Addr 0x54068, Direction=InOut + // VrefDq for rank 3 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR3Nib12 for x16 devices, or VrefDqR3Nib14 for x8 devices. + uint8_t VrefDqR3Nib16; // Byte offset 0xd2, CSR Addr 0x54069, Direction=InOut + // VrefDq for rank 3 nibble 16. Specifies MR6[6:0] + uint8_t VrefDqR3Nib17; // Byte offset 0xd3, CSR Addr 0x54069, Direction=InOut + // VrefDq for rank 3 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR3Nib16 for x8 or x16 devices. + uint8_t VrefDqR3Nib18; // Byte offset 0xd4, CSR Addr 0x5406a, Direction=InOut + // VrefDq for rank 3 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR3Nib16 for x16 devices. + uint8_t VrefDqR3Nib19; // Byte offset 0xd5, CSR Addr 0x5406a, Direction=InOut + // VrefDq for rank 3 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR3Nib16 for x16 devices, or VrefDqR3Nib18 for x8 devices. + uint8_t ReservedD6; // Byte offset 0xd6, CSR Addr 0x5406b, Direction=N/A + + uint8_t ReservedD7; // Byte offset 0xd7, CSR Addr 0x5406b, Direction=N/A + + uint8_t ReservedD8; // Byte offset 0xd8, CSR Addr 0x5406c, Direction=N/A + + uint8_t ReservedD9; // Byte offset 0xd9, CSR Addr 0x5406c, Direction=N/A + + uint8_t ReservedDA; // Byte offset 0xda, CSR Addr 0x5406d, Direction=N/A + + uint8_t ReservedDB; // Byte offset 0xdb, CSR Addr 0x5406d, Direction=N/A + + uint8_t ReservedDC; // Byte offset 0xdc, CSR Addr 0x5406e, Direction=N/A + + uint8_t ReservedDD; // Byte offset 0xdd, CSR Addr 0x5406e, Direction=N/A + + uint8_t ReservedDE; // Byte offset 0xde, CSR Addr 0x5406f, Direction=N/A + + uint8_t ReservedDF; // Byte offset 0xdf, CSR Addr 0x5406f, Direction=N/A + + uint8_t ReservedE0; // Byte offset 0xe0, CSR Addr 0x54070, Direction=N/A + + uint8_t ReservedE1; // Byte offset 0xe1, CSR Addr 0x54070, Direction=N/A + + uint8_t ReservedE2; // Byte offset 0xe2, CSR Addr 0x54071, Direction=N/A + + uint8_t ReservedE3; // Byte offset 0xe3, CSR Addr 0x54071, Direction=N/A + + uint8_t ReservedE4; // Byte offset 0xe4, CSR Addr 0x54072, Direction=N/A + + uint8_t ReservedE5; // Byte offset 0xe5, CSR Addr 0x54072, Direction=N/A + + uint8_t ReservedE6; // Byte offset 0xe6, CSR Addr 0x54073, Direction=N/A + + uint8_t ReservedE7; // Byte offset 0xe7, CSR Addr 0x54073, Direction=N/A + + uint8_t ReservedE8; // Byte offset 0xe8, CSR Addr 0x54074, Direction=N/A + + uint8_t ReservedE9; // Byte offset 0xe9, CSR Addr 0x54074, Direction=N/A + + uint8_t ReservedEA; // Byte offset 0xea, CSR Addr 0x54075, Direction=N/A + + uint8_t ReservedEB; // Byte offset 0xeb, CSR Addr 0x54075, Direction=N/A + + uint8_t ReservedEC; // Byte offset 0xec, CSR Addr 0x54076, Direction=N/A + + uint8_t ReservedED; // Byte offset 0xed, CSR Addr 0x54076, Direction=N/A + + uint8_t ReservedEE; // Byte offset 0xee, CSR Addr 0x54077, Direction=N/A + + uint8_t ReservedEF; // Byte offset 0xef, CSR Addr 0x54077, Direction=N/A + + uint8_t ReservedF0; // Byte offset 0xf0, CSR Addr 0x54078, Direction=N/A + + uint8_t ReservedF1; // Byte offset 0xf1, CSR Addr 0x54078, Direction=N/A + + uint8_t ReservedF2; // Byte offset 0xf2, CSR Addr 0x54079, Direction=N/A + + uint8_t ReservedF3; // Byte offset 0xf3, CSR Addr 0x54079, Direction=N/A + + uint8_t ReservedF4; // Byte offset 0xf4, CSR Addr 0x5407a, Direction=N/A + + uint8_t ReservedF5; // Byte offset 0xf5, CSR Addr 0x5407a, Direction=N/A + + uint8_t ReservedF6; // Byte offset 0xf6, CSR Addr 0x5407b, Direction=N/A + + uint8_t ReservedF7; // Byte offset 0xf7, CSR Addr 0x5407b, Direction=N/A + + uint8_t ReservedF8; // Byte offset 0xf8, CSR Addr 0x5407c, Direction=N/A + + uint8_t ReservedF9; // Byte offset 0xf9, CSR Addr 0x5407c, Direction=N/A + + uint8_t ReservedFA; // Byte offset 0xfa, CSR Addr 0x5407d, Direction=N/A + + uint8_t ReservedFB; // Byte offset 0xfb, CSR Addr 0x5407d, Direction=N/A + + uint8_t ReservedFC; // Byte offset 0xfc, CSR Addr 0x5407e, Direction=N/A + + uint8_t ReservedFD; // Byte offset 0xfd, CSR Addr 0x5407e, Direction=N/A + + uint8_t ReservedFE; // Byte offset 0xfe, CSR Addr 0x5407f, Direction=N/A + + uint8_t ReservedFF; // Byte offset 0xff, CSR Addr 0x5407f, Direction=N/A + + uint8_t Reserved100; // Byte offset 0x100, CSR Addr 0x54080, Direction=N/A + + uint8_t Reserved101; // Byte offset 0x101, CSR Addr 0x54080, Direction=N/A + + uint8_t Reserved102; // Byte offset 0x102, CSR Addr 0x54081, Direction=N/A + + uint8_t Reserved103; // Byte offset 0x103, CSR Addr 0x54081, Direction=N/A + + uint8_t Reserved104; // Byte offset 0x104, CSR Addr 0x54082, Direction=N/A + + uint8_t Reserved105; // Byte offset 0x105, CSR Addr 0x54082, Direction=N/A + + uint8_t Reserved106; // Byte offset 0x106, CSR Addr 0x54083, Direction=N/A + + uint8_t Reserved107; // Byte offset 0x107, CSR Addr 0x54083, Direction=N/A + + uint8_t Reserved108; // Byte offset 0x108, CSR Addr 0x54084, Direction=N/A + + uint8_t Reserved109; // Byte offset 0x109, CSR Addr 0x54084, Direction=N/A + + uint8_t Reserved10A; // Byte offset 0x10a, CSR Addr 0x54085, Direction=N/A + + uint8_t Reserved10B; // Byte offset 0x10b, CSR Addr 0x54085, Direction=N/A + + uint8_t Reserved10C; // Byte offset 0x10c, CSR Addr 0x54086, Direction=N/A + + uint8_t Reserved10D; // Byte offset 0x10d, CSR Addr 0x54086, Direction=N/A + + uint8_t Reserved10E; // Byte offset 0x10e, CSR Addr 0x54087, Direction=N/A + + uint8_t Reserved10F; // Byte offset 0x10f, CSR Addr 0x54087, Direction=N/A + + uint8_t Reserved110; // Byte offset 0x110, CSR Addr 0x54088, Direction=N/A + + uint8_t Reserved111; // Byte offset 0x111, CSR Addr 0x54088, Direction=N/A + + uint8_t Reserved112; // Byte offset 0x112, CSR Addr 0x54089, Direction=N/A + + uint8_t Reserved113; // Byte offset 0x113, CSR Addr 0x54089, Direction=N/A + + uint8_t Reserved114; // Byte offset 0x114, CSR Addr 0x5408a, Direction=N/A + + uint8_t Reserved115; // Byte offset 0x115, CSR Addr 0x5408a, Direction=N/A + + uint8_t Reserved116; // Byte offset 0x116, CSR Addr 0x5408b, Direction=N/A + + uint8_t Reserved117; // Byte offset 0x117, CSR Addr 0x5408b, Direction=N/A + + uint8_t Reserved118; // Byte offset 0x118, CSR Addr 0x5408c, Direction=N/A + + uint8_t Reserved119; // Byte offset 0x119, CSR Addr 0x5408c, Direction=N/A + + uint8_t Reserved11A; // Byte offset 0x11a, CSR Addr 0x5408d, Direction=N/A + + uint8_t Reserved11B; // Byte offset 0x11b, CSR Addr 0x5408d, Direction=N/A + + uint8_t Reserved11C; // Byte offset 0x11c, CSR Addr 0x5408e, Direction=N/A + + uint8_t Reserved11D; // Byte offset 0x11d, CSR Addr 0x5408e, Direction=N/A + + uint8_t Reserved11E; // Byte offset 0x11e, CSR Addr 0x5408f, Direction=N/A + + uint8_t Reserved11F; // Byte offset 0x11f, CSR Addr 0x5408f, Direction=N/A + + uint8_t Reserved120; // Byte offset 0x120, CSR Addr 0x54090, Direction=N/A + + uint8_t Reserved121; // Byte offset 0x121, CSR Addr 0x54090, Direction=N/A + + uint8_t Reserved122; // Byte offset 0x122, CSR Addr 0x54091, Direction=N/A + + uint8_t Reserved123; // Byte offset 0x123, CSR Addr 0x54091, Direction=N/A + + uint8_t Reserved124; // Byte offset 0x124, CSR Addr 0x54092, Direction=N/A + + uint8_t Reserved125; // Byte offset 0x125, CSR Addr 0x54092, Direction=N/A + + uint8_t Reserved126; // Byte offset 0x126, CSR Addr 0x54093, Direction=N/A + + uint8_t Reserved127; // Byte offset 0x127, CSR Addr 0x54093, Direction=N/A + + uint8_t Reserved128; // Byte offset 0x128, CSR Addr 0x54094, Direction=N/A + + uint8_t Reserved129; // Byte offset 0x129, CSR Addr 0x54094, Direction=N/A + + uint8_t Reserved12A; // Byte offset 0x12a, CSR Addr 0x54095, Direction=N/A + + uint8_t Reserved12B; // Byte offset 0x12b, CSR Addr 0x54095, Direction=N/A + + uint8_t Reserved12C; // Byte offset 0x12c, CSR Addr 0x54096, Direction=N/A + + uint8_t Reserved12D; // Byte offset 0x12d, CSR Addr 0x54096, Direction=N/A + + uint8_t Reserved12E; // Byte offset 0x12e, CSR Addr 0x54097, Direction=N/A + + uint8_t Reserved12F; // Byte offset 0x12f, CSR Addr 0x54097, Direction=N/A + + uint8_t Reserved130; // Byte offset 0x130, CSR Addr 0x54098, Direction=N/A + + uint8_t Reserved131; // Byte offset 0x131, CSR Addr 0x54098, Direction=N/A + + uint8_t Reserved132; // Byte offset 0x132, CSR Addr 0x54099, Direction=N/A + + uint8_t Reserved133; // Byte offset 0x133, CSR Addr 0x54099, Direction=N/A + + uint8_t Reserved134; // Byte offset 0x134, CSR Addr 0x5409a, Direction=N/A + + uint8_t Reserved135; // Byte offset 0x135, CSR Addr 0x5409a, Direction=N/A + + uint8_t Reserved136; // Byte offset 0x136, CSR Addr 0x5409b, Direction=N/A + + uint8_t Reserved137; // Byte offset 0x137, CSR Addr 0x5409b, Direction=N/A + + uint8_t Reserved138; // Byte offset 0x138, CSR Addr 0x5409c, Direction=N/A + + uint8_t Reserved139; // Byte offset 0x139, CSR Addr 0x5409c, Direction=N/A + + uint8_t Reserved13A; // Byte offset 0x13a, CSR Addr 0x5409d, Direction=N/A + + uint8_t Reserved13B; // Byte offset 0x13b, CSR Addr 0x5409d, Direction=N/A + + uint8_t Reserved13C; // Byte offset 0x13c, CSR Addr 0x5409e, Direction=N/A + + uint8_t Reserved13D; // Byte offset 0x13d, CSR Addr 0x5409e, Direction=N/A + + uint8_t Reserved13E; // Byte offset 0x13e, CSR Addr 0x5409f, Direction=N/A + + uint8_t Reserved13F; // Byte offset 0x13f, CSR Addr 0x5409f, Direction=N/A + + uint8_t Reserved140; // Byte offset 0x140, CSR Addr 0x540a0, Direction=N/A + + uint8_t Reserved141; // Byte offset 0x141, CSR Addr 0x540a0, Direction=N/A + + uint8_t Reserved142; // Byte offset 0x142, CSR Addr 0x540a1, Direction=N/A + + uint8_t Reserved143; // Byte offset 0x143, CSR Addr 0x540a1, Direction=N/A + + uint8_t Reserved144; // Byte offset 0x144, CSR Addr 0x540a2, Direction=N/A + + uint8_t Reserved145; // Byte offset 0x145, CSR Addr 0x540a2, Direction=N/A + + uint8_t Reserved146; // Byte offset 0x146, CSR Addr 0x540a3, Direction=N/A + + uint8_t Reserved147; // Byte offset 0x147, CSR Addr 0x540a3, Direction=N/A + + uint8_t Reserved148; // Byte offset 0x148, CSR Addr 0x540a4, Direction=N/A + + uint8_t Reserved149; // Byte offset 0x149, CSR Addr 0x540a4, Direction=N/A + + uint8_t Reserved14A; // Byte offset 0x14a, CSR Addr 0x540a5, Direction=N/A + + uint8_t Reserved14B; // Byte offset 0x14b, CSR Addr 0x540a5, Direction=N/A + + uint8_t Reserved14C; // Byte offset 0x14c, CSR Addr 0x540a6, Direction=N/A + + uint8_t Reserved14D; // Byte offset 0x14d, CSR Addr 0x540a6, Direction=N/A + + uint8_t Reserved14E; // Byte offset 0x14e, CSR Addr 0x540a7, Direction=N/A + + uint8_t Reserved14F; // Byte offset 0x14f, CSR Addr 0x540a7, Direction=N/A + + uint8_t Reserved150; // Byte offset 0x150, CSR Addr 0x540a8, Direction=N/A + + uint8_t Reserved151; // Byte offset 0x151, CSR Addr 0x540a8, Direction=N/A + + uint8_t Reserved152; // Byte offset 0x152, CSR Addr 0x540a9, Direction=N/A + + uint8_t Reserved153; // Byte offset 0x153, CSR Addr 0x540a9, Direction=N/A + + uint8_t Reserved154; // Byte offset 0x154, CSR Addr 0x540aa, Direction=N/A + + uint8_t Reserved155; // Byte offset 0x155, CSR Addr 0x540aa, Direction=N/A + + uint8_t Reserved156; // Byte offset 0x156, CSR Addr 0x540ab, Direction=N/A + + uint8_t Reserved157; // Byte offset 0x157, CSR Addr 0x540ab, Direction=N/A + + uint8_t Reserved158; // Byte offset 0x158, CSR Addr 0x540ac, Direction=N/A + + uint8_t Reserved159; // Byte offset 0x159, CSR Addr 0x540ac, Direction=N/A + + uint8_t Reserved15A; // Byte offset 0x15a, CSR Addr 0x540ad, Direction=N/A + + uint8_t Reserved15B; // Byte offset 0x15b, CSR Addr 0x540ad, Direction=N/A + + uint8_t Reserved15C; // Byte offset 0x15c, CSR Addr 0x540ae, Direction=N/A + + uint8_t Reserved15D; // Byte offset 0x15d, CSR Addr 0x540ae, Direction=N/A + + uint8_t Reserved15E; // Byte offset 0x15e, CSR Addr 0x540af, Direction=N/A + + uint8_t Reserved15F; // Byte offset 0x15f, CSR Addr 0x540af, Direction=N/A + + uint8_t Reserved160; // Byte offset 0x160, CSR Addr 0x540b0, Direction=N/A + + uint8_t Reserved161; // Byte offset 0x161, CSR Addr 0x540b0, Direction=N/A + + uint8_t Reserved162; // Byte offset 0x162, CSR Addr 0x540b1, Direction=N/A + + uint8_t Reserved163; // Byte offset 0x163, CSR Addr 0x540b1, Direction=N/A + + uint8_t Reserved164; // Byte offset 0x164, CSR Addr 0x540b2, Direction=N/A + + uint8_t Reserved165; // Byte offset 0x165, CSR Addr 0x540b2, Direction=N/A + + uint8_t Reserved166; // Byte offset 0x166, CSR Addr 0x540b3, Direction=N/A + + uint8_t Reserved167; // Byte offset 0x167, CSR Addr 0x540b3, Direction=N/A + + uint8_t Reserved168; // Byte offset 0x168, CSR Addr 0x540b4, Direction=N/A + + uint8_t Reserved169; // Byte offset 0x169, CSR Addr 0x540b4, Direction=N/A + + uint8_t Reserved16A; // Byte offset 0x16a, CSR Addr 0x540b5, Direction=N/A + + uint8_t Reserved16B; // Byte offset 0x16b, CSR Addr 0x540b5, Direction=N/A + + uint8_t Reserved16C; // Byte offset 0x16c, CSR Addr 0x540b6, Direction=N/A + + uint8_t Reserved16D; // Byte offset 0x16d, CSR Addr 0x540b6, Direction=N/A + + uint8_t Reserved16E; // Byte offset 0x16e, CSR Addr 0x540b7, Direction=N/A + + uint8_t Reserved16F; // Byte offset 0x16f, CSR Addr 0x540b7, Direction=N/A + + uint8_t Reserved170; // Byte offset 0x170, CSR Addr 0x540b8, Direction=N/A + + uint8_t Reserved171; // Byte offset 0x171, CSR Addr 0x540b8, Direction=N/A + + uint8_t Reserved172; // Byte offset 0x172, CSR Addr 0x540b9, Direction=N/A + + uint8_t Reserved173; // Byte offset 0x173, CSR Addr 0x540b9, Direction=N/A + + uint8_t Reserved174; // Byte offset 0x174, CSR Addr 0x540ba, Direction=N/A + + uint8_t Reserved175; // Byte offset 0x175, CSR Addr 0x540ba, Direction=N/A + + uint8_t Reserved176; // Byte offset 0x176, CSR Addr 0x540bb, Direction=N/A + + uint8_t Reserved177; // Byte offset 0x177, CSR Addr 0x540bb, Direction=N/A + + uint8_t Reserved178; // Byte offset 0x178, CSR Addr 0x540bc, Direction=N/A + + uint8_t Reserved179; // Byte offset 0x179, CSR Addr 0x540bc, Direction=N/A + + uint8_t Reserved17A; // Byte offset 0x17a, CSR Addr 0x540bd, Direction=N/A + + uint8_t Reserved17B; // Byte offset 0x17b, CSR Addr 0x540bd, Direction=N/A + + uint8_t Reserved17C; // Byte offset 0x17c, CSR Addr 0x540be, Direction=N/A + + uint8_t Reserved17D; // Byte offset 0x17d, CSR Addr 0x540be, Direction=N/A + + uint8_t Reserved17E; // Byte offset 0x17e, CSR Addr 0x540bf, Direction=N/A + + uint8_t Reserved17F; // Byte offset 0x17f, CSR Addr 0x540bf, Direction=N/A + + uint8_t Reserved180; // Byte offset 0x180, CSR Addr 0x540c0, Direction=N/A + + uint8_t Reserved181; // Byte offset 0x181, CSR Addr 0x540c0, Direction=N/A + + uint8_t Reserved182; // Byte offset 0x182, CSR Addr 0x540c1, Direction=N/A + + uint8_t Reserved183; // Byte offset 0x183, CSR Addr 0x540c1, Direction=N/A + + uint8_t Reserved184; // Byte offset 0x184, CSR Addr 0x540c2, Direction=N/A + + uint8_t Reserved185; // Byte offset 0x185, CSR Addr 0x540c2, Direction=N/A + + uint8_t Reserved186; // Byte offset 0x186, CSR Addr 0x540c3, Direction=N/A + + uint8_t Reserved187; // Byte offset 0x187, CSR Addr 0x540c3, Direction=N/A + + uint8_t Reserved188; // Byte offset 0x188, CSR Addr 0x540c4, Direction=N/A + + uint8_t Reserved189; // Byte offset 0x189, CSR Addr 0x540c4, Direction=N/A + + uint8_t Reserved18A; // Byte offset 0x18a, CSR Addr 0x540c5, Direction=N/A + + uint8_t Reserved18B; // Byte offset 0x18b, CSR Addr 0x540c5, Direction=N/A + + uint8_t Reserved18C; // Byte offset 0x18c, CSR Addr 0x540c6, Direction=N/A + + uint8_t Reserved18D; // Byte offset 0x18d, CSR Addr 0x540c6, Direction=N/A + + uint8_t Reserved18E; // Byte offset 0x18e, CSR Addr 0x540c7, Direction=N/A + + uint8_t Reserved18F; // Byte offset 0x18f, CSR Addr 0x540c7, Direction=N/A + + uint8_t Reserved190; // Byte offset 0x190, CSR Addr 0x540c8, Direction=N/A + + uint8_t Reserved191; // Byte offset 0x191, CSR Addr 0x540c8, Direction=N/A + + uint8_t Reserved192; // Byte offset 0x192, CSR Addr 0x540c9, Direction=N/A + + uint8_t Reserved193; // Byte offset 0x193, CSR Addr 0x540c9, Direction=N/A + + uint8_t Reserved194; // Byte offset 0x194, CSR Addr 0x540ca, Direction=N/A + + uint8_t Reserved195; // Byte offset 0x195, CSR Addr 0x540ca, Direction=N/A + + uint8_t Reserved196; // Byte offset 0x196, CSR Addr 0x540cb, Direction=N/A + + uint8_t Reserved197; // Byte offset 0x197, CSR Addr 0x540cb, Direction=N/A + + uint8_t Reserved198; // Byte offset 0x198, CSR Addr 0x540cc, Direction=N/A + + uint8_t Reserved199; // Byte offset 0x199, CSR Addr 0x540cc, Direction=N/A + + uint8_t Reserved19A; // Byte offset 0x19a, CSR Addr 0x540cd, Direction=N/A + + uint8_t Reserved19B; // Byte offset 0x19b, CSR Addr 0x540cd, Direction=N/A + + uint8_t Reserved19C; // Byte offset 0x19c, CSR Addr 0x540ce, Direction=N/A + + uint8_t Reserved19D; // Byte offset 0x19d, CSR Addr 0x540ce, Direction=N/A + + uint8_t Reserved19E; // Byte offset 0x19e, CSR Addr 0x540cf, Direction=N/A + + uint8_t Reserved19F; // Byte offset 0x19f, CSR Addr 0x540cf, Direction=N/A + + uint8_t Reserved1A0; // Byte offset 0x1a0, CSR Addr 0x540d0, Direction=N/A + + uint8_t Reserved1A1; // Byte offset 0x1a1, CSR Addr 0x540d0, Direction=N/A + + uint8_t Reserved1A2; // Byte offset 0x1a2, CSR Addr 0x540d1, Direction=N/A + + uint8_t Reserved1A3; // Byte offset 0x1a3, CSR Addr 0x540d1, Direction=N/A + + uint8_t Reserved1A4; // Byte offset 0x1a4, CSR Addr 0x540d2, Direction=N/A + + uint8_t Reserved1A5; // Byte offset 0x1a5, CSR Addr 0x540d2, Direction=N/A + + uint8_t Reserved1A6; // Byte offset 0x1a6, CSR Addr 0x540d3, Direction=N/A + + uint8_t Reserved1A7; // Byte offset 0x1a7, CSR Addr 0x540d3, Direction=N/A + + uint8_t Reserved1A8; // Byte offset 0x1a8, CSR Addr 0x540d4, Direction=N/A + + uint8_t Reserved1A9; // Byte offset 0x1a9, CSR Addr 0x540d4, Direction=N/A + + uint8_t Reserved1AA; // Byte offset 0x1aa, CSR Addr 0x540d5, Direction=N/A + + uint8_t Reserved1AB; // Byte offset 0x1ab, CSR Addr 0x540d5, Direction=N/A + + uint8_t Reserved1AC; // Byte offset 0x1ac, CSR Addr 0x540d6, Direction=N/A + + uint8_t Reserved1AD; // Byte offset 0x1ad, CSR Addr 0x540d6, Direction=N/A + + uint8_t Reserved1AE; // Byte offset 0x1ae, CSR Addr 0x540d7, Direction=N/A + + uint8_t Reserved1AF; // Byte offset 0x1af, CSR Addr 0x540d7, Direction=N/A + + uint8_t Reserved1B0; // Byte offset 0x1b0, CSR Addr 0x540d8, Direction=N/A + + uint8_t Reserved1B1; // Byte offset 0x1b1, CSR Addr 0x540d8, Direction=N/A + + uint8_t Reserved1B2; // Byte offset 0x1b2, CSR Addr 0x540d9, Direction=N/A + + uint8_t Reserved1B3; // Byte offset 0x1b3, CSR Addr 0x540d9, Direction=N/A + + uint8_t Reserved1B4; // Byte offset 0x1b4, CSR Addr 0x540da, Direction=N/A + + uint8_t Reserved1B5; // Byte offset 0x1b5, CSR Addr 0x540da, Direction=N/A + + uint8_t Reserved1B6; // Byte offset 0x1b6, CSR Addr 0x540db, Direction=N/A + + uint8_t Reserved1B7; // Byte offset 0x1b7, CSR Addr 0x540db, Direction=N/A + + uint8_t Reserved1B8; // Byte offset 0x1b8, CSR Addr 0x540dc, Direction=N/A + + uint8_t Reserved1B9; // Byte offset 0x1b9, CSR Addr 0x540dc, Direction=N/A + + uint8_t Reserved1BA; // Byte offset 0x1ba, CSR Addr 0x540dd, Direction=N/A + + uint8_t Reserved1BB; // Byte offset 0x1bb, CSR Addr 0x540dd, Direction=N/A + + uint8_t Reserved1BC; // Byte offset 0x1bc, CSR Addr 0x540de, Direction=N/A + + uint8_t Reserved1BD; // Byte offset 0x1bd, CSR Addr 0x540de, Direction=N/A + + uint8_t Reserved1BE; // Byte offset 0x1be, CSR Addr 0x540df, Direction=N/A + + uint8_t Reserved1BF; // Byte offset 0x1bf, CSR Addr 0x540df, Direction=N/A + + uint8_t Reserved1C0; // Byte offset 0x1c0, CSR Addr 0x540e0, Direction=N/A + + uint8_t Reserved1C1; // Byte offset 0x1c1, CSR Addr 0x540e0, Direction=N/A + + uint8_t Reserved1C2; // Byte offset 0x1c2, CSR Addr 0x540e1, Direction=N/A + + uint8_t Reserved1C3; // Byte offset 0x1c3, CSR Addr 0x540e1, Direction=N/A + + uint8_t Reserved1C4; // Byte offset 0x1c4, CSR Addr 0x540e2, Direction=N/A + + uint8_t Reserved1C5; // Byte offset 0x1c5, CSR Addr 0x540e2, Direction=N/A + + uint8_t Reserved1C6; // Byte offset 0x1c6, CSR Addr 0x540e3, Direction=N/A + + uint8_t Reserved1C7; // Byte offset 0x1c7, CSR Addr 0x540e3, Direction=N/A + + uint8_t Reserved1C8; // Byte offset 0x1c8, CSR Addr 0x540e4, Direction=N/A + + uint8_t Reserved1C9; // Byte offset 0x1c9, CSR Addr 0x540e4, Direction=N/A + + uint8_t Reserved1CA; // Byte offset 0x1ca, CSR Addr 0x540e5, Direction=N/A + + uint8_t Reserved1CB; // Byte offset 0x1cb, CSR Addr 0x540e5, Direction=N/A + + uint8_t Reserved1CC; // Byte offset 0x1cc, CSR Addr 0x540e6, Direction=N/A + + uint8_t Reserved1CD; // Byte offset 0x1cd, CSR Addr 0x540e6, Direction=N/A + + uint8_t Reserved1CE; // Byte offset 0x1ce, CSR Addr 0x540e7, Direction=N/A + + uint8_t Reserved1CF; // Byte offset 0x1cf, CSR Addr 0x540e7, Direction=N/A + + uint8_t Reserved1D0; // Byte offset 0x1d0, CSR Addr 0x540e8, Direction=N/A + + uint8_t Reserved1D1; // Byte offset 0x1d1, CSR Addr 0x540e8, Direction=N/A + + uint8_t Reserved1D2; // Byte offset 0x1d2, CSR Addr 0x540e9, Direction=N/A + + uint8_t Reserved1D3; // Byte offset 0x1d3, CSR Addr 0x540e9, Direction=N/A + + uint8_t Reserved1D4; // Byte offset 0x1d4, CSR Addr 0x540ea, Direction=N/A + + uint8_t Reserved1D5; // Byte offset 0x1d5, CSR Addr 0x540ea, Direction=N/A + + uint8_t Reserved1D6; // Byte offset 0x1d6, CSR Addr 0x540eb, Direction=N/A + + uint8_t Reserved1D7; // Byte offset 0x1d7, CSR Addr 0x540eb, Direction=N/A + + uint8_t Reserved1D8; // Byte offset 0x1d8, CSR Addr 0x540ec, Direction=N/A + + uint8_t Reserved1D9; // Byte offset 0x1d9, CSR Addr 0x540ec, Direction=N/A + + uint8_t Reserved1DA; // Byte offset 0x1da, CSR Addr 0x540ed, Direction=N/A + + uint8_t Reserved1DB; // Byte offset 0x1db, CSR Addr 0x540ed, Direction=N/A + + uint8_t Reserved1DC; // Byte offset 0x1dc, CSR Addr 0x540ee, Direction=N/A + + uint8_t Reserved1DD; // Byte offset 0x1dd, CSR Addr 0x540ee, Direction=N/A + + uint8_t Reserved1DE; // Byte offset 0x1de, CSR Addr 0x540ef, Direction=N/A + + uint8_t Reserved1DF; // Byte offset 0x1df, CSR Addr 0x540ef, Direction=N/A + + uint8_t Reserved1E0; // Byte offset 0x1e0, CSR Addr 0x540f0, Direction=N/A + + uint8_t Reserved1E1; // Byte offset 0x1e1, CSR Addr 0x540f0, Direction=N/A + + uint8_t Reserved1E2; // Byte offset 0x1e2, CSR Addr 0x540f1, Direction=N/A + + uint8_t Reserved1E3; // Byte offset 0x1e3, CSR Addr 0x540f1, Direction=N/A + + uint8_t Reserved1E4; // Byte offset 0x1e4, CSR Addr 0x540f2, Direction=N/A + + uint8_t Reserved1E5; // Byte offset 0x1e5, CSR Addr 0x540f2, Direction=N/A + + uint8_t Reserved1E6; // Byte offset 0x1e6, CSR Addr 0x540f3, Direction=N/A + + uint8_t Reserved1E7; // Byte offset 0x1e7, CSR Addr 0x540f3, Direction=N/A + + uint8_t Reserved1E8; // Byte offset 0x1e8, CSR Addr 0x540f4, Direction=N/A + + uint8_t Reserved1E9; // Byte offset 0x1e9, CSR Addr 0x540f4, Direction=N/A + + uint8_t Reserved1EA; // Byte offset 0x1ea, CSR Addr 0x540f5, Direction=N/A + + uint8_t Reserved1EB; // Byte offset 0x1eb, CSR Addr 0x540f5, Direction=N/A + + uint8_t Reserved1EC; // Byte offset 0x1ec, CSR Addr 0x540f6, Direction=N/A + + uint8_t Reserved1ED; // Byte offset 0x1ed, CSR Addr 0x540f6, Direction=N/A + + uint8_t Reserved1EE; // Byte offset 0x1ee, CSR Addr 0x540f7, Direction=N/A + + uint8_t Reserved1EF; // Byte offset 0x1ef, CSR Addr 0x540f7, Direction=N/A + + uint8_t Reserved1F0; // Byte offset 0x1f0, CSR Addr 0x540f8, Direction=N/A + + uint8_t Reserved1F1; // Byte offset 0x1f1, CSR Addr 0x540f8, Direction=N/A + + uint8_t Reserved1F2; // Byte offset 0x1f2, CSR Addr 0x540f9, Direction=N/A + + uint8_t Reserved1F3; // Byte offset 0x1f3, CSR Addr 0x540f9, Direction=N/A + + uint8_t Reserved1F4; // Byte offset 0x1f4, CSR Addr 0x540fa, Direction=N/A + + uint8_t Reserved1F5; // Byte offset 0x1f5, CSR Addr 0x540fa, Direction=N/A + + uint8_t Reserved1F6; // Byte offset 0x1f6, CSR Addr 0x540fb, Direction=N/A + + uint8_t Reserved1F7; // Byte offset 0x1f7, CSR Addr 0x540fb, Direction=N/A + + uint8_t Reserved1F8; // Byte offset 0x1f8, CSR Addr 0x540fc, Direction=N/A + + uint8_t Reserved1F9; // Byte offset 0x1f9, CSR Addr 0x540fc, Direction=N/A + + uint8_t Reserved1FA; // Byte offset 0x1fa, CSR Addr 0x540fd, Direction=N/A + + uint8_t Reserved1FB; // Byte offset 0x1fb, CSR Addr 0x540fd, Direction=N/A + + uint8_t Reserved1FC; // Byte offset 0x1fc, CSR Addr 0x540fe, Direction=N/A + + uint8_t Reserved1FD; // Byte offset 0x1fd, CSR Addr 0x540fe, Direction=N/A + + uint8_t Reserved1FE; // Byte offset 0x1fe, CSR Addr 0x540ff, Direction=N/A + + uint8_t Reserved1FF; // Byte offset 0x1ff, CSR Addr 0x540ff, Direction=N/A + + uint8_t Reserved200; // Byte offset 0x200, CSR Addr 0x54100, Direction=N/A + + uint8_t Reserved201; // Byte offset 0x201, CSR Addr 0x54100, Direction=N/A + + uint8_t Reserved202; // Byte offset 0x202, CSR Addr 0x54101, Direction=N/A + + uint8_t Reserved203; // Byte offset 0x203, CSR Addr 0x54101, Direction=N/A + + uint8_t Reserved204; // Byte offset 0x204, CSR Addr 0x54102, Direction=N/A + + uint8_t Reserved205; // Byte offset 0x205, CSR Addr 0x54102, Direction=N/A + + uint8_t Reserved206; // Byte offset 0x206, CSR Addr 0x54103, Direction=N/A + + uint8_t Reserved207; // Byte offset 0x207, CSR Addr 0x54103, Direction=N/A + + uint8_t Reserved208; // Byte offset 0x208, CSR Addr 0x54104, Direction=N/A + + uint8_t Reserved209; // Byte offset 0x209, CSR Addr 0x54104, Direction=N/A + + uint8_t Reserved20A; // Byte offset 0x20a, CSR Addr 0x54105, Direction=N/A + + uint8_t Reserved20B; // Byte offset 0x20b, CSR Addr 0x54105, Direction=N/A + + uint8_t Reserved20C; // Byte offset 0x20c, CSR Addr 0x54106, Direction=N/A + + uint8_t Reserved20D; // Byte offset 0x20d, CSR Addr 0x54106, Direction=N/A + + uint8_t Reserved20E; // Byte offset 0x20e, CSR Addr 0x54107, Direction=N/A + + uint8_t Reserved20F; // Byte offset 0x20f, CSR Addr 0x54107, Direction=N/A + + uint8_t Reserved210; // Byte offset 0x210, CSR Addr 0x54108, Direction=N/A + + uint8_t Reserved211; // Byte offset 0x211, CSR Addr 0x54108, Direction=N/A + + uint8_t Reserved212; // Byte offset 0x212, CSR Addr 0x54109, Direction=N/A + + uint8_t Reserved213; // Byte offset 0x213, CSR Addr 0x54109, Direction=N/A + + uint8_t Reserved214; // Byte offset 0x214, CSR Addr 0x5410a, Direction=N/A + + uint8_t Reserved215; // Byte offset 0x215, CSR Addr 0x5410a, Direction=N/A + + uint8_t Reserved216; // Byte offset 0x216, CSR Addr 0x5410b, Direction=N/A + + uint8_t Reserved217; // Byte offset 0x217, CSR Addr 0x5410b, Direction=N/A + + uint8_t Reserved218; // Byte offset 0x218, CSR Addr 0x5410c, Direction=N/A + + uint8_t Reserved219; // Byte offset 0x219, CSR Addr 0x5410c, Direction=N/A + + uint8_t Reserved21A; // Byte offset 0x21a, CSR Addr 0x5410d, Direction=N/A + + uint8_t Reserved21B; // Byte offset 0x21b, CSR Addr 0x5410d, Direction=N/A + + uint8_t Reserved21C; // Byte offset 0x21c, CSR Addr 0x5410e, Direction=N/A + + uint8_t Reserved21D; // Byte offset 0x21d, CSR Addr 0x5410e, Direction=N/A + + uint8_t Reserved21E; // Byte offset 0x21e, CSR Addr 0x5410f, Direction=N/A + + uint8_t Reserved21F; // Byte offset 0x21f, CSR Addr 0x5410f, Direction=N/A + + uint8_t Reserved220; // Byte offset 0x220, CSR Addr 0x54110, Direction=N/A + + uint8_t Reserved221; // Byte offset 0x221, CSR Addr 0x54110, Direction=N/A + + uint8_t Reserved222; // Byte offset 0x222, CSR Addr 0x54111, Direction=N/A + + uint8_t Reserved223; // Byte offset 0x223, CSR Addr 0x54111, Direction=N/A + + uint8_t Reserved224; // Byte offset 0x224, CSR Addr 0x54112, Direction=N/A + + uint8_t Reserved225; // Byte offset 0x225, CSR Addr 0x54112, Direction=N/A + + uint8_t Reserved226; // Byte offset 0x226, CSR Addr 0x54113, Direction=N/A + + uint8_t Reserved227; // Byte offset 0x227, CSR Addr 0x54113, Direction=N/A + + uint8_t Reserved228; // Byte offset 0x228, CSR Addr 0x54114, Direction=N/A + + uint8_t Reserved229; // Byte offset 0x229, CSR Addr 0x54114, Direction=N/A + + uint8_t Reserved22A; // Byte offset 0x22a, CSR Addr 0x54115, Direction=N/A + + uint8_t Reserved22B; // Byte offset 0x22b, CSR Addr 0x54115, Direction=N/A + + uint8_t Reserved22C; // Byte offset 0x22c, CSR Addr 0x54116, Direction=N/A + + uint8_t Reserved22D; // Byte offset 0x22d, CSR Addr 0x54116, Direction=N/A + + uint8_t Reserved22E; // Byte offset 0x22e, CSR Addr 0x54117, Direction=N/A + + uint8_t Reserved22F; // Byte offset 0x22f, CSR Addr 0x54117, Direction=N/A + + uint8_t Reserved230; // Byte offset 0x230, CSR Addr 0x54118, Direction=N/A + + uint8_t Reserved231; // Byte offset 0x231, CSR Addr 0x54118, Direction=N/A + + uint8_t Reserved232; // Byte offset 0x232, CSR Addr 0x54119, Direction=N/A + + uint8_t Reserved233; // Byte offset 0x233, CSR Addr 0x54119, Direction=N/A + + uint8_t Reserved234; // Byte offset 0x234, CSR Addr 0x5411a, Direction=N/A + + uint8_t Reserved235; // Byte offset 0x235, CSR Addr 0x5411a, Direction=N/A + + uint8_t Reserved236; // Byte offset 0x236, CSR Addr 0x5411b, Direction=N/A + + uint8_t Reserved237; // Byte offset 0x237, CSR Addr 0x5411b, Direction=N/A + + uint8_t Reserved238; // Byte offset 0x238, CSR Addr 0x5411c, Direction=N/A + + uint8_t Reserved239; // Byte offset 0x239, CSR Addr 0x5411c, Direction=N/A + + uint8_t Reserved23A; // Byte offset 0x23a, CSR Addr 0x5411d, Direction=N/A + + uint8_t Reserved23B; // Byte offset 0x23b, CSR Addr 0x5411d, Direction=N/A + + uint8_t Reserved23C; // Byte offset 0x23c, CSR Addr 0x5411e, Direction=N/A + + uint8_t Reserved23D; // Byte offset 0x23d, CSR Addr 0x5411e, Direction=N/A + + uint8_t Reserved23E; // Byte offset 0x23e, CSR Addr 0x5411f, Direction=N/A + + uint8_t Reserved23F; // Byte offset 0x23f, CSR Addr 0x5411f, Direction=N/A + + uint8_t Reserved240; // Byte offset 0x240, CSR Addr 0x54120, Direction=N/A + + uint8_t Reserved241; // Byte offset 0x241, CSR Addr 0x54120, Direction=N/A + + uint8_t Reserved242; // Byte offset 0x242, CSR Addr 0x54121, Direction=N/A + + uint8_t Reserved243; // Byte offset 0x243, CSR Addr 0x54121, Direction=N/A + + uint8_t Reserved244; // Byte offset 0x244, CSR Addr 0x54122, Direction=N/A + + uint8_t Reserved245; // Byte offset 0x245, CSR Addr 0x54122, Direction=N/A + + uint8_t Reserved246; // Byte offset 0x246, CSR Addr 0x54123, Direction=N/A + + uint8_t Reserved247; // Byte offset 0x247, CSR Addr 0x54123, Direction=N/A + + uint8_t Reserved248; // Byte offset 0x248, CSR Addr 0x54124, Direction=N/A + + uint8_t Reserved249; // Byte offset 0x249, CSR Addr 0x54124, Direction=N/A + + uint8_t Reserved24A; // Byte offset 0x24a, CSR Addr 0x54125, Direction=N/A + + uint8_t Reserved24B; // Byte offset 0x24b, CSR Addr 0x54125, Direction=N/A + + uint8_t Reserved24C; // Byte offset 0x24c, CSR Addr 0x54126, Direction=N/A + + uint8_t Reserved24D; // Byte offset 0x24d, CSR Addr 0x54126, Direction=N/A + + uint8_t Reserved24E; // Byte offset 0x24e, CSR Addr 0x54127, Direction=N/A + + uint8_t Reserved24F; // Byte offset 0x24f, CSR Addr 0x54127, Direction=N/A + + uint8_t Reserved250; // Byte offset 0x250, CSR Addr 0x54128, Direction=N/A + + uint8_t Reserved251; // Byte offset 0x251, CSR Addr 0x54128, Direction=N/A + + uint8_t Reserved252; // Byte offset 0x252, CSR Addr 0x54129, Direction=N/A + + uint8_t Reserved253; // Byte offset 0x253, CSR Addr 0x54129, Direction=N/A + + uint8_t Reserved254; // Byte offset 0x254, CSR Addr 0x5412a, Direction=N/A + + uint8_t Reserved255; // Byte offset 0x255, CSR Addr 0x5412a, Direction=N/A + + uint8_t Reserved256; // Byte offset 0x256, CSR Addr 0x5412b, Direction=N/A + + uint8_t Reserved257; // Byte offset 0x257, CSR Addr 0x5412b, Direction=N/A + + uint8_t Reserved258; // Byte offset 0x258, CSR Addr 0x5412c, Direction=N/A + + uint8_t Reserved259; // Byte offset 0x259, CSR Addr 0x5412c, Direction=N/A + + uint8_t Reserved25A; // Byte offset 0x25a, CSR Addr 0x5412d, Direction=N/A + + uint8_t Reserved25B; // Byte offset 0x25b, CSR Addr 0x5412d, Direction=N/A + + uint8_t Reserved25C; // Byte offset 0x25c, CSR Addr 0x5412e, Direction=N/A + + uint8_t Reserved25D; // Byte offset 0x25d, CSR Addr 0x5412e, Direction=N/A + + uint8_t Reserved25E; // Byte offset 0x25e, CSR Addr 0x5412f, Direction=N/A + + uint8_t Reserved25F; // Byte offset 0x25f, CSR Addr 0x5412f, Direction=N/A + + uint8_t Reserved260; // Byte offset 0x260, CSR Addr 0x54130, Direction=N/A + + uint8_t Reserved261; // Byte offset 0x261, CSR Addr 0x54130, Direction=N/A + + uint8_t Reserved262; // Byte offset 0x262, CSR Addr 0x54131, Direction=N/A + + uint8_t Reserved263; // Byte offset 0x263, CSR Addr 0x54131, Direction=N/A + + uint8_t Reserved264; // Byte offset 0x264, CSR Addr 0x54132, Direction=N/A + + uint8_t Reserved265; // Byte offset 0x265, CSR Addr 0x54132, Direction=N/A + + uint8_t Reserved266; // Byte offset 0x266, CSR Addr 0x54133, Direction=N/A + + uint8_t Reserved267; // Byte offset 0x267, CSR Addr 0x54133, Direction=N/A + + uint8_t Reserved268; // Byte offset 0x268, CSR Addr 0x54134, Direction=N/A + + uint8_t Reserved269; // Byte offset 0x269, CSR Addr 0x54134, Direction=N/A + + uint8_t Reserved26A; // Byte offset 0x26a, CSR Addr 0x54135, Direction=N/A + + uint8_t Reserved26B; // Byte offset 0x26b, CSR Addr 0x54135, Direction=N/A + + uint8_t Reserved26C; // Byte offset 0x26c, CSR Addr 0x54136, Direction=N/A + + uint8_t Reserved26D; // Byte offset 0x26d, CSR Addr 0x54136, Direction=N/A + + uint8_t Reserved26E; // Byte offset 0x26e, CSR Addr 0x54137, Direction=N/A + + uint8_t Reserved26F; // Byte offset 0x26f, CSR Addr 0x54137, Direction=N/A + + uint8_t Reserved270; // Byte offset 0x270, CSR Addr 0x54138, Direction=N/A + + uint8_t Reserved271; // Byte offset 0x271, CSR Addr 0x54138, Direction=N/A + + uint8_t Reserved272; // Byte offset 0x272, CSR Addr 0x54139, Direction=N/A + + uint8_t Reserved273; // Byte offset 0x273, CSR Addr 0x54139, Direction=N/A + + uint8_t Reserved274; // Byte offset 0x274, CSR Addr 0x5413a, Direction=N/A + + uint8_t Reserved275; // Byte offset 0x275, CSR Addr 0x5413a, Direction=N/A + + uint8_t Reserved276; // Byte offset 0x276, CSR Addr 0x5413b, Direction=N/A + + uint8_t Reserved277; // Byte offset 0x277, CSR Addr 0x5413b, Direction=N/A + + uint8_t Reserved278; // Byte offset 0x278, CSR Addr 0x5413c, Direction=N/A + + uint8_t Reserved279; // Byte offset 0x279, CSR Addr 0x5413c, Direction=N/A + + uint8_t Reserved27A; // Byte offset 0x27a, CSR Addr 0x5413d, Direction=N/A + + uint8_t Reserved27B; // Byte offset 0x27b, CSR Addr 0x5413d, Direction=N/A + + uint8_t Reserved27C; // Byte offset 0x27c, CSR Addr 0x5413e, Direction=N/A + + uint8_t Reserved27D; // Byte offset 0x27d, CSR Addr 0x5413e, Direction=N/A + + uint8_t Reserved27E; // Byte offset 0x27e, CSR Addr 0x5413f, Direction=N/A + + uint8_t Reserved27F; // Byte offset 0x27f, CSR Addr 0x5413f, Direction=N/A + + uint8_t Reserved280; // Byte offset 0x280, CSR Addr 0x54140, Direction=N/A + + uint8_t Reserved281; // Byte offset 0x281, CSR Addr 0x54140, Direction=N/A + + uint8_t Reserved282; // Byte offset 0x282, CSR Addr 0x54141, Direction=N/A + + uint8_t Reserved283; // Byte offset 0x283, CSR Addr 0x54141, Direction=N/A + + uint8_t Reserved284; // Byte offset 0x284, CSR Addr 0x54142, Direction=N/A + + uint8_t Reserved285; // Byte offset 0x285, CSR Addr 0x54142, Direction=N/A + + uint8_t Reserved286; // Byte offset 0x286, CSR Addr 0x54143, Direction=N/A + + uint8_t Reserved287; // Byte offset 0x287, CSR Addr 0x54143, Direction=N/A + + uint8_t Reserved288; // Byte offset 0x288, CSR Addr 0x54144, Direction=N/A + + uint8_t Reserved289; // Byte offset 0x289, CSR Addr 0x54144, Direction=N/A + + uint8_t Reserved28A; // Byte offset 0x28a, CSR Addr 0x54145, Direction=N/A + + uint8_t Reserved28B; // Byte offset 0x28b, CSR Addr 0x54145, Direction=N/A + + uint8_t Reserved28C; // Byte offset 0x28c, CSR Addr 0x54146, Direction=N/A + + uint8_t Reserved28D; // Byte offset 0x28d, CSR Addr 0x54146, Direction=N/A + + uint8_t Reserved28E; // Byte offset 0x28e, CSR Addr 0x54147, Direction=N/A + + uint8_t Reserved28F; // Byte offset 0x28f, CSR Addr 0x54147, Direction=N/A + + uint8_t Reserved290; // Byte offset 0x290, CSR Addr 0x54148, Direction=N/A + + uint8_t Reserved291; // Byte offset 0x291, CSR Addr 0x54148, Direction=N/A + + uint8_t Reserved292; // Byte offset 0x292, CSR Addr 0x54149, Direction=N/A + + uint8_t Reserved293; // Byte offset 0x293, CSR Addr 0x54149, Direction=N/A + + uint8_t Reserved294; // Byte offset 0x294, CSR Addr 0x5414a, Direction=N/A + + uint8_t Reserved295; // Byte offset 0x295, CSR Addr 0x5414a, Direction=N/A + + uint8_t Reserved296; // Byte offset 0x296, CSR Addr 0x5414b, Direction=N/A + + uint8_t Reserved297; // Byte offset 0x297, CSR Addr 0x5414b, Direction=N/A + + uint8_t Reserved298; // Byte offset 0x298, CSR Addr 0x5414c, Direction=N/A + + uint8_t Reserved299; // Byte offset 0x299, CSR Addr 0x5414c, Direction=N/A + + uint8_t Reserved29A; // Byte offset 0x29a, CSR Addr 0x5414d, Direction=N/A + + uint8_t Reserved29B; // Byte offset 0x29b, CSR Addr 0x5414d, Direction=N/A + + uint8_t Reserved29C; // Byte offset 0x29c, CSR Addr 0x5414e, Direction=N/A + + uint8_t Reserved29D; // Byte offset 0x29d, CSR Addr 0x5414e, Direction=N/A + + uint8_t Reserved29E; // Byte offset 0x29e, CSR Addr 0x5414f, Direction=N/A + + uint8_t Reserved29F; // Byte offset 0x29f, CSR Addr 0x5414f, Direction=N/A + + uint8_t Reserved2A0; // Byte offset 0x2a0, CSR Addr 0x54150, Direction=N/A + + uint8_t Reserved2A1; // Byte offset 0x2a1, CSR Addr 0x54150, Direction=N/A + + uint8_t Reserved2A2; // Byte offset 0x2a2, CSR Addr 0x54151, Direction=N/A + + uint8_t Reserved2A3; // Byte offset 0x2a3, CSR Addr 0x54151, Direction=N/A + + uint8_t Reserved2A4; // Byte offset 0x2a4, CSR Addr 0x54152, Direction=N/A + + uint8_t Reserved2A5; // Byte offset 0x2a5, CSR Addr 0x54152, Direction=N/A + + uint8_t Reserved2A6; // Byte offset 0x2a6, CSR Addr 0x54153, Direction=N/A + + uint8_t Reserved2A7; // Byte offset 0x2a7, CSR Addr 0x54153, Direction=N/A + + uint8_t Reserved2A8; // Byte offset 0x2a8, CSR Addr 0x54154, Direction=N/A + + uint8_t Reserved2A9; // Byte offset 0x2a9, CSR Addr 0x54154, Direction=N/A + + uint8_t Reserved2AA; // Byte offset 0x2aa, CSR Addr 0x54155, Direction=N/A + + uint8_t Reserved2AB; // Byte offset 0x2ab, CSR Addr 0x54155, Direction=N/A + + uint8_t Reserved2AC; // Byte offset 0x2ac, CSR Addr 0x54156, Direction=N/A + + uint8_t Reserved2AD; // Byte offset 0x2ad, CSR Addr 0x54156, Direction=N/A + + uint8_t Reserved2AE; // Byte offset 0x2ae, CSR Addr 0x54157, Direction=N/A + + uint8_t Reserved2AF; // Byte offset 0x2af, CSR Addr 0x54157, Direction=N/A + + uint8_t Reserved2B0; // Byte offset 0x2b0, CSR Addr 0x54158, Direction=N/A + + uint8_t Reserved2B1; // Byte offset 0x2b1, CSR Addr 0x54158, Direction=N/A + + uint8_t Reserved2B2; // Byte offset 0x2b2, CSR Addr 0x54159, Direction=N/A + + uint8_t Reserved2B3; // Byte offset 0x2b3, CSR Addr 0x54159, Direction=N/A + + uint8_t Reserved2B4; // Byte offset 0x2b4, CSR Addr 0x5415a, Direction=N/A + + uint8_t Reserved2B5; // Byte offset 0x2b5, CSR Addr 0x5415a, Direction=N/A + + uint8_t Reserved2B6; // Byte offset 0x2b6, CSR Addr 0x5415b, Direction=N/A + + uint8_t Reserved2B7; // Byte offset 0x2b7, CSR Addr 0x5415b, Direction=N/A + + uint8_t Reserved2B8; // Byte offset 0x2b8, CSR Addr 0x5415c, Direction=N/A + + uint8_t Reserved2B9; // Byte offset 0x2b9, CSR Addr 0x5415c, Direction=N/A + + uint8_t Reserved2BA; // Byte offset 0x2ba, CSR Addr 0x5415d, Direction=N/A + + uint8_t Reserved2BB; // Byte offset 0x2bb, CSR Addr 0x5415d, Direction=N/A + + uint8_t Reserved2BC; // Byte offset 0x2bc, CSR Addr 0x5415e, Direction=N/A + + uint8_t Reserved2BD; // Byte offset 0x2bd, CSR Addr 0x5415e, Direction=N/A + + uint8_t Reserved2BE; // Byte offset 0x2be, CSR Addr 0x5415f, Direction=N/A + + uint8_t Reserved2BF; // Byte offset 0x2bf, CSR Addr 0x5415f, Direction=N/A + + uint8_t Reserved2C0; // Byte offset 0x2c0, CSR Addr 0x54160, Direction=N/A + + uint8_t Reserved2C1; // Byte offset 0x2c1, CSR Addr 0x54160, Direction=N/A + + uint8_t Reserved2C2; // Byte offset 0x2c2, CSR Addr 0x54161, Direction=N/A + + uint8_t Reserved2C3; // Byte offset 0x2c3, CSR Addr 0x54161, Direction=N/A + + uint8_t Reserved2C4; // Byte offset 0x2c4, CSR Addr 0x54162, Direction=N/A + + uint8_t Reserved2C5; // Byte offset 0x2c5, CSR Addr 0x54162, Direction=N/A + + uint8_t Reserved2C6; // Byte offset 0x2c6, CSR Addr 0x54163, Direction=N/A + + uint8_t Reserved2C7; // Byte offset 0x2c7, CSR Addr 0x54163, Direction=N/A + + uint8_t Reserved2C8; // Byte offset 0x2c8, CSR Addr 0x54164, Direction=N/A + + uint8_t Reserved2C9; // Byte offset 0x2c9, CSR Addr 0x54164, Direction=N/A + + uint8_t Reserved2CA; // Byte offset 0x2ca, CSR Addr 0x54165, Direction=N/A + + uint8_t Reserved2CB; // Byte offset 0x2cb, CSR Addr 0x54165, Direction=N/A + + uint8_t Reserved2CC; // Byte offset 0x2cc, CSR Addr 0x54166, Direction=N/A + + uint8_t Reserved2CD; // Byte offset 0x2cd, CSR Addr 0x54166, Direction=N/A + + uint8_t Reserved2CE; // Byte offset 0x2ce, CSR Addr 0x54167, Direction=N/A + + uint8_t Reserved2CF; // Byte offset 0x2cf, CSR Addr 0x54167, Direction=N/A + + uint8_t Reserved2D0; // Byte offset 0x2d0, CSR Addr 0x54168, Direction=N/A + + uint8_t Reserved2D1; // Byte offset 0x2d1, CSR Addr 0x54168, Direction=N/A + + uint8_t Reserved2D2; // Byte offset 0x2d2, CSR Addr 0x54169, Direction=N/A + + uint8_t Reserved2D3; // Byte offset 0x2d3, CSR Addr 0x54169, Direction=N/A + + uint8_t Reserved2D4; // Byte offset 0x2d4, CSR Addr 0x5416a, Direction=N/A + + uint8_t Reserved2D5; // Byte offset 0x2d5, CSR Addr 0x5416a, Direction=N/A + + uint8_t Reserved2D6; // Byte offset 0x2d6, CSR Addr 0x5416b, Direction=N/A + + uint8_t Reserved2D7; // Byte offset 0x2d7, CSR Addr 0x5416b, Direction=N/A + + uint8_t Reserved2D8; // Byte offset 0x2d8, CSR Addr 0x5416c, Direction=N/A + + uint8_t Reserved2D9; // Byte offset 0x2d9, CSR Addr 0x5416c, Direction=N/A + + uint8_t Reserved2DA; // Byte offset 0x2da, CSR Addr 0x5416d, Direction=N/A + + uint8_t Reserved2DB; // Byte offset 0x2db, CSR Addr 0x5416d, Direction=N/A + + uint8_t Reserved2DC; // Byte offset 0x2dc, CSR Addr 0x5416e, Direction=N/A + + uint8_t Reserved2DD; // Byte offset 0x2dd, CSR Addr 0x5416e, Direction=N/A + + uint8_t Reserved2DE; // Byte offset 0x2de, CSR Addr 0x5416f, Direction=N/A + + uint8_t Reserved2DF; // Byte offset 0x2df, CSR Addr 0x5416f, Direction=N/A + + uint8_t Reserved2E0; // Byte offset 0x2e0, CSR Addr 0x54170, Direction=N/A + + uint8_t Reserved2E1; // Byte offset 0x2e1, CSR Addr 0x54170, Direction=N/A + + uint8_t Reserved2E2; // Byte offset 0x2e2, CSR Addr 0x54171, Direction=N/A + + uint8_t Reserved2E3; // Byte offset 0x2e3, CSR Addr 0x54171, Direction=N/A + + uint8_t Reserved2E4; // Byte offset 0x2e4, CSR Addr 0x54172, Direction=N/A + + uint8_t Reserved2E5; // Byte offset 0x2e5, CSR Addr 0x54172, Direction=N/A + + uint8_t Reserved2E6; // Byte offset 0x2e6, CSR Addr 0x54173, Direction=N/A + + uint8_t Reserved2E7; // Byte offset 0x2e7, CSR Addr 0x54173, Direction=N/A + + uint8_t Reserved2E8; // Byte offset 0x2e8, CSR Addr 0x54174, Direction=N/A + + uint8_t Reserved2E9; // Byte offset 0x2e9, CSR Addr 0x54174, Direction=N/A + + uint8_t Reserved2EA; // Byte offset 0x2ea, CSR Addr 0x54175, Direction=N/A + + uint8_t Reserved2EB; // Byte offset 0x2eb, CSR Addr 0x54175, Direction=N/A + + uint8_t Reserved2EC; // Byte offset 0x2ec, CSR Addr 0x54176, Direction=N/A + + uint8_t Reserved2ED; // Byte offset 0x2ed, CSR Addr 0x54176, Direction=N/A + + uint8_t Reserved2EE; // Byte offset 0x2ee, CSR Addr 0x54177, Direction=N/A + + uint8_t Reserved2EF; // Byte offset 0x2ef, CSR Addr 0x54177, Direction=N/A + + uint8_t Reserved2F0; // Byte offset 0x2f0, CSR Addr 0x54178, Direction=N/A + + uint8_t Reserved2F1; // Byte offset 0x2f1, CSR Addr 0x54178, Direction=N/A + + uint8_t Reserved2F2; // Byte offset 0x2f2, CSR Addr 0x54179, Direction=N/A + + uint8_t Reserved2F3; // Byte offset 0x2f3, CSR Addr 0x54179, Direction=N/A + + uint8_t Reserved2F4; // Byte offset 0x2f4, CSR Addr 0x5417a, Direction=N/A + + uint8_t Reserved2F5; // Byte offset 0x2f5, CSR Addr 0x5417a, Direction=N/A + + uint8_t Reserved2F6; // Byte offset 0x2f6, CSR Addr 0x5417b, Direction=N/A + + uint8_t Reserved2F7; // Byte offset 0x2f7, CSR Addr 0x5417b, Direction=N/A + + uint8_t Reserved2F8; // Byte offset 0x2f8, CSR Addr 0x5417c, Direction=N/A + + uint8_t Reserved2F9; // Byte offset 0x2f9, CSR Addr 0x5417c, Direction=N/A + + uint8_t Reserved2FA; // Byte offset 0x2fa, CSR Addr 0x5417d, Direction=N/A + + uint8_t Reserved2FB; // Byte offset 0x2fb, CSR Addr 0x5417d, Direction=N/A + + uint8_t Reserved2FC; // Byte offset 0x2fc, CSR Addr 0x5417e, Direction=N/A + + uint8_t Reserved2FD; // Byte offset 0x2fd, CSR Addr 0x5417e, Direction=N/A + + uint8_t Reserved2FE; // Byte offset 0x2fe, CSR Addr 0x5417f, Direction=N/A + + uint8_t Reserved2FF; // Byte offset 0x2ff, CSR Addr 0x5417f, Direction=N/A + + uint8_t Reserved300; // Byte offset 0x300, CSR Addr 0x54180, Direction=N/A + + uint8_t Reserved301; // Byte offset 0x301, CSR Addr 0x54180, Direction=N/A + + uint8_t Reserved302; // Byte offset 0x302, CSR Addr 0x54181, Direction=N/A + + uint8_t Reserved303; // Byte offset 0x303, CSR Addr 0x54181, Direction=N/A + + uint8_t Reserved304; // Byte offset 0x304, CSR Addr 0x54182, Direction=N/A + + uint8_t Reserved305; // Byte offset 0x305, CSR Addr 0x54182, Direction=N/A + + uint8_t Reserved306; // Byte offset 0x306, CSR Addr 0x54183, Direction=N/A + + uint8_t Reserved307; // Byte offset 0x307, CSR Addr 0x54183, Direction=N/A + + uint8_t Reserved308; // Byte offset 0x308, CSR Addr 0x54184, Direction=N/A + + uint8_t Reserved309; // Byte offset 0x309, CSR Addr 0x54184, Direction=N/A + + uint8_t Reserved30A; // Byte offset 0x30a, CSR Addr 0x54185, Direction=N/A + + uint8_t Reserved30B; // Byte offset 0x30b, CSR Addr 0x54185, Direction=N/A + + uint8_t Reserved30C; // Byte offset 0x30c, CSR Addr 0x54186, Direction=N/A + + uint8_t Reserved30D; // Byte offset 0x30d, CSR Addr 0x54186, Direction=N/A + + uint8_t Reserved30E; // Byte offset 0x30e, CSR Addr 0x54187, Direction=N/A + + uint8_t Reserved30F; // Byte offset 0x30f, CSR Addr 0x54187, Direction=N/A + + uint8_t Reserved310; // Byte offset 0x310, CSR Addr 0x54188, Direction=N/A + + uint8_t Reserved311; // Byte offset 0x311, CSR Addr 0x54188, Direction=N/A + + uint8_t Reserved312; // Byte offset 0x312, CSR Addr 0x54189, Direction=N/A + + uint8_t Reserved313; // Byte offset 0x313, CSR Addr 0x54189, Direction=N/A + + uint8_t Reserved314; // Byte offset 0x314, CSR Addr 0x5418a, Direction=N/A + + uint8_t Reserved315; // Byte offset 0x315, CSR Addr 0x5418a, Direction=N/A + + uint8_t Reserved316; // Byte offset 0x316, CSR Addr 0x5418b, Direction=N/A + + uint8_t Reserved317; // Byte offset 0x317, CSR Addr 0x5418b, Direction=N/A + + uint8_t Reserved318; // Byte offset 0x318, CSR Addr 0x5418c, Direction=N/A + + uint8_t Reserved319; // Byte offset 0x319, CSR Addr 0x5418c, Direction=N/A + + uint8_t Reserved31A; // Byte offset 0x31a, CSR Addr 0x5418d, Direction=N/A + + uint8_t Reserved31B; // Byte offset 0x31b, CSR Addr 0x5418d, Direction=N/A + + uint8_t Reserved31C; // Byte offset 0x31c, CSR Addr 0x5418e, Direction=N/A + + uint8_t Reserved31D; // Byte offset 0x31d, CSR Addr 0x5418e, Direction=N/A + + uint8_t Reserved31E; // Byte offset 0x31e, CSR Addr 0x5418f, Direction=N/A + + uint8_t Reserved31F; // Byte offset 0x31f, CSR Addr 0x5418f, Direction=N/A + + uint8_t Reserved320; // Byte offset 0x320, CSR Addr 0x54190, Direction=N/A + + uint8_t Reserved321; // Byte offset 0x321, CSR Addr 0x54190, Direction=N/A + + uint8_t Reserved322; // Byte offset 0x322, CSR Addr 0x54191, Direction=N/A + + uint8_t Reserved323; // Byte offset 0x323, CSR Addr 0x54191, Direction=N/A + + uint8_t Reserved324; // Byte offset 0x324, CSR Addr 0x54192, Direction=N/A + + uint8_t Reserved325; // Byte offset 0x325, CSR Addr 0x54192, Direction=N/A + + uint8_t Reserved326; // Byte offset 0x326, CSR Addr 0x54193, Direction=N/A + + uint8_t Reserved327; // Byte offset 0x327, CSR Addr 0x54193, Direction=N/A + + uint8_t Reserved328; // Byte offset 0x328, CSR Addr 0x54194, Direction=N/A + + uint8_t Reserved329; // Byte offset 0x329, CSR Addr 0x54194, Direction=N/A + + uint8_t Reserved32A; // Byte offset 0x32a, CSR Addr 0x54195, Direction=N/A + + uint8_t Reserved32B; // Byte offset 0x32b, CSR Addr 0x54195, Direction=N/A + + uint8_t Reserved32C; // Byte offset 0x32c, CSR Addr 0x54196, Direction=N/A + + uint8_t Reserved32D; // Byte offset 0x32d, CSR Addr 0x54196, Direction=N/A + + uint8_t Reserved32E; // Byte offset 0x32e, CSR Addr 0x54197, Direction=N/A + + uint8_t Reserved32F; // Byte offset 0x32f, CSR Addr 0x54197, Direction=N/A + + uint8_t Reserved330; // Byte offset 0x330, CSR Addr 0x54198, Direction=N/A + + uint8_t Reserved331; // Byte offset 0x331, CSR Addr 0x54198, Direction=N/A + + uint8_t Reserved332; // Byte offset 0x332, CSR Addr 0x54199, Direction=N/A + + uint8_t Reserved333; // Byte offset 0x333, CSR Addr 0x54199, Direction=N/A + + uint8_t Reserved334; // Byte offset 0x334, CSR Addr 0x5419a, Direction=N/A + + uint8_t Reserved335; // Byte offset 0x335, CSR Addr 0x5419a, Direction=N/A + + uint8_t Reserved336; // Byte offset 0x336, CSR Addr 0x5419b, Direction=N/A + + uint8_t Reserved337; // Byte offset 0x337, CSR Addr 0x5419b, Direction=N/A + + uint8_t Reserved338; // Byte offset 0x338, CSR Addr 0x5419c, Direction=N/A + + uint8_t Reserved339; // Byte offset 0x339, CSR Addr 0x5419c, Direction=N/A + + uint8_t Reserved33A; // Byte offset 0x33a, CSR Addr 0x5419d, Direction=N/A + + uint8_t Reserved33B; // Byte offset 0x33b, CSR Addr 0x5419d, Direction=N/A + + uint8_t Reserved33C; // Byte offset 0x33c, CSR Addr 0x5419e, Direction=N/A + + uint8_t Reserved33D; // Byte offset 0x33d, CSR Addr 0x5419e, Direction=N/A + + uint8_t Reserved33E; // Byte offset 0x33e, CSR Addr 0x5419f, Direction=N/A + + uint8_t Reserved33F; // Byte offset 0x33f, CSR Addr 0x5419f, Direction=N/A + + uint8_t Reserved340; // Byte offset 0x340, CSR Addr 0x541a0, Direction=N/A + + uint8_t Reserved341; // Byte offset 0x341, CSR Addr 0x541a0, Direction=N/A + + uint8_t Reserved342; // Byte offset 0x342, CSR Addr 0x541a1, Direction=N/A + + uint8_t Reserved343; // Byte offset 0x343, CSR Addr 0x541a1, Direction=N/A + + uint8_t Reserved344; // Byte offset 0x344, CSR Addr 0x541a2, Direction=N/A + + uint8_t Reserved345; // Byte offset 0x345, CSR Addr 0x541a2, Direction=N/A + + uint8_t Reserved346; // Byte offset 0x346, CSR Addr 0x541a3, Direction=N/A + + uint8_t Reserved347; // Byte offset 0x347, CSR Addr 0x541a3, Direction=N/A + + uint8_t Reserved348; // Byte offset 0x348, CSR Addr 0x541a4, Direction=N/A + + uint8_t Reserved349; // Byte offset 0x349, CSR Addr 0x541a4, Direction=N/A + + uint8_t Reserved34A; // Byte offset 0x34a, CSR Addr 0x541a5, Direction=N/A + + uint8_t Reserved34B; // Byte offset 0x34b, CSR Addr 0x541a5, Direction=N/A + + uint8_t Reserved34C; // Byte offset 0x34c, CSR Addr 0x541a6, Direction=N/A + + uint8_t Reserved34D; // Byte offset 0x34d, CSR Addr 0x541a6, Direction=N/A + + uint8_t Reserved34E; // Byte offset 0x34e, CSR Addr 0x541a7, Direction=N/A + + uint8_t Reserved34F; // Byte offset 0x34f, CSR Addr 0x541a7, Direction=N/A + + uint8_t Reserved350; // Byte offset 0x350, CSR Addr 0x541a8, Direction=N/A + + uint8_t Reserved351; // Byte offset 0x351, CSR Addr 0x541a8, Direction=N/A + + uint8_t Reserved352; // Byte offset 0x352, CSR Addr 0x541a9, Direction=N/A + + uint8_t Reserved353; // Byte offset 0x353, CSR Addr 0x541a9, Direction=N/A + + uint8_t Reserved354; // Byte offset 0x354, CSR Addr 0x541aa, Direction=N/A + + uint8_t Reserved355; // Byte offset 0x355, CSR Addr 0x541aa, Direction=N/A + + uint8_t Reserved356; // Byte offset 0x356, CSR Addr 0x541ab, Direction=N/A + + uint8_t Reserved357; // Byte offset 0x357, CSR Addr 0x541ab, Direction=N/A + + uint8_t Reserved358; // Byte offset 0x358, CSR Addr 0x541ac, Direction=N/A + + uint8_t Reserved359; // Byte offset 0x359, CSR Addr 0x541ac, Direction=N/A + + uint8_t Reserved35A; // Byte offset 0x35a, CSR Addr 0x541ad, Direction=N/A + + uint8_t Reserved35B; // Byte offset 0x35b, CSR Addr 0x541ad, Direction=N/A + + uint8_t Reserved35C; // Byte offset 0x35c, CSR Addr 0x541ae, Direction=N/A + + uint8_t Reserved35D; // Byte offset 0x35d, CSR Addr 0x541ae, Direction=N/A + + uint8_t Reserved35E; // Byte offset 0x35e, CSR Addr 0x541af, Direction=N/A + + uint8_t Reserved35F; // Byte offset 0x35f, CSR Addr 0x541af, Direction=N/A + + uint8_t Reserved360; // Byte offset 0x360, CSR Addr 0x541b0, Direction=N/A + + uint8_t Reserved361; // Byte offset 0x361, CSR Addr 0x541b0, Direction=N/A + + uint8_t Reserved362; // Byte offset 0x362, CSR Addr 0x541b1, Direction=N/A + + uint8_t Reserved363; // Byte offset 0x363, CSR Addr 0x541b1, Direction=N/A + + uint8_t Reserved364; // Byte offset 0x364, CSR Addr 0x541b2, Direction=N/A + + uint8_t Reserved365; // Byte offset 0x365, CSR Addr 0x541b2, Direction=N/A + + uint8_t Reserved366; // Byte offset 0x366, CSR Addr 0x541b3, Direction=N/A + + uint8_t Reserved367; // Byte offset 0x367, CSR Addr 0x541b3, Direction=N/A + + uint8_t Reserved368; // Byte offset 0x368, CSR Addr 0x541b4, Direction=N/A + + uint8_t Reserved369; // Byte offset 0x369, CSR Addr 0x541b4, Direction=N/A + + uint8_t Reserved36A; // Byte offset 0x36a, CSR Addr 0x541b5, Direction=N/A + + uint8_t Reserved36B; // Byte offset 0x36b, CSR Addr 0x541b5, Direction=N/A + + uint8_t Reserved36C; // Byte offset 0x36c, CSR Addr 0x541b6, Direction=N/A + + uint8_t Reserved36D; // Byte offset 0x36d, CSR Addr 0x541b6, Direction=N/A + + uint8_t Reserved36E; // Byte offset 0x36e, CSR Addr 0x541b7, Direction=N/A + + uint8_t Reserved36F; // Byte offset 0x36f, CSR Addr 0x541b7, Direction=N/A + + uint8_t Reserved370; // Byte offset 0x370, CSR Addr 0x541b8, Direction=N/A + + uint8_t Reserved371; // Byte offset 0x371, CSR Addr 0x541b8, Direction=N/A + + uint8_t Reserved372; // Byte offset 0x372, CSR Addr 0x541b9, Direction=N/A + + uint8_t Reserved373; // Byte offset 0x373, CSR Addr 0x541b9, Direction=N/A + + uint8_t Reserved374; // Byte offset 0x374, CSR Addr 0x541ba, Direction=N/A + + uint8_t Reserved375; // Byte offset 0x375, CSR Addr 0x541ba, Direction=N/A + + uint8_t Reserved376; // Byte offset 0x376, CSR Addr 0x541bb, Direction=N/A + + uint8_t Reserved377; // Byte offset 0x377, CSR Addr 0x541bb, Direction=N/A + + uint8_t Reserved378; // Byte offset 0x378, CSR Addr 0x541bc, Direction=N/A + + uint8_t Reserved379; // Byte offset 0x379, CSR Addr 0x541bc, Direction=N/A + + uint8_t Reserved37A; // Byte offset 0x37a, CSR Addr 0x541bd, Direction=N/A + + uint8_t Reserved37B; // Byte offset 0x37b, CSR Addr 0x541bd, Direction=N/A + + uint8_t Reserved37C; // Byte offset 0x37c, CSR Addr 0x541be, Direction=N/A + + uint8_t Reserved37D; // Byte offset 0x37d, CSR Addr 0x541be, Direction=N/A + + uint8_t Reserved37E; // Byte offset 0x37e, CSR Addr 0x541bf, Direction=N/A + + uint8_t Reserved37F; // Byte offset 0x37f, CSR Addr 0x541bf, Direction=N/A + + uint8_t Reserved380; // Byte offset 0x380, CSR Addr 0x541c0, Direction=N/A + + uint8_t Reserved381; // Byte offset 0x381, CSR Addr 0x541c0, Direction=N/A + + uint8_t Reserved382; // Byte offset 0x382, CSR Addr 0x541c1, Direction=N/A + + uint8_t Reserved383; // Byte offset 0x383, CSR Addr 0x541c1, Direction=N/A + + uint8_t Reserved384; // Byte offset 0x384, CSR Addr 0x541c2, Direction=N/A + + uint8_t Reserved385; // Byte offset 0x385, CSR Addr 0x541c2, Direction=N/A + + uint8_t Reserved386; // Byte offset 0x386, CSR Addr 0x541c3, Direction=N/A + + uint8_t Reserved387; // Byte offset 0x387, CSR Addr 0x541c3, Direction=N/A + + uint8_t Reserved388; // Byte offset 0x388, CSR Addr 0x541c4, Direction=N/A + + uint8_t Reserved389; // Byte offset 0x389, CSR Addr 0x541c4, Direction=N/A + + uint8_t Reserved38A; // Byte offset 0x38a, CSR Addr 0x541c5, Direction=N/A + + uint8_t Reserved38B; // Byte offset 0x38b, CSR Addr 0x541c5, Direction=N/A + + uint8_t Reserved38C; // Byte offset 0x38c, CSR Addr 0x541c6, Direction=N/A + + uint8_t Reserved38D; // Byte offset 0x38d, CSR Addr 0x541c6, Direction=N/A + + uint8_t Reserved38E; // Byte offset 0x38e, CSR Addr 0x541c7, Direction=N/A + + uint8_t Reserved38F; // Byte offset 0x38f, CSR Addr 0x541c7, Direction=N/A + + uint8_t Reserved390; // Byte offset 0x390, CSR Addr 0x541c8, Direction=N/A + + uint8_t Reserved391; // Byte offset 0x391, CSR Addr 0x541c8, Direction=N/A + + uint8_t Reserved392; // Byte offset 0x392, CSR Addr 0x541c9, Direction=N/A + + uint8_t Reserved393; // Byte offset 0x393, CSR Addr 0x541c9, Direction=N/A + + uint8_t Reserved394; // Byte offset 0x394, CSR Addr 0x541ca, Direction=N/A + + uint8_t Reserved395; // Byte offset 0x395, CSR Addr 0x541ca, Direction=N/A + + uint8_t Reserved396; // Byte offset 0x396, CSR Addr 0x541cb, Direction=N/A + + uint8_t Reserved397; // Byte offset 0x397, CSR Addr 0x541cb, Direction=N/A + + uint8_t Reserved398; // Byte offset 0x398, CSR Addr 0x541cc, Direction=N/A + + uint8_t Reserved399; // Byte offset 0x399, CSR Addr 0x541cc, Direction=N/A + + uint8_t Reserved39A; // Byte offset 0x39a, CSR Addr 0x541cd, Direction=N/A + + uint8_t Reserved39B; // Byte offset 0x39b, CSR Addr 0x541cd, Direction=N/A + + uint8_t Reserved39C; // Byte offset 0x39c, CSR Addr 0x541ce, Direction=N/A + + uint8_t Reserved39D; // Byte offset 0x39d, CSR Addr 0x541ce, Direction=N/A + + uint8_t Reserved39E; // Byte offset 0x39e, CSR Addr 0x541cf, Direction=N/A + + uint8_t Reserved39F; // Byte offset 0x39f, CSR Addr 0x541cf, Direction=N/A + + uint8_t Reserved3A0; // Byte offset 0x3a0, CSR Addr 0x541d0, Direction=N/A + + uint8_t Reserved3A1; // Byte offset 0x3a1, CSR Addr 0x541d0, Direction=N/A + + uint8_t Reserved3A2; // Byte offset 0x3a2, CSR Addr 0x541d1, Direction=N/A + + uint8_t Reserved3A3; // Byte offset 0x3a3, CSR Addr 0x541d1, Direction=N/A + + uint8_t Reserved3A4; // Byte offset 0x3a4, CSR Addr 0x541d2, Direction=N/A + + uint8_t Reserved3A5; // Byte offset 0x3a5, CSR Addr 0x541d2, Direction=N/A + + uint8_t Reserved3A6; // Byte offset 0x3a6, CSR Addr 0x541d3, Direction=N/A + + uint8_t Reserved3A7; // Byte offset 0x3a7, CSR Addr 0x541d3, Direction=N/A + + uint8_t Reserved3A8; // Byte offset 0x3a8, CSR Addr 0x541d4, Direction=N/A + + uint8_t Reserved3A9; // Byte offset 0x3a9, CSR Addr 0x541d4, Direction=N/A + + uint8_t Reserved3AA; // Byte offset 0x3aa, CSR Addr 0x541d5, Direction=N/A + + uint8_t Reserved3AB; // Byte offset 0x3ab, CSR Addr 0x541d5, Direction=N/A + + uint8_t Reserved3AC; // Byte offset 0x3ac, CSR Addr 0x541d6, Direction=N/A + + uint8_t Reserved3AD; // Byte offset 0x3ad, CSR Addr 0x541d6, Direction=N/A + + uint8_t Reserved3AE; // Byte offset 0x3ae, CSR Addr 0x541d7, Direction=N/A + + uint8_t Reserved3AF; // Byte offset 0x3af, CSR Addr 0x541d7, Direction=N/A + + uint8_t Reserved3B0; // Byte offset 0x3b0, CSR Addr 0x541d8, Direction=N/A + + uint8_t Reserved3B1; // Byte offset 0x3b1, CSR Addr 0x541d8, Direction=N/A + + uint8_t Reserved3B2; // Byte offset 0x3b2, CSR Addr 0x541d9, Direction=N/A + + uint8_t Reserved3B3; // Byte offset 0x3b3, CSR Addr 0x541d9, Direction=N/A + + uint8_t Reserved3B4; // Byte offset 0x3b4, CSR Addr 0x541da, Direction=N/A + + uint8_t Reserved3B5; // Byte offset 0x3b5, CSR Addr 0x541da, Direction=N/A + + uint8_t Reserved3B6; // Byte offset 0x3b6, CSR Addr 0x541db, Direction=N/A + + uint8_t Reserved3B7; // Byte offset 0x3b7, CSR Addr 0x541db, Direction=N/A + + uint8_t Reserved3B8; // Byte offset 0x3b8, CSR Addr 0x541dc, Direction=N/A + + uint8_t Reserved3B9; // Byte offset 0x3b9, CSR Addr 0x541dc, Direction=N/A + + uint8_t Reserved3BA; // Byte offset 0x3ba, CSR Addr 0x541dd, Direction=N/A + + uint8_t Reserved3BB; // Byte offset 0x3bb, CSR Addr 0x541dd, Direction=N/A + + uint8_t Reserved3BC; // Byte offset 0x3bc, CSR Addr 0x541de, Direction=N/A + + uint8_t Reserved3BD; // Byte offset 0x3bd, CSR Addr 0x541de, Direction=N/A + + uint8_t Reserved3BE; // Byte offset 0x3be, CSR Addr 0x541df, Direction=N/A + + uint8_t Reserved3BF; // Byte offset 0x3bf, CSR Addr 0x541df, Direction=N/A + + uint8_t Reserved3C0; // Byte offset 0x3c0, CSR Addr 0x541e0, Direction=N/A + + uint8_t Reserved3C1; // Byte offset 0x3c1, CSR Addr 0x541e0, Direction=N/A + + uint8_t Reserved3C2; // Byte offset 0x3c2, CSR Addr 0x541e1, Direction=N/A + + uint8_t Reserved3C3; // Byte offset 0x3c3, CSR Addr 0x541e1, Direction=N/A + + uint8_t Reserved3C4; // Byte offset 0x3c4, CSR Addr 0x541e2, Direction=N/A + + uint8_t Reserved3C5; // Byte offset 0x3c5, CSR Addr 0x541e2, Direction=N/A + + uint8_t Reserved3C6; // Byte offset 0x3c6, CSR Addr 0x541e3, Direction=N/A + + uint8_t Reserved3C7; // Byte offset 0x3c7, CSR Addr 0x541e3, Direction=N/A + + uint8_t Reserved3C8; // Byte offset 0x3c8, CSR Addr 0x541e4, Direction=N/A + + uint8_t Reserved3C9; // Byte offset 0x3c9, CSR Addr 0x541e4, Direction=N/A + + uint8_t Reserved3CA; // Byte offset 0x3ca, CSR Addr 0x541e5, Direction=N/A + + uint8_t Reserved3CB; // Byte offset 0x3cb, CSR Addr 0x541e5, Direction=N/A + + uint8_t Reserved3CC; // Byte offset 0x3cc, CSR Addr 0x541e6, Direction=N/A + + uint8_t Reserved3CD; // Byte offset 0x3cd, CSR Addr 0x541e6, Direction=N/A + + uint8_t Reserved3CE; // Byte offset 0x3ce, CSR Addr 0x541e7, Direction=N/A + + uint8_t Reserved3CF; // Byte offset 0x3cf, CSR Addr 0x541e7, Direction=N/A + + uint8_t Reserved3D0; // Byte offset 0x3d0, CSR Addr 0x541e8, Direction=N/A + + uint8_t Reserved3D1; // Byte offset 0x3d1, CSR Addr 0x541e8, Direction=N/A + + uint8_t Reserved3D2; // Byte offset 0x3d2, CSR Addr 0x541e9, Direction=N/A + + uint8_t Reserved3D3; // Byte offset 0x3d3, CSR Addr 0x541e9, Direction=N/A + + uint8_t Reserved3D4; // Byte offset 0x3d4, CSR Addr 0x541ea, Direction=N/A + + uint8_t Reserved3D5; // Byte offset 0x3d5, CSR Addr 0x541ea, Direction=N/A + + uint8_t Reserved3D6; // Byte offset 0x3d6, CSR Addr 0x541eb, Direction=N/A + + uint8_t Reserved3D7; // Byte offset 0x3d7, CSR Addr 0x541eb, Direction=N/A + + uint8_t Reserved3D8; // Byte offset 0x3d8, CSR Addr 0x541ec, Direction=N/A + + uint8_t Reserved3D9; // Byte offset 0x3d9, CSR Addr 0x541ec, Direction=N/A + + uint8_t Reserved3DA; // Byte offset 0x3da, CSR Addr 0x541ed, Direction=N/A + + uint8_t Reserved3DB; // Byte offset 0x3db, CSR Addr 0x541ed, Direction=N/A + + uint8_t Reserved3DC; // Byte offset 0x3dc, CSR Addr 0x541ee, Direction=N/A + + uint8_t Reserved3DD; // Byte offset 0x3dd, CSR Addr 0x541ee, Direction=N/A + + uint8_t Reserved3DE; // Byte offset 0x3de, CSR Addr 0x541ef, Direction=N/A + + uint8_t Reserved3DF; // Byte offset 0x3df, CSR Addr 0x541ef, Direction=N/A + + uint8_t Reserved3E0; // Byte offset 0x3e0, CSR Addr 0x541f0, Direction=N/A + + uint8_t Reserved3E1; // Byte offset 0x3e1, CSR Addr 0x541f0, Direction=N/A + + uint8_t Reserved3E2; // Byte offset 0x3e2, CSR Addr 0x541f1, Direction=N/A + + uint8_t Reserved3E3; // Byte offset 0x3e3, CSR Addr 0x541f1, Direction=N/A + + uint8_t Reserved3E4; // Byte offset 0x3e4, CSR Addr 0x541f2, Direction=N/A + + uint8_t Reserved3E5; // Byte offset 0x3e5, CSR Addr 0x541f2, Direction=N/A + + uint8_t Reserved3E6; // Byte offset 0x3e6, CSR Addr 0x541f3, Direction=N/A + + uint8_t Reserved3E7; // Byte offset 0x3e7, CSR Addr 0x541f3, Direction=N/A + + uint8_t Reserved3E8; // Byte offset 0x3e8, CSR Addr 0x541f4, Direction=N/A + + uint8_t Reserved3E9; // Byte offset 0x3e9, CSR Addr 0x541f4, Direction=N/A + + uint8_t Reserved3EA; // Byte offset 0x3ea, CSR Addr 0x541f5, Direction=N/A + + uint8_t Reserved3EB; // Byte offset 0x3eb, CSR Addr 0x541f5, Direction=N/A + + uint8_t Reserved3EC; // Byte offset 0x3ec, CSR Addr 0x541f6, Direction=N/A + + uint8_t Reserved3ED; // Byte offset 0x3ed, CSR Addr 0x541f6, Direction=N/A + + uint8_t Reserved3EE; // Byte offset 0x3ee, CSR Addr 0x541f7, Direction=N/A + + uint8_t Reserved3EF; // Byte offset 0x3ef, CSR Addr 0x541f7, Direction=N/A + + uint8_t Reserved3F0; // Byte offset 0x3f0, CSR Addr 0x541f8, Direction=N/A + + uint8_t Reserved3F1; // Byte offset 0x3f1, CSR Addr 0x541f8, Direction=N/A + + uint8_t Reserved3F2; // Byte offset 0x3f2, CSR Addr 0x541f9, Direction=N/A + + uint8_t Reserved3F3; // Byte offset 0x3f3, CSR Addr 0x541f9, Direction=N/A + + uint8_t Reserved3F4; // Byte offset 0x3f4, CSR Addr 0x541fa, Direction=N/A + + uint8_t Reserved3F5; // Byte offset 0x3f5, CSR Addr 0x541fa, Direction=N/A + + uint16_t ALT_CAS_L; // Byte offset 0x3f6, CSR Addr 0x541fb, Direction=in + // This field must be populated if RdDBI is enabled (applicable when MR5[A12] == 1). + // RdDBI is dynamically disabled in certain training steps, + // and so the [RdDBI disabled] CAS Latency must be provided in this field. + // The required encoding is as follows: + // ALT_CAS_L[0] == 0: use value in MR0 + // ALT_CAS_L[0] == 1: use value in ALT_CAS_L, i.e., MR0{A[12],A[6],A[5],A[4],A[2]} = ALT_CAS_L[12,6,5,4,2] + // Other bits are ignored + uint8_t ALT_WCAS_L; // Byte offset 0x3f8, CSR Addr 0x541fc, Direction=In + // This field must be populated if 2tCK write preambles are enabled (applicable when MR4[A12] == 1). + // 2tCK write prambles are dynamically disabled in certain training steps, + // and so the [1tCK write preamble] WCAS Latency must be provided in this field. + // The required encoding is as follows: + // ALT_WCAS_L[0] == 0: use value in MR2 + // ALT_WCAS_L[0] == 1: use value in ALT_WCAS_L, i.e., MR2{A[5],A[4],A[3]} = ALT_WCAS_L[5,4,3] + // Other bits are ignored + uint8_t D4Misc; // Byte offset 0x3f9, CSR Addr 0x541fc, Direction=In + // Contains various options for training DDR4 Devices. + // + // Bit fields: + // + // D4Misc[7:1] RFU, must be zero + // + // D4Misc[0] = protect memory reset + // 0x1 = dfi_reset_n cannot control BP_MEMRESERT_L to devices after training. + // 0x0 = dfi_resert_n can control BP_MEMRESERT_L to devices after training +} __attribute__ ((packed)) PMU_SMB_DDR4U_1D_t;
diff --git a/arch/arm/include/asm/arch-c1/mnPmuSramMsgBlock_ddr4_2d.h b/arch/arm/include/asm/arch-c1/mnPmuSramMsgBlock_ddr4_2d.h new file mode 100644 index 0000000..35b1e23 --- /dev/null +++ b/arch/arm/include/asm/arch-c1/mnPmuSramMsgBlock_ddr4_2d.h
@@ -0,0 +1,2282 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +/** \brief DDR4U_2D training firmware message block structure + * + * Please refer to the Training Firmware App Note for futher information about + * the usage for Message Block. + */ +typedef struct _PMU_SMB_DDR4U_2D_t { + uint8_t Reserved00; // Byte offset 0x00, CSR Addr 0x54000, Direction=In + // Reserved00[0:4] RFU, must be zero + // + // Reserved00[5] = Train vrefDAC0 During Read Deskew + // 0x1 = Read Deskew will begin by enabling and roughly training the phy’s per-lane reference voltages. Training the vrefDACs CSRs will increase the maximum 1D training time by around half a millisecond, but will improve 1D training accuracy on systems with significant voltage-offsets between lane read eyes. + // 0X0 = Read Deskew will assume the messageblock’s phyVref setting will work for all lanes. + // + // Reserved00[6] = Enable High Effort WrDQ1D + // 0x1 = WrDQ1D will conditionally retry training at several extra RxClkDly Timings. This will increase the maximum 1D training time by up to 4 extra iterations of WrDQ1D. This is only required in systems that suffer from very large, asymmetric eye-collapse when receiving PRBS patterns. + // 0x0 = WrDQ1D assume rxClkDly values found by SI Friendly RdDqs1D will work for receiving PRBS patterns + // + // Reserved00[7] = Optimize for the special hard macros in TSMC28. + // 0x1 = set if the phy being trained was manufactured in any TSMC28 process node. + // 0x0 = otherwise, when not training a TSMC28 phy, leave this field as 0. + uint8_t MsgMisc; // Byte offset 0x01, CSR Addr 0x54000, Direction=In + // Contains various global options for training. + // + // Bit fields: + // + // MsgMisc[0] = MTESTEnable + // 0x1 = Pulse primary digital test output bump at the end of each major training stage. This enables observation of training stage completion by observing the digital test output. + // 0x0 = Do not pulse primary digital test output bump + // + // MsgMisc[1] = SimulationOnlyReset + // 0x1 = Verilog only simulation option to shorten duration of DRAM reset pulse length to 1ns. + // Must never be set to 1 in silicon. + // 0x0 = Use reset pulse length specifed by JEDEC standard + // + // MsgMisc[2] = SimulationOnlyTraining + // 0x1 = Verilog only simulation option to shorten the duration of the training steps by performing fewer iterations. + // Must never be set to 1 in silicon. + // 0x0 = Use standard training duration. + // + // MsgMisc[3] = UseDdr4PerDeviceVrefDq (DDR4 UDIMM and RDIMM only, otherwise RFU, must be zero) + // 0x1 = Program user characterized Vref DQ values per DDR4 DRAM device. The message block VrefDqR*Nib* fields must be populated with the desired per device Vref DQs when using this option. Note: this option is not applicable in 2D training because these values are explicitly trained in 2D. + // 0x0 = Program Vref DQ for all DDR4 devices with the single value provided in MR6 message block field + // + // MsgMisc[4] = Suppress streaming messages, including assertions, regardless of HdtCtrl setting. + // Stage Completion messages, as well as training completion and error messages are + // Still sent depending on HdtCtrl setting. + // + // MsgMisc[5] = PerByteMaxRdLat + // 0x1 = Each DBYTE will return dfi_rddata_valid at the lowest possible latency. This may result in unaligned data between bytes to be returned to the DFI. + // 0x0 = Every DBYTE will return dfi_rddata_valid simultaneously. This will ensure that data bytes will return aligned accesses to the DFI. + // + // MsgMisc[6] = PartialRank (DDR3 UDIMM and DDR4 UDIMM only, otherwise RFU, must be zero) + // 0x1 = Support rank populated with a subset of byte, but where even-odd pair of rank support all the byte + // 0x0 = All rank populated with all the byte (tyical configuration) + // + // MsgMisc[7] RFU, must be zero + // + // Notes: + // + // - SimulationOnlyReset and SimulationOnlyTraining can be used to speed up simulation run times, and must never be used in real silicon. Some VIPs may have checks on DRAM reset parameters that may need to be disabled when using SimulationOnlyReset. + uint16_t PmuRevision; // Byte offset 0x02, CSR Addr 0x54001, Direction=Out + // PMU firmware revision ID + // After training is run, this address will contain the revision ID of the firmware. + // Please reference this revision ID when filing support cases with Synopsys. + uint8_t Pstate; // Byte offset 0x04, CSR Addr 0x54002, Direction=In + // Must be set to the target Pstate to be trained + // 0x0 = Pstate 0 + // 0x1 = Pstate 1 + // 0x2 = Pstate 2 + // 0x3 = Pstate 3 + // All other encodings are reserved + uint8_t PllBypassEn; // Byte offset 0x05, CSR Addr 0x54002, Direction=In + // Set according to whether target Pstate uses PHY PLL bypass + // 0x0 = PHY PLL is enabled for target Pstate + // 0x1 = PHY PLL is bypassed for target Pstate + uint16_t DRAMFreq; // Byte offset 0x06, CSR Addr 0x54003, Direction=In + // DDR data rate for the target Pstate in units of MT/s. + // For example enter 0x0640 for DDR1600. + uint8_t DfiFreqRatio; // Byte offset 0x08, CSR Addr 0x54004, Direction=In + // Frequency ratio betwen DfiCtlClk and SDRAM memclk. + // 0x1 = 1:1 + // 0x2 = 1:2 + // 0x4 = 1:4 + uint8_t BPZNResVal ; // Byte offset 0x09, CSR Addr 0x54004, Direction=In + // Must be programmed to match the precision resistor connected to Phy BP_ZN + // 0x00 = Do not program. Use current CSR value. + // 0xf0 = 240 Ohm (recommended value) + // 0x78 = 120 Ohm + // 0x28 = 40 Ohm + // All other values are reserved. + // + uint8_t PhyOdtImpedance; // Byte offset 0x0a, CSR Addr 0x54005, Direction=In + // Must be programmed to the termination impedance in ohms used by PHY during reads. + // + // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start) + // + // See PHY databook for legal termination impedance values. + // + // For digital simulation, any legal value can be used. For silicon, the users must determine the correct value through SI simulation or other methods. + uint8_t PhyDrvImpedance; // Byte offset 0x0b, CSR Addr 0x54005, Direction=In + // Must be programmed to the driver impedance in ohms used by PHY during writes for all DBYTE drivers (DQ/DM/DBI/DQS). + // + // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start) + // + // See PHY databook for legal R_on driver impedance values. + // + // For digital simulation, any value can be used that is not Hi-Z. For silicon, the users must determine the correct value through SI simulation or other methods. + uint8_t PhyVref; // Byte offset 0x0c, CSR Addr 0x54006, Direction=In + // Must be programmed with the Vref level to be used by the PHY during reads + // + // The units of this field are a percentage of VDDQ according to the following equation: + // + // Receiver Vref = VDDQ*PhyVref[6:0]/128 + // + // For example to set Vref at 0.75*VDDQ, set this field to 0x60. + // + // For digital simulation, any legal value can be used. For silicon, the users must calculate the analytical Vref by using the impedances, terminations, and series resistance present in the system. + uint8_t DramType; // Byte offset 0x0d, CSR Addr 0x54006, Direction=In + // Module Type: + // 0x01 = Reserved + // 0x02 = DDR4 unbuffered + // 0x03 = Reserved + // 0x04 = Reserved + // 0x05 = Reserved + // + uint8_t DisabledDbyte; // Byte offset 0x0e, CSR Addr 0x54007, Direction=In + // Bitmap to indicate which Dbyte are not connected (for DByte 0 to 7): + // Set DisabledDbyte[i] to 1 only to specify that DByte i not need to be trained (DByte 8 can be disabled via EnabledDQs setting) + uint8_t EnabledDQs; // Byte offset 0x0f, CSR Addr 0x54007, Direction=In + // Total number of DQ bits enabled in PHY + uint8_t CsPresent; // Byte offset 0x10, CSR Addr 0x54008, Direction=In + // Indicates presence of DRAM at each chip select for PHY. Each bit corresponds to a logical CS. + // + // If the bit is set to 1, the CS is connected to DRAM. + // If the bit is set to 0, the CS is not connected to DRAM. + // + // CsPresent[0] = CS0 is populated with DRAM + // CsPresent[1] = CS1 is populated with DRAM + // CsPresent[2] = CS2 is populated with DRAM + // CsPresent[3] = CS3 is populated with DRAM + // CsPresent[7:4] = Reserved (must be programmed to 0) + // + // + uint8_t CsPresentD0; // Byte offset 0x11, CSR Addr 0x54008, Direction=In + // The CS signals from field CsPresent that are routed to DIMM connector 0 + uint8_t CsPresentD1; // Byte offset 0x12, CSR Addr 0x54009, Direction=In + // The CS signals from field CsPresent that are routed to DIMM connector 1 + uint8_t AddrMirror; // Byte offset 0x13, CSR Addr 0x54009, Direction=In + // Corresponds to CS[3:0] + // 1 = Address Mirror. + // 0 = No Address Mirror. + uint8_t CsTestFail; // Byte offset 0x14, CSR Addr 0x5400a, Direction=Out + // This field will be set if training fails on any rank. + // 0x0 = No failures + // non-zero = one or more ranks failed training + uint8_t PhyCfg; // Byte offset 0x15, CSR Addr 0x5400a, Direction=In + // Additional mode bits. + // + // Bit fields: + // [0] SlowAccessMode : + // 1 = 2T Address Timing. + // 0 = 1T Address Timing. + // [7-1] RFU, must be zero + uint16_t SequenceCtrl; // Byte offset 0x16, CSR Addr 0x5400b, Direction=In + // Controls the training steps to be run. Each bit corresponds to a training step. + // + // If the bit is set to 1, the training step will run. + // If the bit is set to 0, the training step will be skipped. + // + // Training step to bit mapping: + // SequenceCtrl[0] = Run DevInit - Device/phy initialization. Should always be set. + // SequenceCtrl[1] = RFU, must be zero + // SequenceCtrl[2] = RFU, must be zero + // SequenceCtrl[3] = RFU, must be zero + // SequenceCtrl[4] = RFU, must be zero + // SequenceCtrl[5] = Run rd2D - 2d read dqs training + // SequenceCtrl[6] = Run wr2D - 2d write dq training + // SequenceCtrl[7] = RFU, must be zero + // SequenceCtrl[8] = RFU, must be zero + // SequenceCtrl[9] = RFU, must be zero + // SequenceCtrl[10] = RFU, must be zero + // SequenceCtrl[11] = RFU, must be zero + // SequenceCtrl[12] = RFU, must be zero + // SequenceCtrl[13] = RFU, must be zero + // SequenceCtrl[15-14] = RFU, must be zero + uint8_t HdtCtrl; // Byte offset 0x18, CSR Addr 0x5400c, Direction=In + // To control the total number of debug messages, a verbosity subfield (HdtCtrl, Hardware Debug Trace Control) exists in the message block. Every message has a verbosity level associated with it, and as the HdtCtrl value is increased, less important s messages stop being sent through the mailboxes. The meanings of several major HdtCtrl thresholds are explained below: + // + // 0x05 = Detailed debug messages (e.g. Eye delays) + // 0x0A = Coarse debug messages (e.g. rank information) + // 0xC8 = Stage completion + // 0xC9 = Assertion messages + // 0xFF = Firmware completion messages only + // + // See Training App Note for more detailed information on what messages are included for each threshold. + // + uint8_t RX2D_TrainOpt; // Byte offset 0x19, CSR Addr 0x5400c, Direction=In + // Bit fields, if 2D read training enabled, then use these additional options: + // [0] DFE + // 1 = Run rx2D with DFE + // 0 = Run rx2D with DFE off + // [1-2] Voltage Step Size (2^n) + // 3 = 8 DAC settings between checked values + // 2 = 4 DAC settings between checked values + // 1 = 2 DAC settings between checked values + // 0 = 1 DAC settings between checked values + // [3-4] Delay Step Size (2^n) + // 3 = 8 LCDL delays between checked values + // 2 = 4 LCDL delays between checked values + // 1 = 2 LCDL delays between checked values + // 0 = 1 LCDL delays between checked values + // [5-7] RFU, must be zero + // + uint8_t TX2D_TrainOpt; // Byte offset 0x1a, CSR Addr 0x5400d, Direction=In + // Bit fields, if 2D write training is enabled, then use these additional options: + // [0] FFE + // 1 = Train tx2D with FFE + // 0 = Train tx2D with FFE off + // [1-2] Voltage Step Size (2^n) + // 3 = 8 DAC settings between checked values + // 2 = 4 DAC settings between checked values + // 1 = 2 DAC settings between checked values + // 0 = 1 DAC settings between checked values + // [3-4] Delay Step Size (2^n) + // 3 = 8 LCDL delays between checked values + // 2 = 4 LCDL delays between checked values + // 1 = 2 LCDL delays between checked values + // 0 = 1 LCDL delays between checked values + // [5] FFE Decision Algorithm Control + // 1 = FFE chooses the drive strength that maximizes the average eye-area across the entire phy. + // 0 = FFE chooses the drive strength that maximizes the smallest eye across the entire phy. + // [6-7] RFU, must be zero + // + uint8_t Share2DVrefResult; // Byte offset 0x1b, CSR Addr 0x5400d, Direction=In + // Bitmap that designates the phy's vref source for every pstate + // If Share2DVrefResult[x] = 0, then after 2D training, pstate x will continue using the phyVref provided in pstate x’s 1D messageblock. + // If Share2DVrefResult[x] = 1, then after 2D training, pstate x will use the per-lane VrefDAC0/1 CSRs trained by 2d training. + uint8_t Delay_Weight2D; // Byte offset 0x1c, CSR Addr 0x5400e, Direction=In + // During 2D training, the ideal eye center changes depending on how valuable delay margin is compared to voltage margin. delay_weight2D sets the value, or weight, of one step of delay margin. The ratio of voltage_weight2D to delay_weight2D will be used by 2D training to choose your preferred center point. There are 32 delay steps in a perfect eye. + uint8_t Voltage_Weight2D; // Byte offset 0x1d, CSR Addr 0x5400e, Direction=In + // During 2D training, the ideal eye center changes depending on how valuable voltage margin is compared to delay margin. voltage_weight2D sets the value, or weight, of one step of voltage margin. The ratio of voltage_weight2D to delay_weight2D will be used by 2D training to choose your preferred center point. There are 128 voltage steps in a perfect eye. + uint8_t Reserved1E; // Byte offset 0x1e, CSR Addr 0x5400f, Direction=In + // Input for constraining the range of vref(DQ) values training will collect data for, usually reducing training time. However, too large of a voltage range may cause longer 2D training times while too small of a voltage range may truncate passing regions. When in doubt, leave this field set to 0. + // Used by 2D training in: Rd2D, Wr2D + // + // Reserved1E[0-3]: Rd2D Voltage Range + // 0 = Training will search all phy vref(DQ) settings + // 1 = limit to +/-2 %VDDQ from phyVref + // 2 = limit to +/-4 %VDDQ from phyVref + // … + // 15 = limit to +/-30% VDDQ from phyVref + // + // Reserved1E[4-7]: Wr2D Voltage Range + // 0 = Training will search all dram vref(DQ) settings + // 1 = limit to +/-2 %VDDQ from MR6 + // 2 = limit to +/-4 %VDDQ from MR6 + // … + // 15 = limit to +/-30% VDDQ from MR6 + uint8_t Reserved1F; // Byte offset 0x1f, CSR Addr 0x5400f, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved20; // Byte offset 0x20, CSR Addr 0x54010, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved21; // Byte offset 0x21, CSR Addr 0x54010, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint16_t PhyConfigOverride; // Byte offset 0x22, CSR Addr 0x54011, Direction=In + // Override PhyConfig csr. + // 0x0: Use hardware csr value for PhyConfing (recommended) + // Other values: Use value for PhyConfig instead of Hardware value. + // + uint8_t DFIMRLMargin; // Byte offset 0x24, CSR Addr 0x54012, Direction=In + // Margin added to smallest passing trained DFI Max Read Latency value, in units of DFI clocks. Recommended to be >= 1. See the Training App Note for more details on the training process and the use of this value. + uint8_t R0_RxClkDly_Margin; // Byte offset 0x25, CSR Addr 0x54012, Direction=Out + // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group. + uint8_t R0_VrefDac_Margin; // Byte offset 0x26, CSR Addr 0x54013, Direction=Out + // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group. + uint8_t R0_TxDqDly_Margin; // Byte offset 0x27, CSR Addr 0x54013, Direction=Out + // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group. + uint8_t R0_DeviceVref_Margin; // Byte offset 0x28, CSR Addr 0x54014, Direction=Out + // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group. + uint8_t Reserved29; // Byte offset 0x29, CSR Addr 0x54014, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved2A; // Byte offset 0x2a, CSR Addr 0x54015, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved2B; // Byte offset 0x2b, CSR Addr 0x54015, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved2C; // Byte offset 0x2c, CSR Addr 0x54016, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved2D; // Byte offset 0x2d, CSR Addr 0x54016, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved2E; // Byte offset 0x2e, CSR Addr 0x54017, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved2F; // Byte offset 0x2f, CSR Addr 0x54017, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved30; // Byte offset 0x30, CSR Addr 0x54018, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved31; // Byte offset 0x31, CSR Addr 0x54018, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved32; // Byte offset 0x32, CSR Addr 0x54019, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t R1_RxClkDly_Margin; // Byte offset 0x33, CSR Addr 0x54019, Direction=Out + // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group. + uint8_t R1_VrefDac_Margin; // Byte offset 0x34, CSR Addr 0x5401a, Direction=Out + // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group. + uint8_t R1_TxDqDly_Margin; // Byte offset 0x35, CSR Addr 0x5401a, Direction=Out + // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group. + uint8_t R1_DeviceVref_Margin; // Byte offset 0x36, CSR Addr 0x5401b, Direction=Out + // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group. + uint8_t Reserved37; // Byte offset 0x37, CSR Addr 0x5401b, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved38; // Byte offset 0x38, CSR Addr 0x5401c, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved39; // Byte offset 0x39, CSR Addr 0x5401c, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved3A; // Byte offset 0x3a, CSR Addr 0x5401d, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved3B; // Byte offset 0x3b, CSR Addr 0x5401d, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved3C; // Byte offset 0x3c, CSR Addr 0x5401e, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved3D; // Byte offset 0x3d, CSR Addr 0x5401e, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved3E; // Byte offset 0x3e, CSR Addr 0x5401f, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved3F; // Byte offset 0x3f, CSR Addr 0x5401f, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved40; // Byte offset 0x40, CSR Addr 0x54020, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t R2_RxClkDly_Margin; // Byte offset 0x41, CSR Addr 0x54020, Direction=Out + // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group. + uint8_t R2_VrefDac_Margin; // Byte offset 0x42, CSR Addr 0x54021, Direction=Out + // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group. + uint8_t R2_TxDqDly_Margin; // Byte offset 0x43, CSR Addr 0x54021, Direction=Out + // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group. + uint8_t R2_DeviceVref_Margin; // Byte offset 0x44, CSR Addr 0x54022, Direction=Out + // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group. + uint8_t Reserved45; // Byte offset 0x45, CSR Addr 0x54022, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved46; // Byte offset 0x46, CSR Addr 0x54023, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved47; // Byte offset 0x47, CSR Addr 0x54023, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved48; // Byte offset 0x48, CSR Addr 0x54024, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved49; // Byte offset 0x49, CSR Addr 0x54024, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved4A; // Byte offset 0x4a, CSR Addr 0x54025, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved4B; // Byte offset 0x4b, CSR Addr 0x54025, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved4C; // Byte offset 0x4c, CSR Addr 0x54026, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved4D; // Byte offset 0x4d, CSR Addr 0x54026, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved4E; // Byte offset 0x4e, CSR Addr 0x54027, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t R3_RxClkDly_Margin; // Byte offset 0x4f, CSR Addr 0x54027, Direction=Out + // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group. + uint8_t R3_VrefDac_Margin; // Byte offset 0x50, CSR Addr 0x54028, Direction=Out + // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group. + uint8_t R3_TxDqDly_Margin; // Byte offset 0x51, CSR Addr 0x54028, Direction=Out + // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group. + uint8_t R3_DeviceVref_Margin; // Byte offset 0x52, CSR Addr 0x54029, Direction=Out + // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group. + uint8_t Reserved53; // Byte offset 0x53, CSR Addr 0x54029, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved54; // Byte offset 0x54, CSR Addr 0x5402a, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved55; // Byte offset 0x55, CSR Addr 0x5402a, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved56; // Byte offset 0x56, CSR Addr 0x5402b, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved57; // Byte offset 0x57, CSR Addr 0x5402b, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved58; // Byte offset 0x58, CSR Addr 0x5402c, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved59; // Byte offset 0x59, CSR Addr 0x5402c, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved5A; // Byte offset 0x5a, CSR Addr 0x5402d, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved5B; // Byte offset 0x5b, CSR Addr 0x5402d, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved5C; // Byte offset 0x5c, CSR Addr 0x5402e, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved5D; // Byte offset 0x5d, CSR Addr 0x5402e, Direction=In + // Bit Field for enabling optional 2D training features that impact both Rx2D and Tx2D. + // + // Reserved5D[0-3]: bitTimeControl + // Input for increasing the number of data-comparisons 2D runs per (delay,voltage) point. Every time this input increases by 1, the number of 2D data comparisons is doubled. The 2D run time will increase proportionally to the number of bit times requested per point. + // 0 = 1 kilobit per point (legacy behavior) + // 1 = 2 kilobits per point + // 2 = 4 kilobits per point + // … + // 15 = 32 megabits per point + // + // Reserved5D[4]: Exhaustive2D + // 0 = 2D’s optimization assumes the optimal trained point is near the 1D trained point (legacy behavior) + // 1 = 2D’s optimization searches the entire passing region at the cost of run time. Recommended for optimal results any time the optimal trained point is expected to be near the edges of the eyes instead of near the 1D trained point. + // + // Reserved5D[5:7]: RFU, must be 0 + uint16_t MR0; // Byte offset 0x5e, CSR Addr 0x5402f, Direction=In + // Value of DDR mode register MR0 for all ranks for current pstate + uint16_t MR1; // Byte offset 0x60, CSR Addr 0x54030, Direction=In + // Value of DDR mode register MR1 for all ranks for current pstate + uint16_t MR2; // Byte offset 0x62, CSR Addr 0x54031, Direction=In + // Value of DDR mode register MR2 for all ranks for current pstate + uint16_t MR3; // Byte offset 0x64, CSR Addr 0x54032, Direction=In + // Value of DDR mode register MR3 for all ranks for current pstate + uint16_t MR4; // Byte offset 0x66, CSR Addr 0x54033, Direction=In + // Value of DDR mode register MR4 for all ranks for current pstate + uint16_t MR5; // Byte offset 0x68, CSR Addr 0x54034, Direction=In + // Value of DDR mode register MR5 for all ranks for current pstate + uint16_t MR6; // Byte offset 0x6a, CSR Addr 0x54035, Direction=In + // Value of DDR mode register MR6 for all ranks for current pstate. Note: The initial VrefDq value and range must be set in A6:A0. + uint8_t X16Present; // Byte offset 0x6c, CSR Addr 0x54036, Direction=In + // X16 device map. Corresponds to CS[3:0]. + // X16Present[0] = CS0 is populated with X16 devices + // X16Present[1] = CS1 is populated with X16 devices + // X16Present[2] = CS2 is populated with X16 devices + // X16Present[3] = CS3 is populated with X16 devices + // X16Present[7:4] = Reserved (must be programmed to 0) + // + // Ranks may not contain mixed device types. + uint8_t CsSetupGDDec; // Byte offset 0x6d, CSR Addr 0x54036, Direction=In + // controls timing of chip select signals when DDR4 gear-down mode is active + // 0 - Leave delay of chip select timing group signal the same both before and after gear-down sync occurs + // 1 - Add 1UI of delay to chip select timing group signals when geardown-mode is active. This allows CS signals to have equal setup and hold time in gear-down mode + uint16_t RTT_NOM_WR_PARK0; // Byte offset 0x6e, CSR Addr 0x54037, Direction=In + // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 0 DRAM: + // RTT_NOM_WR_PARK0[0] = 1: Option is enable (otherwise, remaining bit fields are don't care) + // RTT_NOM_WR_PARK0[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 0 + // RTT_NOM_WR_PARK0[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 0 + // RTT_NOM_WR_PARK0[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 0 + uint16_t RTT_NOM_WR_PARK1; // Byte offset 0x70, CSR Addr 0x54038, Direction=In + // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 1 DRAM: + // RTT_NOM_WR_PARK1[0] = 1: Option is enable (otherwise, remaining bit fields are don't care) + // RTT_NOM_WR_PARK1[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 1 + // RTT_NOM_WR_PARK1[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 1 + // RTT_NOM_WR_PARK1[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 1 + uint16_t RTT_NOM_WR_PARK2; // Byte offset 0x72, CSR Addr 0x54039, Direction=In + // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 2 DRAM: + // RTT_NOM_WR_PARK2[0] = 1: Option is enable (otherwise, remaining bit fields are don't care) + // RTT_NOM_WR_PARK2[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 2 + // RTT_NOM_WR_PARK2[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 2 + // RTT_NOM_WR_PARK2[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 2 + uint16_t RTT_NOM_WR_PARK3; // Byte offset 0x74, CSR Addr 0x5403a, Direction=In + // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 3 DRAM: + // RTT_NOM_WR_PARK3[0] = 1: Option is enable (otherwise, remaining bit fields are don't care) + // RTT_NOM_WR_PARK3[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 3 + // RTT_NOM_WR_PARK3[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 3 + // RTT_NOM_WR_PARK3[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 3 + uint16_t RTT_NOM_WR_PARK4; // Byte offset 0x76, CSR Addr 0x5403b, Direction=In + // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 4 DRAM: + // RTT_NOM_WR_PARK4[0] = 1: Option is enable (otherwise, remaining bit fields are don't care) + // RTT_NOM_WR_PARK4[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 4 + // RTT_NOM_WR_PARK4[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 4 + // RTT_NOM_WR_PARK4[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 4 + uint16_t RTT_NOM_WR_PARK5; // Byte offset 0x78, CSR Addr 0x5403c, Direction=In + // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 5 DRAM: + // RTT_NOM_WR_PARK5[0] = 1: Option is enable (otherwise, remaining bit fields are don't care) + // RTT_NOM_WR_PARK5[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 5 + // RTT_NOM_WR_PARK5[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 5 + // RTT_NOM_WR_PARK5[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 5 + uint16_t RTT_NOM_WR_PARK6; // Byte offset 0x7a, CSR Addr 0x5403d, Direction=In + // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 6 DRAM: + // RTT_NOM_WR_PARK6[0] = 1: Option is enable (otherwise, remaining bit fields are don't care) + // RTT_NOM_WR_PARK6[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 6 + // RTT_NOM_WR_PARK6[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 6 + // RTT_NOM_WR_PARK6[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 6 + uint16_t RTT_NOM_WR_PARK7; // Byte offset 0x7c, CSR Addr 0x5403e, Direction=In + // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 7 DRAM: + // RTT_NOM_WR_PARK7[0] = 1: Option is enable (otherwise, remaining bit fields are don't care) + // RTT_NOM_WR_PARK7[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 7 + // RTT_NOM_WR_PARK7[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 7 + // RTT_NOM_WR_PARK7[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 7 + uint8_t AcsmOdtCtrl0; // Byte offset 0x7e, CSR Addr 0x5403f, Direction=In + // Odt pattern for accesses targeting rank 0. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl1; // Byte offset 0x7f, CSR Addr 0x5403f, Direction=In + // Odt pattern for accesses targeting rank 1. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl2; // Byte offset 0x80, CSR Addr 0x54040, Direction=In + // Odt pattern for accesses targeting rank 2. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl3; // Byte offset 0x81, CSR Addr 0x54040, Direction=In + // Odt pattern for accesses targeting rank 3. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl4; // Byte offset 0x82, CSR Addr 0x54041, Direction=In + // Odt pattern for accesses targeting rank 4. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl5; // Byte offset 0x83, CSR Addr 0x54041, Direction=In + // Odt pattern for accesses targeting rank 5. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl6; // Byte offset 0x84, CSR Addr 0x54042, Direction=In + // Odt pattern for accesses targeting rank 6. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl7; // Byte offset 0x85, CSR Addr 0x54042, Direction=In + // Odt pattern for accesses targeting rank 7. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t VrefDqR0Nib0; // Byte offset 0x86, CSR Addr 0x54043, Direction=InOut + // VrefDq for rank 0 nibble 0. Specifies MR6[6:0] + uint8_t VrefDqR0Nib1; // Byte offset 0x87, CSR Addr 0x54043, Direction=InOut + // VrefDq for rank 0 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR0Nib0 for x8 or x16 devices. + uint8_t VrefDqR0Nib2; // Byte offset 0x88, CSR Addr 0x54044, Direction=InOut + // VrefDq for rank 0 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR0Nib0 for x16 devices. + uint8_t VrefDqR0Nib3; // Byte offset 0x89, CSR Addr 0x54044, Direction=InOut + // VrefDq for rank 0 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR0Nib0 for x16 devices, or VrefDqR0Nib2 for x8 devices. + uint8_t VrefDqR0Nib4; // Byte offset 0x8a, CSR Addr 0x54045, Direction=InOut + // VrefDq for rank 0 nibble 4. Specifies MR6[6:0] + uint8_t VrefDqR0Nib5; // Byte offset 0x8b, CSR Addr 0x54045, Direction=InOut + // VrefDq for rank 0 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR0Nib4 for x8 or x16 devices. + uint8_t VrefDqR0Nib6; // Byte offset 0x8c, CSR Addr 0x54046, Direction=InOut + // VrefDq for rank 0 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR0Nib4 for x16 devices. + uint8_t VrefDqR0Nib7; // Byte offset 0x8d, CSR Addr 0x54046, Direction=InOut + // VrefDq for rank 0 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR0Nib4 for x16 devices, or VrefDqR0Nib6 for x8 devices. + uint8_t VrefDqR0Nib8; // Byte offset 0x8e, CSR Addr 0x54047, Direction=InOut + // VrefDq for rank 0 nibble 8. Specifies MR6[6:0] + uint8_t VrefDqR0Nib9; // Byte offset 0x8f, CSR Addr 0x54047, Direction=InOut + // VrefDq for rank 0 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR0Nib8 for x8 or x16 devices. + uint8_t VrefDqR0Nib10; // Byte offset 0x90, CSR Addr 0x54048, Direction=InOut + // VrefDq for rank 0 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR0Nib8 for x16 devices. + uint8_t VrefDqR0Nib11; // Byte offset 0x91, CSR Addr 0x54048, Direction=InOut + // VrefDq for rank 0 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR0Nib8 for x16 devices, or VrefDqR0Nib10 for x8 devices. + uint8_t VrefDqR0Nib12; // Byte offset 0x92, CSR Addr 0x54049, Direction=InOut + // VrefDq for rank 0 nibble 12. Specifies MR6[6:0] + uint8_t VrefDqR0Nib13; // Byte offset 0x93, CSR Addr 0x54049, Direction=InOut + // VrefDq for rank 0 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR0Nib12 for x8 or x16 devices. + uint8_t VrefDqR0Nib14; // Byte offset 0x94, CSR Addr 0x5404a, Direction=InOut + // VrefDq for rank 0 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR0Nib12 for x16 devices. + uint8_t VrefDqR0Nib15; // Byte offset 0x95, CSR Addr 0x5404a, Direction=InOut + // VrefDq for rank 0 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR0Nib12 for x16 devices, or VrefDqR0Nib14 for x8 devices. + uint8_t VrefDqR0Nib16; // Byte offset 0x96, CSR Addr 0x5404b, Direction=InOut + // VrefDq for rank 0 nibble 16. Specifies MR6[6:0] + uint8_t VrefDqR0Nib17; // Byte offset 0x97, CSR Addr 0x5404b, Direction=InOut + // VrefDq for rank 0 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR0Nib16 for x8 or x16 devices. + uint8_t VrefDqR0Nib18; // Byte offset 0x98, CSR Addr 0x5404c, Direction=InOut + // VrefDq for rank 0 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR0Nib16 for x16 devices. + uint8_t VrefDqR0Nib19; // Byte offset 0x99, CSR Addr 0x5404c, Direction=InOut + // VrefDq for rank 0 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR0Nib16 for x16 devices, or VrefDqR0Nib18 for x8 devices. + uint8_t VrefDqR1Nib0; // Byte offset 0x9a, CSR Addr 0x5404d, Direction=InOut + // VrefDq for rank 1 nibble 0. Specifies MR6[6:0] + uint8_t VrefDqR1Nib1; // Byte offset 0x9b, CSR Addr 0x5404d, Direction=InOut + // VrefDq for rank 1 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR1Nib0 for x8 or x16 devices. + uint8_t VrefDqR1Nib2; // Byte offset 0x9c, CSR Addr 0x5404e, Direction=InOut + // VrefDq for rank 1 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR1Nib0 for x16 devices. + uint8_t VrefDqR1Nib3; // Byte offset 0x9d, CSR Addr 0x5404e, Direction=InOut + // VrefDq for rank 1 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR1Nib0 for x16 devices, or VrefDqR1Nib2 for x8 devices. + uint8_t VrefDqR1Nib4; // Byte offset 0x9e, CSR Addr 0x5404f, Direction=InOut + // VrefDq for rank 1 nibble 4. Specifies MR6[6:0] + uint8_t VrefDqR1Nib5; // Byte offset 0x9f, CSR Addr 0x5404f, Direction=InOut + // VrefDq for rank 1 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR1Nib4 for x8 or x16 devices. + uint8_t VrefDqR1Nib6; // Byte offset 0xa0, CSR Addr 0x54050, Direction=InOut + // VrefDq for rank 1 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR1Nib4 for x16 devices. + uint8_t VrefDqR1Nib7; // Byte offset 0xa1, CSR Addr 0x54050, Direction=InOut + // VrefDq for rank 1 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR1Nib4 for x16 devices, or VrefDqR1Nib6 for x8 devices. + uint8_t VrefDqR1Nib8; // Byte offset 0xa2, CSR Addr 0x54051, Direction=InOut + // VrefDq for rank 1 nibble 8. Specifies MR6[6:0] + uint8_t VrefDqR1Nib9; // Byte offset 0xa3, CSR Addr 0x54051, Direction=InOut + // VrefDq for rank 1 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR1Nib8 for x8 or x16 devices. + uint8_t VrefDqR1Nib10; // Byte offset 0xa4, CSR Addr 0x54052, Direction=InOut + // VrefDq for rank 1 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR1Nib8 for x16 devices. + uint8_t VrefDqR1Nib11; // Byte offset 0xa5, CSR Addr 0x54052, Direction=InOut + // VrefDq for rank 1 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR1Nib8 for x16 devices, or VrefDqR1Nib10 for x8 devices. + uint8_t VrefDqR1Nib12; // Byte offset 0xa6, CSR Addr 0x54053, Direction=InOut + // VrefDq for rank 1 nibble 12. Specifies MR6[6:0] + uint8_t VrefDqR1Nib13; // Byte offset 0xa7, CSR Addr 0x54053, Direction=InOut + // VrefDq for rank 1 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR1Nib12 for x8 or x16 devices. + uint8_t VrefDqR1Nib14; // Byte offset 0xa8, CSR Addr 0x54054, Direction=InOut + // VrefDq for rank 1 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR1Nib12 for x16 devices. + uint8_t VrefDqR1Nib15; // Byte offset 0xa9, CSR Addr 0x54054, Direction=InOut + // VrefDq for rank 1 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR1Nib12 for x16 devices, or VrefDqR1Nib14 for x8 devices. + uint8_t VrefDqR1Nib16; // Byte offset 0xaa, CSR Addr 0x54055, Direction=InOut + // VrefDq for rank 1 nibble 16. Specifies MR6[6:0] + uint8_t VrefDqR1Nib17; // Byte offset 0xab, CSR Addr 0x54055, Direction=InOut + // VrefDq for rank 1 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR1Nib16 for x8 or x16 devices. + uint8_t VrefDqR1Nib18; // Byte offset 0xac, CSR Addr 0x54056, Direction=InOut + // VrefDq for rank 1 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR1Nib16 for x16 devices. + uint8_t VrefDqR1Nib19; // Byte offset 0xad, CSR Addr 0x54056, Direction=InOut + // VrefDq for rank 1 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR1Nib16 for x16 devices, or VrefDqR1Nib18 for x8 devices. + uint8_t VrefDqR2Nib0; // Byte offset 0xae, CSR Addr 0x54057, Direction=InOut + // VrefDq for rank 2 nibble 0. Specifies MR6[6:0] + uint8_t VrefDqR2Nib1; // Byte offset 0xaf, CSR Addr 0x54057, Direction=InOut + // VrefDq for rank 2 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR2Nib0 for x8 or x16 devices. + uint8_t VrefDqR2Nib2; // Byte offset 0xb0, CSR Addr 0x54058, Direction=InOut + // VrefDq for rank 2 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR2Nib0 for x16 devices. + uint8_t VrefDqR2Nib3; // Byte offset 0xb1, CSR Addr 0x54058, Direction=InOut + // VrefDq for rank 2 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR2Nib0 for x16 devices, or VrefDqR2Nib2 for x8 devices. + uint8_t VrefDqR2Nib4; // Byte offset 0xb2, CSR Addr 0x54059, Direction=InOut + // VrefDq for rank 2 nibble 4. Specifies MR6[6:0] + uint8_t VrefDqR2Nib5; // Byte offset 0xb3, CSR Addr 0x54059, Direction=InOut + // VrefDq for rank 2 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR2Nib4 for x8 or x16 devices. + uint8_t VrefDqR2Nib6; // Byte offset 0xb4, CSR Addr 0x5405a, Direction=InOut + // VrefDq for rank 2 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR2Nib4 for x16 devices. + uint8_t VrefDqR2Nib7; // Byte offset 0xb5, CSR Addr 0x5405a, Direction=InOut + // VrefDq for rank 2 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR2Nib4 for x16 devices, or VrefDqR2Nib6 for x8 devices. + uint8_t VrefDqR2Nib8; // Byte offset 0xb6, CSR Addr 0x5405b, Direction=InOut + // VrefDq for rank 2 nibble 8. Specifies MR6[6:0] + uint8_t VrefDqR2Nib9; // Byte offset 0xb7, CSR Addr 0x5405b, Direction=InOut + // VrefDq for rank 2 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR2Nib8 for x8 or x16 devices. + uint8_t VrefDqR2Nib10; // Byte offset 0xb8, CSR Addr 0x5405c, Direction=InOut + // VrefDq for rank 2 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR2Nib8 for x16 devices. + uint8_t VrefDqR2Nib11; // Byte offset 0xb9, CSR Addr 0x5405c, Direction=InOut + // VrefDq for rank 2 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR2Nib8 for x16 devices, or VrefDqR2Nib10 for x8 devices. + uint8_t VrefDqR2Nib12; // Byte offset 0xba, CSR Addr 0x5405d, Direction=InOut + // VrefDq for rank 2 nibble 12. Specifies MR6[6:0] + uint8_t VrefDqR2Nib13; // Byte offset 0xbb, CSR Addr 0x5405d, Direction=InOut + // VrefDq for rank 2 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR2Nib12 for x8 or x16 devices. + uint8_t VrefDqR2Nib14; // Byte offset 0xbc, CSR Addr 0x5405e, Direction=InOut + // VrefDq for rank 2 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR2Nib12 for x16 devices. + uint8_t VrefDqR2Nib15; // Byte offset 0xbd, CSR Addr 0x5405e, Direction=InOut + // VrefDq for rank 2 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR2Nib12 for x16 devices, or VrefDqR2Nib14 for x8 devices. + uint8_t VrefDqR2Nib16; // Byte offset 0xbe, CSR Addr 0x5405f, Direction=InOut + // VrefDq for rank 2 nibble 16. Specifies MR6[6:0] + uint8_t VrefDqR2Nib17; // Byte offset 0xbf, CSR Addr 0x5405f, Direction=InOut + // VrefDq for rank 2 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR2Nib16 for x8 or x16 devices. + uint8_t VrefDqR2Nib18; // Byte offset 0xc0, CSR Addr 0x54060, Direction=InOut + // VrefDq for rank 2 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR2Nib16 for x16 devices. + uint8_t VrefDqR2Nib19; // Byte offset 0xc1, CSR Addr 0x54060, Direction=InOut + // VrefDq for rank 2 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR2Nib16 for x16 devices, or VrefDqR2Nib18 for x8 devices. + uint8_t VrefDqR3Nib0; // Byte offset 0xc2, CSR Addr 0x54061, Direction=InOut + // VrefDq for rank 3 nibble 0. Specifies MR6[6:0] + uint8_t VrefDqR3Nib1; // Byte offset 0xc3, CSR Addr 0x54061, Direction=InOut + // VrefDq for rank 3 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR3Nib0 for x8 or x16 devices. + uint8_t VrefDqR3Nib2; // Byte offset 0xc4, CSR Addr 0x54062, Direction=InOut + // VrefDq for rank 3 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR3Nib0 for x16 devices. + uint8_t VrefDqR3Nib3; // Byte offset 0xc5, CSR Addr 0x54062, Direction=InOut + // VrefDq for rank 3 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR3Nib0 for x16 devices, or VrefDqR3Nib2 for x8 devices. + uint8_t VrefDqR3Nib4; // Byte offset 0xc6, CSR Addr 0x54063, Direction=InOut + // VrefDq for rank 3 nibble 4. Specifies MR6[6:0] + uint8_t VrefDqR3Nib5; // Byte offset 0xc7, CSR Addr 0x54063, Direction=InOut + // VrefDq for rank 3 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR3Nib4 for x8 or x16 devices. + uint8_t VrefDqR3Nib6; // Byte offset 0xc8, CSR Addr 0x54064, Direction=InOut + // VrefDq for rank 3 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR3Nib4 for x16 devices. + uint8_t VrefDqR3Nib7; // Byte offset 0xc9, CSR Addr 0x54064, Direction=InOut + // VrefDq for rank 3 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR3Nib4 for x16 devices, or VrefDqR3Nib6 for x8 devices. + uint8_t VrefDqR3Nib8; // Byte offset 0xca, CSR Addr 0x54065, Direction=InOut + // VrefDq for rank 3 nibble 8. Specifies MR6[6:0] + uint8_t VrefDqR3Nib9; // Byte offset 0xcb, CSR Addr 0x54065, Direction=InOut + // VrefDq for rank 3 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR3Nib8 for x8 or x16 devices. + uint8_t VrefDqR3Nib10; // Byte offset 0xcc, CSR Addr 0x54066, Direction=InOut + // VrefDq for rank 3 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR3Nib8 for x16 devices. + uint8_t VrefDqR3Nib11; // Byte offset 0xcd, CSR Addr 0x54066, Direction=InOut + // VrefDq for rank 3 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR3Nib8 for x16 devices, or VrefDqR3Nib10 for x8 devices. + uint8_t VrefDqR3Nib12; // Byte offset 0xce, CSR Addr 0x54067, Direction=InOut + // VrefDq for rank 3 nibble 12. Specifies MR6[6:0] + uint8_t VrefDqR3Nib13; // Byte offset 0xcf, CSR Addr 0x54067, Direction=InOut + // VrefDq for rank 3 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR3Nib12 for x8 or x16 devices. + uint8_t VrefDqR3Nib14; // Byte offset 0xd0, CSR Addr 0x54068, Direction=InOut + // VrefDq for rank 3 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR3Nib12 for x16 devices. + uint8_t VrefDqR3Nib15; // Byte offset 0xd1, CSR Addr 0x54068, Direction=InOut + // VrefDq for rank 3 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR3Nib12 for x16 devices, or VrefDqR3Nib14 for x8 devices. + uint8_t VrefDqR3Nib16; // Byte offset 0xd2, CSR Addr 0x54069, Direction=InOut + // VrefDq for rank 3 nibble 16. Specifies MR6[6:0] + uint8_t VrefDqR3Nib17; // Byte offset 0xd3, CSR Addr 0x54069, Direction=InOut + // VrefDq for rank 3 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR3Nib16 for x8 or x16 devices. + uint8_t VrefDqR3Nib18; // Byte offset 0xd4, CSR Addr 0x5406a, Direction=InOut + // VrefDq for rank 3 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR3Nib16 for x16 devices. + uint8_t VrefDqR3Nib19; // Byte offset 0xd5, CSR Addr 0x5406a, Direction=InOut + // VrefDq for rank 3 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR3Nib16 for x16 devices, or VrefDqR3Nib18 for x8 devices. + uint8_t ReservedD6; // Byte offset 0xd6, CSR Addr 0x5406b, Direction=N/A + + uint8_t ReservedD7; // Byte offset 0xd7, CSR Addr 0x5406b, Direction=N/A + + uint8_t ReservedD8; // Byte offset 0xd8, CSR Addr 0x5406c, Direction=N/A + + uint8_t ReservedD9; // Byte offset 0xd9, CSR Addr 0x5406c, Direction=N/A + + uint8_t ReservedDA; // Byte offset 0xda, CSR Addr 0x5406d, Direction=N/A + + uint8_t ReservedDB; // Byte offset 0xdb, CSR Addr 0x5406d, Direction=N/A + + uint8_t ReservedDC; // Byte offset 0xdc, CSR Addr 0x5406e, Direction=N/A + + uint8_t ReservedDD; // Byte offset 0xdd, CSR Addr 0x5406e, Direction=N/A + + uint8_t ReservedDE; // Byte offset 0xde, CSR Addr 0x5406f, Direction=N/A + + uint8_t ReservedDF; // Byte offset 0xdf, CSR Addr 0x5406f, Direction=N/A + + uint8_t ReservedE0; // Byte offset 0xe0, CSR Addr 0x54070, Direction=N/A + + uint8_t ReservedE1; // Byte offset 0xe1, CSR Addr 0x54070, Direction=N/A + + uint8_t ReservedE2; // Byte offset 0xe2, CSR Addr 0x54071, Direction=N/A + + uint8_t ReservedE3; // Byte offset 0xe3, CSR Addr 0x54071, Direction=N/A + + uint8_t ReservedE4; // Byte offset 0xe4, CSR Addr 0x54072, Direction=N/A + + uint8_t ReservedE5; // Byte offset 0xe5, CSR Addr 0x54072, Direction=N/A + + uint8_t ReservedE6; // Byte offset 0xe6, CSR Addr 0x54073, Direction=N/A + + uint8_t ReservedE7; // Byte offset 0xe7, CSR Addr 0x54073, Direction=N/A + + uint8_t ReservedE8; // Byte offset 0xe8, CSR Addr 0x54074, Direction=N/A + + uint8_t ReservedE9; // Byte offset 0xe9, CSR Addr 0x54074, Direction=N/A + + uint8_t ReservedEA; // Byte offset 0xea, CSR Addr 0x54075, Direction=N/A + + uint8_t ReservedEB; // Byte offset 0xeb, CSR Addr 0x54075, Direction=N/A + + uint8_t ReservedEC; // Byte offset 0xec, CSR Addr 0x54076, Direction=N/A + + uint8_t ReservedED; // Byte offset 0xed, CSR Addr 0x54076, Direction=N/A + + uint8_t ReservedEE; // Byte offset 0xee, CSR Addr 0x54077, Direction=N/A + + uint8_t ReservedEF; // Byte offset 0xef, CSR Addr 0x54077, Direction=N/A + + uint8_t ReservedF0; // Byte offset 0xf0, CSR Addr 0x54078, Direction=N/A + + uint8_t ReservedF1; // Byte offset 0xf1, CSR Addr 0x54078, Direction=N/A + + uint8_t ReservedF2; // Byte offset 0xf2, CSR Addr 0x54079, Direction=N/A + + uint8_t ReservedF3; // Byte offset 0xf3, CSR Addr 0x54079, Direction=N/A + + uint8_t ReservedF4; // Byte offset 0xf4, CSR Addr 0x5407a, Direction=N/A + + uint8_t ReservedF5; // Byte offset 0xf5, CSR Addr 0x5407a, Direction=N/A + + uint8_t ReservedF6; // Byte offset 0xf6, CSR Addr 0x5407b, Direction=N/A + + uint8_t ReservedF7; // Byte offset 0xf7, CSR Addr 0x5407b, Direction=N/A + + uint8_t ReservedF8; // Byte offset 0xf8, CSR Addr 0x5407c, Direction=N/A + + uint8_t ReservedF9; // Byte offset 0xf9, CSR Addr 0x5407c, Direction=N/A + + uint8_t ReservedFA; // Byte offset 0xfa, CSR Addr 0x5407d, Direction=N/A + + uint8_t ReservedFB; // Byte offset 0xfb, CSR Addr 0x5407d, Direction=N/A + + uint8_t ReservedFC; // Byte offset 0xfc, CSR Addr 0x5407e, Direction=N/A + + uint8_t ReservedFD; // Byte offset 0xfd, CSR Addr 0x5407e, Direction=N/A + + uint8_t ReservedFE; // Byte offset 0xfe, CSR Addr 0x5407f, Direction=N/A + + uint8_t ReservedFF; // Byte offset 0xff, CSR Addr 0x5407f, Direction=N/A + + uint8_t Reserved100; // Byte offset 0x100, CSR Addr 0x54080, Direction=N/A + + uint8_t Reserved101; // Byte offset 0x101, CSR Addr 0x54080, Direction=N/A + + uint8_t Reserved102; // Byte offset 0x102, CSR Addr 0x54081, Direction=N/A + + uint8_t Reserved103; // Byte offset 0x103, CSR Addr 0x54081, Direction=N/A + + uint8_t Reserved104; // Byte offset 0x104, CSR Addr 0x54082, Direction=N/A + + uint8_t Reserved105; // Byte offset 0x105, CSR Addr 0x54082, Direction=N/A + + uint8_t Reserved106; // Byte offset 0x106, CSR Addr 0x54083, Direction=N/A + + uint8_t Reserved107; // Byte offset 0x107, CSR Addr 0x54083, Direction=N/A + + uint8_t Reserved108; // Byte offset 0x108, CSR Addr 0x54084, Direction=N/A + + uint8_t Reserved109; // Byte offset 0x109, CSR Addr 0x54084, Direction=N/A + + uint8_t Reserved10A; // Byte offset 0x10a, CSR Addr 0x54085, Direction=N/A + + uint8_t Reserved10B; // Byte offset 0x10b, CSR Addr 0x54085, Direction=N/A + + uint8_t Reserved10C; // Byte offset 0x10c, CSR Addr 0x54086, Direction=N/A + + uint8_t Reserved10D; // Byte offset 0x10d, CSR Addr 0x54086, Direction=N/A + + uint8_t Reserved10E; // Byte offset 0x10e, CSR Addr 0x54087, Direction=N/A + + uint8_t Reserved10F; // Byte offset 0x10f, CSR Addr 0x54087, Direction=N/A + + uint8_t Reserved110; // Byte offset 0x110, CSR Addr 0x54088, Direction=N/A + + uint8_t Reserved111; // Byte offset 0x111, CSR Addr 0x54088, Direction=N/A + + uint8_t Reserved112; // Byte offset 0x112, CSR Addr 0x54089, Direction=N/A + + uint8_t Reserved113; // Byte offset 0x113, CSR Addr 0x54089, Direction=N/A + + uint8_t Reserved114; // Byte offset 0x114, CSR Addr 0x5408a, Direction=N/A + + uint8_t Reserved115; // Byte offset 0x115, CSR Addr 0x5408a, Direction=N/A + + uint8_t Reserved116; // Byte offset 0x116, CSR Addr 0x5408b, Direction=N/A + + uint8_t Reserved117; // Byte offset 0x117, CSR Addr 0x5408b, Direction=N/A + + uint8_t Reserved118; // Byte offset 0x118, CSR Addr 0x5408c, Direction=N/A + + uint8_t Reserved119; // Byte offset 0x119, CSR Addr 0x5408c, Direction=N/A + + uint8_t Reserved11A; // Byte offset 0x11a, CSR Addr 0x5408d, Direction=N/A + + uint8_t Reserved11B; // Byte offset 0x11b, CSR Addr 0x5408d, Direction=N/A + + uint8_t Reserved11C; // Byte offset 0x11c, CSR Addr 0x5408e, Direction=N/A + + uint8_t Reserved11D; // Byte offset 0x11d, CSR Addr 0x5408e, Direction=N/A + + uint8_t Reserved11E; // Byte offset 0x11e, CSR Addr 0x5408f, Direction=N/A + + uint8_t Reserved11F; // Byte offset 0x11f, CSR Addr 0x5408f, Direction=N/A + + uint8_t Reserved120; // Byte offset 0x120, CSR Addr 0x54090, Direction=N/A + + uint8_t Reserved121; // Byte offset 0x121, CSR Addr 0x54090, Direction=N/A + + uint8_t Reserved122; // Byte offset 0x122, CSR Addr 0x54091, Direction=N/A + + uint8_t Reserved123; // Byte offset 0x123, CSR Addr 0x54091, Direction=N/A + + uint8_t Reserved124; // Byte offset 0x124, CSR Addr 0x54092, Direction=N/A + + uint8_t Reserved125; // Byte offset 0x125, CSR Addr 0x54092, Direction=N/A + + uint8_t Reserved126; // Byte offset 0x126, CSR Addr 0x54093, Direction=N/A + + uint8_t Reserved127; // Byte offset 0x127, CSR Addr 0x54093, Direction=N/A + + uint8_t Reserved128; // Byte offset 0x128, CSR Addr 0x54094, Direction=N/A + + uint8_t Reserved129; // Byte offset 0x129, CSR Addr 0x54094, Direction=N/A + + uint8_t Reserved12A; // Byte offset 0x12a, CSR Addr 0x54095, Direction=N/A + + uint8_t Reserved12B; // Byte offset 0x12b, CSR Addr 0x54095, Direction=N/A + + uint8_t Reserved12C; // Byte offset 0x12c, CSR Addr 0x54096, Direction=N/A + + uint8_t Reserved12D; // Byte offset 0x12d, CSR Addr 0x54096, Direction=N/A + + uint8_t Reserved12E; // Byte offset 0x12e, CSR Addr 0x54097, Direction=N/A + + uint8_t Reserved12F; // Byte offset 0x12f, CSR Addr 0x54097, Direction=N/A + + uint8_t Reserved130; // Byte offset 0x130, CSR Addr 0x54098, Direction=N/A + + uint8_t Reserved131; // Byte offset 0x131, CSR Addr 0x54098, Direction=N/A + + uint8_t Reserved132; // Byte offset 0x132, CSR Addr 0x54099, Direction=N/A + + uint8_t Reserved133; // Byte offset 0x133, CSR Addr 0x54099, Direction=N/A + + uint8_t Reserved134; // Byte offset 0x134, CSR Addr 0x5409a, Direction=N/A + + uint8_t Reserved135; // Byte offset 0x135, CSR Addr 0x5409a, Direction=N/A + + uint8_t Reserved136; // Byte offset 0x136, CSR Addr 0x5409b, Direction=N/A + + uint8_t Reserved137; // Byte offset 0x137, CSR Addr 0x5409b, Direction=N/A + + uint8_t Reserved138; // Byte offset 0x138, CSR Addr 0x5409c, Direction=N/A + + uint8_t Reserved139; // Byte offset 0x139, CSR Addr 0x5409c, Direction=N/A + + uint8_t Reserved13A; // Byte offset 0x13a, CSR Addr 0x5409d, Direction=N/A + + uint8_t Reserved13B; // Byte offset 0x13b, CSR Addr 0x5409d, Direction=N/A + + uint8_t Reserved13C; // Byte offset 0x13c, CSR Addr 0x5409e, Direction=N/A + + uint8_t Reserved13D; // Byte offset 0x13d, CSR Addr 0x5409e, Direction=N/A + + uint8_t Reserved13E; // Byte offset 0x13e, CSR Addr 0x5409f, Direction=N/A + + uint8_t Reserved13F; // Byte offset 0x13f, CSR Addr 0x5409f, Direction=N/A + + uint8_t Reserved140; // Byte offset 0x140, CSR Addr 0x540a0, Direction=N/A + + uint8_t Reserved141; // Byte offset 0x141, CSR Addr 0x540a0, Direction=N/A + + uint8_t Reserved142; // Byte offset 0x142, CSR Addr 0x540a1, Direction=N/A + + uint8_t Reserved143; // Byte offset 0x143, CSR Addr 0x540a1, Direction=N/A + + uint8_t Reserved144; // Byte offset 0x144, CSR Addr 0x540a2, Direction=N/A + + uint8_t Reserved145; // Byte offset 0x145, CSR Addr 0x540a2, Direction=N/A + + uint8_t Reserved146; // Byte offset 0x146, CSR Addr 0x540a3, Direction=N/A + + uint8_t Reserved147; // Byte offset 0x147, CSR Addr 0x540a3, Direction=N/A + + uint8_t Reserved148; // Byte offset 0x148, CSR Addr 0x540a4, Direction=N/A + + uint8_t Reserved149; // Byte offset 0x149, CSR Addr 0x540a4, Direction=N/A + + uint8_t Reserved14A; // Byte offset 0x14a, CSR Addr 0x540a5, Direction=N/A + + uint8_t Reserved14B; // Byte offset 0x14b, CSR Addr 0x540a5, Direction=N/A + + uint8_t Reserved14C; // Byte offset 0x14c, CSR Addr 0x540a6, Direction=N/A + + uint8_t Reserved14D; // Byte offset 0x14d, CSR Addr 0x540a6, Direction=N/A + + uint8_t Reserved14E; // Byte offset 0x14e, CSR Addr 0x540a7, Direction=N/A + + uint8_t Reserved14F; // Byte offset 0x14f, CSR Addr 0x540a7, Direction=N/A + + uint8_t Reserved150; // Byte offset 0x150, CSR Addr 0x540a8, Direction=N/A + + uint8_t Reserved151; // Byte offset 0x151, CSR Addr 0x540a8, Direction=N/A + + uint8_t Reserved152; // Byte offset 0x152, CSR Addr 0x540a9, Direction=N/A + + uint8_t Reserved153; // Byte offset 0x153, CSR Addr 0x540a9, Direction=N/A + + uint8_t Reserved154; // Byte offset 0x154, CSR Addr 0x540aa, Direction=N/A + + uint8_t Reserved155; // Byte offset 0x155, CSR Addr 0x540aa, Direction=N/A + + uint8_t Reserved156; // Byte offset 0x156, CSR Addr 0x540ab, Direction=N/A + + uint8_t Reserved157; // Byte offset 0x157, CSR Addr 0x540ab, Direction=N/A + + uint8_t Reserved158; // Byte offset 0x158, CSR Addr 0x540ac, Direction=N/A + + uint8_t Reserved159; // Byte offset 0x159, CSR Addr 0x540ac, Direction=N/A + + uint8_t Reserved15A; // Byte offset 0x15a, CSR Addr 0x540ad, Direction=N/A + + uint8_t Reserved15B; // Byte offset 0x15b, CSR Addr 0x540ad, Direction=N/A + + uint8_t Reserved15C; // Byte offset 0x15c, CSR Addr 0x540ae, Direction=N/A + + uint8_t Reserved15D; // Byte offset 0x15d, CSR Addr 0x540ae, Direction=N/A + + uint8_t Reserved15E; // Byte offset 0x15e, CSR Addr 0x540af, Direction=N/A + + uint8_t Reserved15F; // Byte offset 0x15f, CSR Addr 0x540af, Direction=N/A + + uint8_t Reserved160; // Byte offset 0x160, CSR Addr 0x540b0, Direction=N/A + + uint8_t Reserved161; // Byte offset 0x161, CSR Addr 0x540b0, Direction=N/A + + uint8_t Reserved162; // Byte offset 0x162, CSR Addr 0x540b1, Direction=N/A + + uint8_t Reserved163; // Byte offset 0x163, CSR Addr 0x540b1, Direction=N/A + + uint8_t Reserved164; // Byte offset 0x164, CSR Addr 0x540b2, Direction=N/A + + uint8_t Reserved165; // Byte offset 0x165, CSR Addr 0x540b2, Direction=N/A + + uint8_t Reserved166; // Byte offset 0x166, CSR Addr 0x540b3, Direction=N/A + + uint8_t Reserved167; // Byte offset 0x167, CSR Addr 0x540b3, Direction=N/A + + uint8_t Reserved168; // Byte offset 0x168, CSR Addr 0x540b4, Direction=N/A + + uint8_t Reserved169; // Byte offset 0x169, CSR Addr 0x540b4, Direction=N/A + + uint8_t Reserved16A; // Byte offset 0x16a, CSR Addr 0x540b5, Direction=N/A + + uint8_t Reserved16B; // Byte offset 0x16b, CSR Addr 0x540b5, Direction=N/A + + uint8_t Reserved16C; // Byte offset 0x16c, CSR Addr 0x540b6, Direction=N/A + + uint8_t Reserved16D; // Byte offset 0x16d, CSR Addr 0x540b6, Direction=N/A + + uint8_t Reserved16E; // Byte offset 0x16e, CSR Addr 0x540b7, Direction=N/A + + uint8_t Reserved16F; // Byte offset 0x16f, CSR Addr 0x540b7, Direction=N/A + + uint8_t Reserved170; // Byte offset 0x170, CSR Addr 0x540b8, Direction=N/A + + uint8_t Reserved171; // Byte offset 0x171, CSR Addr 0x540b8, Direction=N/A + + uint8_t Reserved172; // Byte offset 0x172, CSR Addr 0x540b9, Direction=N/A + + uint8_t Reserved173; // Byte offset 0x173, CSR Addr 0x540b9, Direction=N/A + + uint8_t Reserved174; // Byte offset 0x174, CSR Addr 0x540ba, Direction=N/A + + uint8_t Reserved175; // Byte offset 0x175, CSR Addr 0x540ba, Direction=N/A + + uint8_t Reserved176; // Byte offset 0x176, CSR Addr 0x540bb, Direction=N/A + + uint8_t Reserved177; // Byte offset 0x177, CSR Addr 0x540bb, Direction=N/A + + uint8_t Reserved178; // Byte offset 0x178, CSR Addr 0x540bc, Direction=N/A + + uint8_t Reserved179; // Byte offset 0x179, CSR Addr 0x540bc, Direction=N/A + + uint8_t Reserved17A; // Byte offset 0x17a, CSR Addr 0x540bd, Direction=N/A + + uint8_t Reserved17B; // Byte offset 0x17b, CSR Addr 0x540bd, Direction=N/A + + uint8_t Reserved17C; // Byte offset 0x17c, CSR Addr 0x540be, Direction=N/A + + uint8_t Reserved17D; // Byte offset 0x17d, CSR Addr 0x540be, Direction=N/A + + uint8_t Reserved17E; // Byte offset 0x17e, CSR Addr 0x540bf, Direction=N/A + + uint8_t Reserved17F; // Byte offset 0x17f, CSR Addr 0x540bf, Direction=N/A + + uint8_t Reserved180; // Byte offset 0x180, CSR Addr 0x540c0, Direction=N/A + + uint8_t Reserved181; // Byte offset 0x181, CSR Addr 0x540c0, Direction=N/A + + uint8_t Reserved182; // Byte offset 0x182, CSR Addr 0x540c1, Direction=N/A + + uint8_t Reserved183; // Byte offset 0x183, CSR Addr 0x540c1, Direction=N/A + + uint8_t Reserved184; // Byte offset 0x184, CSR Addr 0x540c2, Direction=N/A + + uint8_t Reserved185; // Byte offset 0x185, CSR Addr 0x540c2, Direction=N/A + + uint8_t Reserved186; // Byte offset 0x186, CSR Addr 0x540c3, Direction=N/A + + uint8_t Reserved187; // Byte offset 0x187, CSR Addr 0x540c3, Direction=N/A + + uint8_t Reserved188; // Byte offset 0x188, CSR Addr 0x540c4, Direction=N/A + + uint8_t Reserved189; // Byte offset 0x189, CSR Addr 0x540c4, Direction=N/A + + uint8_t Reserved18A; // Byte offset 0x18a, CSR Addr 0x540c5, Direction=N/A + + uint8_t Reserved18B; // Byte offset 0x18b, CSR Addr 0x540c5, Direction=N/A + + uint8_t Reserved18C; // Byte offset 0x18c, CSR Addr 0x540c6, Direction=N/A + + uint8_t Reserved18D; // Byte offset 0x18d, CSR Addr 0x540c6, Direction=N/A + + uint8_t Reserved18E; // Byte offset 0x18e, CSR Addr 0x540c7, Direction=N/A + + uint8_t Reserved18F; // Byte offset 0x18f, CSR Addr 0x540c7, Direction=N/A + + uint8_t Reserved190; // Byte offset 0x190, CSR Addr 0x540c8, Direction=N/A + + uint8_t Reserved191; // Byte offset 0x191, CSR Addr 0x540c8, Direction=N/A + + uint8_t Reserved192; // Byte offset 0x192, CSR Addr 0x540c9, Direction=N/A + + uint8_t Reserved193; // Byte offset 0x193, CSR Addr 0x540c9, Direction=N/A + + uint8_t Reserved194; // Byte offset 0x194, CSR Addr 0x540ca, Direction=N/A + + uint8_t Reserved195; // Byte offset 0x195, CSR Addr 0x540ca, Direction=N/A + + uint8_t Reserved196; // Byte offset 0x196, CSR Addr 0x540cb, Direction=N/A + + uint8_t Reserved197; // Byte offset 0x197, CSR Addr 0x540cb, Direction=N/A + + uint8_t Reserved198; // Byte offset 0x198, CSR Addr 0x540cc, Direction=N/A + + uint8_t Reserved199; // Byte offset 0x199, CSR Addr 0x540cc, Direction=N/A + + uint8_t Reserved19A; // Byte offset 0x19a, CSR Addr 0x540cd, Direction=N/A + + uint8_t Reserved19B; // Byte offset 0x19b, CSR Addr 0x540cd, Direction=N/A + + uint8_t Reserved19C; // Byte offset 0x19c, CSR Addr 0x540ce, Direction=N/A + + uint8_t Reserved19D; // Byte offset 0x19d, CSR Addr 0x540ce, Direction=N/A + + uint8_t Reserved19E; // Byte offset 0x19e, CSR Addr 0x540cf, Direction=N/A + + uint8_t Reserved19F; // Byte offset 0x19f, CSR Addr 0x540cf, Direction=N/A + + uint8_t Reserved1A0; // Byte offset 0x1a0, CSR Addr 0x540d0, Direction=N/A + + uint8_t Reserved1A1; // Byte offset 0x1a1, CSR Addr 0x540d0, Direction=N/A + + uint8_t Reserved1A2; // Byte offset 0x1a2, CSR Addr 0x540d1, Direction=N/A + + uint8_t Reserved1A3; // Byte offset 0x1a3, CSR Addr 0x540d1, Direction=N/A + + uint8_t Reserved1A4; // Byte offset 0x1a4, CSR Addr 0x540d2, Direction=N/A + + uint8_t Reserved1A5; // Byte offset 0x1a5, CSR Addr 0x540d2, Direction=N/A + + uint8_t Reserved1A6; // Byte offset 0x1a6, CSR Addr 0x540d3, Direction=N/A + + uint8_t Reserved1A7; // Byte offset 0x1a7, CSR Addr 0x540d3, Direction=N/A + + uint8_t Reserved1A8; // Byte offset 0x1a8, CSR Addr 0x540d4, Direction=N/A + + uint8_t Reserved1A9; // Byte offset 0x1a9, CSR Addr 0x540d4, Direction=N/A + + uint8_t Reserved1AA; // Byte offset 0x1aa, CSR Addr 0x540d5, Direction=N/A + + uint8_t Reserved1AB; // Byte offset 0x1ab, CSR Addr 0x540d5, Direction=N/A + + uint8_t Reserved1AC; // Byte offset 0x1ac, CSR Addr 0x540d6, Direction=N/A + + uint8_t Reserved1AD; // Byte offset 0x1ad, CSR Addr 0x540d6, Direction=N/A + + uint8_t Reserved1AE; // Byte offset 0x1ae, CSR Addr 0x540d7, Direction=N/A + + uint8_t Reserved1AF; // Byte offset 0x1af, CSR Addr 0x540d7, Direction=N/A + + uint8_t Reserved1B0; // Byte offset 0x1b0, CSR Addr 0x540d8, Direction=N/A + + uint8_t Reserved1B1; // Byte offset 0x1b1, CSR Addr 0x540d8, Direction=N/A + + uint8_t Reserved1B2; // Byte offset 0x1b2, CSR Addr 0x540d9, Direction=N/A + + uint8_t Reserved1B3; // Byte offset 0x1b3, CSR Addr 0x540d9, Direction=N/A + + uint8_t Reserved1B4; // Byte offset 0x1b4, CSR Addr 0x540da, Direction=N/A + + uint8_t Reserved1B5; // Byte offset 0x1b5, CSR Addr 0x540da, Direction=N/A + + uint8_t Reserved1B6; // Byte offset 0x1b6, CSR Addr 0x540db, Direction=N/A + + uint8_t Reserved1B7; // Byte offset 0x1b7, CSR Addr 0x540db, Direction=N/A + + uint8_t Reserved1B8; // Byte offset 0x1b8, CSR Addr 0x540dc, Direction=N/A + + uint8_t Reserved1B9; // Byte offset 0x1b9, CSR Addr 0x540dc, Direction=N/A + + uint8_t Reserved1BA; // Byte offset 0x1ba, CSR Addr 0x540dd, Direction=N/A + + uint8_t Reserved1BB; // Byte offset 0x1bb, CSR Addr 0x540dd, Direction=N/A + + uint8_t Reserved1BC; // Byte offset 0x1bc, CSR Addr 0x540de, Direction=N/A + + uint8_t Reserved1BD; // Byte offset 0x1bd, CSR Addr 0x540de, Direction=N/A + + uint8_t Reserved1BE; // Byte offset 0x1be, CSR Addr 0x540df, Direction=N/A + + uint8_t Reserved1BF; // Byte offset 0x1bf, CSR Addr 0x540df, Direction=N/A + + uint8_t Reserved1C0; // Byte offset 0x1c0, CSR Addr 0x540e0, Direction=N/A + + uint8_t Reserved1C1; // Byte offset 0x1c1, CSR Addr 0x540e0, Direction=N/A + + uint8_t Reserved1C2; // Byte offset 0x1c2, CSR Addr 0x540e1, Direction=N/A + + uint8_t Reserved1C3; // Byte offset 0x1c3, CSR Addr 0x540e1, Direction=N/A + + uint8_t Reserved1C4; // Byte offset 0x1c4, CSR Addr 0x540e2, Direction=N/A + + uint8_t Reserved1C5; // Byte offset 0x1c5, CSR Addr 0x540e2, Direction=N/A + + uint8_t Reserved1C6; // Byte offset 0x1c6, CSR Addr 0x540e3, Direction=N/A + + uint8_t Reserved1C7; // Byte offset 0x1c7, CSR Addr 0x540e3, Direction=N/A + + uint8_t Reserved1C8; // Byte offset 0x1c8, CSR Addr 0x540e4, Direction=N/A + + uint8_t Reserved1C9; // Byte offset 0x1c9, CSR Addr 0x540e4, Direction=N/A + + uint8_t Reserved1CA; // Byte offset 0x1ca, CSR Addr 0x540e5, Direction=N/A + + uint8_t Reserved1CB; // Byte offset 0x1cb, CSR Addr 0x540e5, Direction=N/A + + uint8_t Reserved1CC; // Byte offset 0x1cc, CSR Addr 0x540e6, Direction=N/A + + uint8_t Reserved1CD; // Byte offset 0x1cd, CSR Addr 0x540e6, Direction=N/A + + uint8_t Reserved1CE; // Byte offset 0x1ce, CSR Addr 0x540e7, Direction=N/A + + uint8_t Reserved1CF; // Byte offset 0x1cf, CSR Addr 0x540e7, Direction=N/A + + uint8_t Reserved1D0; // Byte offset 0x1d0, CSR Addr 0x540e8, Direction=N/A + + uint8_t Reserved1D1; // Byte offset 0x1d1, CSR Addr 0x540e8, Direction=N/A + + uint8_t Reserved1D2; // Byte offset 0x1d2, CSR Addr 0x540e9, Direction=N/A + + uint8_t Reserved1D3; // Byte offset 0x1d3, CSR Addr 0x540e9, Direction=N/A + + uint8_t Reserved1D4; // Byte offset 0x1d4, CSR Addr 0x540ea, Direction=N/A + + uint8_t Reserved1D5; // Byte offset 0x1d5, CSR Addr 0x540ea, Direction=N/A + + uint8_t Reserved1D6; // Byte offset 0x1d6, CSR Addr 0x540eb, Direction=N/A + + uint8_t Reserved1D7; // Byte offset 0x1d7, CSR Addr 0x540eb, Direction=N/A + + uint8_t Reserved1D8; // Byte offset 0x1d8, CSR Addr 0x540ec, Direction=N/A + + uint8_t Reserved1D9; // Byte offset 0x1d9, CSR Addr 0x540ec, Direction=N/A + + uint8_t Reserved1DA; // Byte offset 0x1da, CSR Addr 0x540ed, Direction=N/A + + uint8_t Reserved1DB; // Byte offset 0x1db, CSR Addr 0x540ed, Direction=N/A + + uint8_t Reserved1DC; // Byte offset 0x1dc, CSR Addr 0x540ee, Direction=N/A + + uint8_t Reserved1DD; // Byte offset 0x1dd, CSR Addr 0x540ee, Direction=N/A + + uint8_t Reserved1DE; // Byte offset 0x1de, CSR Addr 0x540ef, Direction=N/A + + uint8_t Reserved1DF; // Byte offset 0x1df, CSR Addr 0x540ef, Direction=N/A + + uint8_t Reserved1E0; // Byte offset 0x1e0, CSR Addr 0x540f0, Direction=N/A + + uint8_t Reserved1E1; // Byte offset 0x1e1, CSR Addr 0x540f0, Direction=N/A + + uint8_t Reserved1E2; // Byte offset 0x1e2, CSR Addr 0x540f1, Direction=N/A + + uint8_t Reserved1E3; // Byte offset 0x1e3, CSR Addr 0x540f1, Direction=N/A + + uint8_t Reserved1E4; // Byte offset 0x1e4, CSR Addr 0x540f2, Direction=N/A + + uint8_t Reserved1E5; // Byte offset 0x1e5, CSR Addr 0x540f2, Direction=N/A + + uint8_t Reserved1E6; // Byte offset 0x1e6, CSR Addr 0x540f3, Direction=N/A + + uint8_t Reserved1E7; // Byte offset 0x1e7, CSR Addr 0x540f3, Direction=N/A + + uint8_t Reserved1E8; // Byte offset 0x1e8, CSR Addr 0x540f4, Direction=N/A + + uint8_t Reserved1E9; // Byte offset 0x1e9, CSR Addr 0x540f4, Direction=N/A + + uint8_t Reserved1EA; // Byte offset 0x1ea, CSR Addr 0x540f5, Direction=N/A + + uint8_t Reserved1EB; // Byte offset 0x1eb, CSR Addr 0x540f5, Direction=N/A + + uint8_t Reserved1EC; // Byte offset 0x1ec, CSR Addr 0x540f6, Direction=N/A + + uint8_t Reserved1ED; // Byte offset 0x1ed, CSR Addr 0x540f6, Direction=N/A + + uint8_t Reserved1EE; // Byte offset 0x1ee, CSR Addr 0x540f7, Direction=N/A + + uint8_t Reserved1EF; // Byte offset 0x1ef, CSR Addr 0x540f7, Direction=N/A + + uint8_t Reserved1F0; // Byte offset 0x1f0, CSR Addr 0x540f8, Direction=N/A + + uint8_t Reserved1F1; // Byte offset 0x1f1, CSR Addr 0x540f8, Direction=N/A + + uint8_t Reserved1F2; // Byte offset 0x1f2, CSR Addr 0x540f9, Direction=N/A + + uint8_t Reserved1F3; // Byte offset 0x1f3, CSR Addr 0x540f9, Direction=N/A + + uint8_t Reserved1F4; // Byte offset 0x1f4, CSR Addr 0x540fa, Direction=N/A + + uint8_t Reserved1F5; // Byte offset 0x1f5, CSR Addr 0x540fa, Direction=N/A + + uint8_t Reserved1F6; // Byte offset 0x1f6, CSR Addr 0x540fb, Direction=N/A + + uint8_t Reserved1F7; // Byte offset 0x1f7, CSR Addr 0x540fb, Direction=N/A + + uint8_t Reserved1F8; // Byte offset 0x1f8, CSR Addr 0x540fc, Direction=N/A + + uint8_t Reserved1F9; // Byte offset 0x1f9, CSR Addr 0x540fc, Direction=N/A + + uint8_t Reserved1FA; // Byte offset 0x1fa, CSR Addr 0x540fd, Direction=N/A + + uint8_t Reserved1FB; // Byte offset 0x1fb, CSR Addr 0x540fd, Direction=N/A + + uint8_t Reserved1FC; // Byte offset 0x1fc, CSR Addr 0x540fe, Direction=N/A + + uint8_t Reserved1FD; // Byte offset 0x1fd, CSR Addr 0x540fe, Direction=N/A + + uint8_t Reserved1FE; // Byte offset 0x1fe, CSR Addr 0x540ff, Direction=N/A + + uint8_t Reserved1FF; // Byte offset 0x1ff, CSR Addr 0x540ff, Direction=N/A + + uint8_t Reserved200; // Byte offset 0x200, CSR Addr 0x54100, Direction=N/A + + uint8_t Reserved201; // Byte offset 0x201, CSR Addr 0x54100, Direction=N/A + + uint8_t Reserved202; // Byte offset 0x202, CSR Addr 0x54101, Direction=N/A + + uint8_t Reserved203; // Byte offset 0x203, CSR Addr 0x54101, Direction=N/A + + uint8_t Reserved204; // Byte offset 0x204, CSR Addr 0x54102, Direction=N/A + + uint8_t Reserved205; // Byte offset 0x205, CSR Addr 0x54102, Direction=N/A + + uint8_t Reserved206; // Byte offset 0x206, CSR Addr 0x54103, Direction=N/A + + uint8_t Reserved207; // Byte offset 0x207, CSR Addr 0x54103, Direction=N/A + + uint8_t Reserved208; // Byte offset 0x208, CSR Addr 0x54104, Direction=N/A + + uint8_t Reserved209; // Byte offset 0x209, CSR Addr 0x54104, Direction=N/A + + uint8_t Reserved20A; // Byte offset 0x20a, CSR Addr 0x54105, Direction=N/A + + uint8_t Reserved20B; // Byte offset 0x20b, CSR Addr 0x54105, Direction=N/A + + uint8_t Reserved20C; // Byte offset 0x20c, CSR Addr 0x54106, Direction=N/A + + uint8_t Reserved20D; // Byte offset 0x20d, CSR Addr 0x54106, Direction=N/A + + uint8_t Reserved20E; // Byte offset 0x20e, CSR Addr 0x54107, Direction=N/A + + uint8_t Reserved20F; // Byte offset 0x20f, CSR Addr 0x54107, Direction=N/A + + uint8_t Reserved210; // Byte offset 0x210, CSR Addr 0x54108, Direction=N/A + + uint8_t Reserved211; // Byte offset 0x211, CSR Addr 0x54108, Direction=N/A + + uint8_t Reserved212; // Byte offset 0x212, CSR Addr 0x54109, Direction=N/A + + uint8_t Reserved213; // Byte offset 0x213, CSR Addr 0x54109, Direction=N/A + + uint8_t Reserved214; // Byte offset 0x214, CSR Addr 0x5410a, Direction=N/A + + uint8_t Reserved215; // Byte offset 0x215, CSR Addr 0x5410a, Direction=N/A + + uint8_t Reserved216; // Byte offset 0x216, CSR Addr 0x5410b, Direction=N/A + + uint8_t Reserved217; // Byte offset 0x217, CSR Addr 0x5410b, Direction=N/A + + uint8_t Reserved218; // Byte offset 0x218, CSR Addr 0x5410c, Direction=N/A + + uint8_t Reserved219; // Byte offset 0x219, CSR Addr 0x5410c, Direction=N/A + + uint8_t Reserved21A; // Byte offset 0x21a, CSR Addr 0x5410d, Direction=N/A + + uint8_t Reserved21B; // Byte offset 0x21b, CSR Addr 0x5410d, Direction=N/A + + uint8_t Reserved21C; // Byte offset 0x21c, CSR Addr 0x5410e, Direction=N/A + + uint8_t Reserved21D; // Byte offset 0x21d, CSR Addr 0x5410e, Direction=N/A + + uint8_t Reserved21E; // Byte offset 0x21e, CSR Addr 0x5410f, Direction=N/A + + uint8_t Reserved21F; // Byte offset 0x21f, CSR Addr 0x5410f, Direction=N/A + + uint8_t Reserved220; // Byte offset 0x220, CSR Addr 0x54110, Direction=N/A + + uint8_t Reserved221; // Byte offset 0x221, CSR Addr 0x54110, Direction=N/A + + uint8_t Reserved222; // Byte offset 0x222, CSR Addr 0x54111, Direction=N/A + + uint8_t Reserved223; // Byte offset 0x223, CSR Addr 0x54111, Direction=N/A + + uint8_t Reserved224; // Byte offset 0x224, CSR Addr 0x54112, Direction=N/A + + uint8_t Reserved225; // Byte offset 0x225, CSR Addr 0x54112, Direction=N/A + + uint8_t Reserved226; // Byte offset 0x226, CSR Addr 0x54113, Direction=N/A + + uint8_t Reserved227; // Byte offset 0x227, CSR Addr 0x54113, Direction=N/A + + uint8_t Reserved228; // Byte offset 0x228, CSR Addr 0x54114, Direction=N/A + + uint8_t Reserved229; // Byte offset 0x229, CSR Addr 0x54114, Direction=N/A + + uint8_t Reserved22A; // Byte offset 0x22a, CSR Addr 0x54115, Direction=N/A + + uint8_t Reserved22B; // Byte offset 0x22b, CSR Addr 0x54115, Direction=N/A + + uint8_t Reserved22C; // Byte offset 0x22c, CSR Addr 0x54116, Direction=N/A + + uint8_t Reserved22D; // Byte offset 0x22d, CSR Addr 0x54116, Direction=N/A + + uint8_t Reserved22E; // Byte offset 0x22e, CSR Addr 0x54117, Direction=N/A + + uint8_t Reserved22F; // Byte offset 0x22f, CSR Addr 0x54117, Direction=N/A + + uint8_t Reserved230; // Byte offset 0x230, CSR Addr 0x54118, Direction=N/A + + uint8_t Reserved231; // Byte offset 0x231, CSR Addr 0x54118, Direction=N/A + + uint8_t Reserved232; // Byte offset 0x232, CSR Addr 0x54119, Direction=N/A + + uint8_t Reserved233; // Byte offset 0x233, CSR Addr 0x54119, Direction=N/A + + uint8_t Reserved234; // Byte offset 0x234, CSR Addr 0x5411a, Direction=N/A + + uint8_t Reserved235; // Byte offset 0x235, CSR Addr 0x5411a, Direction=N/A + + uint8_t Reserved236; // Byte offset 0x236, CSR Addr 0x5411b, Direction=N/A + + uint8_t Reserved237; // Byte offset 0x237, CSR Addr 0x5411b, Direction=N/A + + uint8_t Reserved238; // Byte offset 0x238, CSR Addr 0x5411c, Direction=N/A + + uint8_t Reserved239; // Byte offset 0x239, CSR Addr 0x5411c, Direction=N/A + + uint8_t Reserved23A; // Byte offset 0x23a, CSR Addr 0x5411d, Direction=N/A + + uint8_t Reserved23B; // Byte offset 0x23b, CSR Addr 0x5411d, Direction=N/A + + uint8_t Reserved23C; // Byte offset 0x23c, CSR Addr 0x5411e, Direction=N/A + + uint8_t Reserved23D; // Byte offset 0x23d, CSR Addr 0x5411e, Direction=N/A + + uint8_t Reserved23E; // Byte offset 0x23e, CSR Addr 0x5411f, Direction=N/A + + uint8_t Reserved23F; // Byte offset 0x23f, CSR Addr 0x5411f, Direction=N/A + + uint8_t Reserved240; // Byte offset 0x240, CSR Addr 0x54120, Direction=N/A + + uint8_t Reserved241; // Byte offset 0x241, CSR Addr 0x54120, Direction=N/A + + uint8_t Reserved242; // Byte offset 0x242, CSR Addr 0x54121, Direction=N/A + + uint8_t Reserved243; // Byte offset 0x243, CSR Addr 0x54121, Direction=N/A + + uint8_t Reserved244; // Byte offset 0x244, CSR Addr 0x54122, Direction=N/A + + uint8_t Reserved245; // Byte offset 0x245, CSR Addr 0x54122, Direction=N/A + + uint8_t Reserved246; // Byte offset 0x246, CSR Addr 0x54123, Direction=N/A + + uint8_t Reserved247; // Byte offset 0x247, CSR Addr 0x54123, Direction=N/A + + uint8_t Reserved248; // Byte offset 0x248, CSR Addr 0x54124, Direction=N/A + + uint8_t Reserved249; // Byte offset 0x249, CSR Addr 0x54124, Direction=N/A + + uint8_t Reserved24A; // Byte offset 0x24a, CSR Addr 0x54125, Direction=N/A + + uint8_t Reserved24B; // Byte offset 0x24b, CSR Addr 0x54125, Direction=N/A + + uint8_t Reserved24C; // Byte offset 0x24c, CSR Addr 0x54126, Direction=N/A + + uint8_t Reserved24D; // Byte offset 0x24d, CSR Addr 0x54126, Direction=N/A + + uint8_t Reserved24E; // Byte offset 0x24e, CSR Addr 0x54127, Direction=N/A + + uint8_t Reserved24F; // Byte offset 0x24f, CSR Addr 0x54127, Direction=N/A + + uint8_t Reserved250; // Byte offset 0x250, CSR Addr 0x54128, Direction=N/A + + uint8_t Reserved251; // Byte offset 0x251, CSR Addr 0x54128, Direction=N/A + + uint8_t Reserved252; // Byte offset 0x252, CSR Addr 0x54129, Direction=N/A + + uint8_t Reserved253; // Byte offset 0x253, CSR Addr 0x54129, Direction=N/A + + uint8_t Reserved254; // Byte offset 0x254, CSR Addr 0x5412a, Direction=N/A + + uint8_t Reserved255; // Byte offset 0x255, CSR Addr 0x5412a, Direction=N/A + + uint8_t Reserved256; // Byte offset 0x256, CSR Addr 0x5412b, Direction=N/A + + uint8_t Reserved257; // Byte offset 0x257, CSR Addr 0x5412b, Direction=N/A + + uint8_t Reserved258; // Byte offset 0x258, CSR Addr 0x5412c, Direction=N/A + + uint8_t Reserved259; // Byte offset 0x259, CSR Addr 0x5412c, Direction=N/A + + uint8_t Reserved25A; // Byte offset 0x25a, CSR Addr 0x5412d, Direction=N/A + + uint8_t Reserved25B; // Byte offset 0x25b, CSR Addr 0x5412d, Direction=N/A + + uint8_t Reserved25C; // Byte offset 0x25c, CSR Addr 0x5412e, Direction=N/A + + uint8_t Reserved25D; // Byte offset 0x25d, CSR Addr 0x5412e, Direction=N/A + + uint8_t Reserved25E; // Byte offset 0x25e, CSR Addr 0x5412f, Direction=N/A + + uint8_t Reserved25F; // Byte offset 0x25f, CSR Addr 0x5412f, Direction=N/A + + uint8_t Reserved260; // Byte offset 0x260, CSR Addr 0x54130, Direction=N/A + + uint8_t Reserved261; // Byte offset 0x261, CSR Addr 0x54130, Direction=N/A + + uint8_t Reserved262; // Byte offset 0x262, CSR Addr 0x54131, Direction=N/A + + uint8_t Reserved263; // Byte offset 0x263, CSR Addr 0x54131, Direction=N/A + + uint8_t Reserved264; // Byte offset 0x264, CSR Addr 0x54132, Direction=N/A + + uint8_t Reserved265; // Byte offset 0x265, CSR Addr 0x54132, Direction=N/A + + uint8_t Reserved266; // Byte offset 0x266, CSR Addr 0x54133, Direction=N/A + + uint8_t Reserved267; // Byte offset 0x267, CSR Addr 0x54133, Direction=N/A + + uint8_t Reserved268; // Byte offset 0x268, CSR Addr 0x54134, Direction=N/A + + uint8_t Reserved269; // Byte offset 0x269, CSR Addr 0x54134, Direction=N/A + + uint8_t Reserved26A; // Byte offset 0x26a, CSR Addr 0x54135, Direction=N/A + + uint8_t Reserved26B; // Byte offset 0x26b, CSR Addr 0x54135, Direction=N/A + + uint8_t Reserved26C; // Byte offset 0x26c, CSR Addr 0x54136, Direction=N/A + + uint8_t Reserved26D; // Byte offset 0x26d, CSR Addr 0x54136, Direction=N/A + + uint8_t Reserved26E; // Byte offset 0x26e, CSR Addr 0x54137, Direction=N/A + + uint8_t Reserved26F; // Byte offset 0x26f, CSR Addr 0x54137, Direction=N/A + + uint8_t Reserved270; // Byte offset 0x270, CSR Addr 0x54138, Direction=N/A + + uint8_t Reserved271; // Byte offset 0x271, CSR Addr 0x54138, Direction=N/A + + uint8_t Reserved272; // Byte offset 0x272, CSR Addr 0x54139, Direction=N/A + + uint8_t Reserved273; // Byte offset 0x273, CSR Addr 0x54139, Direction=N/A + + uint8_t Reserved274; // Byte offset 0x274, CSR Addr 0x5413a, Direction=N/A + + uint8_t Reserved275; // Byte offset 0x275, CSR Addr 0x5413a, Direction=N/A + + uint8_t Reserved276; // Byte offset 0x276, CSR Addr 0x5413b, Direction=N/A + + uint8_t Reserved277; // Byte offset 0x277, CSR Addr 0x5413b, Direction=N/A + + uint8_t Reserved278; // Byte offset 0x278, CSR Addr 0x5413c, Direction=N/A + + uint8_t Reserved279; // Byte offset 0x279, CSR Addr 0x5413c, Direction=N/A + + uint8_t Reserved27A; // Byte offset 0x27a, CSR Addr 0x5413d, Direction=N/A + + uint8_t Reserved27B; // Byte offset 0x27b, CSR Addr 0x5413d, Direction=N/A + + uint8_t Reserved27C; // Byte offset 0x27c, CSR Addr 0x5413e, Direction=N/A + + uint8_t Reserved27D; // Byte offset 0x27d, CSR Addr 0x5413e, Direction=N/A + + uint8_t Reserved27E; // Byte offset 0x27e, CSR Addr 0x5413f, Direction=N/A + + uint8_t Reserved27F; // Byte offset 0x27f, CSR Addr 0x5413f, Direction=N/A + + uint8_t Reserved280; // Byte offset 0x280, CSR Addr 0x54140, Direction=N/A + + uint8_t Reserved281; // Byte offset 0x281, CSR Addr 0x54140, Direction=N/A + + uint8_t Reserved282; // Byte offset 0x282, CSR Addr 0x54141, Direction=N/A + + uint8_t Reserved283; // Byte offset 0x283, CSR Addr 0x54141, Direction=N/A + + uint8_t Reserved284; // Byte offset 0x284, CSR Addr 0x54142, Direction=N/A + + uint8_t Reserved285; // Byte offset 0x285, CSR Addr 0x54142, Direction=N/A + + uint8_t Reserved286; // Byte offset 0x286, CSR Addr 0x54143, Direction=N/A + + uint8_t Reserved287; // Byte offset 0x287, CSR Addr 0x54143, Direction=N/A + + uint8_t Reserved288; // Byte offset 0x288, CSR Addr 0x54144, Direction=N/A + + uint8_t Reserved289; // Byte offset 0x289, CSR Addr 0x54144, Direction=N/A + + uint8_t Reserved28A; // Byte offset 0x28a, CSR Addr 0x54145, Direction=N/A + + uint8_t Reserved28B; // Byte offset 0x28b, CSR Addr 0x54145, Direction=N/A + + uint8_t Reserved28C; // Byte offset 0x28c, CSR Addr 0x54146, Direction=N/A + + uint8_t Reserved28D; // Byte offset 0x28d, CSR Addr 0x54146, Direction=N/A + + uint8_t Reserved28E; // Byte offset 0x28e, CSR Addr 0x54147, Direction=N/A + + uint8_t Reserved28F; // Byte offset 0x28f, CSR Addr 0x54147, Direction=N/A + + uint8_t Reserved290; // Byte offset 0x290, CSR Addr 0x54148, Direction=N/A + + uint8_t Reserved291; // Byte offset 0x291, CSR Addr 0x54148, Direction=N/A + + uint8_t Reserved292; // Byte offset 0x292, CSR Addr 0x54149, Direction=N/A + + uint8_t Reserved293; // Byte offset 0x293, CSR Addr 0x54149, Direction=N/A + + uint8_t Reserved294; // Byte offset 0x294, CSR Addr 0x5414a, Direction=N/A + + uint8_t Reserved295; // Byte offset 0x295, CSR Addr 0x5414a, Direction=N/A + + uint8_t Reserved296; // Byte offset 0x296, CSR Addr 0x5414b, Direction=N/A + + uint8_t Reserved297; // Byte offset 0x297, CSR Addr 0x5414b, Direction=N/A + + uint8_t Reserved298; // Byte offset 0x298, CSR Addr 0x5414c, Direction=N/A + + uint8_t Reserved299; // Byte offset 0x299, CSR Addr 0x5414c, Direction=N/A + + uint8_t Reserved29A; // Byte offset 0x29a, CSR Addr 0x5414d, Direction=N/A + + uint8_t Reserved29B; // Byte offset 0x29b, CSR Addr 0x5414d, Direction=N/A + + uint8_t Reserved29C; // Byte offset 0x29c, CSR Addr 0x5414e, Direction=N/A + + uint8_t Reserved29D; // Byte offset 0x29d, CSR Addr 0x5414e, Direction=N/A + + uint8_t Reserved29E; // Byte offset 0x29e, CSR Addr 0x5414f, Direction=N/A + + uint8_t Reserved29F; // Byte offset 0x29f, CSR Addr 0x5414f, Direction=N/A + + uint8_t Reserved2A0; // Byte offset 0x2a0, CSR Addr 0x54150, Direction=N/A + + uint8_t Reserved2A1; // Byte offset 0x2a1, CSR Addr 0x54150, Direction=N/A + + uint8_t Reserved2A2; // Byte offset 0x2a2, CSR Addr 0x54151, Direction=N/A + + uint8_t Reserved2A3; // Byte offset 0x2a3, CSR Addr 0x54151, Direction=N/A + + uint8_t Reserved2A4; // Byte offset 0x2a4, CSR Addr 0x54152, Direction=N/A + + uint8_t Reserved2A5; // Byte offset 0x2a5, CSR Addr 0x54152, Direction=N/A + + uint8_t Reserved2A6; // Byte offset 0x2a6, CSR Addr 0x54153, Direction=N/A + + uint8_t Reserved2A7; // Byte offset 0x2a7, CSR Addr 0x54153, Direction=N/A + + uint8_t Reserved2A8; // Byte offset 0x2a8, CSR Addr 0x54154, Direction=N/A + + uint8_t Reserved2A9; // Byte offset 0x2a9, CSR Addr 0x54154, Direction=N/A + + uint8_t Reserved2AA; // Byte offset 0x2aa, CSR Addr 0x54155, Direction=N/A + + uint8_t Reserved2AB; // Byte offset 0x2ab, CSR Addr 0x54155, Direction=N/A + + uint8_t Reserved2AC; // Byte offset 0x2ac, CSR Addr 0x54156, Direction=N/A + + uint8_t Reserved2AD; // Byte offset 0x2ad, CSR Addr 0x54156, Direction=N/A + + uint8_t Reserved2AE; // Byte offset 0x2ae, CSR Addr 0x54157, Direction=N/A + + uint8_t Reserved2AF; // Byte offset 0x2af, CSR Addr 0x54157, Direction=N/A + + uint8_t Reserved2B0; // Byte offset 0x2b0, CSR Addr 0x54158, Direction=N/A + + uint8_t Reserved2B1; // Byte offset 0x2b1, CSR Addr 0x54158, Direction=N/A + + uint8_t Reserved2B2; // Byte offset 0x2b2, CSR Addr 0x54159, Direction=N/A + + uint8_t Reserved2B3; // Byte offset 0x2b3, CSR Addr 0x54159, Direction=N/A + + uint8_t Reserved2B4; // Byte offset 0x2b4, CSR Addr 0x5415a, Direction=N/A + + uint8_t Reserved2B5; // Byte offset 0x2b5, CSR Addr 0x5415a, Direction=N/A + + uint8_t Reserved2B6; // Byte offset 0x2b6, CSR Addr 0x5415b, Direction=N/A + + uint8_t Reserved2B7; // Byte offset 0x2b7, CSR Addr 0x5415b, Direction=N/A + + uint8_t Reserved2B8; // Byte offset 0x2b8, CSR Addr 0x5415c, Direction=N/A + + uint8_t Reserved2B9; // Byte offset 0x2b9, CSR Addr 0x5415c, Direction=N/A + + uint8_t Reserved2BA; // Byte offset 0x2ba, CSR Addr 0x5415d, Direction=N/A + + uint8_t Reserved2BB; // Byte offset 0x2bb, CSR Addr 0x5415d, Direction=N/A + + uint8_t Reserved2BC; // Byte offset 0x2bc, CSR Addr 0x5415e, Direction=N/A + + uint8_t Reserved2BD; // Byte offset 0x2bd, CSR Addr 0x5415e, Direction=N/A + + uint8_t Reserved2BE; // Byte offset 0x2be, CSR Addr 0x5415f, Direction=N/A + + uint8_t Reserved2BF; // Byte offset 0x2bf, CSR Addr 0x5415f, Direction=N/A + + uint8_t Reserved2C0; // Byte offset 0x2c0, CSR Addr 0x54160, Direction=N/A + + uint8_t Reserved2C1; // Byte offset 0x2c1, CSR Addr 0x54160, Direction=N/A + + uint8_t Reserved2C2; // Byte offset 0x2c2, CSR Addr 0x54161, Direction=N/A + + uint8_t Reserved2C3; // Byte offset 0x2c3, CSR Addr 0x54161, Direction=N/A + + uint8_t Reserved2C4; // Byte offset 0x2c4, CSR Addr 0x54162, Direction=N/A + + uint8_t Reserved2C5; // Byte offset 0x2c5, CSR Addr 0x54162, Direction=N/A + + uint8_t Reserved2C6; // Byte offset 0x2c6, CSR Addr 0x54163, Direction=N/A + + uint8_t Reserved2C7; // Byte offset 0x2c7, CSR Addr 0x54163, Direction=N/A + + uint8_t Reserved2C8; // Byte offset 0x2c8, CSR Addr 0x54164, Direction=N/A + + uint8_t Reserved2C9; // Byte offset 0x2c9, CSR Addr 0x54164, Direction=N/A + + uint8_t Reserved2CA; // Byte offset 0x2ca, CSR Addr 0x54165, Direction=N/A + + uint8_t Reserved2CB; // Byte offset 0x2cb, CSR Addr 0x54165, Direction=N/A + + uint8_t Reserved2CC; // Byte offset 0x2cc, CSR Addr 0x54166, Direction=N/A + + uint8_t Reserved2CD; // Byte offset 0x2cd, CSR Addr 0x54166, Direction=N/A + + uint8_t Reserved2CE; // Byte offset 0x2ce, CSR Addr 0x54167, Direction=N/A + + uint8_t Reserved2CF; // Byte offset 0x2cf, CSR Addr 0x54167, Direction=N/A + + uint8_t Reserved2D0; // Byte offset 0x2d0, CSR Addr 0x54168, Direction=N/A + + uint8_t Reserved2D1; // Byte offset 0x2d1, CSR Addr 0x54168, Direction=N/A + + uint8_t Reserved2D2; // Byte offset 0x2d2, CSR Addr 0x54169, Direction=N/A + + uint8_t Reserved2D3; // Byte offset 0x2d3, CSR Addr 0x54169, Direction=N/A + + uint8_t Reserved2D4; // Byte offset 0x2d4, CSR Addr 0x5416a, Direction=N/A + + uint8_t Reserved2D5; // Byte offset 0x2d5, CSR Addr 0x5416a, Direction=N/A + + uint8_t Reserved2D6; // Byte offset 0x2d6, CSR Addr 0x5416b, Direction=N/A + + uint8_t Reserved2D7; // Byte offset 0x2d7, CSR Addr 0x5416b, Direction=N/A + + uint8_t Reserved2D8; // Byte offset 0x2d8, CSR Addr 0x5416c, Direction=N/A + + uint8_t Reserved2D9; // Byte offset 0x2d9, CSR Addr 0x5416c, Direction=N/A + + uint8_t Reserved2DA; // Byte offset 0x2da, CSR Addr 0x5416d, Direction=N/A + + uint8_t Reserved2DB; // Byte offset 0x2db, CSR Addr 0x5416d, Direction=N/A + + uint8_t Reserved2DC; // Byte offset 0x2dc, CSR Addr 0x5416e, Direction=N/A + + uint8_t Reserved2DD; // Byte offset 0x2dd, CSR Addr 0x5416e, Direction=N/A + + uint8_t Reserved2DE; // Byte offset 0x2de, CSR Addr 0x5416f, Direction=N/A + + uint8_t Reserved2DF; // Byte offset 0x2df, CSR Addr 0x5416f, Direction=N/A + + uint8_t Reserved2E0; // Byte offset 0x2e0, CSR Addr 0x54170, Direction=N/A + + uint8_t Reserved2E1; // Byte offset 0x2e1, CSR Addr 0x54170, Direction=N/A + + uint8_t Reserved2E2; // Byte offset 0x2e2, CSR Addr 0x54171, Direction=N/A + + uint8_t Reserved2E3; // Byte offset 0x2e3, CSR Addr 0x54171, Direction=N/A + + uint8_t Reserved2E4; // Byte offset 0x2e4, CSR Addr 0x54172, Direction=N/A + + uint8_t Reserved2E5; // Byte offset 0x2e5, CSR Addr 0x54172, Direction=N/A + + uint8_t Reserved2E6; // Byte offset 0x2e6, CSR Addr 0x54173, Direction=N/A + + uint8_t Reserved2E7; // Byte offset 0x2e7, CSR Addr 0x54173, Direction=N/A + + uint8_t Reserved2E8; // Byte offset 0x2e8, CSR Addr 0x54174, Direction=N/A + + uint8_t Reserved2E9; // Byte offset 0x2e9, CSR Addr 0x54174, Direction=N/A + + uint8_t Reserved2EA; // Byte offset 0x2ea, CSR Addr 0x54175, Direction=N/A + + uint8_t Reserved2EB; // Byte offset 0x2eb, CSR Addr 0x54175, Direction=N/A + + uint8_t Reserved2EC; // Byte offset 0x2ec, CSR Addr 0x54176, Direction=N/A + + uint8_t Reserved2ED; // Byte offset 0x2ed, CSR Addr 0x54176, Direction=N/A + + uint8_t Reserved2EE; // Byte offset 0x2ee, CSR Addr 0x54177, Direction=N/A + + uint8_t Reserved2EF; // Byte offset 0x2ef, CSR Addr 0x54177, Direction=N/A + + uint8_t Reserved2F0; // Byte offset 0x2f0, CSR Addr 0x54178, Direction=N/A + + uint8_t Reserved2F1; // Byte offset 0x2f1, CSR Addr 0x54178, Direction=N/A + + uint8_t Reserved2F2; // Byte offset 0x2f2, CSR Addr 0x54179, Direction=N/A + + uint8_t Reserved2F3; // Byte offset 0x2f3, CSR Addr 0x54179, Direction=N/A + + uint8_t Reserved2F4; // Byte offset 0x2f4, CSR Addr 0x5417a, Direction=N/A + + uint8_t Reserved2F5; // Byte offset 0x2f5, CSR Addr 0x5417a, Direction=N/A + + uint8_t Reserved2F6; // Byte offset 0x2f6, CSR Addr 0x5417b, Direction=N/A + + uint8_t Reserved2F7; // Byte offset 0x2f7, CSR Addr 0x5417b, Direction=N/A + + uint8_t Reserved2F8; // Byte offset 0x2f8, CSR Addr 0x5417c, Direction=N/A + + uint8_t Reserved2F9; // Byte offset 0x2f9, CSR Addr 0x5417c, Direction=N/A + + uint8_t Reserved2FA; // Byte offset 0x2fa, CSR Addr 0x5417d, Direction=N/A + + uint8_t Reserved2FB; // Byte offset 0x2fb, CSR Addr 0x5417d, Direction=N/A + + uint8_t Reserved2FC; // Byte offset 0x2fc, CSR Addr 0x5417e, Direction=N/A + + uint8_t Reserved2FD; // Byte offset 0x2fd, CSR Addr 0x5417e, Direction=N/A + + uint8_t Reserved2FE; // Byte offset 0x2fe, CSR Addr 0x5417f, Direction=N/A + + uint8_t Reserved2FF; // Byte offset 0x2ff, CSR Addr 0x5417f, Direction=N/A + + uint8_t Reserved300; // Byte offset 0x300, CSR Addr 0x54180, Direction=N/A + + uint8_t Reserved301; // Byte offset 0x301, CSR Addr 0x54180, Direction=N/A + + uint8_t Reserved302; // Byte offset 0x302, CSR Addr 0x54181, Direction=N/A + + uint8_t Reserved303; // Byte offset 0x303, CSR Addr 0x54181, Direction=N/A + + uint8_t Reserved304; // Byte offset 0x304, CSR Addr 0x54182, Direction=N/A + + uint8_t Reserved305; // Byte offset 0x305, CSR Addr 0x54182, Direction=N/A + + uint8_t Reserved306; // Byte offset 0x306, CSR Addr 0x54183, Direction=N/A + + uint8_t Reserved307; // Byte offset 0x307, CSR Addr 0x54183, Direction=N/A + + uint8_t Reserved308; // Byte offset 0x308, CSR Addr 0x54184, Direction=N/A + + uint8_t Reserved309; // Byte offset 0x309, CSR Addr 0x54184, Direction=N/A + + uint8_t Reserved30A; // Byte offset 0x30a, CSR Addr 0x54185, Direction=N/A + + uint8_t Reserved30B; // Byte offset 0x30b, CSR Addr 0x54185, Direction=N/A + + uint8_t Reserved30C; // Byte offset 0x30c, CSR Addr 0x54186, Direction=N/A + + uint8_t Reserved30D; // Byte offset 0x30d, CSR Addr 0x54186, Direction=N/A + + uint8_t Reserved30E; // Byte offset 0x30e, CSR Addr 0x54187, Direction=N/A + + uint8_t Reserved30F; // Byte offset 0x30f, CSR Addr 0x54187, Direction=N/A + + uint8_t Reserved310; // Byte offset 0x310, CSR Addr 0x54188, Direction=N/A + + uint8_t Reserved311; // Byte offset 0x311, CSR Addr 0x54188, Direction=N/A + + uint8_t Reserved312; // Byte offset 0x312, CSR Addr 0x54189, Direction=N/A + + uint8_t Reserved313; // Byte offset 0x313, CSR Addr 0x54189, Direction=N/A + + uint8_t Reserved314; // Byte offset 0x314, CSR Addr 0x5418a, Direction=N/A + + uint8_t Reserved315; // Byte offset 0x315, CSR Addr 0x5418a, Direction=N/A + + uint8_t Reserved316; // Byte offset 0x316, CSR Addr 0x5418b, Direction=N/A + + uint8_t Reserved317; // Byte offset 0x317, CSR Addr 0x5418b, Direction=N/A + + uint8_t Reserved318; // Byte offset 0x318, CSR Addr 0x5418c, Direction=N/A + + uint8_t Reserved319; // Byte offset 0x319, CSR Addr 0x5418c, Direction=N/A + + uint8_t Reserved31A; // Byte offset 0x31a, CSR Addr 0x5418d, Direction=N/A + + uint8_t Reserved31B; // Byte offset 0x31b, CSR Addr 0x5418d, Direction=N/A + + uint8_t Reserved31C; // Byte offset 0x31c, CSR Addr 0x5418e, Direction=N/A + + uint8_t Reserved31D; // Byte offset 0x31d, CSR Addr 0x5418e, Direction=N/A + + uint8_t Reserved31E; // Byte offset 0x31e, CSR Addr 0x5418f, Direction=N/A + + uint8_t Reserved31F; // Byte offset 0x31f, CSR Addr 0x5418f, Direction=N/A + + uint8_t Reserved320; // Byte offset 0x320, CSR Addr 0x54190, Direction=N/A + + uint8_t Reserved321; // Byte offset 0x321, CSR Addr 0x54190, Direction=N/A + + uint8_t Reserved322; // Byte offset 0x322, CSR Addr 0x54191, Direction=N/A + + uint8_t Reserved323; // Byte offset 0x323, CSR Addr 0x54191, Direction=N/A + + uint8_t Reserved324; // Byte offset 0x324, CSR Addr 0x54192, Direction=N/A + + uint8_t Reserved325; // Byte offset 0x325, CSR Addr 0x54192, Direction=N/A + + uint8_t Reserved326; // Byte offset 0x326, CSR Addr 0x54193, Direction=N/A + + uint8_t Reserved327; // Byte offset 0x327, CSR Addr 0x54193, Direction=N/A + + uint8_t Reserved328; // Byte offset 0x328, CSR Addr 0x54194, Direction=N/A + + uint8_t Reserved329; // Byte offset 0x329, CSR Addr 0x54194, Direction=N/A + + uint8_t Reserved32A; // Byte offset 0x32a, CSR Addr 0x54195, Direction=N/A + + uint8_t Reserved32B; // Byte offset 0x32b, CSR Addr 0x54195, Direction=N/A + + uint8_t Reserved32C; // Byte offset 0x32c, CSR Addr 0x54196, Direction=N/A + + uint8_t Reserved32D; // Byte offset 0x32d, CSR Addr 0x54196, Direction=N/A + + uint8_t Reserved32E; // Byte offset 0x32e, CSR Addr 0x54197, Direction=N/A + + uint8_t Reserved32F; // Byte offset 0x32f, CSR Addr 0x54197, Direction=N/A + + uint8_t Reserved330; // Byte offset 0x330, CSR Addr 0x54198, Direction=N/A + + uint8_t Reserved331; // Byte offset 0x331, CSR Addr 0x54198, Direction=N/A + + uint8_t Reserved332; // Byte offset 0x332, CSR Addr 0x54199, Direction=N/A + + uint8_t Reserved333; // Byte offset 0x333, CSR Addr 0x54199, Direction=N/A + + uint8_t Reserved334; // Byte offset 0x334, CSR Addr 0x5419a, Direction=N/A + + uint8_t Reserved335; // Byte offset 0x335, CSR Addr 0x5419a, Direction=N/A + + uint8_t Reserved336; // Byte offset 0x336, CSR Addr 0x5419b, Direction=N/A + + uint8_t Reserved337; // Byte offset 0x337, CSR Addr 0x5419b, Direction=N/A + + uint8_t Reserved338; // Byte offset 0x338, CSR Addr 0x5419c, Direction=N/A + + uint8_t Reserved339; // Byte offset 0x339, CSR Addr 0x5419c, Direction=N/A + + uint8_t Reserved33A; // Byte offset 0x33a, CSR Addr 0x5419d, Direction=N/A + + uint8_t Reserved33B; // Byte offset 0x33b, CSR Addr 0x5419d, Direction=N/A + + uint8_t Reserved33C; // Byte offset 0x33c, CSR Addr 0x5419e, Direction=N/A + + uint8_t Reserved33D; // Byte offset 0x33d, CSR Addr 0x5419e, Direction=N/A + + uint8_t Reserved33E; // Byte offset 0x33e, CSR Addr 0x5419f, Direction=N/A + + uint8_t Reserved33F; // Byte offset 0x33f, CSR Addr 0x5419f, Direction=N/A + + uint8_t Reserved340; // Byte offset 0x340, CSR Addr 0x541a0, Direction=N/A + + uint8_t Reserved341; // Byte offset 0x341, CSR Addr 0x541a0, Direction=N/A + + uint8_t Reserved342; // Byte offset 0x342, CSR Addr 0x541a1, Direction=N/A + + uint8_t Reserved343; // Byte offset 0x343, CSR Addr 0x541a1, Direction=N/A + + uint8_t Reserved344; // Byte offset 0x344, CSR Addr 0x541a2, Direction=N/A + + uint8_t Reserved345; // Byte offset 0x345, CSR Addr 0x541a2, Direction=N/A + + uint8_t Reserved346; // Byte offset 0x346, CSR Addr 0x541a3, Direction=N/A + + uint8_t Reserved347; // Byte offset 0x347, CSR Addr 0x541a3, Direction=N/A + + uint8_t Reserved348; // Byte offset 0x348, CSR Addr 0x541a4, Direction=N/A + + uint8_t Reserved349; // Byte offset 0x349, CSR Addr 0x541a4, Direction=N/A + + uint8_t Reserved34A; // Byte offset 0x34a, CSR Addr 0x541a5, Direction=N/A + + uint8_t Reserved34B; // Byte offset 0x34b, CSR Addr 0x541a5, Direction=N/A + + uint8_t Reserved34C; // Byte offset 0x34c, CSR Addr 0x541a6, Direction=N/A + + uint8_t Reserved34D; // Byte offset 0x34d, CSR Addr 0x541a6, Direction=N/A + + uint8_t Reserved34E; // Byte offset 0x34e, CSR Addr 0x541a7, Direction=N/A + + uint8_t Reserved34F; // Byte offset 0x34f, CSR Addr 0x541a7, Direction=N/A + + uint8_t Reserved350; // Byte offset 0x350, CSR Addr 0x541a8, Direction=N/A + + uint8_t Reserved351; // Byte offset 0x351, CSR Addr 0x541a8, Direction=N/A + + uint8_t Reserved352; // Byte offset 0x352, CSR Addr 0x541a9, Direction=N/A + + uint8_t Reserved353; // Byte offset 0x353, CSR Addr 0x541a9, Direction=N/A + + uint8_t Reserved354; // Byte offset 0x354, CSR Addr 0x541aa, Direction=N/A + + uint8_t Reserved355; // Byte offset 0x355, CSR Addr 0x541aa, Direction=N/A + + uint8_t Reserved356; // Byte offset 0x356, CSR Addr 0x541ab, Direction=N/A + + uint8_t Reserved357; // Byte offset 0x357, CSR Addr 0x541ab, Direction=N/A + + uint8_t Reserved358; // Byte offset 0x358, CSR Addr 0x541ac, Direction=N/A + + uint8_t Reserved359; // Byte offset 0x359, CSR Addr 0x541ac, Direction=N/A + + uint8_t Reserved35A; // Byte offset 0x35a, CSR Addr 0x541ad, Direction=N/A + + uint8_t Reserved35B; // Byte offset 0x35b, CSR Addr 0x541ad, Direction=N/A + + uint8_t Reserved35C; // Byte offset 0x35c, CSR Addr 0x541ae, Direction=N/A + + uint8_t Reserved35D; // Byte offset 0x35d, CSR Addr 0x541ae, Direction=N/A + + uint8_t Reserved35E; // Byte offset 0x35e, CSR Addr 0x541af, Direction=N/A + + uint8_t Reserved35F; // Byte offset 0x35f, CSR Addr 0x541af, Direction=N/A + + uint8_t Reserved360; // Byte offset 0x360, CSR Addr 0x541b0, Direction=N/A + + uint8_t Reserved361; // Byte offset 0x361, CSR Addr 0x541b0, Direction=N/A + + uint8_t Reserved362; // Byte offset 0x362, CSR Addr 0x541b1, Direction=N/A + + uint8_t Reserved363; // Byte offset 0x363, CSR Addr 0x541b1, Direction=N/A + + uint8_t Reserved364; // Byte offset 0x364, CSR Addr 0x541b2, Direction=N/A + + uint8_t Reserved365; // Byte offset 0x365, CSR Addr 0x541b2, Direction=N/A + + uint8_t Reserved366; // Byte offset 0x366, CSR Addr 0x541b3, Direction=N/A + + uint8_t Reserved367; // Byte offset 0x367, CSR Addr 0x541b3, Direction=N/A + + uint8_t Reserved368; // Byte offset 0x368, CSR Addr 0x541b4, Direction=N/A + + uint8_t Reserved369; // Byte offset 0x369, CSR Addr 0x541b4, Direction=N/A + + uint8_t Reserved36A; // Byte offset 0x36a, CSR Addr 0x541b5, Direction=N/A + + uint8_t Reserved36B; // Byte offset 0x36b, CSR Addr 0x541b5, Direction=N/A + + uint8_t Reserved36C; // Byte offset 0x36c, CSR Addr 0x541b6, Direction=N/A + + uint8_t Reserved36D; // Byte offset 0x36d, CSR Addr 0x541b6, Direction=N/A + + uint8_t Reserved36E; // Byte offset 0x36e, CSR Addr 0x541b7, Direction=N/A + + uint8_t Reserved36F; // Byte offset 0x36f, CSR Addr 0x541b7, Direction=N/A + + uint8_t Reserved370; // Byte offset 0x370, CSR Addr 0x541b8, Direction=N/A + + uint8_t Reserved371; // Byte offset 0x371, CSR Addr 0x541b8, Direction=N/A + + uint8_t Reserved372; // Byte offset 0x372, CSR Addr 0x541b9, Direction=N/A + + uint8_t Reserved373; // Byte offset 0x373, CSR Addr 0x541b9, Direction=N/A + + uint8_t Reserved374; // Byte offset 0x374, CSR Addr 0x541ba, Direction=N/A + + uint8_t Reserved375; // Byte offset 0x375, CSR Addr 0x541ba, Direction=N/A + + uint8_t Reserved376; // Byte offset 0x376, CSR Addr 0x541bb, Direction=N/A + + uint8_t Reserved377; // Byte offset 0x377, CSR Addr 0x541bb, Direction=N/A + + uint8_t Reserved378; // Byte offset 0x378, CSR Addr 0x541bc, Direction=N/A + + uint8_t Reserved379; // Byte offset 0x379, CSR Addr 0x541bc, Direction=N/A + + uint8_t Reserved37A; // Byte offset 0x37a, CSR Addr 0x541bd, Direction=N/A + + uint8_t Reserved37B; // Byte offset 0x37b, CSR Addr 0x541bd, Direction=N/A + + uint8_t Reserved37C; // Byte offset 0x37c, CSR Addr 0x541be, Direction=N/A + + uint8_t Reserved37D; // Byte offset 0x37d, CSR Addr 0x541be, Direction=N/A + + uint8_t Reserved37E; // Byte offset 0x37e, CSR Addr 0x541bf, Direction=N/A + + uint8_t Reserved37F; // Byte offset 0x37f, CSR Addr 0x541bf, Direction=N/A + + uint8_t Reserved380; // Byte offset 0x380, CSR Addr 0x541c0, Direction=N/A + + uint8_t Reserved381; // Byte offset 0x381, CSR Addr 0x541c0, Direction=N/A + + uint8_t Reserved382; // Byte offset 0x382, CSR Addr 0x541c1, Direction=N/A + + uint8_t Reserved383; // Byte offset 0x383, CSR Addr 0x541c1, Direction=N/A + + uint8_t Reserved384; // Byte offset 0x384, CSR Addr 0x541c2, Direction=N/A + + uint8_t Reserved385; // Byte offset 0x385, CSR Addr 0x541c2, Direction=N/A + + uint8_t Reserved386; // Byte offset 0x386, CSR Addr 0x541c3, Direction=N/A + + uint8_t Reserved387; // Byte offset 0x387, CSR Addr 0x541c3, Direction=N/A + + uint8_t Reserved388; // Byte offset 0x388, CSR Addr 0x541c4, Direction=N/A + + uint8_t Reserved389; // Byte offset 0x389, CSR Addr 0x541c4, Direction=N/A + + uint8_t Reserved38A; // Byte offset 0x38a, CSR Addr 0x541c5, Direction=N/A + + uint8_t Reserved38B; // Byte offset 0x38b, CSR Addr 0x541c5, Direction=N/A + + uint8_t Reserved38C; // Byte offset 0x38c, CSR Addr 0x541c6, Direction=N/A + + uint8_t Reserved38D; // Byte offset 0x38d, CSR Addr 0x541c6, Direction=N/A + + uint8_t Reserved38E; // Byte offset 0x38e, CSR Addr 0x541c7, Direction=N/A + + uint8_t Reserved38F; // Byte offset 0x38f, CSR Addr 0x541c7, Direction=N/A + + uint8_t Reserved390; // Byte offset 0x390, CSR Addr 0x541c8, Direction=N/A + + uint8_t Reserved391; // Byte offset 0x391, CSR Addr 0x541c8, Direction=N/A + + uint8_t Reserved392; // Byte offset 0x392, CSR Addr 0x541c9, Direction=N/A + + uint8_t Reserved393; // Byte offset 0x393, CSR Addr 0x541c9, Direction=N/A + + uint8_t Reserved394; // Byte offset 0x394, CSR Addr 0x541ca, Direction=N/A + + uint8_t Reserved395; // Byte offset 0x395, CSR Addr 0x541ca, Direction=N/A + + uint8_t Reserved396; // Byte offset 0x396, CSR Addr 0x541cb, Direction=N/A + + uint8_t Reserved397; // Byte offset 0x397, CSR Addr 0x541cb, Direction=N/A + + uint8_t Reserved398; // Byte offset 0x398, CSR Addr 0x541cc, Direction=N/A + + uint8_t Reserved399; // Byte offset 0x399, CSR Addr 0x541cc, Direction=N/A + + uint8_t Reserved39A; // Byte offset 0x39a, CSR Addr 0x541cd, Direction=N/A + + uint8_t Reserved39B; // Byte offset 0x39b, CSR Addr 0x541cd, Direction=N/A + + uint8_t Reserved39C; // Byte offset 0x39c, CSR Addr 0x541ce, Direction=N/A + + uint8_t Reserved39D; // Byte offset 0x39d, CSR Addr 0x541ce, Direction=N/A + + uint8_t Reserved39E; // Byte offset 0x39e, CSR Addr 0x541cf, Direction=N/A + + uint8_t Reserved39F; // Byte offset 0x39f, CSR Addr 0x541cf, Direction=N/A + + uint8_t Reserved3A0; // Byte offset 0x3a0, CSR Addr 0x541d0, Direction=N/A + + uint8_t Reserved3A1; // Byte offset 0x3a1, CSR Addr 0x541d0, Direction=N/A + + uint8_t Reserved3A2; // Byte offset 0x3a2, CSR Addr 0x541d1, Direction=N/A + + uint8_t Reserved3A3; // Byte offset 0x3a3, CSR Addr 0x541d1, Direction=N/A + + uint8_t Reserved3A4; // Byte offset 0x3a4, CSR Addr 0x541d2, Direction=N/A + + uint8_t Reserved3A5; // Byte offset 0x3a5, CSR Addr 0x541d2, Direction=N/A + + uint8_t Reserved3A6; // Byte offset 0x3a6, CSR Addr 0x541d3, Direction=N/A + + uint8_t Reserved3A7; // Byte offset 0x3a7, CSR Addr 0x541d3, Direction=N/A + + uint8_t Reserved3A8; // Byte offset 0x3a8, CSR Addr 0x541d4, Direction=N/A + + uint8_t Reserved3A9; // Byte offset 0x3a9, CSR Addr 0x541d4, Direction=N/A + + uint8_t Reserved3AA; // Byte offset 0x3aa, CSR Addr 0x541d5, Direction=N/A + + uint8_t Reserved3AB; // Byte offset 0x3ab, CSR Addr 0x541d5, Direction=N/A + + uint8_t Reserved3AC; // Byte offset 0x3ac, CSR Addr 0x541d6, Direction=N/A + + uint8_t Reserved3AD; // Byte offset 0x3ad, CSR Addr 0x541d6, Direction=N/A + + uint8_t Reserved3AE; // Byte offset 0x3ae, CSR Addr 0x541d7, Direction=N/A + + uint8_t Reserved3AF; // Byte offset 0x3af, CSR Addr 0x541d7, Direction=N/A + + uint8_t Reserved3B0; // Byte offset 0x3b0, CSR Addr 0x541d8, Direction=N/A + + uint8_t Reserved3B1; // Byte offset 0x3b1, CSR Addr 0x541d8, Direction=N/A + + uint8_t Reserved3B2; // Byte offset 0x3b2, CSR Addr 0x541d9, Direction=N/A + + uint8_t Reserved3B3; // Byte offset 0x3b3, CSR Addr 0x541d9, Direction=N/A + + uint8_t Reserved3B4; // Byte offset 0x3b4, CSR Addr 0x541da, Direction=N/A + + uint8_t Reserved3B5; // Byte offset 0x3b5, CSR Addr 0x541da, Direction=N/A + + uint8_t Reserved3B6; // Byte offset 0x3b6, CSR Addr 0x541db, Direction=N/A + + uint8_t Reserved3B7; // Byte offset 0x3b7, CSR Addr 0x541db, Direction=N/A + + uint8_t Reserved3B8; // Byte offset 0x3b8, CSR Addr 0x541dc, Direction=N/A + + uint8_t Reserved3B9; // Byte offset 0x3b9, CSR Addr 0x541dc, Direction=N/A + + uint8_t Reserved3BA; // Byte offset 0x3ba, CSR Addr 0x541dd, Direction=N/A + + uint8_t Reserved3BB; // Byte offset 0x3bb, CSR Addr 0x541dd, Direction=N/A + + uint8_t Reserved3BC; // Byte offset 0x3bc, CSR Addr 0x541de, Direction=N/A + + uint8_t Reserved3BD; // Byte offset 0x3bd, CSR Addr 0x541de, Direction=N/A + + uint8_t Reserved3BE; // Byte offset 0x3be, CSR Addr 0x541df, Direction=N/A + + uint8_t Reserved3BF; // Byte offset 0x3bf, CSR Addr 0x541df, Direction=N/A + + uint8_t Reserved3C0; // Byte offset 0x3c0, CSR Addr 0x541e0, Direction=N/A + + uint8_t Reserved3C1; // Byte offset 0x3c1, CSR Addr 0x541e0, Direction=N/A + + uint8_t Reserved3C2; // Byte offset 0x3c2, CSR Addr 0x541e1, Direction=N/A + + uint8_t Reserved3C3; // Byte offset 0x3c3, CSR Addr 0x541e1, Direction=N/A + + uint8_t Reserved3C4; // Byte offset 0x3c4, CSR Addr 0x541e2, Direction=N/A + + uint8_t Reserved3C5; // Byte offset 0x3c5, CSR Addr 0x541e2, Direction=N/A + + uint8_t Reserved3C6; // Byte offset 0x3c6, CSR Addr 0x541e3, Direction=N/A + + uint8_t Reserved3C7; // Byte offset 0x3c7, CSR Addr 0x541e3, Direction=N/A + + uint8_t Reserved3C8; // Byte offset 0x3c8, CSR Addr 0x541e4, Direction=N/A + + uint8_t Reserved3C9; // Byte offset 0x3c9, CSR Addr 0x541e4, Direction=N/A + + uint8_t Reserved3CA; // Byte offset 0x3ca, CSR Addr 0x541e5, Direction=N/A + + uint8_t Reserved3CB; // Byte offset 0x3cb, CSR Addr 0x541e5, Direction=N/A + + uint8_t Reserved3CC; // Byte offset 0x3cc, CSR Addr 0x541e6, Direction=N/A + + uint8_t Reserved3CD; // Byte offset 0x3cd, CSR Addr 0x541e6, Direction=N/A + + uint8_t Reserved3CE; // Byte offset 0x3ce, CSR Addr 0x541e7, Direction=N/A + + uint8_t Reserved3CF; // Byte offset 0x3cf, CSR Addr 0x541e7, Direction=N/A + + uint8_t Reserved3D0; // Byte offset 0x3d0, CSR Addr 0x541e8, Direction=N/A + + uint8_t Reserved3D1; // Byte offset 0x3d1, CSR Addr 0x541e8, Direction=N/A + + uint8_t Reserved3D2; // Byte offset 0x3d2, CSR Addr 0x541e9, Direction=N/A + + uint8_t Reserved3D3; // Byte offset 0x3d3, CSR Addr 0x541e9, Direction=N/A + + uint8_t Reserved3D4; // Byte offset 0x3d4, CSR Addr 0x541ea, Direction=N/A + + uint8_t Reserved3D5; // Byte offset 0x3d5, CSR Addr 0x541ea, Direction=N/A + + uint8_t Reserved3D6; // Byte offset 0x3d6, CSR Addr 0x541eb, Direction=N/A + + uint8_t Reserved3D7; // Byte offset 0x3d7, CSR Addr 0x541eb, Direction=N/A + + uint8_t Reserved3D8; // Byte offset 0x3d8, CSR Addr 0x541ec, Direction=N/A + + uint8_t Reserved3D9; // Byte offset 0x3d9, CSR Addr 0x541ec, Direction=N/A + + uint8_t Reserved3DA; // Byte offset 0x3da, CSR Addr 0x541ed, Direction=N/A + + uint8_t Reserved3DB; // Byte offset 0x3db, CSR Addr 0x541ed, Direction=N/A + + uint8_t Reserved3DC; // Byte offset 0x3dc, CSR Addr 0x541ee, Direction=N/A + + uint8_t Reserved3DD; // Byte offset 0x3dd, CSR Addr 0x541ee, Direction=N/A + + uint8_t Reserved3DE; // Byte offset 0x3de, CSR Addr 0x541ef, Direction=N/A + + uint8_t Reserved3DF; // Byte offset 0x3df, CSR Addr 0x541ef, Direction=N/A + + uint8_t Reserved3E0; // Byte offset 0x3e0, CSR Addr 0x541f0, Direction=N/A + + uint8_t Reserved3E1; // Byte offset 0x3e1, CSR Addr 0x541f0, Direction=N/A + + uint8_t Reserved3E2; // Byte offset 0x3e2, CSR Addr 0x541f1, Direction=N/A + + uint8_t Reserved3E3; // Byte offset 0x3e3, CSR Addr 0x541f1, Direction=N/A + + uint8_t Reserved3E4; // Byte offset 0x3e4, CSR Addr 0x541f2, Direction=N/A + + uint8_t Reserved3E5; // Byte offset 0x3e5, CSR Addr 0x541f2, Direction=N/A + + uint8_t Reserved3E6; // Byte offset 0x3e6, CSR Addr 0x541f3, Direction=N/A + + uint8_t Reserved3E7; // Byte offset 0x3e7, CSR Addr 0x541f3, Direction=N/A + + uint8_t Reserved3E8; // Byte offset 0x3e8, CSR Addr 0x541f4, Direction=N/A + + uint8_t Reserved3E9; // Byte offset 0x3e9, CSR Addr 0x541f4, Direction=N/A + + uint8_t Reserved3EA; // Byte offset 0x3ea, CSR Addr 0x541f5, Direction=N/A + + uint8_t Reserved3EB; // Byte offset 0x3eb, CSR Addr 0x541f5, Direction=N/A + + uint8_t Reserved3EC; // Byte offset 0x3ec, CSR Addr 0x541f6, Direction=N/A + + uint8_t Reserved3ED; // Byte offset 0x3ed, CSR Addr 0x541f6, Direction=N/A + + uint8_t Reserved3EE; // Byte offset 0x3ee, CSR Addr 0x541f7, Direction=N/A + + uint8_t Reserved3EF; // Byte offset 0x3ef, CSR Addr 0x541f7, Direction=N/A + + uint8_t Reserved3F0; // Byte offset 0x3f0, CSR Addr 0x541f8, Direction=N/A + + uint8_t Reserved3F1; // Byte offset 0x3f1, CSR Addr 0x541f8, Direction=N/A + + uint8_t Reserved3F2; // Byte offset 0x3f2, CSR Addr 0x541f9, Direction=N/A + + uint8_t Reserved3F3; // Byte offset 0x3f3, CSR Addr 0x541f9, Direction=N/A + + uint8_t Reserved3F4; // Byte offset 0x3f4, CSR Addr 0x541fa, Direction=N/A + + uint8_t Reserved3F5; // Byte offset 0x3f5, CSR Addr 0x541fa, Direction=N/A + + uint16_t ALT_CAS_L; // Byte offset 0x3f6, CSR Addr 0x541fb, Direction=in + // This field must be populated if RdDBI is enabled (applicable when MR5[A12] == 1). + // RdDBI is dynamically disabled in certain training steps, + // and so the [RdDBI disabled] CAS Latency must be provided in this field. + // The required encoding is as follows: + // ALT_CAS_L[0] == 0: use value in MR0 + // ALT_CAS_L[0] == 1: use value in ALT_CAS_L, i.e., MR0{A[12],A[6],A[5],A[4],A[2]} = ALT_CAS_L[12,6,5,4,2] + // Other bits are ignored + uint8_t ALT_WCAS_L; // Byte offset 0x3f8, CSR Addr 0x541fc, Direction=In + // This field must be populated if 2tCK write preambles are enabled (applicable when MR4[A12] == 1). + // 2tCK write prambles are dynamically disabled in certain training steps, + // and so the [1tCK write preamble] WCAS Latency must be provided in this field. + // The required encoding is as follows: + // ALT_WCAS_L[0] == 0: use value in MR2 + // ALT_WCAS_L[0] == 1: use value in ALT_WCAS_L, i.e., MR2{A[5],A[4],A[3]} = ALT_WCAS_L[5,4,3] + // Other bits are ignored + uint8_t D4Misc; // Byte offset 0x3f9, CSR Addr 0x541fc, Direction=In + // Contains various options for training DDR4 Devices. + // + // Bit fields: + // + // D4Misc[7:1] RFU, must be zero + // + // D4Misc[0] = protect memory reset + // 0x1 = dfi_reset_n cannot control BP_MEMRESERT_L to devices after training. + // 0x0 = dfi_resert_n can control BP_MEMRESERT_L to devices after training +} __attribute__ ((packed)) PMU_SMB_DDR4U_2D_t;
diff --git a/arch/arm/include/asm/arch-c1/mnPmuSramMsgBlock_lpddr3.h b/arch/arm/include/asm/arch-c1/mnPmuSramMsgBlock_lpddr3.h new file mode 100644 index 0000000..6850d06 --- /dev/null +++ b/arch/arm/include/asm/arch-c1/mnPmuSramMsgBlock_lpddr3.h
@@ -0,0 +1,434 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +/** \brief LPDDR3_1D training firmware message block structure + * + * Please refer to the Training Firmware App Note for futher information about + * the usage for Message Block. + */ +typedef struct _PMU_SMB_LPDDR3_1D_t { + uint8_t Reserved00; // Byte offset 0x00, CSR Addr 0x54000, Direction=In + // Reserved00[0:5] RFU, must be zero + // + // Reserved00[6] = Enable High Effort WrDQ1D + // 0x1 = WrDQ1D will conditionally retry training at several extra RxClkDly Timings. This will increase the maximum 1D training time by up to 4 extra iterations of WrDQ1D. This is only required in systems that suffer from very large, asymmetric eye-collapse when receiving PRBS patterns. + // 0x0 = WrDQ1D assume rxClkDly values found by SI Friendly RdDqs1D will work for receiving PRBS patterns + // + // Reserved00[7] = Optimize for the special hard macros in TSMC28. + // 0x1 = set if the phy being trained was manufactured in any TSMC28 process node. + // 0x0 = otherwise, when not training a TSMC28 phy, leave this field as 0. + uint8_t MsgMisc; // Byte offset 0x01, CSR Addr 0x54000, Direction=In + // Contains various global options for training. + // + // Bit fields: + // + // MsgMisc[0] MTESTEnable + // 0x1 = Pulse primary digital test output bump at the end of each major training stage. This enables observation of training stage completion by observing the digital test output. + // 0x0 = Do not pulse primary digital test output bump + // + // MsgMisc[1] SimulationOnlyReset + // 0x1 = Verilog only simulation option to shorten duration of DRAM reset pulse length to 1ns. + // Must never be set to 1 in silicon. + // 0x0 = Use reset pulse length specifed by JEDEC standard + // + // MsgMisc[2] SimulationOnlyTraining + // 0x1 = Verilog only simulation option to shorten the duration of the training steps by performing fewer iterations. + // Must never be set to 1 in silicon. + // 0x0 = Use standard training duration. + // + // MsgMisc[3] RFU, must be zero + // + // MsgMisc[4] Suppress streaming messages, including assertions, regardless of HdtCtrl setting. + // Stage Completion messages, as well as training completion and error messages are + // Still sent depending on HdtCtrl setting. + // + // MsgMisc[5] PerByteMaxRdLat + // 0x1 = Each DBYTE will return dfi_rddata_valid at the lowest possible latency. This may result in unaligned data between bytes to be returned to the DFI. + // 0x0 = Every DBYTE will return dfi_rddata_valid simultaneously. This will ensure that data bytes will return aligned accesses to the DFI. + // + // MsgMisc[7-6] RFU, must be zero + // + // Notes: + // + // - SimulationOnlyReset and SimulationOnlyTraining can be used to speed up simulation run times, and must never be used in real silicon. Some VIPs may have checks on DRAM reset parameters that may need to be disabled when using SimulationOnlyReset. + uint16_t PmuRevision; // Byte offset 0x02, CSR Addr 0x54001, Direction=Out + // PMU firmware revision ID + // After training is run, this address will contain the revision ID of the firmware + uint8_t Pstate; // Byte offset 0x04, CSR Addr 0x54002, Direction=In + // Must be set to the target Pstate to be trained + // 0x0 = Pstate 0 + // 0x1 = Pstate 1 + // 0x2 = Pstate 2 + // 0x3 = Pstate 3 + // All other encodings are reserved + uint8_t PllBypassEn; // Byte offset 0x05, CSR Addr 0x54002, Direction=In + // Set according to whether target Pstate uses PHY PLL bypass + // 0x0 = PHY PLL is enabled for target Pstate + // 0x1 = PHY PLL is bypassed for target Pstate + uint16_t DRAMFreq; // Byte offset 0x06, CSR Addr 0x54003, Direction=In + // DDR data rate for the target Pstate in units of MT/s. + // For example enter 0x0640 for DDR1600. + uint8_t DfiFreqRatio; // Byte offset 0x08, CSR Addr 0x54004, Direction=In + // Frequency ratio betwen DfiCtlClk and SDRAM memclk. + // 0x1 = 1:1 + // 0x2 = 1:2 + // 0x4 = 1:4 + uint8_t BPZNResVal ; // Byte offset 0x09, CSR Addr 0x54004, Direction=In + // Must be programmed to match the precision resistor connected to Phy BP_ZN + // 0x00 = Do not program. Use current CSR value. + // 0xf0 = 240 Ohm (recommended value) + // 0x78 = 120 Ohm + // 0x28 = 40 Ohm + // All other values are reserved. + // + uint8_t PhyOdtImpedance; // Byte offset 0x0a, CSR Addr 0x54005, Direction=In + // Must be programmed to the termination impedance in ohms used by PHY during reads. + // + // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start) + // + // See PHY databook for legal termination impedance values. + // + // For digital simulation, any legal value can be used. For silicon, the users must determine the correct value through SI simulation or other methods. + uint8_t PhyDrvImpedance; // Byte offset 0x0b, CSR Addr 0x54005, Direction=In + // Must be programmed to the driver impedance in ohms used by PHY during writes for all DBYTE drivers (DQ/DM/DBI/DQS). + // + // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start) + // + // See PHY databook for legal R_on driver impedance values. + // + // For digital simulation, any value can be used that is not Hi-Z. For silicon, the users must determine the correct value through SI simulation or other methods. + uint8_t PhyVref; // Byte offset 0x0c, CSR Addr 0x54006, Direction=In + // Must be programmed with the Vref level to be used by the PHY during reads + // + // The units of this field are a percentage of VDDQ according to the following equation: + // + // Receiver Vref = VDDQ*PhyVref[6:0]/128 + // + // For example to set Vref at 0.75*VDDQ, set this field to 0x60. + // + // For digital simulation, any legal value can be used. For silicon, the users must calculate the analytical Vref by using the impedances, terminations, and series resistance present in the system. + uint8_t Reserved0D; // Byte offset 0x0d, CSR Addr 0x54006, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved0E; // Byte offset 0x0e, CSR Addr 0x54007, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t CsTestFail; // Byte offset 0x0f, CSR Addr 0x54007, Direction=Out + // This field will be set if training fails on any rank. + // 0x0 = No failures + // non-zero = one or more ranks failed training + uint16_t SequenceCtrl; // Byte offset 0x10, CSR Addr 0x54008, Direction=In + // Controls the training steps to be run. Each bit corresponds to a training step. + // + // If the bit is set to 1, the training step will run. + // If the bit is set to 0, the training step will be skipped. + // + // Training step to bit mapping: + // SequenceCtrl[0] = Run DevInit - Device/phy initialization. Should always be set. + // SequenceCtrl[1] = Run WrLvl - Write leveling + // SequenceCtrl[2] = Run RxEn - Read gate training + // SequenceCtrl[3] = Run RdDQS1D - 1d read dqs training + // SequenceCtrl[4] = RunWrDQ1D - 1d write dq training + // SequenceCtrl[5] = RFU, must be zero + // SequenceCtrl[6] = RFU, must be zero + // SequenceCtrl[7] = RFU, must be zero + // SequenceCtrl[8] = Run RdDeskew - Per lane read dq deskew training + // SequenceCtrl[9] = Run MxRdLat - Max read latency training + // SequenceCtrl[10] = RFU, must be zero + // SequenceCtrl[11] = RFU, must be zero + // SequenceCtrl[12] = Run LPCA - CA Training + // SequenceCtrl[13] = RFU, must be zero + // SequenceCtrl[14] = RFU, must be zero + // SequenceCtrl[15] = RFU, must be zero + // + uint8_t HdtCtrl; // Byte offset 0x12, CSR Addr 0x54009, Direction=In + // To control the total number of debug messages, a verbosity subfield (HdtCtrl, Hardware Debug Trace Control) exists in the message block. Every message has a verbosity level associated with it, and as the HdtCtrl value is increased, less important s messages stop being sent through the mailboxes. The meanings of several major HdtCtrl thresholds are explained below: + // + // 0x05 = Detailed debug messages (e.g. Eye delays) + // 0x0A = Coarse debug messages (e.g. rank information) + // 0xC8 = Stage completion + // 0xC9 = Assertion messages + // 0xFF = Firmware completion messages only + // + // See Training App Note for more detailed information on what messages are included for each threshold. + // + uint8_t Reserved13; // Byte offset 0x13, CSR Addr 0x54009, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t DFIMRLMargin; // Byte offset 0x14, CSR Addr 0x5400a, Direction=In + // Margin added to smallest passing trained DFI Max Read Latency value, in units of DFI clocks. Recommended to be >= 1. See the Training App Note for more details on the training process and the use of this value. + // + // This margin must include the maximum positive drift expected in tDQSCK over the target temperature and voltage range of the users system. + uint8_t Reserved15; // Byte offset 0x15, CSR Addr 0x5400a, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t UseBroadcastMR; // Byte offset 0x16, CSR Addr 0x5400b, Direction=In + // Training firmware can optionally set per rank mode register values for DRAM partial array self-refresh features if desired. + // + // 0x0 = Use MR<0:17>_A0 for rank 0 channel A + // Use MR<0:17>_B0 for rank 0 channel B + // Use MR<0:17>_A1 for rank 1 channel A + // Use MR<0:17>_B1 for rank 1 channel B + // + // 0x1 = Use MR<0:17>_A0 setting for all channels/ranks + // + // This should be set to 1 for all systems. + // + // Note: If setting this to 0, only mode register settings related to DRAM partial array self-refresh may be different between the ranks and channels. All other mode register settings must be the same for all ranks and channels. + uint8_t Reserved17; // Byte offset 0x17, CSR Addr 0x5400b, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t LogToPhyByteMap0; // Byte offset 0x18, CSR Addr 0x5400c, Direction=In + // Physical Byte associated with Channel A logical Byte 0, depending on LogToPhyByteMap0[7] value: + // LogToPhyByteMap0[7]==0: Logical Byte 0 map on Physical Byte 0 + // LogToPhyByteMap0[7]==1: Logical Byte 0 map on Physical Byte LogToPhyByteMap0[6:0] + uint8_t LogToPhyByteMap1; // Byte offset 0x19, CSR Addr 0x5400c, Direction=In + // Physical Byte associated with Channel A logical Byte 1, depending on LogToPhyByteMap1[7] value: + // LogToPhyByteMap1[7]==0: Logical Byte 1 map on Physical Byte 1 + // LogToPhyByteMap1[7]==1: Logical Byte 1 map on Physical Byte LogToPhyByteMap1[6:0] + uint8_t LogToPhyByteMap2; // Byte offset 0x1a, CSR Addr 0x5400d, Direction=In + // Physical Byte associated with Channel A logical Byte 2, depending on LogToPhyByteMap2[7] value: + // LogToPhyByteMap2[7]==0: Logical Byte 2 map on Physical Byte 2 + // LogToPhyByteMap2[7]==1: Logical Byte 2 map on Physical Byte LogToPhyByteMap2[6:0] + uint8_t LogToPhyByteMap3; // Byte offset 0x1b, CSR Addr 0x5400d, Direction=In + // Physical Byte associated with Channel A logical Byte 3, depending on LogToPhyByteMap3[7] value: + // LogToPhyByteMap3[7]==0: Logical Byte 3 map on Physical Byte 3 + // LogToPhyByteMap3[7]==1: Logical Byte 3 map on Physical Byte LogToPhyByteMap3[6:0] + uint8_t LogToPhyByteMap4; // Byte offset 0x1c, CSR Addr 0x5400e, Direction=In + // Physical Byte associated with Channel B logical Byte 0, depending on LogToPhyByteMap4[7] value: + // LogToPhyByteMap4[7]==0: Logical Byte 0 map on Physical Byte 4 + // LogToPhyByteMap4[7]==1: Logical Byte 0 map on Physical Byte LogToPhyByteMap4[6:0] + uint8_t LogToPhyByteMap5; // Byte offset 0x1d, CSR Addr 0x5400e, Direction=In + // Physical Byte associated with Channel B logical Byte 1, depending on LogToPhyByteMap5[7] value: + // LogToPhyByteMap5[7]==0: Logical Byte 1 map on Physical Byte 5 + // LogToPhyByteMap5[7]==1: Logical Byte 1 map on Physical Byte LogToPhyByteMap5[6:0] + uint8_t LogToPhyByteMap6; // Byte offset 0x1e, CSR Addr 0x5400f, Direction=In + // Physical Byte associated with Channel B logical Byte 2, depending on LogToPhyByteMap6[7] value: + // LogToPhyByteMap6[7]==0: Logical Byte 2 map on Physical Byte 6 + // LogToPhyByteMap6[7]==1: Logical Byte 2 map on Physical Byte LogToPhyByteMap6[6:0] + uint8_t LogToPhyByteMap7; // Byte offset 0x1f, CSR Addr 0x5400f, Direction=In + // Physical Byte associated with Channel B logical Byte 3, depending on LogToPhyByteMap7[7] value: + // LogToPhyByteMap7[7]==0: Logical Byte 3 map on Physical Byte 7 + // LogToPhyByteMap7[7]==1: Logical Byte 3 map on Physical Byte LogToPhyByteMap7[6:0] + uint8_t LogToPhyByteMap8; // Byte offset 0x20, CSR Addr 0x54010, Direction=In + // This field is reserved and must be programmed to 0x00. + uint8_t LogToPhyByteMap9; // Byte offset 0x21, CSR Addr 0x54010, Direction=In + // This field is reserved and must be programmed to 0x00. + uint8_t EnabledDQsChA; // Byte offset 0x22, CSR Addr 0x54011, Direction=In + // Total number of DQ bits enabled in PHY Channel A + uint8_t CsPresentChA; // Byte offset 0x23, CSR Addr 0x54011, Direction=In + // Indicates presence of DRAM at each chip select for PHY channel A. + // + // 0x1 = CS0 is populated with DRAM + // 0x3 = CS0 and CS1 are populated with DRAM + // + // All other encodings are illegal + // + int8_t CDD_ChA_RR_1_0; // Byte offset 0x24, CSR Addr 0x54012, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 1 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_RR_0_1; // Byte offset 0x25, CSR Addr 0x54012, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 0 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_RW_1_1; // Byte offset 0x26, CSR Addr 0x54013, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_RW_1_0; // Byte offset 0x27, CSR Addr 0x54013, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_RW_0_1; // Byte offset 0x28, CSR Addr 0x54014, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 0 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_RW_0_0; // Byte offset 0x29, CSR Addr 0x54014, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs0 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WR_1_1; // Byte offset 0x2a, CSR Addr 0x54015, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WR_1_0; // Byte offset 0x2b, CSR Addr 0x54015, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WR_0_1; // Byte offset 0x2c, CSR Addr 0x54016, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WR_0_0; // Byte offset 0x2d, CSR Addr 0x54016, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WW_1_0; // Byte offset 0x2e, CSR Addr 0x54017, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 1 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WW_0_1; // Byte offset 0x2f, CSR Addr 0x54017, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 0 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + uint8_t Reserved30; // Byte offset 0x30, CSR Addr 0x54018, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t MR1_A0; // Byte offset 0x31, CSR Addr 0x54018, Direction=In + // Value to be programmed in DRAM Mode Register 1 {Channel A, Rank 0} + uint8_t MR2_A0; // Byte offset 0x32, CSR Addr 0x54019, Direction=In + // Value to be programmed in DRAM Mode Register 2 {Channel A, Rank 0} + uint8_t MR3_A0; // Byte offset 0x33, CSR Addr 0x54019, Direction=In + // Value to be programmed in DRAM Mode Register 3 {Channel A, Rank 0} + uint8_t Reserved34; // Byte offset 0x34, CSR Addr 0x5401a, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t MR11_A0; // Byte offset 0x35, CSR Addr 0x5401a, Direction=In + // Value to be programmed in DRAM Mode Register 11 {Channel A, Rank 0} + uint8_t MR16_A0; // Byte offset 0x36, CSR Addr 0x5401b, Direction=In + // Value to be programmed in DRAM Mode Register 16 {Channel A, Rank 0} + uint8_t MR17_A0; // Byte offset 0x37, CSR Addr 0x5401b, Direction=In + // Value to be programmed in DRAM Mode Register 17 {Channel A, Rank 0} + uint8_t Reserved38; // Byte offset 0x38, CSR Addr 0x5401c, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t MR1_A1; // Byte offset 0x39, CSR Addr 0x5401c, Direction=In + // Must be programmed the same as MR1_A0 + uint8_t MR2_A1; // Byte offset 0x3a, CSR Addr 0x5401d, Direction=In + // Must be programmed the same as MR2_A0 + uint8_t MR3_A1; // Byte offset 0x3b, CSR Addr 0x5401d, Direction=In + // Must be programmed the same as MR3_A0 + uint8_t Reserved3C; // Byte offset 0x3c, CSR Addr 0x5401e, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t MR11_A1; // Byte offset 0x3d, CSR Addr 0x5401e, Direction=In + // Must be programmed the same as MR11_A0 + uint8_t MR16_A1; // Byte offset 0x3e, CSR Addr 0x5401f, Direction=In + // Value to be programmed in DRAM Mode Register 16 {Channel A, Rank 1} + uint8_t MR17_A1; // Byte offset 0x3f, CSR Addr 0x5401f, Direction=In + // Value to be programmed in DRAM Mode Register 17 {Channel A, Rank 1} + uint8_t Reserved40; // Byte offset 0x40, CSR Addr 0x54020, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved41; // Byte offset 0x41, CSR Addr 0x54020, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved42; // Byte offset 0x42, CSR Addr 0x54021, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved43; // Byte offset 0x43, CSR Addr 0x54021, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved44; // Byte offset 0x44, CSR Addr 0x54022, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved45; // Byte offset 0x45, CSR Addr 0x54022, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved46; // Byte offset 0x46, CSR Addr 0x54023, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved47; // Byte offset 0x47, CSR Addr 0x54023, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t EnabledDQsChB; // Byte offset 0x48, CSR Addr 0x54024, Direction=In + // Total number of DQ bits enabled in PHY Channel B + uint8_t CsPresentChB; // Byte offset 0x49, CSR Addr 0x54024, Direction=In + // Indicates presence of DRAM at each chip select for PHY channel B. + // + // 0x0 = No chip selects are populated with DRAM + // 0x1 = CS0 is populated with DRAM + // 0x3 = CS0 and CS1 are populated with DRAM + // + // All other encodings are illegal + // + int8_t CDD_ChB_RR_1_0; // Byte offset 0x4a, CSR Addr 0x54025, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 1 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_RR_0_1; // Byte offset 0x4b, CSR Addr 0x54025, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 0 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_RW_1_1; // Byte offset 0x4c, CSR Addr 0x54026, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_RW_1_0; // Byte offset 0x4d, CSR Addr 0x54026, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_RW_0_1; // Byte offset 0x4e, CSR Addr 0x54027, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 0 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_RW_0_0; // Byte offset 0x4f, CSR Addr 0x54027, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs01 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WR_1_1; // Byte offset 0x50, CSR Addr 0x54028, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WR_1_0; // Byte offset 0x51, CSR Addr 0x54028, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WR_0_1; // Byte offset 0x52, CSR Addr 0x54029, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WR_0_0; // Byte offset 0x53, CSR Addr 0x54029, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WW_1_0; // Byte offset 0x54, CSR Addr 0x5402a, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 1 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WW_0_1; // Byte offset 0x55, CSR Addr 0x5402a, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 0 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + uint8_t Reserved56; // Byte offset 0x56, CSR Addr 0x5402b, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t MR1_B0; // Byte offset 0x57, CSR Addr 0x5402b, Direction=In + // Must be programmed the same as MR1_A0 + uint8_t MR2_B0; // Byte offset 0x58, CSR Addr 0x5402c, Direction=In + // Must be programmed the same as MR2_A0 + uint8_t MR3_B0; // Byte offset 0x59, CSR Addr 0x5402c, Direction=In + // Must be programmed the same as MR3_A0 + uint8_t Reserved5A; // Byte offset 0x5a, CSR Addr 0x5402d, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t MR11_B0; // Byte offset 0x5b, CSR Addr 0x5402d, Direction=In + // Must be programmed the same as MR11_A0 + uint8_t MR16_B0; // Byte offset 0x5c, CSR Addr 0x5402e, Direction=In + // Value to be programmed in DRAM Mode Register 16 {Channel B, Rank 0} + uint8_t MR17_B0; // Byte offset 0x5d, CSR Addr 0x5402e, Direction=In + // Value to be programmed in DRAM Mode Register 17 {Channel B, Rank 0} + uint8_t Reserved5E; // Byte offset 0x5e, CSR Addr 0x5402f, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t MR1_B1; // Byte offset 0x5f, CSR Addr 0x5402f, Direction=In + // Must be programmed the same as MR1_A0 + uint8_t MR2_B1; // Byte offset 0x60, CSR Addr 0x54030, Direction=In + // Must be programmed the same as MR2_A0 + uint8_t MR3_B1; // Byte offset 0x61, CSR Addr 0x54030, Direction=In + // Must be programmed the same as MR3_A0 + uint8_t Reserved62; // Byte offset 0x62, CSR Addr 0x54031, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t MR11_B1; // Byte offset 0x63, CSR Addr 0x54031, Direction=In + // Must be programmed the same as MR11_A0 + uint8_t MR16_B1; // Byte offset 0x64, CSR Addr 0x54032, Direction=In + // Value to be programmed in DRAM Mode Register 16 {Channel B, Rank 1} + uint8_t MR17_B1; // Byte offset 0x65, CSR Addr 0x54032, Direction=In + // Value to be programmed in DRAM Mode Register 17 {Channel B, Rank 1} + uint8_t Reserved66; // Byte offset 0x66, CSR Addr 0x54033, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved67; // Byte offset 0x67, CSR Addr 0x54033, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved68; // Byte offset 0x68, CSR Addr 0x54034, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved69; // Byte offset 0x69, CSR Addr 0x54034, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved6A; // Byte offset 0x6a, CSR Addr 0x54035, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved6B; // Byte offset 0x6b, CSR Addr 0x54035, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved6C; // Byte offset 0x6c, CSR Addr 0x54036, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved6D; // Byte offset 0x6d, CSR Addr 0x54036, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint16_t PhyConfigOverride; // Byte offset 0x6e, CSR Addr 0x54037, Direction=In + // Override PhyConfig csr. + // 0x0: Use hardware csr value for PhyConfing (recommended) + // Other values: Use value for PhyConfig instead of Hardware value. + // + uint8_t Reserved70; // Byte offset 0x70, CSR Addr 0x54038, Direction=N/A + // This field is reserved and must be programmed to 0x00. +} __attribute__ ((packed)) PMU_SMB_LPDDR3_1D_t;
diff --git a/arch/arm/include/asm/arch-c1/mnPmuSramMsgBlock_lpddr4.h b/arch/arm/include/asm/arch-c1/mnPmuSramMsgBlock_lpddr4.h new file mode 100644 index 0000000..d194621 --- /dev/null +++ b/arch/arm/include/asm/arch-c1/mnPmuSramMsgBlock_lpddr4.h
@@ -0,0 +1,557 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +/** \brief LPDDR4_1D training firmware message block structure + * + * Please refer to the Training Firmware App Note for futher information about + * the usage for Message Block. + */ +typedef struct _PMU_SMB_LPDDR4_1D_t { + uint8_t Reserved00; // Byte offset 0x00, CSR Addr 0x54000, Direction=In + // Reserved00[0:4] RFU, must be zero + // + // Reserved00[5] = Quick Rd2D during 1D Training + // 0x1 = Read Deskew will begin by enabling and quickly training the phy’s per-lane reference voltages. Training the vrefDACs CSRs will increase the maximum 1D training time by around half a millisecond, but will improve 1D training accuracy on systems with significant voltage-offsets between lane read eyes. + // 0X0 = Read Deskew will assume the messageblock’s phyVref setting is optimal for all lanes. + // + // Reserved00[6] = Enable High Effort WrDQ1D + // 0x1 = WrDQ1D will conditionally retry training at several extra RxClkDly Timings. This will increase the maximum 1D training time by up to 4 extra iterations of WrDQ1D. This is only required in systems that suffer from very large, asymmetric eye-collapse when receiving PRBS patterns. + // 0x0 = WrDQ1D assume rxClkDly values found by SI Friendly RdDqs1D will work for receiving PRBS patterns + // + // Reserved00[7] = Optimize for the special hard macros in TSMC28. + // 0x1 = set if the phy being trained was manufactured in any TSMC28 process node. + // 0x0 = otherwise, when not training a TSMC28 phy, leave this field as 0. + uint8_t MsgMisc; // Byte offset 0x01, CSR Addr 0x54000, Direction=In + // Contains various global options for training. + // + // Bit fields: + // + // MsgMisc[0] MTESTEnable + // 0x1 = Pulse primary digital test output bump at the end of each major training stage. This enables observation of training stage completion by observing the digital test output. + // 0x0 = Do not pulse primary digital test output bump + // + // MsgMisc[1] SimulationOnlyReset + // 0x1 = Verilog only simulation option to shorten duration of DRAM reset pulse length to 1ns. + // Must never be set to 1 in silicon. + // 0x0 = Use reset pulse length specifed by JEDEC standard + // + // MsgMisc[2] SimulationOnlyTraining + // 0x1 = Verilog only simulation option to shorten the duration of the training steps by performing fewer iterations. + // Must never be set to 1 in silicon. + // 0x0 = Use standard training duration. + // + // MsgMisc[3] Disable Boot Clock + // 0x1 = Disable boot frequency clock when initializing DRAM. (not recommended) + // 0x0 = Use Boot Frequency Clock + // + // MsgMisc[4] Suppress streaming messages, including assertions, regardless of HdtCtrl setting. + // Stage Completion messages, as well as training completion and error messages are + // Still sent depending on HdtCtrl setting. + // + // MsgMisc[5] PerByteMaxRdLat + // 0x1 = Each DBYTE will return dfi_rddata_valid at the lowest possible latency. This may result in unaligned data between bytes to be returned to the DFI. + // 0x0 = Every DBYTE will return dfi_rddata_valid simultaneously. This will ensure that data bytes will return aligned accesses to the DFI. + // + // MsgMisc[7-6] RFU, must be zero + // + // Notes: + // + // - SimulationOnlyReset and SimulationOnlyTraining can be used to speed up simulation run times, and must never be used in real silicon. Some VIPs may have checks on DRAM reset parameters that may need to be disabled when using SimulationOnlyReset. + uint16_t PmuRevision; // Byte offset 0x02, CSR Addr 0x54001, Direction=Out + // PMU firmware revision ID + // After training is run, this address will contain the revision ID of the firmware + uint8_t Pstate; // Byte offset 0x04, CSR Addr 0x54002, Direction=In + // Must be set to the target Pstate to be trained + // 0x0 = Pstate 0 + // 0x1 = Pstate 1 + // 0x2 = Pstate 2 + // 0x3 = Pstate 3 + // All other encodings are reserved + uint8_t PllBypassEn; // Byte offset 0x05, CSR Addr 0x54002, Direction=In + // Set according to whether target Pstate uses PHY PLL bypass + // 0x0 = PHY PLL is enabled for target Pstate + // 0x1 = PHY PLL is bypassed for target Pstate + uint16_t DRAMFreq; // Byte offset 0x06, CSR Addr 0x54003, Direction=In + // DDR data rate for the target Pstate in units of MT/s. + // For example enter 0x0640 for DDR1600. + uint8_t DfiFreqRatio; // Byte offset 0x08, CSR Addr 0x54004, Direction=In + // Frequency ratio betwen DfiCtlClk and SDRAM memclk. + // 0x1 = 1:1 + // 0x2 = 1:2 + // 0x4 = 1:4 + uint8_t BPZNResVal ; // Byte offset 0x09, CSR Addr 0x54004, Direction=In + // Must be programmed to match the precision resistor connected to Phy BP_ZN + // 0x00 = Do not program. Use current CSR value. + // 0xf0 = 240 Ohm (recommended value) + // 0x78 = 120 Ohm + // 0x28 = 40 Ohm + // All other values are reserved. + // + uint8_t PhyOdtImpedance; // Byte offset 0x0a, CSR Addr 0x54005, Direction=In + // Must be programmed to the termination impedance in ohms used by PHY during reads. + // + // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start) + // + // See PHY databook for legal termination impedance values. + // + // For digital simulation, any legal value can be used. For silicon, the users must determine the correct value through SI simulation or other methods. + uint8_t PhyDrvImpedance; // Byte offset 0x0b, CSR Addr 0x54005, Direction=In + // Must be programmed to the driver impedance in ohms used by PHY during writes for all DBYTE drivers (DQ/DM/DBI/DQS). + // + // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start) + // + // See PHY databook for legal R_on driver impedance values. + // + // For digital simulation, any value can be used that is not Hi-Z. For silicon, the users must determine the correct value through SI simulation or other methods. + uint8_t PhyVref; // Byte offset 0x0c, CSR Addr 0x54006, Direction=In + // Must be programmed with the Vref level to be used by the PHY during reads + // + // The units of this field are a percentage of VDDQ according to the following equation: + // + // Receiver Vref = VDDQ*PhyVref[6:0]/128 + // + // For example to set Vref at 0.25*VDDQ, set this field to 0x20. + // + // For digital simulation, any legal value can be used. For silicon, the users must calculate the analytical Vref by using the impedances, terminations, and series resistance present in the system. + uint8_t Lp4Misc; // Byte offset 0x0d, CSR Addr 0x54006, Direction=In + // Lp4 specific options for training. + // + // Bit fields: + // + // Lp4Misc[0] Enable dfi_reset_n + // + // 0x0 = (Recommended) PHY internal registers control memreset during training, and also after training. + // dfi_reset_n cannot control the PHY BP_MEMRESET_L pin. + // + // 0x1 = Enables dfi_reset_n to control memreset after training. + // PHY Internal registers control memreset during training only. + // To ensure that no glitches occur on BP_MEMRESET at the end of training, + // The MC must drive dfi_reset_n=1'b1 _prior to starting training_ + // + // Lp4Misc[7-1] RFU, must be zero + uint8_t Reserved0E; // Byte offset 0x0e, CSR Addr 0x54007, Direction=In + // Bit Field for enabling optional 2D training features that impact both Rx2D and Tx2D. + // + // Reserved0E[0:3]: bitTimeControl + // Input for increasing the number of data-comparisons 2D runs per (delay,voltage) point. Every time this input increases by 1, the number of 2D data comparisons is doubled. The 2D run time will increase proportionally to the number of bit times requested per point. + // 0 = 288 bits per point (legacy behavior) + // 1 = 576 bits per point + // 2 = 1.125 kilobits per point + // … + // 15 = 9 megabits per point + // + // Reserved0E[4]: Exhaustive2D + // 0 = 2D’s optimization assumes the optimal trained point is near the 1D trained point (legacy behavior) + // 1 = 2D’s optimization searches the entire passing region at the cost of run time. Recommended for optimal results any time the optimal trained point is expected to be near the edges of the eyes instead of near the 1D trained point. + // + // Reserved0E[5:7]: RFU, must be 0 + uint8_t CsTestFail; // Byte offset 0x0f, CSR Addr 0x54007, Direction=Out + // This field will be set if training fails on any rank. + // 0x0 = No failures + // non-zero = one or more ranks failed training + uint16_t SequenceCtrl; // Byte offset 0x10, CSR Addr 0x54008, Direction=In + // Controls the training steps to be run. Each bit corresponds to a training step. + // + // If the bit is set to 1, the training step will run. + // If the bit is set to 0, the training step will be skipped. + // + // Training step to bit mapping: + // SequenceCtrl[0] = Run DevInit - Device/phy initialization. Should always be set. + // SequenceCtrl[1] = Run WrLvl - Write leveling + // SequenceCtrl[2] = Run RxEn - Read gate training + // SequenceCtrl[3] = Run RdDQS1D - 1d read dqs training + // SequenceCtrl[4] = Run WrDQ1D - 1d write dq training + // SequenceCtrl[5] = RFU, must be zero + // SequenceCtrl[6] = RFU, must be zero + // SequenceCtrl[7] = RFU, must be zero + // SequenceCtrl[8] = Run RdDeskew - Per lane read dq deskew training + // SequenceCtrl[9] = Run MxRdLat - Max read latency training + // SequenceCtrl[11-10] = RFU, must be zero + // SequenceCtrl[12] = Run LPCA - CA Training + // SequenceCtrl[15-13] = RFU, must be zero + uint8_t HdtCtrl; // Byte offset 0x12, CSR Addr 0x54009, Direction=In + // To control the total number of debug messages, a verbosity subfield (HdtCtrl, Hardware Debug Trace Control) exists in the message block. Every message has a verbosity level associated with it, and as the HdtCtrl value is increased, less important s messages stop being sent through the mailboxes. The meanings of several major HdtCtrl thresholds are explained below: + // + // 0x05 = Detailed debug messages (e.g. Eye delays) + // 0x0A = Coarse debug messages (e.g. rank information) + // 0xC8 = Stage completion + // 0xC9 = Assertion messages + // 0xFF = Firmware completion messages only + // + // See Training App Note for more detailed information on what messages are included for each threshold. + // + uint8_t Reserved13; // Byte offset 0x13, CSR Addr 0x54009, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved14; // Byte offset 0x14, CSR Addr 0x5400a, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved15; // Byte offset 0x15, CSR Addr 0x5400a, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t DFIMRLMargin; // Byte offset 0x16, CSR Addr 0x5400b, Direction=In + // Margin added to smallest passing trained DFI Max Read Latency value, in units of DFI clocks. Recommended to be >= 1. See the Training App Note for more details on the training process and the use of this value. + // + // This margin must include the maximum positive drift expected in tDQSCK over the target temperature and voltage range of the users system. + uint8_t Reserved17; // Byte offset 0x17, CSR Addr 0x5400b, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t UseBroadcastMR; // Byte offset 0x18, CSR Addr 0x5400c, Direction=In + // Training firmware can optionally set per rank mode register values for DRAM partial array self-refresh features if desired. + // + // 0x0 = Use MR<0:17>_A0 for rank 0 channel A + // Use MR<0:17>_B0 for rank 0 channel B + // Use MR<0:17>_A1 for rank 1 channel A + // Use MR<0:17>_B1 for rank 1 channel B + // + // 0x1 = Use MR<0:17>_A0 setting for all channels/ranks + // + // It is recommended in most LPDDR4 system configurations to set this to 1. + // + // Note: When set to 0, only mode registers associated with Vref CA, Vref DQ, and DRAM partial array self-refresh may differ between ranks and channels. + // + uint8_t Lp4Quickboot; // Byte offset 0x19, CSR Addr 0x5400c, Direction=In + // Enable Quickboot. + uint8_t Reserved1A; // Byte offset 0x1a, CSR Addr 0x5400d, Direction=In + // Input for constraining the range of vref(DQ) values training will collect data for, usually reducing training time. However, too large of a voltage range may cause longer 2D training times while too small of a voltage range may truncate passing regions. When in doubt, leave this field set to 0. + // Used by 2D stages: Rd2D, Wr2D + // + // Reserved1A[0-3]: Rd2D Voltage Range + // 0 = Training will search all phy vref(DQ) settings + // 1 = limit to +/-2 %VDDQ from phyVref + // 2 = limit to +/-4 %VDDQ from phyVref + // … + // 15 = limit to +/-30% VDDQ from phyVref + // + // Reserved1A[4-7]: Wr2D Voltage Range + // 0 = Training will search all dram vref(DQ) settings + // 1 = limit to +/-2 %VDDQ from MR14 + // 2 = limit to +/-4 %VDDQ from MR14 + // … + // 15 = limit to +/-30% VDDQ from MR14 + uint8_t CATrainOpt; // Byte offset 0x1b, CSR Addr 0x5400d, Direction=In + // CA training option bit field + // [0] CA VREF Training + // 1 = Enable CA VREF Training + // 0 = Disable CA VREF Training + // [1-7] RFU must be zero + uint8_t X8Mode; // Byte offset 0x1c, CSR Addr 0x5400e, Direction=In + // X8 mode configuration: + // 0x0 = x16 configuration for all devices + // 0xF = x8 configuration for all devices + // All other values are RFU + uint8_t Reserved1D; // Byte offset 0x1d, CSR Addr 0x5400e, Direction=N/A + + + + + + + + + + + + + + + + + uint8_t Reserved1E; // Byte offset 0x1e, CSR Addr 0x5400f, Direction=N/A + + + + + + + + + + + + + + + + + uint8_t Reserved1F; // Byte offset 0x1f, CSR Addr 0x5400f, Direction=N/A + + + + uint8_t Reserved20; // Byte offset 0x20, CSR Addr 0x54010, Direction=N/A + + uint8_t Reserved21; // Byte offset 0x21, CSR Addr 0x54010, Direction=N/A + + uint16_t PhyConfigOverride; // Byte offset 0x22, CSR Addr 0x54011, Direction=In + // Override PhyConfig csr. + // 0x0: Use hardware csr value for PhyConfing (recommended) + // Other values: Use value for PhyConfig instead of Hardware value. + // + uint8_t EnabledDQsChA; // Byte offset 0x24, CSR Addr 0x54012, Direction=In + // Total number of DQ bits enabled in PHY Channel A + uint8_t CsPresentChA; // Byte offset 0x25, CSR Addr 0x54012, Direction=In + // Indicates presence of DRAM at each chip select for PHY channel A. + // + // 0x1 = CS0 is populated with DRAM + // 0x3 = CS0 and CS1 are populated with DRAM + // + // All other encodings are illegal + // + int8_t CDD_ChA_RR_1_0; // Byte offset 0x26, CSR Addr 0x54013, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 1 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_RR_0_1; // Byte offset 0x27, CSR Addr 0x54013, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 0 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_RW_1_1; // Byte offset 0x28, CSR Addr 0x54014, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_RW_1_0; // Byte offset 0x29, CSR Addr 0x54014, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_RW_0_1; // Byte offset 0x2a, CSR Addr 0x54015, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 0 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_RW_0_0; // Byte offset 0x2b, CSR Addr 0x54015, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs0 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WR_1_1; // Byte offset 0x2c, CSR Addr 0x54016, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WR_1_0; // Byte offset 0x2d, CSR Addr 0x54016, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WR_0_1; // Byte offset 0x2e, CSR Addr 0x54017, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WR_0_0; // Byte offset 0x2f, CSR Addr 0x54017, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WW_1_0; // Byte offset 0x30, CSR Addr 0x54018, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 1 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WW_0_1; // Byte offset 0x31, CSR Addr 0x54018, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 0 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + uint8_t MR1_A0; // Byte offset 0x32, CSR Addr 0x54019, Direction=In + // Value to be programmed in DRAM Mode Register 1 {Channel A, Rank 0} + uint8_t MR2_A0; // Byte offset 0x33, CSR Addr 0x54019, Direction=In + // Value to be programmed in DRAM Mode Register 2 {Channel A, Rank 0} + uint8_t MR3_A0; // Byte offset 0x34, CSR Addr 0x5401a, Direction=In + // Value to be programmed in DRAM Mode Register 3 {Channel A, Rank 0} + uint8_t MR4_A0; // Byte offset 0x35, CSR Addr 0x5401a, Direction=In + // Value to be programmed in DRAM Mode Register 4 {Channel A, Rank 0} + uint8_t MR11_A0; // Byte offset 0x36, CSR Addr 0x5401b, Direction=In + // Value to be programmed in DRAM Mode Register 11 {Channel A, Rank 0} + uint8_t MR12_A0; // Byte offset 0x37, CSR Addr 0x5401b, Direction=In + // Value to be programmed in DRAM Mode Register 12 {Channel A, Rank 0} + uint8_t MR13_A0; // Byte offset 0x38, CSR Addr 0x5401c, Direction=In + // Value to be programmed in DRAM Mode Register 13 {Channel A, Rank 0} + uint8_t MR14_A0; // Byte offset 0x39, CSR Addr 0x5401c, Direction=In + // Value to be programmed in DRAM Mode Register 14 {Channel A, Rank 0} + uint8_t MR16_A0; // Byte offset 0x3a, CSR Addr 0x5401d, Direction=In + // Value to be programmed in DRAM Mode Register 16 {Channel A, Rank 0} + uint8_t MR17_A0; // Byte offset 0x3b, CSR Addr 0x5401d, Direction=In + // Value to be programmed in DRAM Mode Register 17 {Channel A, Rank 0} + uint8_t MR22_A0; // Byte offset 0x3c, CSR Addr 0x5401e, Direction=In + // Value to be programmed in DRAM Mode Register 22 {Channel A, Rank 0} + uint8_t MR24_A0; // Byte offset 0x3d, CSR Addr 0x5401e, Direction=In + // Value to be programmed in DRAM Mode Register 24 {Channel A, Rank 0} + uint8_t MR1_A1; // Byte offset 0x3e, CSR Addr 0x5401f, Direction=In + // Value to be programmed in DRAM Mode Register 1 {Channel A, Rank 1} + uint8_t MR2_A1; // Byte offset 0x3f, CSR Addr 0x5401f, Direction=In + // Value to be programmed in DRAM Mode Register 2 {Channel A, Rank 1} + uint8_t MR3_A1; // Byte offset 0x40, CSR Addr 0x54020, Direction=In + // Value to be programmed in DRAM Mode Register 3 {Channel A, Rank 1} + uint8_t MR4_A1; // Byte offset 0x41, CSR Addr 0x54020, Direction=In + // Value to be programmed in DRAM Mode Register 4 {Channel A, Rank 1} + uint8_t MR11_A1; // Byte offset 0x42, CSR Addr 0x54021, Direction=In + // Value to be programmed in DRAM Mode Register 11 {Channel A, Rank 1} + uint8_t MR12_A1; // Byte offset 0x43, CSR Addr 0x54021, Direction=In + // Value to be programmed in DRAM Mode Register 12 {Channel A, Rank 1} + uint8_t MR13_A1; // Byte offset 0x44, CSR Addr 0x54022, Direction=In + // Value to be programmed in DRAM Mode Register 13 {Channel A, Rank 1} + uint8_t MR14_A1; // Byte offset 0x45, CSR Addr 0x54022, Direction=In + // Value to be programmed in DRAM Mode Register 14 {Channel A, Rank 1} + uint8_t MR16_A1; // Byte offset 0x46, CSR Addr 0x54023, Direction=In + // Value to be programmed in DRAM Mode Register 16 {Channel A, Rank 1} + uint8_t MR17_A1; // Byte offset 0x47, CSR Addr 0x54023, Direction=In + // Value to be programmed in DRAM Mode Register 17 {Channel A, Rank 1} + uint8_t MR22_A1; // Byte offset 0x48, CSR Addr 0x54024, Direction=In + // Value to be programmed in DRAM Mode Register 22 {Channel A, Rank 1} + uint8_t MR24_A1; // Byte offset 0x49, CSR Addr 0x54024, Direction=In + // Value to be programmed in DRAM Mode Register 24 {Channel A, Rank 1} + uint8_t CATerminatingRankChA; // Byte offset 0x4a, CSR Addr 0x54025, Direction=In + // Terminating Rank for CA bus on Channel A + // 0x0 = Rank 0 is terminating rank + // 0x1 = Rank 1 is terminating rank + uint8_t Reserved4B; // Byte offset 0x4b, CSR Addr 0x54025, Direction=N/A + + uint8_t Reserved4C; // Byte offset 0x4c, CSR Addr 0x54026, Direction=N/A + + uint8_t Reserved4D; // Byte offset 0x4d, CSR Addr 0x54026, Direction=N/A + + uint8_t Reserved4E; // Byte offset 0x4e, CSR Addr 0x54027, Direction=N/A + + uint8_t Reserved4F; // Byte offset 0x4f, CSR Addr 0x54027, Direction=N/A + + uint8_t Reserved50; // Byte offset 0x50, CSR Addr 0x54028, Direction=N/A + + uint8_t Reserved51; // Byte offset 0x51, CSR Addr 0x54028, Direction=N/A + + uint8_t Reserved52; // Byte offset 0x52, CSR Addr 0x54029, Direction=N/A + + uint8_t Reserved53; // Byte offset 0x53, CSR Addr 0x54029, Direction=N/A + + uint8_t Reserved54; // Byte offset 0x54, CSR Addr 0x5402a, Direction=N/A + + uint8_t Reserved55; // Byte offset 0x55, CSR Addr 0x5402a, Direction=N/A + + uint8_t Reserved56; // Byte offset 0x56, CSR Addr 0x5402b, Direction=N/A + + uint8_t EnabledDQsChB; // Byte offset 0x57, CSR Addr 0x5402b, Direction=In + // Total number of DQ bits enabled in PHY Channel B + uint8_t CsPresentChB; // Byte offset 0x58, CSR Addr 0x5402c, Direction=In + // Indicates presence of DRAM at each chip select for PHY channel B. + // + // 0x0 = No chip selects are populated with DRAM + // 0x1 = CS0 is populated with DRAM + // 0x3 = CS0 and CS1 are populated with DRAM + // + // All other encodings are illegal + // + int8_t CDD_ChB_RR_1_0; // Byte offset 0x59, CSR Addr 0x5402c, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 1 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_RR_0_1; // Byte offset 0x5a, CSR Addr 0x5402d, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 0 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_RW_1_1; // Byte offset 0x5b, CSR Addr 0x5402d, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_RW_1_0; // Byte offset 0x5c, CSR Addr 0x5402e, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_RW_0_1; // Byte offset 0x5d, CSR Addr 0x5402e, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 0 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_RW_0_0; // Byte offset 0x5e, CSR Addr 0x5402f, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs01 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WR_1_1; // Byte offset 0x5f, CSR Addr 0x5402f, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WR_1_0; // Byte offset 0x60, CSR Addr 0x54030, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WR_0_1; // Byte offset 0x61, CSR Addr 0x54030, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WR_0_0; // Byte offset 0x62, CSR Addr 0x54031, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WW_1_0; // Byte offset 0x63, CSR Addr 0x54031, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 1 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WW_0_1; // Byte offset 0x64, CSR Addr 0x54032, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 0 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + uint8_t MR1_B0; // Byte offset 0x65, CSR Addr 0x54032, Direction=In + // Value to be programmed in DRAM Mode Register 1 {Channel B, Rank 0} + uint8_t MR2_B0; // Byte offset 0x66, CSR Addr 0x54033, Direction=In + // Value to be programmed in DRAM Mode Register 2 {Channel B, Rank 0} + uint8_t MR3_B0; // Byte offset 0x67, CSR Addr 0x54033, Direction=In + // Value to be programmed in DRAM Mode Register 3 {Channel B, Rank 0} + uint8_t MR4_B0; // Byte offset 0x68, CSR Addr 0x54034, Direction=In + // Value to be programmed in DRAM Mode Register 4 {Channel B, Rank 0} + uint8_t MR11_B0; // Byte offset 0x69, CSR Addr 0x54034, Direction=In + // Value to be programmed in DRAM Mode Register 11 {Channel B, Rank 0} + uint8_t MR12_B0; // Byte offset 0x6a, CSR Addr 0x54035, Direction=In + // Value to be programmed in DRAM Mode Register 12 {Channel B, Rank 0} + uint8_t MR13_B0; // Byte offset 0x6b, CSR Addr 0x54035, Direction=In + // Value to be programmed in DRAM Mode Register 13 {Channel B, Rank 0} + uint8_t MR14_B0; // Byte offset 0x6c, CSR Addr 0x54036, Direction=In + // Value to be programmed in DRAM Mode Register 14 {Channel B, Rank 0} + uint8_t MR16_B0; // Byte offset 0x6d, CSR Addr 0x54036, Direction=In + // Value to be programmed in DRAM Mode Register 16 {Channel B, Rank 0} + uint8_t MR17_B0; // Byte offset 0x6e, CSR Addr 0x54037, Direction=In + // Value to be programmed in DRAM Mode Register 17 {Channel B, Rank 0} + uint8_t MR22_B0; // Byte offset 0x6f, CSR Addr 0x54037, Direction=In + // Value to be programmed in DRAM Mode Register 22 {Channel B, Rank 0} + uint8_t MR24_B0; // Byte offset 0x70, CSR Addr 0x54038, Direction=In + // Value to be programmed in DRAM Mode Register 24 {Channel B, Rank 0} + uint8_t MR1_B1; // Byte offset 0x71, CSR Addr 0x54038, Direction=In + // Value to be programmed in DRAM Mode Register 1 {Channel B, Rank 1} + uint8_t MR2_B1; // Byte offset 0x72, CSR Addr 0x54039, Direction=In + // Value to be programmed in DRAM Mode Register 2 {Channel B, Rank 1} + uint8_t MR3_B1; // Byte offset 0x73, CSR Addr 0x54039, Direction=In + // Value to be programmed in DRAM Mode Register 3 {Channel B, Rank 1} + uint8_t MR4_B1; // Byte offset 0x74, CSR Addr 0x5403a, Direction=In + // Value to be programmed in DRAM Mode Register 4 {Channel B, Rank 1} + uint8_t MR11_B1; // Byte offset 0x75, CSR Addr 0x5403a, Direction=In + // Value to be programmed in DRAM Mode Register 11 {Channel B, Rank 1} + uint8_t MR12_B1; // Byte offset 0x76, CSR Addr 0x5403b, Direction=In + // Value to be programmed in DRAM Mode Register 12 {Channel B, Rank 1} + uint8_t MR13_B1; // Byte offset 0x77, CSR Addr 0x5403b, Direction=In + // Value to be programmed in DRAM Mode Register 13 {Channel B, Rank 1} + uint8_t MR14_B1; // Byte offset 0x78, CSR Addr 0x5403c, Direction=In + // Value to be programmed in DRAM Mode Register 14 {Channel B, Rank 1} + uint8_t MR16_B1; // Byte offset 0x79, CSR Addr 0x5403c, Direction=In + // Value to be programmed in DRAM Mode Register 16 {Channel B, Rank 1} + uint8_t MR17_B1; // Byte offset 0x7a, CSR Addr 0x5403d, Direction=In + // Value to be programmed in DRAM Mode Register 17 {Channel B, Rank 1} + uint8_t MR22_B1; // Byte offset 0x7b, CSR Addr 0x5403d, Direction=In + // Value to be programmed in DRAM Mode Register 22 {Channel B, Rank 1} + uint8_t MR24_B1; // Byte offset 0x7c, CSR Addr 0x5403e, Direction=In + // Value to be programmed in DRAM Mode Register 24 {Channel B, Rank 1} + uint8_t CATerminatingRankChB; // Byte offset 0x7d, CSR Addr 0x5403e, Direction=In + // Terminating Rank for CA bus on Channel B + // 0x0 = Rank 0 is terminating rank + // 0x1 = Rank 1 is terminating rank + uint8_t Reserved7E; // Byte offset 0x7e, CSR Addr 0x5403f, Direction=N/A + + uint8_t Reserved7F; // Byte offset 0x7f, CSR Addr 0x5403f, Direction=N/A + + uint8_t Reserved80; // Byte offset 0x80, CSR Addr 0x54040, Direction=N/A + + uint8_t Reserved81; // Byte offset 0x81, CSR Addr 0x54040, Direction=N/A + + uint8_t Reserved82; // Byte offset 0x82, CSR Addr 0x54041, Direction=N/A + + uint8_t Reserved83; // Byte offset 0x83, CSR Addr 0x54041, Direction=N/A + + uint8_t Reserved84; // Byte offset 0x84, CSR Addr 0x54042, Direction=N/A + + uint8_t Reserved85; // Byte offset 0x85, CSR Addr 0x54042, Direction=N/A + + uint8_t Reserved86; // Byte offset 0x86, CSR Addr 0x54043, Direction=N/A + + uint8_t Reserved87; // Byte offset 0x87, CSR Addr 0x54043, Direction=N/A + + uint8_t Reserved88; // Byte offset 0x88, CSR Addr 0x54044, Direction=N/A + + uint8_t Reserved89; // Byte offset 0x89, CSR Addr 0x54044, Direction=N/A + +} __attribute__ ((packed)) PMU_SMB_LPDDR4_1D_t;
diff --git a/arch/arm/include/asm/arch-c1/mnPmuSramMsgBlock_lpddr4_2d.h b/arch/arm/include/asm/arch-c1/mnPmuSramMsgBlock_lpddr4_2d.h new file mode 100644 index 0000000..c6ab3d3 --- /dev/null +++ b/arch/arm/include/asm/arch-c1/mnPmuSramMsgBlock_lpddr4_2d.h
@@ -0,0 +1,557 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +/** \brief LPDDR4_2D training firmware message block structure + * + * Please refer to the Training Firmware App Note for futher information about + * the usage for Message Block. + */ +typedef struct _PMU_SMB_LPDDR4_2D_t { + uint8_t Reserved00; // Byte offset 0x00, CSR Addr 0x54000, Direction=In + // Reserved00[0:4] RFU, must be zero + // + // Reserved00[5] = Quick Rd2D during 1D Training + // 0x1 = Read Deskew will begin by enabling and quickly training the phy’s per-lane reference voltages. Training the vrefDACs CSRs will increase the maximum 1D training time by around half a millisecond, but will improve 1D training accuracy on systems with significant voltage-offsets between lane read eyes. + // 0X0 = Read Deskew will assume the messageblock’s phyVref setting is optimal for all lanes. + // + // Reserved00[6] = Enable High Effort WrDQ1D + // 0x1 = WrDQ1D will conditionally retry training at several extra RxClkDly Timings. This will increase the maximum 1D training time by up to 4 extra iterations of WrDQ1D. This is only required in systems that suffer from very large, asymmetric eye-collapse when receiving PRBS patterns. + // 0x0 = WrDQ1D assume rxClkDly values found by SI Friendly RdDqs1D will work for receiving PRBS patterns + // + // Reserved00[7] = Optimize for the special hard macros in TSMC28. + // 0x1 = set if the phy being trained was manufactured in any TSMC28 process node. + // 0x0 = otherwise, when not training a TSMC28 phy, leave this field as 0. + uint8_t MsgMisc; // Byte offset 0x01, CSR Addr 0x54000, Direction=In + // Contains various global options for training. + // + // Bit fields: + // + // MsgMisc[0] MTESTEnable + // 0x1 = Pulse primary digital test output bump at the end of each major training stage. This enables observation of training stage completion by observing the digital test output. + // 0x0 = Do not pulse primary digital test output bump + // + // MsgMisc[1] SimulationOnlyReset + // 0x1 = Verilog only simulation option to shorten duration of DRAM reset pulse length to 1ns. + // Must never be set to 1 in silicon. + // 0x0 = Use reset pulse length specifed by JEDEC standard + // + // MsgMisc[2] SimulationOnlyTraining + // 0x1 = Verilog only simulation option to shorten the duration of the training steps by performing fewer iterations. + // Must never be set to 1 in silicon. + // 0x0 = Use standard training duration. + // + // MsgMisc[3] Disable Boot Clock + // 0x1 = Disable boot frequency clock when initializing DRAM. (not recommended) + // 0x0 = Use Boot Frequency Clock + // + // MsgMisc[4] Suppress streaming messages, including assertions, regardless of HdtCtrl setting. + // Stage Completion messages, as well as training completion and error messages are + // Still sent depending on HdtCtrl setting. + // + // MsgMisc[5] PerByteMaxRdLat + // 0x1 = Each DBYTE will return dfi_rddata_valid at the lowest possible latency. This may result in unaligned data between bytes to be returned to the DFI. + // 0x0 = Every DBYTE will return dfi_rddata_valid simultaneously. This will ensure that data bytes will return aligned accesses to the DFI. + // + // MsgMisc[7-6] RFU, must be zero + // + // Notes: + // + // - SimulationOnlyReset and SimulationOnlyTraining can be used to speed up simulation run times, and must never be used in real silicon. Some VIPs may have checks on DRAM reset parameters that may need to be disabled when using SimulationOnlyReset. + uint16_t PmuRevision; // Byte offset 0x02, CSR Addr 0x54001, Direction=Out + // PMU firmware revision ID + // After training is run, this address will contain the revision ID of the firmware + uint8_t Pstate; // Byte offset 0x04, CSR Addr 0x54002, Direction=In + // Must be set to the target Pstate to be trained + // 0x0 = Pstate 0 + // 0x1 = Pstate 1 + // 0x2 = Pstate 2 + // 0x3 = Pstate 3 + // All other encodings are reserved + uint8_t PllBypassEn; // Byte offset 0x05, CSR Addr 0x54002, Direction=In + // Set according to whether target Pstate uses PHY PLL bypass + // 0x0 = PHY PLL is enabled for target Pstate + // 0x1 = PHY PLL is bypassed for target Pstate + uint16_t DRAMFreq; // Byte offset 0x06, CSR Addr 0x54003, Direction=In + // DDR data rate for the target Pstate in units of MT/s. + // For example enter 0x0640 for DDR1600. + uint8_t DfiFreqRatio; // Byte offset 0x08, CSR Addr 0x54004, Direction=In + // Frequency ratio betwen DfiCtlClk and SDRAM memclk. + // 0x1 = 1:1 + // 0x2 = 1:2 + // 0x4 = 1:4 + uint8_t BPZNResVal ; // Byte offset 0x09, CSR Addr 0x54004, Direction=In + // Must be programmed to match the precision resistor connected to Phy BP_ZN + // 0x00 = Do not program. Use current CSR value. + // 0xf0 = 240 Ohm (recommended value) + // 0x78 = 120 Ohm + // 0x28 = 40 Ohm + // All other values are reserved. + // + uint8_t PhyOdtImpedance; // Byte offset 0x0a, CSR Addr 0x54005, Direction=In + // Must be programmed to the termination impedance in ohms used by PHY during reads. + // + // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start) + // + // See PHY databook for legal termination impedance values. + // + // For digital simulation, any legal value can be used. For silicon, the users must determine the correct value through SI simulation or other methods. + uint8_t PhyDrvImpedance; // Byte offset 0x0b, CSR Addr 0x54005, Direction=In + // Must be programmed to the driver impedance in ohms used by PHY during writes for all DBYTE drivers (DQ/DM/DBI/DQS). + // + // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start) + // + // See PHY databook for legal R_on driver impedance values. + // + // For digital simulation, any value can be used that is not Hi-Z. For silicon, the users must determine the correct value through SI simulation or other methods. + uint8_t PhyVref; // Byte offset 0x0c, CSR Addr 0x54006, Direction=In + // Must be programmed with the Vref level to be used by the PHY during reads + // + // The units of this field are a percentage of VDDQ according to the following equation: + // + // Receiver Vref = VDDQ*PhyVref[6:0]/128 + // + // For example to set Vref at 0.25*VDDQ, set this field to 0x20. + // + // For digital simulation, any legal value can be used. For silicon, the users must calculate the analytical Vref by using the impedances, terminations, and series resistance present in the system. + uint8_t Lp4Misc; // Byte offset 0x0d, CSR Addr 0x54006, Direction=In + // Lp4 specific options for training. + // + // Bit fields: + // + // Lp4Misc[0] Enable dfi_reset_n + // + // 0x0 = (Recommended) PHY internal registers control memreset during training, and also after training. + // dfi_reset_n cannot control the PHY BP_MEMRESET_L pin. + // + // 0x1 = Enables dfi_reset_n to control memreset after training. + // PHY Internal registers control memreset during training only. + // To ensure that no glitches occur on BP_MEMRESET at the end of training, + // The MC must drive dfi_reset_n=1'b1 _prior to starting training_ + // + // Lp4Misc[7-1] RFU, must be zero + uint8_t Reserved0E; // Byte offset 0x0e, CSR Addr 0x54007, Direction=In + // Bit Field for enabling optional 2D training features that impact both Rx2D and Tx2D. + // + // Reserved0E[0:3]: bitTimeControl + // Input for increasing the number of data-comparisons 2D runs per (delay,voltage) point. Every time this input increases by 1, the number of 2D data comparisons is doubled. The 2D run time will increase proportionally to the number of bit times requested per point. + // 0 = 288 bits per point (legacy behavior) + // 1 = 576 bits per point + // 2 = 1.125 kilobits per point + // … + // 15 = 9 megabits per point + // + // Reserved0E[4]: Exhaustive2D + // 0 = 2D’s optimization assumes the optimal trained point is near the 1D trained point (legacy behavior) + // 1 = 2D’s optimization searches the entire passing region at the cost of run time. Recommended for optimal results any time the optimal trained point is expected to be near the edges of the eyes instead of near the 1D trained point. + // + // Reserved0E[5:7]: RFU, must be 0 + uint8_t CsTestFail; // Byte offset 0x0f, CSR Addr 0x54007, Direction=Out + // This field will be set if training fails on any rank. + // 0x0 = No failures + // non-zero = one or more ranks failed training + uint16_t SequenceCtrl; // Byte offset 0x10, CSR Addr 0x54008, Direction=In + // Controls the training steps to be run. Each bit corresponds to a training step. + // + // If the bit is set to 1, the training step will run. + // If the bit is set to 0, the training step will be skipped. + // + // Training step to bit mapping: + // SequenceCtrl[0] = Run DevInit - Device/phy initialization. Should always be set. + // SequenceCtrl[1] = RFU, must be zero + // SequenceCtrl[2] = RFU, must be zero + // SequenceCtrl[3] = RFU, must be zero + // SequenceCtrl[4] = RFU, must be zero + // SequenceCtrl[5] = Run rd2D - 2d read dqs training + // SequenceCtrl[6] = Run wr2D - 2d write dq training + // SequenceCtrl[7] = RFU, must be zero + // SequenceCtrl[8] = RFU, must be zero + // SequenceCtrl[9] = RFU, must be zero + // SequenceCtrl[11-10] = RFU, must be zero + // SequenceCtrl[12] = RFU, must be zero + // SequenceCtrl[15-13] = RFU, must be zero + uint8_t HdtCtrl; // Byte offset 0x12, CSR Addr 0x54009, Direction=In + // To control the total number of debug messages, a verbosity subfield (HdtCtrl, Hardware Debug Trace Control) exists in the message block. Every message has a verbosity level associated with it, and as the HdtCtrl value is increased, less important s messages stop being sent through the mailboxes. The meanings of several major HdtCtrl thresholds are explained below: + // + // 0x05 = Detailed debug messages (e.g. Eye delays) + // 0x0A = Coarse debug messages (e.g. rank information) + // 0xC8 = Stage completion + // 0xC9 = Assertion messages + // 0xFF = Firmware completion messages only + // + // See Training App Note for more detailed information on what messages are included for each threshold. + // + uint8_t Reserved13; // Byte offset 0x13, CSR Addr 0x54009, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved14; // Byte offset 0x14, CSR Addr 0x5400a, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved15; // Byte offset 0x15, CSR Addr 0x5400a, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t DFIMRLMargin; // Byte offset 0x16, CSR Addr 0x5400b, Direction=In + // Margin added to smallest passing trained DFI Max Read Latency value, in units of DFI clocks. Recommended to be >= 1. See the Training App Note for more details on the training process and the use of this value. + // + // This margin must include the maximum positive drift expected in tDQSCK over the target temperature and voltage range of the users system. + uint8_t Reserved17; // Byte offset 0x17, CSR Addr 0x5400b, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t UseBroadcastMR; // Byte offset 0x18, CSR Addr 0x5400c, Direction=In + // Training firmware can optionally set per rank mode register values for DRAM partial array self-refresh features if desired. + // + // 0x0 = Use MR<0:17>_A0 for rank 0 channel A + // Use MR<0:17>_B0 for rank 0 channel B + // Use MR<0:17>_A1 for rank 1 channel A + // Use MR<0:17>_B1 for rank 1 channel B + // + // 0x1 = Use MR<0:17>_A0 setting for all channels/ranks + // + // It is recommended in most LPDDR4 system configurations to set this to 1. + // + // Note: When set to 0, only mode registers associated with Vref CA, Vref DQ, and DRAM partial array self-refresh may differ between ranks and channels. + // + uint8_t Reserved19; // Byte offset 0x19, CSR Addr 0x5400c, Direction=N/A + + uint8_t Reserved1A; // Byte offset 0x1a, CSR Addr 0x5400d, Direction=In + // Input for constraining the range of vref(DQ) values training will collect data for, usually reducing training time. However, too large of a voltage range may cause longer 2D training times while too small of a voltage range may truncate passing regions. When in doubt, leave this field set to 0. + // Used by 2D stages: Rd2D, Wr2D + // + // Reserved1A[0-3]: Rd2D Voltage Range + // 0 = Training will search all phy vref(DQ) settings + // 1 = limit to +/-2 %VDDQ from phyVref + // 2 = limit to +/-4 %VDDQ from phyVref + // … + // 15 = limit to +/-30% VDDQ from phyVref + // + // Reserved1A[4-7]: Wr2D Voltage Range + // 0 = Training will search all dram vref(DQ) settings + // 1 = limit to +/-2 %VDDQ from MR14 + // 2 = limit to +/-4 %VDDQ from MR14 + // … + // 15 = limit to +/-30% VDDQ from MR14 + uint8_t CATrainOpt; // Byte offset 0x1b, CSR Addr 0x5400d, Direction=In + // CA training option bit field + // [0] CA VREF Setting + // 1 = Set MR12 from internal register + // 0 = Set MR12 from message block + // [1-7] RFU must be zero + uint8_t X8Mode; // Byte offset 0x1c, CSR Addr 0x5400e, Direction=In + // X8 mode configuration: + // 0x0 = x16 configuration for all devices + // 0xF = x8 configuration for all devices + // All other values are RFU + uint8_t RX2D_TrainOpt; // Byte offset 0x1d, CSR Addr 0x5400e, Direction=In + // Bit fields, if 2D read training enabled, then use these additional options: + // [0] DFE + // 1 = Run rx2D with DFE + // 0 = Run rx2D with DFE off + // [1-2] Voltage Step Size (2^n) + // 3 = 8 DAC settings between checked values + // 2 = 4 DAC settings between checked values + // 1 = 2 DAC settings between checked values + // 0 = 1 DAC settings between checked values + // [3-4] Delay Step Size (2^n) + // 3 = 8 LCDL delays between checked values + // 2 = 4 LCDL delays between checked values + // 1 = 2 LCDL delays between checked values + // 0 = 1 LCDL delays between checked values + // [5-7] RFU, must be zero + // + uint8_t TX2D_TrainOpt; // Byte offset 0x1e, CSR Addr 0x5400f, Direction=In + // Bit fields, if 2D write training is enabled, then use these additional options: + // [0] FFE + // 1 = Train tx2D with FFE + // 0 = Train tx2D with FFE off + // [1-2] Voltage Step Size (2^n) + // 3 = 8 DAC settings between checked values + // 2 = 4 DAC settings between checked values + // 1 = 2 DAC settings between checked values + // 0 = 1 DAC settings between checked values + // [3-4] Delay Step Size (2^n) + // 3 = 8 LCDL delays between checked values + // 2 = 4 LCDL delays between checked values + // 1 = 2 LCDL delays between checked values + // 0 = 1 LCDL delays between checked values + // [5-7] RFU, must be zero + // + uint8_t Share2DVrefResult; // Byte offset 0x1f, CSR Addr 0x5400f, Direction=In + // Bitmap that designates the phy's vref source for every pstate + // If Share2DVrefResult[x] = 0, then after 2D training, pstate x will continue using the phyVref provided in pstate x’s 1D messageblock. + // If Share2DVrefResult[x] = 1, then after 2D training, pstate x will use the per-lane VrefDAC0/1 CSRs trained by 2d training. + uint8_t Delay_Weight2D; // Byte offset 0x20, CSR Addr 0x54010, Direction=In + // During 2D training, the ideal eye center changes depending on how valuable delay margin is compared to voltage margin. delay_weight2D sets the value, or weight, of one step of delay margin. The ratio of voltage_weight2D to delay_weight2D will be used by 2D training to choose your preferred center point. There are 32 delay steps in a perfect eye. + uint8_t Voltage_Weight2D; // Byte offset 0x21, CSR Addr 0x54010, Direction=In + // During 2D training, the ideal eye center changes depending on how valuable voltage margin is compared to delay margin. voltage_weight2D sets the value, or weight, of one step of voltage margin. The ratio of voltage_weight2D to delay_weight2D will be used by 2D training to choose your preferred center point. There are 128 voltage steps in a perfect eye. + uint16_t PhyConfigOverride; // Byte offset 0x22, CSR Addr 0x54011, Direction=In + // Override PhyConfig csr. + // 0x0: Use hardware csr value for PhyConfing (recommended) + // Other values: Use value for PhyConfig instead of Hardware value. + // + uint8_t EnabledDQsChA; // Byte offset 0x24, CSR Addr 0x54012, Direction=In + // Total number of DQ bits enabled in PHY Channel A + uint8_t CsPresentChA; // Byte offset 0x25, CSR Addr 0x54012, Direction=In + // Indicates presence of DRAM at each chip select for PHY channel A. + // + // 0x1 = CS0 is populated with DRAM + // 0x3 = CS0 and CS1 are populated with DRAM + // + // All other encodings are illegal + // + int8_t CDD_ChA_RR_1_0; // Byte offset 0x26, CSR Addr 0x54013, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 1 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_RR_0_1; // Byte offset 0x27, CSR Addr 0x54013, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 0 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_RW_1_1; // Byte offset 0x28, CSR Addr 0x54014, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_RW_1_0; // Byte offset 0x29, CSR Addr 0x54014, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_RW_0_1; // Byte offset 0x2a, CSR Addr 0x54015, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 0 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_RW_0_0; // Byte offset 0x2b, CSR Addr 0x54015, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs0 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WR_1_1; // Byte offset 0x2c, CSR Addr 0x54016, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WR_1_0; // Byte offset 0x2d, CSR Addr 0x54016, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WR_0_1; // Byte offset 0x2e, CSR Addr 0x54017, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WR_0_0; // Byte offset 0x2f, CSR Addr 0x54017, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WW_1_0; // Byte offset 0x30, CSR Addr 0x54018, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 1 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WW_0_1; // Byte offset 0x31, CSR Addr 0x54018, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 0 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + uint8_t MR1_A0; // Byte offset 0x32, CSR Addr 0x54019, Direction=In + // Value to be programmed in DRAM Mode Register 1 {Channel A, Rank 0} + uint8_t MR2_A0; // Byte offset 0x33, CSR Addr 0x54019, Direction=In + // Value to be programmed in DRAM Mode Register 2 {Channel A, Rank 0} + uint8_t MR3_A0; // Byte offset 0x34, CSR Addr 0x5401a, Direction=In + // Value to be programmed in DRAM Mode Register 3 {Channel A, Rank 0} + uint8_t MR4_A0; // Byte offset 0x35, CSR Addr 0x5401a, Direction=In + // Value to be programmed in DRAM Mode Register 4 {Channel A, Rank 0} + uint8_t MR11_A0; // Byte offset 0x36, CSR Addr 0x5401b, Direction=In + // Value to be programmed in DRAM Mode Register 11 {Channel A, Rank 0} + uint8_t MR12_A0; // Byte offset 0x37, CSR Addr 0x5401b, Direction=In + // Value to be programmed in DRAM Mode Register 12 {Channel A, Rank 0} + uint8_t MR13_A0; // Byte offset 0x38, CSR Addr 0x5401c, Direction=In + // Value to be programmed in DRAM Mode Register 13 {Channel A, Rank 0} + uint8_t MR14_A0; // Byte offset 0x39, CSR Addr 0x5401c, Direction=In + // Value to be programmed in DRAM Mode Register 14 {Channel A, Rank 0} + uint8_t MR16_A0; // Byte offset 0x3a, CSR Addr 0x5401d, Direction=In + // Value to be programmed in DRAM Mode Register 16 {Channel A, Rank 0} + uint8_t MR17_A0; // Byte offset 0x3b, CSR Addr 0x5401d, Direction=In + // Value to be programmed in DRAM Mode Register 17 {Channel A, Rank 0} + uint8_t MR22_A0; // Byte offset 0x3c, CSR Addr 0x5401e, Direction=In + // Value to be programmed in DRAM Mode Register 22 {Channel A, Rank 0} + uint8_t MR24_A0; // Byte offset 0x3d, CSR Addr 0x5401e, Direction=In + // Value to be programmed in DRAM Mode Register 24 {Channel A, Rank 0} + uint8_t MR1_A1; // Byte offset 0x3e, CSR Addr 0x5401f, Direction=In + // Value to be programmed in DRAM Mode Register 1 {Channel A, Rank 1} + uint8_t MR2_A1; // Byte offset 0x3f, CSR Addr 0x5401f, Direction=In + // Value to be programmed in DRAM Mode Register 2 {Channel A, Rank 1} + uint8_t MR3_A1; // Byte offset 0x40, CSR Addr 0x54020, Direction=In + // Value to be programmed in DRAM Mode Register 3 {Channel A, Rank 1} + uint8_t MR4_A1; // Byte offset 0x41, CSR Addr 0x54020, Direction=In + // Value to be programmed in DRAM Mode Register 4 {Channel A, Rank 1} + uint8_t MR11_A1; // Byte offset 0x42, CSR Addr 0x54021, Direction=In + // Value to be programmed in DRAM Mode Register 11 {Channel A, Rank 1} + uint8_t MR12_A1; // Byte offset 0x43, CSR Addr 0x54021, Direction=In + // Value to be programmed in DRAM Mode Register 12 {Channel A, Rank 1} + uint8_t MR13_A1; // Byte offset 0x44, CSR Addr 0x54022, Direction=In + // Value to be programmed in DRAM Mode Register 13 {Channel A, Rank 1} + uint8_t MR14_A1; // Byte offset 0x45, CSR Addr 0x54022, Direction=In + // Value to be programmed in DRAM Mode Register 14 {Channel A, Rank 1} + uint8_t MR16_A1; // Byte offset 0x46, CSR Addr 0x54023, Direction=In + // Value to be programmed in DRAM Mode Register 16 {Channel A, Rank 1} + uint8_t MR17_A1; // Byte offset 0x47, CSR Addr 0x54023, Direction=In + // Value to be programmed in DRAM Mode Register 17 {Channel A, Rank 1} + uint8_t MR22_A1; // Byte offset 0x48, CSR Addr 0x54024, Direction=In + // Value to be programmed in DRAM Mode Register 22 {Channel A, Rank 1} + uint8_t MR24_A1; // Byte offset 0x49, CSR Addr 0x54024, Direction=In + // Value to be programmed in DRAM Mode Register 24 {Channel A, Rank 1} + uint8_t CATerminatingRankChA; // Byte offset 0x4a, CSR Addr 0x54025, Direction=In + // Terminating Rank for CA bus on Channel A + // 0x0 = Rank 0 is terminating rank + // 0x1 = Rank 1 is terminating rank + uint8_t Reserved4B; // Byte offset 0x4b, CSR Addr 0x54025, Direction=N/A + + uint8_t Reserved4C; // Byte offset 0x4c, CSR Addr 0x54026, Direction=N/A + + uint8_t TrainedVREFDQ_A0; // Byte offset 0x4d, CSR Addr 0x54026, Direction=Out + // Trained DQ Vref setting for Ch A Rank 0 + uint8_t TrainedVREFDQ_A1; // Byte offset 0x4e, CSR Addr 0x54027, Direction=Out + // Trained DQ Vref setting for Ch A Rank 1 + uint8_t RxClkDly_Margin_A0; // Byte offset 0x4f, CSR Addr 0x54027, Direction=Out + // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group. + uint8_t VrefDac_Margin_A0; // Byte offset 0x50, CSR Addr 0x54028, Direction=Out + // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group. + uint8_t TxDqDly_Margin_A0; // Byte offset 0x51, CSR Addr 0x54028, Direction=Out + // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group. + uint8_t DeviceVref_Margin_A0; // Byte offset 0x52, CSR Addr 0x54029, Direction=Out + // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group. + uint8_t RxClkDly_Margin_A1; // Byte offset 0x53, CSR Addr 0x54029, Direction=Out + // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group. + uint8_t VrefDac_Margin_A1; // Byte offset 0x54, CSR Addr 0x5402a, Direction=Out + // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group. + uint8_t TxDqDly_Margin_A1; // Byte offset 0x55, CSR Addr 0x5402a, Direction=Out + // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group. + uint8_t DeviceVref_Margin_A1; // Byte offset 0x56, CSR Addr 0x5402b, Direction=Out + // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group. + uint8_t EnabledDQsChB; // Byte offset 0x57, CSR Addr 0x5402b, Direction=In + // Total number of DQ bits enabled in PHY Channel B + uint8_t CsPresentChB; // Byte offset 0x58, CSR Addr 0x5402c, Direction=In + // Indicates presence of DRAM at each chip select for PHY channel B. + // + // 0x0 = No chip selects are populated with DRAM + // 0x1 = CS0 is populated with DRAM + // 0x3 = CS0 and CS1 are populated with DRAM + // + // All other encodings are illegal + // + int8_t CDD_ChB_RR_1_0; // Byte offset 0x59, CSR Addr 0x5402c, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 1 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_RR_0_1; // Byte offset 0x5a, CSR Addr 0x5402d, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 0 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_RW_1_1; // Byte offset 0x5b, CSR Addr 0x5402d, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_RW_1_0; // Byte offset 0x5c, CSR Addr 0x5402e, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_RW_0_1; // Byte offset 0x5d, CSR Addr 0x5402e, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 0 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_RW_0_0; // Byte offset 0x5e, CSR Addr 0x5402f, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs01 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WR_1_1; // Byte offset 0x5f, CSR Addr 0x5402f, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WR_1_0; // Byte offset 0x60, CSR Addr 0x54030, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WR_0_1; // Byte offset 0x61, CSR Addr 0x54030, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WR_0_0; // Byte offset 0x62, CSR Addr 0x54031, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WW_1_0; // Byte offset 0x63, CSR Addr 0x54031, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 1 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WW_0_1; // Byte offset 0x64, CSR Addr 0x54032, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 0 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + uint8_t MR1_B0; // Byte offset 0x65, CSR Addr 0x54032, Direction=In + // Value to be programmed in DRAM Mode Register 1 {Channel B, Rank 0} + uint8_t MR2_B0; // Byte offset 0x66, CSR Addr 0x54033, Direction=In + // Value to be programmed in DRAM Mode Register 2 {Channel B, Rank 0} + uint8_t MR3_B0; // Byte offset 0x67, CSR Addr 0x54033, Direction=In + // Value to be programmed in DRAM Mode Register 3 {Channel B, Rank 0} + uint8_t MR4_B0; // Byte offset 0x68, CSR Addr 0x54034, Direction=In + // Value to be programmed in DRAM Mode Register 4 {Channel B, Rank 0} + uint8_t MR11_B0; // Byte offset 0x69, CSR Addr 0x54034, Direction=In + // Value to be programmed in DRAM Mode Register 11 {Channel B, Rank 0} + uint8_t MR12_B0; // Byte offset 0x6a, CSR Addr 0x54035, Direction=In + // Value to be programmed in DRAM Mode Register 12 {Channel B, Rank 0} + uint8_t MR13_B0; // Byte offset 0x6b, CSR Addr 0x54035, Direction=In + // Value to be programmed in DRAM Mode Register 13 {Channel B, Rank 0} + uint8_t MR14_B0; // Byte offset 0x6c, CSR Addr 0x54036, Direction=In + // Value to be programmed in DRAM Mode Register 14 {Channel B, Rank 0} + uint8_t MR16_B0; // Byte offset 0x6d, CSR Addr 0x54036, Direction=In + // Value to be programmed in DRAM Mode Register 16 {Channel B, Rank 0} + uint8_t MR17_B0; // Byte offset 0x6e, CSR Addr 0x54037, Direction=In + // Value to be programmed in DRAM Mode Register 17 {Channel B, Rank 0} + uint8_t MR22_B0; // Byte offset 0x6f, CSR Addr 0x54037, Direction=In + // Value to be programmed in DRAM Mode Register 22 {Channel B, Rank 0} + uint8_t MR24_B0; // Byte offset 0x70, CSR Addr 0x54038, Direction=In + // Value to be programmed in DRAM Mode Register 24 {Channel B, Rank 0} + uint8_t MR1_B1; // Byte offset 0x71, CSR Addr 0x54038, Direction=In + // Value to be programmed in DRAM Mode Register 1 {Channel B, Rank 1} + uint8_t MR2_B1; // Byte offset 0x72, CSR Addr 0x54039, Direction=In + // Value to be programmed in DRAM Mode Register 2 {Channel B, Rank 1} + uint8_t MR3_B1; // Byte offset 0x73, CSR Addr 0x54039, Direction=In + // Value to be programmed in DRAM Mode Register 3 {Channel B, Rank 1} + uint8_t MR4_B1; // Byte offset 0x74, CSR Addr 0x5403a, Direction=In + // Value to be programmed in DRAM Mode Register 4 {Channel B, Rank 1} + uint8_t MR11_B1; // Byte offset 0x75, CSR Addr 0x5403a, Direction=In + // Value to be programmed in DRAM Mode Register 11 {Channel B, Rank 1} + uint8_t MR12_B1; // Byte offset 0x76, CSR Addr 0x5403b, Direction=In + // Value to be programmed in DRAM Mode Register 12 {Channel B, Rank 1} + uint8_t MR13_B1; // Byte offset 0x77, CSR Addr 0x5403b, Direction=In + // Value to be programmed in DRAM Mode Register 13 {Channel B, Rank 1} + uint8_t MR14_B1; // Byte offset 0x78, CSR Addr 0x5403c, Direction=In + // Value to be programmed in DRAM Mode Register 14 {Channel B, Rank 1} + uint8_t MR16_B1; // Byte offset 0x79, CSR Addr 0x5403c, Direction=In + // Value to be programmed in DRAM Mode Register 16 {Channel B, Rank 1} + uint8_t MR17_B1; // Byte offset 0x7a, CSR Addr 0x5403d, Direction=In + // Value to be programmed in DRAM Mode Register 17 {Channel B, Rank 1} + uint8_t MR22_B1; // Byte offset 0x7b, CSR Addr 0x5403d, Direction=In + // Value to be programmed in DRAM Mode Register 22 {Channel B, Rank 1} + uint8_t MR24_B1; // Byte offset 0x7c, CSR Addr 0x5403e, Direction=In + // Value to be programmed in DRAM Mode Register 24 {Channel B, Rank 1} + uint8_t CATerminatingRankChB; // Byte offset 0x7d, CSR Addr 0x5403e, Direction=In + // Terminating Rank for CA bus on Channel B + // 0x0 = Rank 0 is terminating rank + // 0x1 = Rank 1 is terminating rank + uint8_t Reserved7E; // Byte offset 0x7e, CSR Addr 0x5403f, Direction=N/A + + uint8_t Reserved7F; // Byte offset 0x7f, CSR Addr 0x5403f, Direction=N/A + + uint8_t TrainedVREFDQ_B0; // Byte offset 0x80, CSR Addr 0x54040, Direction=Out + // Trained DQ Vref setting for Ch B Rank 0 + uint8_t TrainedVREFDQ_B1; // Byte offset 0x81, CSR Addr 0x54040, Direction=Out + // Trained DQ Vref setting for Ch B Rank 1 + uint8_t RxClkDly_Margin_B0; // Byte offset 0x82, CSR Addr 0x54041, Direction=Out + // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group. + uint8_t VrefDac_Margin_B0; // Byte offset 0x83, CSR Addr 0x54041, Direction=Out + // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group. + uint8_t TxDqDly_Margin_B0; // Byte offset 0x84, CSR Addr 0x54042, Direction=Out + // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group. + uint8_t DeviceVref_Margin_B0; // Byte offset 0x85, CSR Addr 0x54042, Direction=Out + // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group. + uint8_t RxClkDly_Margin_B1; // Byte offset 0x86, CSR Addr 0x54043, Direction=Out + // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group. + uint8_t VrefDac_Margin_B1; // Byte offset 0x87, CSR Addr 0x54043, Direction=Out + // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group. + uint8_t TxDqDly_Margin_B1; // Byte offset 0x88, CSR Addr 0x54044, Direction=Out + // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group. + uint8_t DeviceVref_Margin_B1; // Byte offset 0x89, CSR Addr 0x54044, Direction=Out + // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group. +} __attribute__ ((packed)) PMU_SMB_LPDDR4_2D_t;
diff --git a/arch/arm/include/asm/arch-c1/nand.h b/arch/arm/include/asm/arch-c1/nand.h new file mode 100644 index 0000000..91484ac --- /dev/null +++ b/arch/arm/include/asm/arch-c1/nand.h
@@ -0,0 +1,135 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __NAND_H__ +#define __NAND_H__ +#include <asm/arch/cpu_config.h> + +#ifndef SD_EMMC_BASE_C +#define SD_EMMC_BASE_C 0xd0074000 +#endif + +#define P_NAND_BASE (SD_EMMC_BASE_C | (1<<11)) +#define P_CLK_CNTL (volatile uint32_t *)(SD_EMMC_BASE_C) +#define P_NAND_CMD (volatile uint32_t *)(P_NAND_BASE + 0x00) +#define P_NAND_CFG (volatile uint32_t *)(P_NAND_BASE + 0x04) +#define P_NAND_DADR (volatile uint32_t *)(P_NAND_BASE + 0x08) +#define P_NAND_IADR (volatile uint32_t *)(P_NAND_BASE + 0x0c) +#define P_NAND_BUF (volatile uint32_t *)(P_NAND_BASE + 0x10) +#define P_NAND_INFO (volatile uint32_t *)(P_NAND_BASE + 0x14) +#define P_NAND_DC (volatile uint32_t *)(P_NAND_BASE + 0x18) +#define P_NAND_ADR (volatile uint32_t *)(P_NAND_BASE + 0x1c) +#define P_NAND_DL (volatile uint32_t *)(P_NAND_BASE + 0x20) +#define P_NAND_DH (volatile uint32_t *)(P_NAND_BASE + 0x24) +#define P_NAND_CADR (volatile uint32_t *)(P_NAND_BASE + 0x28) +#define P_NAND_SADR (volatile uint32_t *)(P_NAND_BASE + 0x2c) + +#define CEF (0xf<<10) +#define CE0 (0xe<<10) +#define CE1 (0xd<<10) +#define CE2 (0xb<<10) +#define CE3 (0x7<<10) + +#define IO4 ((0xe<<10)|(1<<18)) +#define IO5 ((0xd<<10)|(1<<18)) +#define IO6 ((0xb<<10)|(1<<18)) + +#define CLE (0x5<<14) +#define ALE (0x6<<14) +#define DWR (0x4<<14) +#define DRD (0x8<<14) +#define IDLE (0xc<<14) +#define RB (1<<20) + +#define M2N ((0<<17) | (2<<20) | (1<<19)) +#define N2M ((1<<17) | (2<<20) | (1<<19)) +#define STS ((3<<17) | (2<<20)) +#define ADL ((0<<16) | (3<<20)) +#define ADH ((1<<16) | (3<<20)) +#define AIL ((2<<16) | (3<<20)) +#define AIH ((3<<16) | (3<<20)) +#define ASL ((4<<16) | (3<<20)) +#define ASH ((5<<16) | (3<<20)) +#define SEED ((8<<16) | (3<<20)) + +// NAND Flash Manufacturer ID Codes +#define NAND_MFR_TOSHIBA 0x98 +#define NAND_MFR_SAMSUNG 0xec +#define NAND_MFR_FUJITSU 0x04 +#define NAND_MFR_NATIONAL 0x8f +#define NAND_MFR_RENESAS 0x07 +#define NAND_MFR_STMICRO 0x20 +#define NAND_MFR_HYNIX 0xad +#define NAND_MFR_MICRON 0x2c +#define NAND_MFR_AMD 0x01 +#define NAND_MFR_INTEL 0x89 +#define NAND_MFR_SANDISK 0x45 +#define NAND_MFR_USER 0x100 +#define NAND_MFR_EFUSE 0x101 + +typedef struct nand_setup { + union { + uint32_t d32; + struct { + unsigned cmd:22; + unsigned large_page:1; // 22 + unsigned no_rb:1; // 23 from efuse + unsigned a2:1; // 24 + unsigned reserved25:1; // 25 + unsigned page_list:1; // 26 + unsigned sync_mode:2; // 27 from efuse + unsigned size:2; // 29 from efuse + unsigned active:1; // 31 + } b; + } cfg; + uint16_t id; + uint16_t max; // id:0x100 user, max:0 disable. +} nand_setup_t; + +typedef struct _nand_cmd{ + unsigned char type; + unsigned char val; +} nand_cmd_t; + +typedef struct _ext_info{ + uint32_t read_info; //nand_read_info; + uint32_t new_type; //new_nand_type; + uint32_t page_per_blk; //pages_in_block; + uint32_t xlc; //slc=1, mlc=2, tlc=3. + uint32_t rsv1[5]; +} ext_info_t; + +typedef struct _nand_page0 { + nand_setup_t nand_setup; //8 + unsigned char page_list[16]; //16 + nand_cmd_t retry_usr[32]; //64 (32 cmd max I/F) + ext_info_t ext_info; //64 +} nand_page0_t; //384 bytes max. + +//#define NAND_PAGE0_BUF BL1_NAND_BUFF +#define NAND_PAGE0_BUF (0x1800000) +#define NAND_PAGE_LIST (NAND_PAGE0_BUF + sizeof(nand_setup_t)) +#define NAND_RETRY_USER (NAND_PAGE_LIST + 16) +#define NAND_INFO_BUF (NAND_PAGE0_BUF + 512) +#define DEFAULT_ECC_MODE ((1<<23) |(1<<22) | (2<<20) |(1<<19) |(1<<17)|(7<<14)|(1<<13)|(48<<6)|1) +//#define DEFAULT_ECC_MODE ((1<<23) |(1<<22) | (2<<20) |(1<<19) |(1<<17)|(7<<14)|(1<<13)|(48<<6)|1) + +#define ERROR_MOD(mod,num) ((uint32_t)(((mod<<6)|num))) +#define ERROR_NAND_TIMEOUT ERROR_MOD(2,1) // +#define ERROR_NAND_ECC ERROR_MOD(2,2) // +#define ERROR_NAND_MAGIC_WORD ERROR_MOD(2,3) // +#define ERROR_NAND_INIT_READ ERROR_MOD(2,4) // +#define ERROR_NAND_BLANK_PAGE ERROR_MOD(2,5) // +#define ERROR_NAND_UNALIGN_SRC ERROR_MOD(2,6) // + +#define NAND_SECTOR_SIZE (512) +#define NAND_MAX_PAGESIZE (0x4000) //16K +#define SRC_ALIGN_SIZE (NAND_MAX_PAGESIZE) + +#define INFO_BYTE_PER_ECCPAGE (8) +uint32_t nfio_init(void); +uint32_t nf_read(uint32_t boot_device, uint32_t src, uint32_t des, uint32_t size); +#endif /* __NAND_H__ */ +
diff --git a/arch/arm/include/asm/arch-c1/oscring.h b/arch/arm/include/asm/arch-c1/oscring.h new file mode 100644 index 0000000..a1fa6fc --- /dev/null +++ b/arch/arm/include/asm/arch-c1/oscring.h
@@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __OSCRING_H__ +#define __OSCRING_H__ + +#define OSCRING_CTL_REG0 SYSCTRL_OSC_RING_CTRL0 +#define OSCRING_CTL_DATA0 0x55555555 /*0:25*/ +#define OSCRING_CTL_REG1 SYSCTRL_OSC_RING_CTRL1 +#define OSCRING_CTL_DATA1 0x55555555 /*0:7*/ + +#define RING_PWM_VCCK PWMAB_PWM_B +#define RING_PWM_EE PWMAB_PWM_A + +int ring_msr(int index); +#endif
diff --git a/arch/arm/include/asm/arch-c1/p_register.h b/arch/arm/include/asm/arch-c1/p_register.h new file mode 100644 index 0000000..24b136d --- /dev/null +++ b/arch/arm/include/asm/arch-c1/p_register.h
@@ -0,0 +1,4083 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifdef P_REGISTER_H +#else +#define P_REGISTER_H + +// +// Reading file: ./REG_LIST_RTL.h +// +// synopsys translate_off +// synopsys translate_on +// +// Reading file: REG_LIST_AUDIO_RTL.h +// +//======================================================================== +// AUDIO - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe050000 +// ----------------------------------------------- +#define P_EE_AUDIO_CLK_GATE_EN0 ((volatile uint32_t *)0xfe050000) +#define P_EE_AUDIO_CLK_GATE_EN1 ((volatile uint32_t *)0xfe050004) +#define P_EE_AUDIO_MCLK_A_CTRL ((volatile uint32_t *)0xfe050008) +#define P_EE_AUDIO_MCLK_B_CTRL ((volatile uint32_t *)0xfe05000c) +#define P_EE_AUDIO_MCLK_C_CTRL ((volatile uint32_t *)0xfe050010) +#define P_EE_AUDIO_MCLK_D_CTRL ((volatile uint32_t *)0xfe050014) +#define P_EE_AUDIO_MCLK_E_CTRL ((volatile uint32_t *)0xfe050018) +#define P_EE_AUDIO_MCLK_F_CTRL ((volatile uint32_t *)0xfe05001c) +#define P_EE_AUDIO_PAD_CTRL0 ((volatile uint32_t *)0xfe050020) +#define P_EE_AUDIO_PAD_CTRL1 ((volatile uint32_t *)0xfe050024) +#define P_EE_AUDIO_SW_RESET0 ((volatile uint32_t *)0xfe050028) +#define P_EE_AUDIO_SW_RESET1 ((volatile uint32_t *)0xfe05002c) +#define P_EE_AUDIO_CLK81_CTRL ((volatile uint32_t *)0xfe050030) +#define P_EE_AUDIO_CLK81_EN ((volatile uint32_t *)0xfe050034) +#define P_EE_AUDIO_MST_A_SCLK_CTRL0 ((volatile uint32_t *)0xfe050040) +#define P_EE_AUDIO_MST_A_SCLK_CTRL1 ((volatile uint32_t *)0xfe050044) +#define P_EE_AUDIO_MST_B_SCLK_CTRL0 ((volatile uint32_t *)0xfe050048) +#define P_EE_AUDIO_MST_B_SCLK_CTRL1 ((volatile uint32_t *)0xfe05004c) +#define P_EE_AUDIO_MST_C_SCLK_CTRL0 ((volatile uint32_t *)0xfe050050) +#define P_EE_AUDIO_MST_C_SCLK_CTRL1 ((volatile uint32_t *)0xfe050054) +#define P_EE_AUDIO_MST_D_SCLK_CTRL0 ((volatile uint32_t *)0xfe050058) +#define P_EE_AUDIO_MST_D_SCLK_CTRL1 ((volatile uint32_t *)0xfe05005c) +#define P_EE_AUDIO_MST_E_SCLK_CTRL0 ((volatile uint32_t *)0xfe050060) +#define P_EE_AUDIO_MST_E_SCLK_CTRL1 ((volatile uint32_t *)0xfe050064) +#define P_EE_AUDIO_MST_F_SCLK_CTRL0 ((volatile uint32_t *)0xfe050068) +#define P_EE_AUDIO_MST_F_SCLK_CTRL1 ((volatile uint32_t *)0xfe05006c) +#define P_EE_AUDIO_MST_DLY_CTRL0 ((volatile uint32_t *)0xfe050070) +#define P_EE_AUDIO_MST_DLY_CTRL1 ((volatile uint32_t *)0xfe050074) +#define P_EE_AUDIO_CLK_TDMIN_A_CTRL ((volatile uint32_t *)0xfe050080) +#define P_EE_AUDIO_CLK_TDMIN_B_CTRL ((volatile uint32_t *)0xfe050084) +#define P_EE_AUDIO_CLK_TDMIN_C_CTRL ((volatile uint32_t *)0xfe050088) +#define P_EE_AUDIO_CLK_TDMIN_LB_CTRL ((volatile uint32_t *)0xfe05008c) +#define P_EE_AUDIO_CLK_TDMOUT_A_CTRL ((volatile uint32_t *)0xfe050090) +#define P_EE_AUDIO_CLK_TDMOUT_B_CTRL ((volatile uint32_t *)0xfe050094) +#define P_EE_AUDIO_CLK_TDMOUT_C_CTRL ((volatile uint32_t *)0xfe050098) +#define P_EE_AUDIO_CLK_SPDIFIN_CTRL ((volatile uint32_t *)0xfe05009c) +#define P_EE_AUDIO_CLK_SPDIFOUT_CTRL ((volatile uint32_t *)0xfe0500a0) +#define P_EE_AUDIO_CLK_RESAMPLEA_CTRL ((volatile uint32_t *)0xfe0500a4) +#define P_EE_AUDIO_CLK_LOCKER_CTRL ((volatile uint32_t *)0xfe0500a8) +#define P_EE_AUDIO_CLK_PDMIN_CTRL0 ((volatile uint32_t *)0xfe0500ac) +#define P_EE_AUDIO_CLK_PDMIN_CTRL1 ((volatile uint32_t *)0xfe0500b0) +#define P_EE_AUDIO_CLK_SPDIFOUT_B_CTRL ((volatile uint32_t *)0xfe0500b4) +#define P_EE_AUDIO_CLK_RESAMPLEB_CTRL ((volatile uint32_t *)0xfe0500b8) +#define P_EE_AUDIO_CLK_SPDIFIN_LB_CTRL ((volatile uint32_t *)0xfe0500bc) +#define P_EE_AUDIO_CLK_EQDRC_CTRL0 ((volatile uint32_t *)0xfe0500c0) +#define P_EE_AUDIO_VAD_CLK_CTRL ((volatile uint32_t *)0xfe0500c4) +#define P_EE_AUDIO_EARCTX_CMDC_CLK_CTRL ((volatile uint32_t *)0xfe0500c8) +#define P_EE_AUDIO_EARCTX_DMAC_CLK_CTRL ((volatile uint32_t *)0xfe0500cc) +#define P_EE_AUDIO_EARCRX_CMDC_CLK_CTRL ((volatile uint32_t *)0xfe0500d0) +#define P_EE_AUDIO_EARCRX_DMAC_CLK_CTRL ((volatile uint32_t *)0xfe0500d4) +#define P_EE_AUDIO_CLK_LOCKERB_CTRL ((volatile uint32_t *)0xfe0500d8) +#define P_EE_AUDIO_TODDR_A_CTRL0 ((volatile uint32_t *)0xfe050100) +#define P_EE_AUDIO_TODDR_A_CTRL1 ((volatile uint32_t *)0xfe050104) +#define P_EE_AUDIO_TODDR_A_START_ADDR ((volatile uint32_t *)0xfe050108) +#define P_EE_AUDIO_TODDR_A_FINISH_ADDR ((volatile uint32_t *)0xfe05010c) +#define P_EE_AUDIO_TODDR_A_INT_ADDR ((volatile uint32_t *)0xfe050110) +#define P_EE_AUDIO_TODDR_A_STATUS1 ((volatile uint32_t *)0xfe050114) +#define P_EE_AUDIO_TODDR_A_STATUS2 ((volatile uint32_t *)0xfe050118) +#define P_EE_AUDIO_TODDR_A_START_ADDRB ((volatile uint32_t *)0xfe05011c) +#define P_EE_AUDIO_TODDR_A_FINISH_ADDRB ((volatile uint32_t *)0xfe050120) +#define P_EE_AUDIO_TODDR_A_INIT_ADDR ((volatile uint32_t *)0xfe050124) +#define P_EE_AUDIO_TODDR_A_CTRL2 ((volatile uint32_t *)0xfe050128) +#define P_EE_AUDIO_TODDR_B_CTRL0 ((volatile uint32_t *)0xfe050140) +#define P_EE_AUDIO_TODDR_B_CTRL1 ((volatile uint32_t *)0xfe050144) +#define P_EE_AUDIO_TODDR_B_START_ADDR ((volatile uint32_t *)0xfe050148) +#define P_EE_AUDIO_TODDR_B_FINISH_ADDR ((volatile uint32_t *)0xfe05014c) +#define P_EE_AUDIO_TODDR_B_INT_ADDR ((volatile uint32_t *)0xfe050150) +#define P_EE_AUDIO_TODDR_B_STATUS1 ((volatile uint32_t *)0xfe050154) +#define P_EE_AUDIO_TODDR_B_STATUS2 ((volatile uint32_t *)0xfe050158) +#define P_EE_AUDIO_TODDR_B_START_ADDRB ((volatile uint32_t *)0xfe05015c) +#define P_EE_AUDIO_TODDR_B_FINISH_ADDRB ((volatile uint32_t *)0xfe050160) +#define P_EE_AUDIO_TODDR_B_INIT_ADDR ((volatile uint32_t *)0xfe050164) +#define P_EE_AUDIO_TODDR_B_CTRL2 ((volatile uint32_t *)0xfe050168) +#define P_EE_AUDIO_TODDR_C_CTRL0 ((volatile uint32_t *)0xfe050180) +#define P_EE_AUDIO_TODDR_C_CTRL1 ((volatile uint32_t *)0xfe050184) +#define P_EE_AUDIO_TODDR_C_START_ADDR ((volatile uint32_t *)0xfe050188) +#define P_EE_AUDIO_TODDR_C_FINISH_ADDR ((volatile uint32_t *)0xfe05018c) +#define P_EE_AUDIO_TODDR_C_INT_ADDR ((volatile uint32_t *)0xfe050190) +#define P_EE_AUDIO_TODDR_C_STATUS1 ((volatile uint32_t *)0xfe050194) +#define P_EE_AUDIO_TODDR_C_STATUS2 ((volatile uint32_t *)0xfe050198) +#define P_EE_AUDIO_TODDR_C_START_ADDRB ((volatile uint32_t *)0xfe05019c) +#define P_EE_AUDIO_TODDR_C_FINISH_ADDRB ((volatile uint32_t *)0xfe0501a0) +#define P_EE_AUDIO_TODDR_C_INIT_ADDR ((volatile uint32_t *)0xfe0501a4) +#define P_EE_AUDIO_TODDR_C_CTRL2 ((volatile uint32_t *)0xfe0501a8) +#define P_EE_AUDIO_FRDDR_A_CTRL0 ((volatile uint32_t *)0xfe0501c0) +#define P_EE_AUDIO_FRDDR_A_CTRL1 ((volatile uint32_t *)0xfe0501c4) +#define P_EE_AUDIO_FRDDR_A_START_ADDR ((volatile uint32_t *)0xfe0501c8) +#define P_EE_AUDIO_FRDDR_A_FINISH_ADDR ((volatile uint32_t *)0xfe0501cc) +#define P_EE_AUDIO_FRDDR_A_INT_ADDR ((volatile uint32_t *)0xfe0501d0) +#define P_EE_AUDIO_FRDDR_A_STATUS1 ((volatile uint32_t *)0xfe0501d4) +#define P_EE_AUDIO_FRDDR_A_STATUS2 ((volatile uint32_t *)0xfe0501d8) +#define P_EE_AUDIO_FRDDR_A_START_ADDRB ((volatile uint32_t *)0xfe0501dc) +#define P_EE_AUDIO_FRDDR_A_FINISH_ADDRB ((volatile uint32_t *)0xfe0501e0) +#define P_EE_AUDIO_FRDDR_A_INIT_ADDR ((volatile uint32_t *)0xfe0501e4) +#define P_EE_AUDIO_FRDDR_A_CTRL2 ((volatile uint32_t *)0xfe0501e8) +#define P_EE_AUDIO_FRDDR_B_CTRL0 ((volatile uint32_t *)0xfe050200) +#define P_EE_AUDIO_FRDDR_B_CTRL1 ((volatile uint32_t *)0xfe050204) +#define P_EE_AUDIO_FRDDR_B_START_ADDR ((volatile uint32_t *)0xfe050208) +#define P_EE_AUDIO_FRDDR_B_FINISH_ADDR ((volatile uint32_t *)0xfe05020c) +#define P_EE_AUDIO_FRDDR_B_INT_ADDR ((volatile uint32_t *)0xfe050210) +#define P_EE_AUDIO_FRDDR_B_STATUS1 ((volatile uint32_t *)0xfe050214) +#define P_EE_AUDIO_FRDDR_B_STATUS2 ((volatile uint32_t *)0xfe050218) +#define P_EE_AUDIO_FRDDR_B_START_ADDRB ((volatile uint32_t *)0xfe05021c) +#define P_EE_AUDIO_FRDDR_B_FINISH_ADDRB ((volatile uint32_t *)0xfe050220) +#define P_EE_AUDIO_FRDDR_B_INIT_ADDR ((volatile uint32_t *)0xfe050224) +#define P_EE_AUDIO_FRDDR_B_CTRL2 ((volatile uint32_t *)0xfe050228) +#define P_EE_AUDIO_FRDDR_C_CTRL0 ((volatile uint32_t *)0xfe050240) +#define P_EE_AUDIO_FRDDR_C_CTRL1 ((volatile uint32_t *)0xfe050244) +#define P_EE_AUDIO_FRDDR_C_START_ADDR ((volatile uint32_t *)0xfe050248) +#define P_EE_AUDIO_FRDDR_C_FINISH_ADDR ((volatile uint32_t *)0xfe05024c) +#define P_EE_AUDIO_FRDDR_C_INT_ADDR ((volatile uint32_t *)0xfe050250) +#define P_EE_AUDIO_FRDDR_C_STATUS1 ((volatile uint32_t *)0xfe050254) +#define P_EE_AUDIO_FRDDR_C_STATUS2 ((volatile uint32_t *)0xfe050258) +#define P_EE_AUDIO_FRDDR_C_START_ADDRB ((volatile uint32_t *)0xfe05025c) +#define P_EE_AUDIO_FRDDR_C_FINISH_ADDRB ((volatile uint32_t *)0xfe050260) +#define P_EE_AUDIO_FRDDR_C_INIT_ADDR ((volatile uint32_t *)0xfe050264) +#define P_EE_AUDIO_FRDDR_C_CTRL2 ((volatile uint32_t *)0xfe050268) +#define P_EE_AUDIO_ARB_CTRL ((volatile uint32_t *)0xfe050280) +#define P_EE_AUDIO_LB_A_CTRL0 ((volatile uint32_t *)0xfe0502c0) +#define P_EE_AUDIO_LB_A_CTRL1 ((volatile uint32_t *)0xfe0502c4) +#define P_EE_AUDIO_LB_A_CTRL2 ((volatile uint32_t *)0xfe0502c8) +#define P_EE_AUDIO_LB_A_CTRL3 ((volatile uint32_t *)0xfe0502cc) +#define P_EE_AUDIO_LB_A_DAT_CH_ID0 ((volatile uint32_t *)0xfe0502d0) +#define P_EE_AUDIO_LB_A_DAT_CH_ID1 ((volatile uint32_t *)0xfe0502d4) +#define P_EE_AUDIO_LB_A_DAT_CH_ID2 ((volatile uint32_t *)0xfe0502d8) +#define P_EE_AUDIO_LB_A_DAT_CH_ID3 ((volatile uint32_t *)0xfe0502dc) +#define P_EE_AUDIO_LB_A_LB_CH_ID0 ((volatile uint32_t *)0xfe0502e0) +#define P_EE_AUDIO_LB_A_LB_CH_ID1 ((volatile uint32_t *)0xfe0502e4) +#define P_EE_AUDIO_LB_A_LB_CH_ID2 ((volatile uint32_t *)0xfe0502e8) +#define P_EE_AUDIO_LB_A_LB_CH_ID3 ((volatile uint32_t *)0xfe0502ec) +#define P_EE_AUDIO_LB_A_STS ((volatile uint32_t *)0xfe0502f0) +#define P_EE_AUDIO_TDMIN_A_CTRL ((volatile uint32_t *)0xfe050300) +#define P_EE_AUDIO_TDMIN_A_SWAP0 ((volatile uint32_t *)0xfe050304) +#define P_EE_AUDIO_TDMIN_A_MASK0 ((volatile uint32_t *)0xfe050308) +#define P_EE_AUDIO_TDMIN_A_MASK1 ((volatile uint32_t *)0xfe05030c) +#define P_EE_AUDIO_TDMIN_A_MASK2 ((volatile uint32_t *)0xfe050310) +#define P_EE_AUDIO_TDMIN_A_MASK3 ((volatile uint32_t *)0xfe050314) +#define P_EE_AUDIO_TDMIN_A_STAT ((volatile uint32_t *)0xfe050318) +#define P_EE_AUDIO_TDMIN_A_MUTE_VAL ((volatile uint32_t *)0xfe05031c) +#define P_EE_AUDIO_TDMIN_A_MUTE0 ((volatile uint32_t *)0xfe050320) +#define P_EE_AUDIO_TDMIN_A_MUTE1 ((volatile uint32_t *)0xfe050324) +#define P_EE_AUDIO_TDMIN_A_MUTE2 ((volatile uint32_t *)0xfe050328) +#define P_EE_AUDIO_TDMIN_A_MUTE3 ((volatile uint32_t *)0xfe05032c) +#define P_EE_AUDIO_TDMIN_B_CTRL ((volatile uint32_t *)0xfe050340) +#define P_EE_AUDIO_TDMIN_B_SWAP0 ((volatile uint32_t *)0xfe050344) +#define P_EE_AUDIO_TDMIN_B_MASK0 ((volatile uint32_t *)0xfe050348) +#define P_EE_AUDIO_TDMIN_B_MASK1 ((volatile uint32_t *)0xfe05034c) +#define P_EE_AUDIO_TDMIN_B_MASK2 ((volatile uint32_t *)0xfe050350) +#define P_EE_AUDIO_TDMIN_B_MASK3 ((volatile uint32_t *)0xfe050354) +#define P_EE_AUDIO_TDMIN_B_STAT ((volatile uint32_t *)0xfe050358) +#define P_EE_AUDIO_TDMIN_B_MUTE_VAL ((volatile uint32_t *)0xfe05035c) +#define P_EE_AUDIO_TDMIN_B_MUTE0 ((volatile uint32_t *)0xfe050360) +#define P_EE_AUDIO_TDMIN_B_MUTE1 ((volatile uint32_t *)0xfe050364) +#define P_EE_AUDIO_TDMIN_B_MUTE2 ((volatile uint32_t *)0xfe050368) +#define P_EE_AUDIO_TDMIN_B_MUTE3 ((volatile uint32_t *)0xfe05036c) +#define P_EE_AUDIO_TDMIN_C_CTRL ((volatile uint32_t *)0xfe050380) +#define P_EE_AUDIO_TDMIN_C_SWAP0 ((volatile uint32_t *)0xfe050384) +#define P_EE_AUDIO_TDMIN_C_MASK0 ((volatile uint32_t *)0xfe050388) +#define P_EE_AUDIO_TDMIN_C_MASK1 ((volatile uint32_t *)0xfe05038c) +#define P_EE_AUDIO_TDMIN_C_MASK2 ((volatile uint32_t *)0xfe050390) +#define P_EE_AUDIO_TDMIN_C_MASK3 ((volatile uint32_t *)0xfe050394) +#define P_EE_AUDIO_TDMIN_C_STAT ((volatile uint32_t *)0xfe050398) +#define P_EE_AUDIO_TDMIN_C_MUTE_VAL ((volatile uint32_t *)0xfe05039c) +#define P_EE_AUDIO_TDMIN_C_MUTE0 ((volatile uint32_t *)0xfe0503a0) +#define P_EE_AUDIO_TDMIN_C_MUTE1 ((volatile uint32_t *)0xfe0503a4) +#define P_EE_AUDIO_TDMIN_C_MUTE2 ((volatile uint32_t *)0xfe0503a8) +#define P_EE_AUDIO_TDMIN_C_MUTE3 ((volatile uint32_t *)0xfe0503ac) +#define P_EE_AUDIO_TDMIN_LB_CTRL ((volatile uint32_t *)0xfe0503c0) +#define P_EE_AUDIO_TDMIN_LB_SWAP0 ((volatile uint32_t *)0xfe0503c4) +#define P_EE_AUDIO_TDMIN_LB_MASK0 ((volatile uint32_t *)0xfe0503c8) +#define P_EE_AUDIO_TDMIN_LB_MASK1 ((volatile uint32_t *)0xfe0503cc) +#define P_EE_AUDIO_TDMIN_LB_MASK2 ((volatile uint32_t *)0xfe0503d0) +#define P_EE_AUDIO_TDMIN_LB_MASK3 ((volatile uint32_t *)0xfe0503d4) +#define P_EE_AUDIO_TDMIN_LB_STAT ((volatile uint32_t *)0xfe0503d8) +#define P_EE_AUDIO_TDMIN_LB_MUTE_VAL ((volatile uint32_t *)0xfe0503dc) +#define P_EE_AUDIO_TDMIN_LB_MUTE0 ((volatile uint32_t *)0xfe0503e0) +#define P_EE_AUDIO_TDMIN_LB_MUTE1 ((volatile uint32_t *)0xfe0503e4) +#define P_EE_AUDIO_TDMIN_LB_MUTE2 ((volatile uint32_t *)0xfe0503e8) +#define P_EE_AUDIO_TDMIN_LB_MUTE3 ((volatile uint32_t *)0xfe0503ec) +#define P_EE_AUDIO_SPDIFIN_CTRL0 ((volatile uint32_t *)0xfe050400) +#define P_EE_AUDIO_SPDIFIN_CTRL1 ((volatile uint32_t *)0xfe050404) +#define P_EE_AUDIO_SPDIFIN_CTRL2 ((volatile uint32_t *)0xfe050408) +#define P_EE_AUDIO_SPDIFIN_CTRL3 ((volatile uint32_t *)0xfe05040c) +#define P_EE_AUDIO_SPDIFIN_CTRL4 ((volatile uint32_t *)0xfe050410) +#define P_EE_AUDIO_SPDIFIN_CTRL5 ((volatile uint32_t *)0xfe050414) +#define P_EE_AUDIO_SPDIFIN_CTRL6 ((volatile uint32_t *)0xfe050418) +#define P_EE_AUDIO_SPDIFIN_STAT0 ((volatile uint32_t *)0xfe05041c) +#define P_EE_AUDIO_SPDIFIN_STAT1 ((volatile uint32_t *)0xfe050420) +#define P_EE_AUDIO_SPDIFIN_STAT2 ((volatile uint32_t *)0xfe050424) +#define P_EE_AUDIO_SPDIFIN_MUTE_VAL ((volatile uint32_t *)0xfe050428) +#define P_EE_AUDIO_RESAMPLEA_CTRL0 ((volatile uint32_t *)0xfe050440) +#define P_EE_AUDIO_RESAMPLEA_CTRL1 ((volatile uint32_t *)0xfe050444) +#define P_EE_AUDIO_RESAMPLEA_CTRL2 ((volatile uint32_t *)0xfe050448) +#define P_EE_AUDIO_RESAMPLEA_CTRL3 ((volatile uint32_t *)0xfe05044c) +#define P_EE_AUDIO_RESAMPLEA_COEF0 ((volatile uint32_t *)0xfe050450) +#define P_EE_AUDIO_RESAMPLEA_COEF1 ((volatile uint32_t *)0xfe050454) +#define P_EE_AUDIO_RESAMPLEA_COEF2 ((volatile uint32_t *)0xfe050458) +#define P_EE_AUDIO_RESAMPLEA_COEF3 ((volatile uint32_t *)0xfe05045c) +#define P_EE_AUDIO_RESAMPLEA_COEF4 ((volatile uint32_t *)0xfe050460) +#define P_EE_AUDIO_RESAMPLEA_STATUS1 ((volatile uint32_t *)0xfe050464) +#define P_EE_AUDIO_SPDIFOUT_STAT ((volatile uint32_t *)0xfe050480) +#define P_EE_AUDIO_SPDIFOUT_GAIN0 ((volatile uint32_t *)0xfe050484) +#define P_EE_AUDIO_SPDIFOUT_GAIN1 ((volatile uint32_t *)0xfe050488) +#define P_EE_AUDIO_SPDIFOUT_CTRL0 ((volatile uint32_t *)0xfe05048c) +#define P_EE_AUDIO_SPDIFOUT_CTRL1 ((volatile uint32_t *)0xfe050490) +#define P_EE_AUDIO_SPDIFOUT_PREAMB ((volatile uint32_t *)0xfe050494) +#define P_EE_AUDIO_SPDIFOUT_SWAP ((volatile uint32_t *)0xfe050498) +#define P_EE_AUDIO_SPDIFOUT_CHSTS0 ((volatile uint32_t *)0xfe05049c) +#define P_EE_AUDIO_SPDIFOUT_CHSTS1 ((volatile uint32_t *)0xfe0504a0) +#define P_EE_AUDIO_SPDIFOUT_CHSTS2 ((volatile uint32_t *)0xfe0504a4) +#define P_EE_AUDIO_SPDIFOUT_CHSTS3 ((volatile uint32_t *)0xfe0504a8) +#define P_EE_AUDIO_SPDIFOUT_CHSTS4 ((volatile uint32_t *)0xfe0504ac) +#define P_EE_AUDIO_SPDIFOUT_CHSTS5 ((volatile uint32_t *)0xfe0504b0) +#define P_EE_AUDIO_SPDIFOUT_CHSTS6 ((volatile uint32_t *)0xfe0504b4) +#define P_EE_AUDIO_SPDIFOUT_CHSTS7 ((volatile uint32_t *)0xfe0504b8) +#define P_EE_AUDIO_SPDIFOUT_CHSTS8 ((volatile uint32_t *)0xfe0504bc) +#define P_EE_AUDIO_SPDIFOUT_CHSTS9 ((volatile uint32_t *)0xfe0504c0) +#define P_EE_AUDIO_SPDIFOUT_CHSTSA ((volatile uint32_t *)0xfe0504c4) +#define P_EE_AUDIO_SPDIFOUT_CHSTSB ((volatile uint32_t *)0xfe0504c8) +#define P_EE_AUDIO_SPDIFOUT_MUTE_VAL ((volatile uint32_t *)0xfe0504cc) +#define P_EE_AUDIO_TDMOUT_A_CTRL0 ((volatile uint32_t *)0xfe050500) +#define P_EE_AUDIO_TDMOUT_A_CTRL1 ((volatile uint32_t *)0xfe050504) +#define P_EE_AUDIO_TDMOUT_A_SWAP0 ((volatile uint32_t *)0xfe050508) +#define P_EE_AUDIO_TDMOUT_A_MASK0 ((volatile uint32_t *)0xfe05050c) +#define P_EE_AUDIO_TDMOUT_A_MASK1 ((volatile uint32_t *)0xfe050510) +#define P_EE_AUDIO_TDMOUT_A_MASK2 ((volatile uint32_t *)0xfe050514) +#define P_EE_AUDIO_TDMOUT_A_MASK3 ((volatile uint32_t *)0xfe050518) +#define P_EE_AUDIO_TDMOUT_A_STAT ((volatile uint32_t *)0xfe05051c) +#define P_EE_AUDIO_TDMOUT_A_GAIN0 ((volatile uint32_t *)0xfe050520) +#define P_EE_AUDIO_TDMOUT_A_GAIN1 ((volatile uint32_t *)0xfe050524) +#define P_EE_AUDIO_TDMOUT_A_MUTE_VAL ((volatile uint32_t *)0xfe050528) +#define P_EE_AUDIO_TDMOUT_A_MUTE0 ((volatile uint32_t *)0xfe05052c) +#define P_EE_AUDIO_TDMOUT_A_MUTE1 ((volatile uint32_t *)0xfe050530) +#define P_EE_AUDIO_TDMOUT_A_MUTE2 ((volatile uint32_t *)0xfe050534) +#define P_EE_AUDIO_TDMOUT_A_MUTE3 ((volatile uint32_t *)0xfe050538) +#define P_EE_AUDIO_TDMOUT_A_MASK_VAL ((volatile uint32_t *)0xfe05053c) +#define P_EE_AUDIO_TDMOUT_B_CTRL0 ((volatile uint32_t *)0xfe050540) +#define P_EE_AUDIO_TDMOUT_B_CTRL1 ((volatile uint32_t *)0xfe050544) +#define P_EE_AUDIO_TDMOUT_B_SWAP0 ((volatile uint32_t *)0xfe050548) +#define P_EE_AUDIO_TDMOUT_B_MASK0 ((volatile uint32_t *)0xfe05054c) +#define P_EE_AUDIO_TDMOUT_B_MASK1 ((volatile uint32_t *)0xfe050550) +#define P_EE_AUDIO_TDMOUT_B_MASK2 ((volatile uint32_t *)0xfe050554) +#define P_EE_AUDIO_TDMOUT_B_MASK3 ((volatile uint32_t *)0xfe050558) +#define P_EE_AUDIO_TDMOUT_B_STAT ((volatile uint32_t *)0xfe05055c) +#define P_EE_AUDIO_TDMOUT_B_GAIN0 ((volatile uint32_t *)0xfe050560) +#define P_EE_AUDIO_TDMOUT_B_GAIN1 ((volatile uint32_t *)0xfe050564) +#define P_EE_AUDIO_TDMOUT_B_MUTE_VAL ((volatile uint32_t *)0xfe050568) +#define P_EE_AUDIO_TDMOUT_B_MUTE0 ((volatile uint32_t *)0xfe05056c) +#define P_EE_AUDIO_TDMOUT_B_MUTE1 ((volatile uint32_t *)0xfe050570) +#define P_EE_AUDIO_TDMOUT_B_MUTE2 ((volatile uint32_t *)0xfe050574) +#define P_EE_AUDIO_TDMOUT_B_MUTE3 ((volatile uint32_t *)0xfe050578) +#define P_EE_AUDIO_TDMOUT_B_MASK_VAL ((volatile uint32_t *)0xfe05057c) +#define P_EE_AUDIO_TDMOUT_C_CTRL0 ((volatile uint32_t *)0xfe050580) +#define P_EE_AUDIO_TDMOUT_C_CTRL1 ((volatile uint32_t *)0xfe050584) +#define P_EE_AUDIO_TDMOUT_C_SWAP0 ((volatile uint32_t *)0xfe050588) +#define P_EE_AUDIO_TDMOUT_C_MASK0 ((volatile uint32_t *)0xfe05058c) +#define P_EE_AUDIO_TDMOUT_C_MASK1 ((volatile uint32_t *)0xfe050590) +#define P_EE_AUDIO_TDMOUT_C_MASK2 ((volatile uint32_t *)0xfe050594) +#define P_EE_AUDIO_TDMOUT_C_MASK3 ((volatile uint32_t *)0xfe050598) +#define P_EE_AUDIO_TDMOUT_C_STAT ((volatile uint32_t *)0xfe05059c) +#define P_EE_AUDIO_TDMOUT_C_GAIN0 ((volatile uint32_t *)0xfe0505a0) +#define P_EE_AUDIO_TDMOUT_C_GAIN1 ((volatile uint32_t *)0xfe0505a4) +#define P_EE_AUDIO_TDMOUT_C_MUTE_VAL ((volatile uint32_t *)0xfe0505a8) +#define P_EE_AUDIO_TDMOUT_C_MUTE0 ((volatile uint32_t *)0xfe0505ac) +#define P_EE_AUDIO_TDMOUT_C_MUTE1 ((volatile uint32_t *)0xfe0505b0) +#define P_EE_AUDIO_TDMOUT_C_MUTE2 ((volatile uint32_t *)0xfe0505b4) +#define P_EE_AUDIO_TDMOUT_C_MUTE3 ((volatile uint32_t *)0xfe0505b8) +#define P_EE_AUDIO_TDMOUT_C_MASK_VAL ((volatile uint32_t *)0xfe0505bc) +//`define EE_AUDIO_POW_DET_CTRL0 10'h180 +//`define EE_AUDIO_POW_DET_CTRL1 10'h181 +//`define EE_AUDIO_POW_DET_TH_HI 10'h182 +//`define EE_AUDIO_POW_DET_TH_LO 10'h183 +//`define EE_AUDIO_POW_DET_VALUE 10'h184 +#define P_EE_AUDIO_SECURITY_CTRL0 ((volatile uint32_t *)0xfe050640) +#define P_EE_AUDIO_SECURITY_CTRL1 ((volatile uint32_t *)0xfe050644) +#define P_EE_AUDIO_SPDIFOUT_B_STAT ((volatile uint32_t *)0xfe050680) +#define P_EE_AUDIO_SPDIFOUT_B_GAIN0 ((volatile uint32_t *)0xfe050684) +#define P_EE_AUDIO_SPDIFOUT_B_GAIN1 ((volatile uint32_t *)0xfe050688) +#define P_EE_AUDIO_SPDIFOUT_B_CTRL0 ((volatile uint32_t *)0xfe05068c) +#define P_EE_AUDIO_SPDIFOUT_B_CTRL1 ((volatile uint32_t *)0xfe050690) +#define P_EE_AUDIO_SPDIFOUT_B_PREAMB ((volatile uint32_t *)0xfe050694) +#define P_EE_AUDIO_SPDIFOUT_B_SWAP ((volatile uint32_t *)0xfe050698) +#define P_EE_AUDIO_SPDIFOUT_B_CHSTS0 ((volatile uint32_t *)0xfe05069c) +#define P_EE_AUDIO_SPDIFOUT_B_CHSTS1 ((volatile uint32_t *)0xfe0506a0) +#define P_EE_AUDIO_SPDIFOUT_B_CHSTS2 ((volatile uint32_t *)0xfe0506a4) +#define P_EE_AUDIO_SPDIFOUT_B_CHSTS3 ((volatile uint32_t *)0xfe0506a8) +#define P_EE_AUDIO_SPDIFOUT_B_CHSTS4 ((volatile uint32_t *)0xfe0506ac) +#define P_EE_AUDIO_SPDIFOUT_B_CHSTS5 ((volatile uint32_t *)0xfe0506b0) +#define P_EE_AUDIO_SPDIFOUT_B_CHSTS6 ((volatile uint32_t *)0xfe0506b4) +#define P_EE_AUDIO_SPDIFOUT_B_CHSTS7 ((volatile uint32_t *)0xfe0506b8) +#define P_EE_AUDIO_SPDIFOUT_B_CHSTS8 ((volatile uint32_t *)0xfe0506bc) +#define P_EE_AUDIO_SPDIFOUT_B_CHSTS9 ((volatile uint32_t *)0xfe0506c0) +#define P_EE_AUDIO_SPDIFOUT_B_CHSTSA ((volatile uint32_t *)0xfe0506c4) +#define P_EE_AUDIO_SPDIFOUT_B_CHSTSB ((volatile uint32_t *)0xfe0506c8) +#define P_EE_AUDIO_SPDIFOUT_B_MUTE_VAL ((volatile uint32_t *)0xfe0506cc) +#define P_EE_AUDIO_TORAM_CTRL0 ((volatile uint32_t *)0xfe050700) +#define P_EE_AUDIO_TORAM_CTRL1 ((volatile uint32_t *)0xfe050704) +#define P_EE_AUDIO_TORAM_START_ADDR ((volatile uint32_t *)0xfe050708) +#define P_EE_AUDIO_TORAM_FINISH_ADDR ((volatile uint32_t *)0xfe05070c) +#define P_EE_AUDIO_TORAM_INT_ADDR ((volatile uint32_t *)0xfe050710) +#define P_EE_AUDIO_TORAM_STATUS1 ((volatile uint32_t *)0xfe050714) +#define P_EE_AUDIO_TORAM_STATUS2 ((volatile uint32_t *)0xfe050718) +#define P_EE_AUDIO_TORAM_INIT_ADDR ((volatile uint32_t *)0xfe05071c) +#define P_EE_AUDIO_TOACODEC_CTRL0 ((volatile uint32_t *)0xfe050740) +#define P_EE_AUDIO_TOHDMITX_CTRL0 ((volatile uint32_t *)0xfe050744) +#define P_EE_AUDIO_TOVAD_CTRL0 ((volatile uint32_t *)0xfe050748) +#define P_EE_AUDIO_FRATV_CTRL0 ((volatile uint32_t *)0xfe05074c) +#define P_EE_AUDIO_RESAMPLEB_CTRL0 ((volatile uint32_t *)0xfe050780) +#define P_EE_AUDIO_RESAMPLEB_CTRL1 ((volatile uint32_t *)0xfe050784) +#define P_EE_AUDIO_RESAMPLEB_CTRL2 ((volatile uint32_t *)0xfe050788) +#define P_EE_AUDIO_RESAMPLEB_CTRL3 ((volatile uint32_t *)0xfe05078c) +#define P_EE_AUDIO_RESAMPLEB_COEF0 ((volatile uint32_t *)0xfe050790) +#define P_EE_AUDIO_RESAMPLEB_COEF1 ((volatile uint32_t *)0xfe050794) +#define P_EE_AUDIO_RESAMPLEB_COEF2 ((volatile uint32_t *)0xfe050798) +#define P_EE_AUDIO_RESAMPLEB_COEF3 ((volatile uint32_t *)0xfe05079c) +#define P_EE_AUDIO_RESAMPLEB_COEF4 ((volatile uint32_t *)0xfe0507a0) +#define P_EE_AUDIO_RESAMPLEB_STATUS1 ((volatile uint32_t *)0xfe0507a4) +#define P_EE_AUDIO_SPDIFIN_LB_CTRL0 ((volatile uint32_t *)0xfe0507c0) +#define P_EE_AUDIO_SPDIFIN_LB_CTRL1 ((volatile uint32_t *)0xfe0507c4) +#define P_EE_AUDIO_SPDIFIN_LB_CTRL6 ((volatile uint32_t *)0xfe0507d8) +#define P_EE_AUDIO_SPDIFIN_LB_STAT0 ((volatile uint32_t *)0xfe0507dc) +#define P_EE_AUDIO_SPDIFIN_LB_STAT1 ((volatile uint32_t *)0xfe0507e0) +#define P_EE_AUDIO_SPDIFIN_LB_MUTE_VAL ((volatile uint32_t *)0xfe0507e8) +#define P_EE_AUDIO_FRHDMIRX_CTRL0 ((volatile uint32_t *)0xfe050800) +#define P_EE_AUDIO_FRHDMIRX_CTRL1 ((volatile uint32_t *)0xfe050804) +#define P_EE_AUDIO_FRHDMIRX_CTRL2 ((volatile uint32_t *)0xfe050808) +#define P_EE_AUDIO_FRHDMIRX_CTRL3 ((volatile uint32_t *)0xfe05080c) +#define P_EE_AUDIO_FRHDMIRX_CTRL4 ((volatile uint32_t *)0xfe050810) +#define P_EE_AUDIO_FRHDMIRX_CTRL5 ((volatile uint32_t *)0xfe050814) +#define P_EE_AUDIO_FRHDMIRX_STAT0 ((volatile uint32_t *)0xfe050828) +#define P_EE_AUDIO_FRHDMIRX_STAT1 ((volatile uint32_t *)0xfe05082c) +#define P_EE_AUDIO_TODDR_D_CTRL0 ((volatile uint32_t *)0xfe050840) +#define P_EE_AUDIO_TODDR_D_CTRL1 ((volatile uint32_t *)0xfe050844) +#define P_EE_AUDIO_TODDR_D_START_ADDR ((volatile uint32_t *)0xfe050848) +#define P_EE_AUDIO_TODDR_D_FINISH_ADDR ((volatile uint32_t *)0xfe05084c) +#define P_EE_AUDIO_TODDR_D_INT_ADDR ((volatile uint32_t *)0xfe050850) +#define P_EE_AUDIO_TODDR_D_STATUS1 ((volatile uint32_t *)0xfe050854) +#define P_EE_AUDIO_TODDR_D_STATUS2 ((volatile uint32_t *)0xfe050858) +#define P_EE_AUDIO_TODDR_D_START_ADDRB ((volatile uint32_t *)0xfe05085c) +#define P_EE_AUDIO_TODDR_D_FINISH_ADDRB ((volatile uint32_t *)0xfe050860) +#define P_EE_AUDIO_TODDR_D_INIT_ADDR ((volatile uint32_t *)0xfe050864) +#define P_EE_AUDIO_TODDR_D_CTRL2 ((volatile uint32_t *)0xfe050868) +#define P_EE_AUDIO_FRDDR_D_CTRL0 ((volatile uint32_t *)0xfe050880) +#define P_EE_AUDIO_FRDDR_D_CTRL1 ((volatile uint32_t *)0xfe050884) +#define P_EE_AUDIO_FRDDR_D_START_ADDR ((volatile uint32_t *)0xfe050888) +#define P_EE_AUDIO_FRDDR_D_FINISH_ADDR ((volatile uint32_t *)0xfe05088c) +#define P_EE_AUDIO_FRDDR_D_INT_ADDR ((volatile uint32_t *)0xfe050890) +#define P_EE_AUDIO_FRDDR_D_STATUS1 ((volatile uint32_t *)0xfe050894) +#define P_EE_AUDIO_FRDDR_D_STATUS2 ((volatile uint32_t *)0xfe050898) +#define P_EE_AUDIO_FRDDR_D_START_ADDRB ((volatile uint32_t *)0xfe05089c) +#define P_EE_AUDIO_FRDDR_D_FINISH_ADDRB ((volatile uint32_t *)0xfe0508a0) +#define P_EE_AUDIO_FRDDR_D_INIT_ADDR ((volatile uint32_t *)0xfe0508a4) +#define P_EE_AUDIO_FRDDR_D_CTRL2 ((volatile uint32_t *)0xfe0508a8) +#define P_EE_AUDIO_LB_B_CTRL0 ((volatile uint32_t *)0xfe0508c0) +#define P_EE_AUDIO_LB_B_CTRL1 ((volatile uint32_t *)0xfe0508c4) +#define P_EE_AUDIO_LB_B_CTRL2 ((volatile uint32_t *)0xfe0508c8) +#define P_EE_AUDIO_LB_B_CTRL3 ((volatile uint32_t *)0xfe0508cc) +#define P_EE_AUDIO_LB_B_DAT_CH_ID0 ((volatile uint32_t *)0xfe0508d0) +#define P_EE_AUDIO_LB_B_DAT_CH_ID1 ((volatile uint32_t *)0xfe0508d4) +#define P_EE_AUDIO_LB_B_DAT_CH_ID2 ((volatile uint32_t *)0xfe0508d8) +#define P_EE_AUDIO_LB_B_DAT_CH_ID3 ((volatile uint32_t *)0xfe0508dc) +#define P_EE_AUDIO_LB_B_LB_CH_ID0 ((volatile uint32_t *)0xfe0508e0) +#define P_EE_AUDIO_LB_B_LB_CH_ID1 ((volatile uint32_t *)0xfe0508e4) +#define P_EE_AUDIO_LB_B_LB_CH_ID2 ((volatile uint32_t *)0xfe0508e8) +#define P_EE_AUDIO_LB_B_LB_CH_ID3 ((volatile uint32_t *)0xfe0508ec) +#define P_EE_AUDIO_LB_B_STS ((volatile uint32_t *)0xfe0508f0) +#define P_EE_AUDIO_TODDR_E_CTRL0 ((volatile uint32_t *)0xfe050900) +#define P_EE_AUDIO_TODDR_E_CTRL1 ((volatile uint32_t *)0xfe050904) +#define P_EE_AUDIO_TODDR_E_START_ADDR ((volatile uint32_t *)0xfe050908) +#define P_EE_AUDIO_TODDR_E_FINISH_ADDR ((volatile uint32_t *)0xfe05090c) +#define P_EE_AUDIO_TODDR_E_INT_ADDR ((volatile uint32_t *)0xfe050910) +#define P_EE_AUDIO_TODDR_E_STATUS1 ((volatile uint32_t *)0xfe050914) +#define P_EE_AUDIO_TODDR_E_STATUS2 ((volatile uint32_t *)0xfe050918) +#define P_EE_AUDIO_TODDR_E_START_ADDRB ((volatile uint32_t *)0xfe05091c) +#define P_EE_AUDIO_TODDR_E_FINISH_ADDRB ((volatile uint32_t *)0xfe050920) +#define P_EE_AUDIO_TODDR_E_INIT_ADDR ((volatile uint32_t *)0xfe050924) +#define P_EE_AUDIO_TODDR_E_CTRL2 ((volatile uint32_t *)0xfe050928) +#define P_EE_AUDIO_FRDDR_E_CTRL0 ((volatile uint32_t *)0xfe050940) +#define P_EE_AUDIO_FRDDR_E_CTRL1 ((volatile uint32_t *)0xfe050944) +#define P_EE_AUDIO_FRDDR_E_START_ADDR ((volatile uint32_t *)0xfe050948) +#define P_EE_AUDIO_FRDDR_E_FINISH_ADDR ((volatile uint32_t *)0xfe05094c) +#define P_EE_AUDIO_FRDDR_E_INT_ADDR ((volatile uint32_t *)0xfe050950) +#define P_EE_AUDIO_FRDDR_E_STATUS1 ((volatile uint32_t *)0xfe050954) +#define P_EE_AUDIO_FRDDR_E_STATUS2 ((volatile uint32_t *)0xfe050958) +#define P_EE_AUDIO_FRDDR_E_START_ADDRB ((volatile uint32_t *)0xfe05095c) +#define P_EE_AUDIO_FRDDR_E_FINISH_ADDRB ((volatile uint32_t *)0xfe050960) +#define P_EE_AUDIO_FRDDR_E_INIT_ADDR ((volatile uint32_t *)0xfe050964) +#define P_EE_AUDIO_FRDDR_E_CTRL2 ((volatile uint32_t *)0xfe050968) +#define P_EE_AUDIO_TDMIN_A_SWAP1 ((volatile uint32_t *)0xfe050980) +#define P_EE_AUDIO_TDMIN_A_MASK4 ((volatile uint32_t *)0xfe050984) +#define P_EE_AUDIO_TDMIN_A_MASK5 ((volatile uint32_t *)0xfe050988) +#define P_EE_AUDIO_TDMIN_A_MASK6 ((volatile uint32_t *)0xfe05098c) +#define P_EE_AUDIO_TDMIN_A_MASK7 ((volatile uint32_t *)0xfe050990) +#define P_EE_AUDIO_TDMIN_A_MUTE4 ((volatile uint32_t *)0xfe050994) +#define P_EE_AUDIO_TDMIN_A_MUTE5 ((volatile uint32_t *)0xfe050998) +#define P_EE_AUDIO_TDMIN_A_MUTE6 ((volatile uint32_t *)0xfe05099c) +#define P_EE_AUDIO_TDMIN_A_MUTE7 ((volatile uint32_t *)0xfe0509a0) +#define P_EE_AUDIO_TDMIN_B_SWAP1 ((volatile uint32_t *)0xfe0509c0) +#define P_EE_AUDIO_TDMIN_B_MASK4 ((volatile uint32_t *)0xfe0509c4) +#define P_EE_AUDIO_TDMIN_B_MASK5 ((volatile uint32_t *)0xfe0509c8) +#define P_EE_AUDIO_TDMIN_B_MASK6 ((volatile uint32_t *)0xfe0509cc) +#define P_EE_AUDIO_TDMIN_B_MASK7 ((volatile uint32_t *)0xfe0509d0) +#define P_EE_AUDIO_TDMIN_B_MUTE4 ((volatile uint32_t *)0xfe0509d4) +#define P_EE_AUDIO_TDMIN_B_MUTE5 ((volatile uint32_t *)0xfe0509d8) +#define P_EE_AUDIO_TDMIN_B_MUTE6 ((volatile uint32_t *)0xfe0509dc) +#define P_EE_AUDIO_TDMIN_B_MUTE7 ((volatile uint32_t *)0xfe0509e0) +#define P_EE_AUDIO_TDMIN_C_SWAP1 ((volatile uint32_t *)0xfe050a00) +#define P_EE_AUDIO_TDMIN_C_MASK4 ((volatile uint32_t *)0xfe050a04) +#define P_EE_AUDIO_TDMIN_C_MASK5 ((volatile uint32_t *)0xfe050a08) +#define P_EE_AUDIO_TDMIN_C_MASK6 ((volatile uint32_t *)0xfe050a0c) +#define P_EE_AUDIO_TDMIN_C_MASK7 ((volatile uint32_t *)0xfe050a10) +#define P_EE_AUDIO_TDMIN_C_MUTE4 ((volatile uint32_t *)0xfe050a14) +#define P_EE_AUDIO_TDMIN_C_MUTE5 ((volatile uint32_t *)0xfe050a18) +#define P_EE_AUDIO_TDMIN_C_MUTE6 ((volatile uint32_t *)0xfe050a1c) +#define P_EE_AUDIO_TDMIN_C_MUTE7 ((volatile uint32_t *)0xfe050a20) +#define P_EE_AUDIO_TDMIN_LB_SWAP1 ((volatile uint32_t *)0xfe050a40) +#define P_EE_AUDIO_TDMIN_LB_MASK4 ((volatile uint32_t *)0xfe050a44) +#define P_EE_AUDIO_TDMIN_LB_MASK5 ((volatile uint32_t *)0xfe050a48) +#define P_EE_AUDIO_TDMIN_LB_MASK6 ((volatile uint32_t *)0xfe050a4c) +#define P_EE_AUDIO_TDMIN_LB_MASK7 ((volatile uint32_t *)0xfe050a50) +#define P_EE_AUDIO_TDMIN_LB_MUTE4 ((volatile uint32_t *)0xfe050a54) +#define P_EE_AUDIO_TDMIN_LB_MUTE5 ((volatile uint32_t *)0xfe050a58) +#define P_EE_AUDIO_TDMIN_LB_MUTE6 ((volatile uint32_t *)0xfe050a5c) +#define P_EE_AUDIO_TDMIN_LB_MUTE7 ((volatile uint32_t *)0xfe050a60) +#define P_EE_AUDIO_TDMOUT_A_CTRL2 ((volatile uint32_t *)0xfe050a80) +#define P_EE_AUDIO_TDMOUT_A_SWAP1 ((volatile uint32_t *)0xfe050a84) +#define P_EE_AUDIO_TDMOUT_A_GAIN2 ((volatile uint32_t *)0xfe050a88) +#define P_EE_AUDIO_TDMOUT_A_GAIN3 ((volatile uint32_t *)0xfe050a8c) +#define P_EE_AUDIO_TDMOUT_A_MASK4 ((volatile uint32_t *)0xfe050a90) +#define P_EE_AUDIO_TDMOUT_A_MASK5 ((volatile uint32_t *)0xfe050a94) +#define P_EE_AUDIO_TDMOUT_A_MASK6 ((volatile uint32_t *)0xfe050a98) +#define P_EE_AUDIO_TDMOUT_A_MASK7 ((volatile uint32_t *)0xfe050a9c) +#define P_EE_AUDIO_TDMOUT_A_MUTE4 ((volatile uint32_t *)0xfe050aa0) +#define P_EE_AUDIO_TDMOUT_A_MUTE5 ((volatile uint32_t *)0xfe050aa4) +#define P_EE_AUDIO_TDMOUT_A_MUTE6 ((volatile uint32_t *)0xfe050aa8) +#define P_EE_AUDIO_TDMOUT_A_MUTE7 ((volatile uint32_t *)0xfe050aac) +#define P_EE_AUDIO_TDMOUT_B_CTRL2 ((volatile uint32_t *)0xfe050ac0) +#define P_EE_AUDIO_TDMOUT_B_SWAP1 ((volatile uint32_t *)0xfe050ac4) +#define P_EE_AUDIO_TDMOUT_B_GAIN2 ((volatile uint32_t *)0xfe050ac8) +#define P_EE_AUDIO_TDMOUT_B_GAIN3 ((volatile uint32_t *)0xfe050acc) +#define P_EE_AUDIO_TDMOUT_B_MASK4 ((volatile uint32_t *)0xfe050ad0) +#define P_EE_AUDIO_TDMOUT_B_MASK5 ((volatile uint32_t *)0xfe050ad4) +#define P_EE_AUDIO_TDMOUT_B_MASK6 ((volatile uint32_t *)0xfe050ad8) +#define P_EE_AUDIO_TDMOUT_B_MASK7 ((volatile uint32_t *)0xfe050adc) +#define P_EE_AUDIO_TDMOUT_B_MUTE4 ((volatile uint32_t *)0xfe050ae0) +#define P_EE_AUDIO_TDMOUT_B_MUTE5 ((volatile uint32_t *)0xfe050ae4) +#define P_EE_AUDIO_TDMOUT_B_MUTE6 ((volatile uint32_t *)0xfe050ae8) +#define P_EE_AUDIO_TDMOUT_B_MUTE7 ((volatile uint32_t *)0xfe050aec) +#define P_EE_AUDIO_TDMOUT_C_CTRL2 ((volatile uint32_t *)0xfe050b00) +#define P_EE_AUDIO_TDMOUT_C_SWAP1 ((volatile uint32_t *)0xfe050b04) +#define P_EE_AUDIO_TDMOUT_C_GAIN2 ((volatile uint32_t *)0xfe050b08) +#define P_EE_AUDIO_TDMOUT_C_GAIN3 ((volatile uint32_t *)0xfe050b0c) +#define P_EE_AUDIO_TDMOUT_C_MASK4 ((volatile uint32_t *)0xfe050b10) +#define P_EE_AUDIO_TDMOUT_C_MASK5 ((volatile uint32_t *)0xfe050b14) +#define P_EE_AUDIO_TDMOUT_C_MASK6 ((volatile uint32_t *)0xfe050b18) +#define P_EE_AUDIO_TDMOUT_C_MASK7 ((volatile uint32_t *)0xfe050b1c) +#define P_EE_AUDIO_TDMOUT_C_MUTE4 ((volatile uint32_t *)0xfe050b20) +#define P_EE_AUDIO_TDMOUT_C_MUTE5 ((volatile uint32_t *)0xfe050b24) +#define P_EE_AUDIO_TDMOUT_C_MUTE6 ((volatile uint32_t *)0xfe050b28) +#define P_EE_AUDIO_TDMOUT_C_MUTE7 ((volatile uint32_t *)0xfe050b2c) +//======================================================================== +// PDM - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe051000 +// ----------------------------------------------- +#define P_PDM_CTRL ((volatile uint32_t *)0xfe051000) +//bit 31: PDM enable. +//bit 30: invert the PDM_DCLK. +//bit 29: output mode: 1: 24bits. 0: 32 bits. +//bit 28: bypass mode. 1: bypass all filter. directly output the PDM input to DDR. 0: normal mode. +//bit 27~9: not used. +//bit 16:. PDM Asynchronous FIFO soft reset. write 1 to soft reset AFIFO. +//bit 15:8 PDM channel reset. 0: to reset each PDM channel. 1: normal mode. +//bit 7:0. PDM channel enable. each bit for one channel. +#define P_PDM_HCIC_CTRL1 ((volatile uint32_t *)0xfe051004) +//bit 31 hcic filter enable. 1 use sinc filter. 0 bypass input to output. +//bit 29:24. hcic final gain shift parameter. +//bit 23:16 hcic final gain multiplier. +//bit 8:4 hcic down sample rate. +//bit 3:0 hcic stage number. must be between 3 to 9. +#define P_PDM_HCIC_CTRL2 ((volatile uint32_t *)0xfe051008) +//Not used. +#define P_PDM_F1_CTRL ((volatile uint32_t *)0xfe05100c) +//bit 31 . filter 1 enable. +//bit 16:15. f1 round mode. 2'b00 : sign bit at bit 49. 28bits output [49:22] round at bit 21. 32bits output [49:18]. 24bits output [49:26] +// 2'b01 : sign bit at bit 50. 28bits output [50:23] round at bit 22. 32bits output [49:18]. 24bits output [49:26] +// 2'b10 : sign bit at bit 51. 28bits output [51:24] round at bit 23 32bits output [49:18]. 24bits output [49:26]. +//bit 15:12. filter 1 down sample rate. +//bit 8:0. filter 1 stage number. +#define P_PDM_F2_CTRL ((volatile uint32_t *)0xfe051010) +//bit 31 . filter 2 enable. +//bit 16:15. f2 round mode. 2'b00 : round at bit 21. 2'b01 : round at bit 22. 2'b10 : round at bit 23. +//bit 15:12. filter 2 down sample rate. +//bit 8:0. filter 2 stage number. +#define P_PDM_F3_CTRL ((volatile uint32_t *)0xfe051014) +//bit 31 . filter 3 enable. +//bit 16:15. f3 round mode. 2'b00 : round at bit 21. 2'b01 : round at bit 22. 2'b10 : round at bit 23. +//bit 15:12. filter 3 down sample rate. +//bit 8:0. filter 3 stage number. +#define P_PDM_HPF_CTRL ((volatile uint32_t *)0xfe051018) +//bit 31 High pass filter enable. +//bit 20:16 high pass filter shift steps. 6~19 steps. +//bit 15:0 high pass filter output factor. +#define P_PDM_CHAN_CTRL ((volatile uint32_t *)0xfe05101c) +//bit 31:24. chan3 data sample pointer vs edge of the PDM_DCLK. +//bit 23:16 chan2 data sample pointer vs edge of the PDM_DCLK. +//bit 15:8. chan1 data sample pointer vs edge of the PDM_DCLK. +//bit 7:0 chan0 data sample pointer vs edge of the PDM_DCLK. +#define P_PDM_CHAN_CTRL1 ((volatile uint32_t *)0xfe051020) +//bit 31:24. chan7 data sample pointer vs edge of the PDM_DCLK. +//bit 23:16 chan6 data sample pointer vs edge of the PDM_DCLK. +//bit 15:8. chan5 data sample pointer vs edge of the PDM_DCLK. +//bit 7:0 chan4 data sample pointer vs edge of the PDM_DCLK. +#define P_PDM_COEFF_ADDR ((volatile uint32_t *)0xfe051024) +// address of the write/read of coeff data. +#define P_PDM_COEFF_DATA ((volatile uint32_t *)0xfe051028) +//write/read data to coeff memory. +#define P_PDM_CLKG_CTRL ((volatile uint32_t *)0xfe05102c) +// auto clock gating control. 1: disable the clock gating function. the clock will awlays enabled. 0 : use RTL auto clock gating. +//31:7 not used. +//bit 6 filt_ctrl module auto clock gating control. +//bit 5 sinc fifo module auto clock gating control. +//bit 4 filter module auto clock gating control. +//bit 3 apb module auto clock gating control. +//bit 2 coeff memory module auto clock gating control. +//bit 1 each channel module auto clock gating control. +//bit 0 cts_pdm_clk auto clock gating control. +#define P_PDM_STS ((volatile uint32_t *)0xfe051030) +//bit 1 HPF filter output overflow. means the PCLK is too slow. +//bit 0 HCIC filter output overflow. means the CTS_PDM_CLK is too slow. can't finished the filter function. +#define P_PDM_MUTE_VALUE ((volatile uint32_t *)0xfe051034) +#define P_PDM_MASK_NUM ((volatile uint32_t *)0xfe051038) +//======================================================================== +// EQ DRC - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe052000 +// ----------------------------------------------- +#define P_AED_COEF_RAM_CNTL ((volatile uint32_t *)0xfe052000) +#define P_AED_COEF_RAM_DATA ((volatile uint32_t *)0xfe052004) +#define P_AED_EQ_EN ((volatile uint32_t *)0xfe052008) +#define P_AED_EQ_TAP_CNTL ((volatile uint32_t *)0xfe05200c) +#define P_AED_EQ_VOLUME ((volatile uint32_t *)0xfe052010) +#define P_AED_EQ_VOLUME_SLEW_CNT ((volatile uint32_t *)0xfe052014) +#define P_AED_MUTE ((volatile uint32_t *)0xfe052018) +#define P_AED_DRC_CNTL ((volatile uint32_t *)0xfe05201c) +#define P_AED_DRC_RMS_COEF0 ((volatile uint32_t *)0xfe052020) +#define P_AED_DRC_RMS_COEF1 ((volatile uint32_t *)0xfe052024) +#define P_AED_DRC_THD0 ((volatile uint32_t *)0xfe052028) +#define P_AED_DRC_THD1 ((volatile uint32_t *)0xfe05202c) +#define P_AED_DRC_THD2 ((volatile uint32_t *)0xfe052030) +#define P_AED_DRC_THD3 ((volatile uint32_t *)0xfe052034) +#define P_AED_DRC_THD4 ((volatile uint32_t *)0xfe052038) +#define P_AED_DRC_K0 ((volatile uint32_t *)0xfe05203c) +#define P_AED_DRC_K1 ((volatile uint32_t *)0xfe052040) +#define P_AED_DRC_K2 ((volatile uint32_t *)0xfe052044) +#define P_AED_DRC_K3 ((volatile uint32_t *)0xfe052048) +#define P_AED_DRC_K4 ((volatile uint32_t *)0xfe05204c) +#define P_AED_DRC_K5 ((volatile uint32_t *)0xfe052050) +#define P_AED_DRC_THD_OUT0 ((volatile uint32_t *)0xfe052054) +#define P_AED_DRC_THD_OUT1 ((volatile uint32_t *)0xfe052058) +#define P_AED_DRC_THD_OUT2 ((volatile uint32_t *)0xfe05205c) +#define P_AED_DRC_THD_OUT3 ((volatile uint32_t *)0xfe052060) +#define P_AED_DRC_OFFSET ((volatile uint32_t *)0xfe052064) +#define P_AED_DRC_RELEASE_COEF00 ((volatile uint32_t *)0xfe052068) +#define P_AED_DRC_RELEASE_COEF01 ((volatile uint32_t *)0xfe05206c) +#define P_AED_DRC_RELEASE_COEF10 ((volatile uint32_t *)0xfe052070) +#define P_AED_DRC_RELEASE_COEF11 ((volatile uint32_t *)0xfe052074) +#define P_AED_DRC_RELEASE_COEF20 ((volatile uint32_t *)0xfe052078) +#define P_AED_DRC_RELEASE_COEF21 ((volatile uint32_t *)0xfe05207c) +#define P_AED_DRC_RELEASE_COEF30 ((volatile uint32_t *)0xfe052080) +#define P_AED_DRC_RELEASE_COEF31 ((volatile uint32_t *)0xfe052084) +#define P_AED_DRC_RELEASE_COEF40 ((volatile uint32_t *)0xfe052088) +#define P_AED_DRC_RELEASE_COEF41 ((volatile uint32_t *)0xfe05208c) +#define P_AED_DRC_RELEASE_COEF50 ((volatile uint32_t *)0xfe052090) +#define P_AED_DRC_RELEASE_COEF51 ((volatile uint32_t *)0xfe052094) +#define P_AED_DRC_ATTACK_COEF00 ((volatile uint32_t *)0xfe052098) +#define P_AED_DRC_ATTACK_COEF01 ((volatile uint32_t *)0xfe05209c) +#define P_AED_DRC_ATTACK_COEF10 ((volatile uint32_t *)0xfe0520a0) +#define P_AED_DRC_ATTACK_COEF11 ((volatile uint32_t *)0xfe0520a4) +#define P_AED_DRC_ATTACK_COEF20 ((volatile uint32_t *)0xfe0520a8) +#define P_AED_DRC_ATTACK_COEF21 ((volatile uint32_t *)0xfe0520ac) +#define P_AED_DRC_ATTACK_COEF30 ((volatile uint32_t *)0xfe0520b0) +#define P_AED_DRC_ATTACK_COEF31 ((volatile uint32_t *)0xfe0520b4) +#define P_AED_DRC_ATTACK_COEF40 ((volatile uint32_t *)0xfe0520b8) +#define P_AED_DRC_ATTACK_COEF41 ((volatile uint32_t *)0xfe0520bc) +#define P_AED_DRC_ATTACK_COEF50 ((volatile uint32_t *)0xfe0520c0) +#define P_AED_DRC_ATTACK_COEF51 ((volatile uint32_t *)0xfe0520c4) +#define P_AED_DRC_LOOPBACK_CNTL ((volatile uint32_t *)0xfe0520c8) +#define P_AED_MDRC_CNTL ((volatile uint32_t *)0xfe0520cc) +#define P_AED_MDRC_RMS_COEF00 ((volatile uint32_t *)0xfe0520d0) +#define P_AED_MDRC_RMS_COEF01 ((volatile uint32_t *)0xfe0520d4) +#define P_AED_MDRC_RELEASE_COEF00 ((volatile uint32_t *)0xfe0520d8) +#define P_AED_MDRC_RELEASE_COEF01 ((volatile uint32_t *)0xfe0520dc) +#define P_AED_MDRC_ATTACK_COEF00 ((volatile uint32_t *)0xfe0520e0) +#define P_AED_MDRC_ATTACK_COEF01 ((volatile uint32_t *)0xfe0520e4) +#define P_AED_MDRC_THD0 ((volatile uint32_t *)0xfe0520e8) +#define P_AED_MDRC_K0 ((volatile uint32_t *)0xfe0520ec) +#define P_AED_MDRC_LOW_GAIN ((volatile uint32_t *)0xfe0520f0) +#define P_AED_MDRC_OFFSET0 ((volatile uint32_t *)0xfe0520f4) +#define P_AED_MDRC_RMS_COEF10 ((volatile uint32_t *)0xfe0520f8) +#define P_AED_MDRC_RMS_COEF11 ((volatile uint32_t *)0xfe0520fc) +#define P_AED_MDRC_RELEASE_COEF10 ((volatile uint32_t *)0xfe052100) +#define P_AED_MDRC_RELEASE_COEF11 ((volatile uint32_t *)0xfe052104) +#define P_AED_MDRC_ATTACK_COEF10 ((volatile uint32_t *)0xfe052108) +#define P_AED_MDRC_ATTACK_COEF11 ((volatile uint32_t *)0xfe05210c) +#define P_AED_MDRC_THD1 ((volatile uint32_t *)0xfe052110) +#define P_AED_MDRC_K1 ((volatile uint32_t *)0xfe052114) +#define P_AED_MDRC_OFFSET1 ((volatile uint32_t *)0xfe052118) +#define P_AED_MDRC_MID_GAIN ((volatile uint32_t *)0xfe05211c) +#define P_AED_MDRC_RMS_COEF20 ((volatile uint32_t *)0xfe052120) +#define P_AED_MDRC_RMS_COEF21 ((volatile uint32_t *)0xfe052124) +#define P_AED_MDRC_RELEASE_COEF20 ((volatile uint32_t *)0xfe052128) +#define P_AED_MDRC_RELEASE_COEF21 ((volatile uint32_t *)0xfe05212c) +#define P_AED_MDRC_ATTACK_COEF20 ((volatile uint32_t *)0xfe052130) +#define P_AED_MDRC_ATTACK_COEF21 ((volatile uint32_t *)0xfe052134) +#define P_AED_MDRC_THD2 ((volatile uint32_t *)0xfe052138) +#define P_AED_MDRC_K2 ((volatile uint32_t *)0xfe05213c) +#define P_AED_MDRC_OFFSET2 ((volatile uint32_t *)0xfe052140) +#define P_AED_MDRC_HIGH_GAIN ((volatile uint32_t *)0xfe052144) +#define P_AED_ED_CNTL ((volatile uint32_t *)0xfe052148) +#define P_AED_DC_EN ((volatile uint32_t *)0xfe05214c) +#define P_AED_ND_LOW_THD ((volatile uint32_t *)0xfe052150) +#define P_AED_ND_HIGH_THD ((volatile uint32_t *)0xfe052154) +#define P_AED_ND_CNT_THD ((volatile uint32_t *)0xfe052158) +#define P_AED_ND_SUM_NUM ((volatile uint32_t *)0xfe05215c) +#define P_AED_ND_CZ_NUM ((volatile uint32_t *)0xfe052160) +#define P_AED_ND_SUM_THD0 ((volatile uint32_t *)0xfe052164) +#define P_AED_ND_SUM_THD1 ((volatile uint32_t *)0xfe052168) +#define P_AED_ND_CZ_THD0 ((volatile uint32_t *)0xfe05216c) +#define P_AED_ND_CZ_THD1 ((volatile uint32_t *)0xfe052170) +#define P_AED_ND_COND_CNTL ((volatile uint32_t *)0xfe052174) +#define P_AED_ND_RELEASE_COEF0 ((volatile uint32_t *)0xfe052178) +#define P_AED_ND_RELEASE_COEF1 ((volatile uint32_t *)0xfe05217c) +#define P_AED_ND_ATTACK_COEF0 ((volatile uint32_t *)0xfe052180) +#define P_AED_ND_ATTACK_COEF1 ((volatile uint32_t *)0xfe052184) +#define P_AED_ND_CNTL ((volatile uint32_t *)0xfe052188) +#define P_AED_MIX0_LL ((volatile uint32_t *)0xfe05218c) +#define P_AED_MIX0_RL ((volatile uint32_t *)0xfe052190) +#define P_AED_MIX0_LR ((volatile uint32_t *)0xfe052194) +#define P_AED_MIX0_RR ((volatile uint32_t *)0xfe052198) +#define P_AED_CLIP_THD ((volatile uint32_t *)0xfe05219c) +#define P_AED_CH1_ND_SUM_OUT ((volatile uint32_t *)0xfe0521a0) +#define P_AED_CH2_ND_SUM_OUT ((volatile uint32_t *)0xfe0521a4) +#define P_AED_CH1_ND_CZ_OUT ((volatile uint32_t *)0xfe0521a8) +#define P_AED_CH2_ND_CZ_OUT ((volatile uint32_t *)0xfe0521ac) +#define P_AED_NOISE_STATUS ((volatile uint32_t *)0xfe0521b0) +#define P_AED_POW_CURRENT_S0 ((volatile uint32_t *)0xfe0521b4) +#define P_AED_POW_CURRENT_S1 ((volatile uint32_t *)0xfe0521b8) +#define P_AED_POW_CURRENT_S2 ((volatile uint32_t *)0xfe0521bc) +#define P_AED_POW_OUT0 ((volatile uint32_t *)0xfe0521c0) +#define P_AED_POW_OUT1 ((volatile uint32_t *)0xfe0521c4) +#define P_AED_POW_OUT2 ((volatile uint32_t *)0xfe0521c8) +#define P_AED_POW_ADJ_INDEX0 ((volatile uint32_t *)0xfe0521cc) +#define P_AED_POW_ADJ_INDEX1 ((volatile uint32_t *)0xfe0521d0) +#define P_AED_POW_ADJ_INDEX2 ((volatile uint32_t *)0xfe0521d4) +#define P_AED_DRC_GAIN_INDEX0 ((volatile uint32_t *)0xfe0521d8) +#define P_AED_DRC_GAIN_INDEX1 ((volatile uint32_t *)0xfe0521dc) +#define P_AED_DRC_GAIN_INDEX2 ((volatile uint32_t *)0xfe0521e0) +#define P_AED_CH1_VOLUME_STATE ((volatile uint32_t *)0xfe0521e4) +#define P_AED_CH2_VOLUME_STATE ((volatile uint32_t *)0xfe0521e8) +#define P_AED_CH1_VOLUME_GAIN ((volatile uint32_t *)0xfe0521ec) +#define P_AED_CH2_VOLUME_GAIN ((volatile uint32_t *)0xfe0521f0) +#define P_AED_FULL_POW_CURRENT ((volatile uint32_t *)0xfe0521f4) +#define P_AED_FULL_POW_OUT ((volatile uint32_t *)0xfe0521f8) +#define P_AED_FULL_POW_ADJ ((volatile uint32_t *)0xfe0521fc) +#define P_AED_FULL_DRC_GAIN ((volatile uint32_t *)0xfe052200) +#define P_AED_MASTER_VOLUME_STATE ((volatile uint32_t *)0xfe052204) +#define P_AED_MASTER_VOLUME_GAIN ((volatile uint32_t *)0xfe052208) +#define P_AED_TOP_CTL0 ((volatile uint32_t *)0xfe05220c) +#define P_AED_TOP_CTL1 ((volatile uint32_t *)0xfe052210) +#define P_AED_TOP_CTL2 ((volatile uint32_t *)0xfe052214) +//======================================================================== +// AUDIO locker - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe051400 +// ----------------------------------------------- +#define P_AUD_LOCK_EN ((volatile uint32_t *)0xfe051400) +#define P_AUD_LOCK_SW_RESET ((volatile uint32_t *)0xfe051404) +#define P_AUD_LOCK_SW_LATCH ((volatile uint32_t *)0xfe051408) +#define P_AUD_LOCK_HW_LATCH ((volatile uint32_t *)0xfe05140c) +#define P_AUD_LOCK_REFCLK_SRC ((volatile uint32_t *)0xfe051410) +#define P_AUD_LOCK_REFCLK_LAT_INT ((volatile uint32_t *)0xfe051414) +#define P_AUD_LOCK_IMCLK_LAT_INT ((volatile uint32_t *)0xfe051418) +#define P_AUD_LOCK_OMCLK_LAT_INT ((volatile uint32_t *)0xfe05141c) +#define P_AUD_LOCK_REFCLK_DS_INT ((volatile uint32_t *)0xfe051420) +#define P_AUD_LOCK_IMCLK_DS_INT ((volatile uint32_t *)0xfe051424) +#define P_AUD_LOCK_OMCLK_DS_INT ((volatile uint32_t *)0xfe051428) +#define P_AUD_LOCK_INT_CLR ((volatile uint32_t *)0xfe05142c) +#define P_AUD_LOCK_GCLK_CTRL ((volatile uint32_t *)0xfe051430) +#define P_AUD_LOCK_INT_CTRL ((volatile uint32_t *)0xfe051434) +#define P_RO_REF2IMCLK_CNT_L ((volatile uint32_t *)0xfe051440) +#define P_RO_REF2IMCLK_CNT_H ((volatile uint32_t *)0xfe051444) +#define P_RO_REF2OMCLK_CNT_L ((volatile uint32_t *)0xfe051448) +#define P_RO_REF2OMCLK_CNT_H ((volatile uint32_t *)0xfe05144c) +#define P_RO_IMCLK2REF_CNT_L ((volatile uint32_t *)0xfe051450) +#define P_RO_IMCLK2REF_CNT_H ((volatile uint32_t *)0xfe051454) +#define P_RO_OMCLK2REF_CNT_L ((volatile uint32_t *)0xfe051458) +#define P_RO_OMCLK2REF_CNT_H ((volatile uint32_t *)0xfe05145c) +#define P_RO_REFCLK_PKG_CNT ((volatile uint32_t *)0xfe051460) +#define P_RO_IMCLK_PKG_CNT ((volatile uint32_t *)0xfe051464) +#define P_RO_OMCLK_PKG_CNT ((volatile uint32_t *)0xfe051468) +#define P_RO_AUD_LOCK_INT_STATUS ((volatile uint32_t *)0xfe05146c) +//======================================================================== +// AUDIO VAD - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe051800 +// ----------------------------------------------- +// +// Reading file: VAD_REG.h +// +#define P_VAD_TOP_CTRL0 ((volatile uint32_t *)0xfe051800) +#define P_VAD_TOP_CTRL1 ((volatile uint32_t *)0xfe051804) +#define P_VAD_TOP_CTRL2 ((volatile uint32_t *)0xfe051808) +#define P_VAD_FIR_CTRL ((volatile uint32_t *)0xfe05180c) +#define P_VAD_FIR_EMP ((volatile uint32_t *)0xfe051810) +#define P_VAD_FIR_COEF0 ((volatile uint32_t *)0xfe051814) +#define P_VAD_FIR_COEF1 ((volatile uint32_t *)0xfe051818) +#define P_VAD_FIR_COEF2 ((volatile uint32_t *)0xfe05181c) +#define P_VAD_FIR_COEF3 ((volatile uint32_t *)0xfe051820) +#define P_VAD_FIR_COEF4 ((volatile uint32_t *)0xfe051824) +#define P_VAD_FIR_COEF5 ((volatile uint32_t *)0xfe051828) +#define P_VAD_FIR_COEF6 ((volatile uint32_t *)0xfe05182c) +#define P_VAD_FIR_COEF7 ((volatile uint32_t *)0xfe051830) +#define P_VAD_FIR_COEF8 ((volatile uint32_t *)0xfe051834) +#define P_VAD_FIR_COEF9 ((volatile uint32_t *)0xfe051838) +#define P_VAD_FIR_COEF10 ((volatile uint32_t *)0xfe05183c) +#define P_VAD_FIR_COEF11 ((volatile uint32_t *)0xfe051840) +#define P_VAD_FIR_COEF12 ((volatile uint32_t *)0xfe051844) +#define P_VAD_FRAME_CTRL0 ((volatile uint32_t *)0xfe051848) +#define P_VAD_FRAME_CTRL1 ((volatile uint32_t *)0xfe05184c) +#define P_VAD_FRAME_CTRL2 ((volatile uint32_t *)0xfe051850) +#define P_VAD_CEP_CTRL0 ((volatile uint32_t *)0xfe051854) +#define P_VAD_CEP_CTRL1 ((volatile uint32_t *)0xfe051858) +#define P_VAD_CEP_CTRL2 ((volatile uint32_t *)0xfe05185c) +#define P_VAD_CEP_CTRL3 ((volatile uint32_t *)0xfe051860) +#define P_VAD_CEP_CTRL4 ((volatile uint32_t *)0xfe051864) +#define P_VAD_CEP_CTRL5 ((volatile uint32_t *)0xfe051868) +#define P_VAD_DEC_CTRL ((volatile uint32_t *)0xfe05186c) +#define P_VAD_TOP_STS0 ((volatile uint32_t *)0xfe051870) +#define P_VAD_TOP_STS1 ((volatile uint32_t *)0xfe051874) +#define P_VAD_TOP_STS2 ((volatile uint32_t *)0xfe051878) +#define P_VAD_FIR_STS0 ((volatile uint32_t *)0xfe05187c) +#define P_VAD_FIR_STS1 ((volatile uint32_t *)0xfe051880) +#define P_VAD_POW_STS0 ((volatile uint32_t *)0xfe051884) +#define P_VAD_POW_STS1 ((volatile uint32_t *)0xfe051888) +#define P_VAD_POW_STS2 ((volatile uint32_t *)0xfe05188c) +#define P_VAD_FFT_STS0 ((volatile uint32_t *)0xfe051890) +#define P_VAD_FFT_STS1 ((volatile uint32_t *)0xfe051894) +#define P_VAD_SPE_STS0 ((volatile uint32_t *)0xfe051898) +#define P_VAD_SPE_STS1 ((volatile uint32_t *)0xfe05189c) +#define P_VAD_SPE_STS2 ((volatile uint32_t *)0xfe0518a0) +#define P_VAD_SPE_STS3 ((volatile uint32_t *)0xfe0518a4) +#define P_VAD_DEC_STS0 ((volatile uint32_t *)0xfe0518a8) +#define P_VAD_DEC_STS1 ((volatile uint32_t *)0xfe0518ac) +#define P_VAD_LUT_CTRL ((volatile uint32_t *)0xfe0518b0) +#define P_VAD_LUT_WR ((volatile uint32_t *)0xfe0518b4) +#define P_VAD_LUT_RD ((volatile uint32_t *)0xfe0518b8) +#define P_VAD_IN_SEL0 ((volatile uint32_t *)0xfe0518bc) +#define P_VAD_IN_SEL1 ((volatile uint32_t *)0xfe0518c0) +#define P_VAD_TO_DDR ((volatile uint32_t *)0xfe0518c4) +// +// Closing file: VAD_REG.h +// +//======================================================================== +// AUDIO RESAMPLEA - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe051c00 +// ----------------------------------------------- +// +// Reading file: RESAMPLE.h +// +#define P_AUDIO_RSAMP_CTRL0 ((volatile uint32_t *)0xfe051c00) +//Bit 31:3 reserved +//Bit 2 reg_lock_rst //unsigned , default =0; +//Bit 1 reg_rsamp_rst //unsigned , default =0; +//Bit 0 reg_sw_rst //unsigned , default =0; +#define P_AUDIO_RSAMP_CTRL1 ((volatile uint32_t *)0xfe051c04) +//Bit 31:26 reserved //unsigned , default =0; +//Bit 25 reg_rsamp_rst_sel //unsigned , default =0; +//Bit 24 reg_module_bypas //unsigned , default =0; +//Bit 23:18 reg_gclk_ctrl //unsigned , default =0; +//Bit 17:13 reg_in_msb //unsigned , default =23; +//Bit 12 reg_output_en //unsigned , default =0; +//Bit 11 reg_rsamp_en //unsigned , default =0; +//Bit 10 reg_filt_en //unsigned , default =0; +//Bit 9 reg_post_en //unsigned , default =0; +//Bit 8 reg_inp_mux_mode //unsigned , default =0; +//Bit 7:4 reserved //unsigned , default =2; +//Bit 3:0 reg_inp_mux //unsigned , default =0; +#define P_AUDIO_RSAMP_CTRL2 ((volatile uint32_t *)0xfe051c08) +//Bit 31:30 reserved //unsigned , default =0; +//Bit 29:24 reg_chx_size //unsigned , default =2; +//Bit 23:18 reserved //unsigned , default =0; +//Bit 17:16 reg_scl_step //unsigned , default =0; 0: 1/1 1: 1/2 2: 1/4 +//Bit 15:8 reg_filt_tap //unsigned , default =63; +//Bit 7:0 reg_intp_tap //unsigned , default =63; +#define P_AUDIO_RSAMP_PHSINIT ((volatile uint32_t *)0xfe051c0c) +//Bit 31:28 reserved //unsigned , default = 0; +//Bit 27:0 reg_init_phs //unsigned , default = 0; +#define P_AUDIO_RSAMP_PHSSTEP ((volatile uint32_t *)0xfe051c10) +//Bit 31 reserved //unsigned , default = 0; +//Bit 30:0 reg_rsamp_step //unsigned , default = 134217728;//'h800_0000 +#define P_AUDIO_RSAMP_SHIFT ((volatile uint32_t *)0xfe051c14) +//Bit 31:24 reg_rsft_iir //unsigned , default = 23; +//Bit 23:16 reg_rsft_blnd //unsigned , default = 21; +//Bit 15:8 reg_rsft_sinc //unsigned , default = 31; +//Bit 7:0 reg_rsft_aa //unsigned , default = 31; +#define P_AUDIO_RSAMP_ADJ_CTRL0 ((volatile uint32_t *)0xfe051c18) +//Bit 31:3 reserved //unsigned +//Bit 2 reg_rsamp_adj_out_inv //unsigned , default = 0; +//Bit 1 reg_rsamp_adj_force_en //unsigned , default = 0; +//Bit 0 reg_rsamp_adj_en //unsigned , default = 0; +#define P_AUDIO_RSAMP_ADJ_CTRL1 ((volatile uint32_t *)0xfe051c1c) +//Bit 31:16 reg_rsamp_adj_odet_step //unsigned , default = 8; +//Bit 15:0 reg_rsamp_adj_kmax //unsigned , default = 32768; +#define P_AUDIO_RSAMP_ADJ_SFT ((volatile uint32_t *)0xfe051c20) +//Bit 31:30 reserved //unsigned , default = 0; +//Bit 29 reg_rsamp_adj_dif_sel //unsigned , default = 0; +//Bit 28:24 reg_rsamp_adj_ki //unsigned , default = 9; +//Bit 23:21 reserved //unsigned , default = 0; +//Bit 20:16 reg_rsamp_adj_kp //unsigned , default = 1; +//Bit 15:13 reserved //unsigned , default = 0; +//Bit 12:8 reg_rsamp_adj_ki_sft //unsigned , default = 6; +//Bit 7:6 reserved //unsigned , default = 0; +//Bit 5:0 reg_rsamp_adj_out_sft //unsigned , default = 12; +#define P_AUDIO_RSAMP_ADJ_IDET_LEN ((volatile uint32_t *)0xfe051c24) +//Bit 31:0 reg_rsamp_adj_idet_len //unsigned , default = 10000; +#define P_AUDIO_RSAMP_ADJ_FORCE ((volatile uint32_t *)0xfe051c28) +//Bit 31:0 reg_rsamp_adj_force_err //signed , default = 8; +#define P_AUDIO_RSAMP_ADJ_KI_FORCE ((volatile uint32_t *)0xfe051c2c) +//Bit 31:0 reg_rsamp_adj_ki_force //signed , default = 0; +#define P_AUDIO_RSAMP_RO_STATUS ((volatile uint32_t *)0xfe051c40) +//Bit 31:0 ro_rsamp_stat //{din_chx_chk_err,is_idle_st,rsamp_fifo_over_cnt[7:0]} +#define P_AUDIO_RSAMP_RO_ADJ_FREQ ((volatile uint32_t *)0xfe051c44) +//Bit 31:0 ro_rsamp_adj_freq +#define P_AUDIO_RSAMP_RO_ADJ_DIFF_BAK ((volatile uint32_t *)0xfe051c48) +//Bit 31:0 ro_det_diff_bak +#define P_AUDIO_RSAMP_RO_ADJ_DIFF_DLT ((volatile uint32_t *)0xfe051c4c) +//Bit 31:0 ro_det_diff_dlt +#define P_AUDIO_RSAMP_RO_ADJ_PHS_ERR ((volatile uint32_t *)0xfe051c50) +//Bit 31:0 ro_det_phase_err +#define P_AUDIO_RSAMP_RO_ADJ_KI_OUT ((volatile uint32_t *)0xfe051c54) +//Bit 31:0 ro_rsamp_ki_out +#define P_AUDIO_RSAMP_RO_IN_CNT ((volatile uint32_t *)0xfe051c58) +//Bit 31:0 ro_rsamp_in_cnt +#define P_AUDIO_RSAMP_RO_OUT_CNT ((volatile uint32_t *)0xfe051c5c) +//Bit 31:0 ro_rsamp_out_cnt +#define P_AUDIO_RSAMP_POST_COEF0 ((volatile uint32_t *)0xfe051c80) +//Bit 31:0 reg_post_coef0 //signed , default = 0; +#define P_AUDIO_RSAMP_POST_COEF1 ((volatile uint32_t *)0xfe051c84) +//Bit 31:0 reg_post_coef1 //signed , default = 0; +#define P_AUDIO_RSAMP_POST_COEF2 ((volatile uint32_t *)0xfe051c88) +//Bit 31:0 reg_post_coef2 //signed , default = 0; +#define P_AUDIO_RSAMP_POST_COEF3 ((volatile uint32_t *)0xfe051c8c) +//Bit 31:0 reg_post_coef3 //signed , default = 0; +#define P_AUDIO_RSAMP_POST_COEF4 ((volatile uint32_t *)0xfe051c90) +//Bit 31:0 reg_post_coef4 //signed , default = 0; +#define P_AUDIO_RSAMP_AA_COEF_ADDR ((volatile uint32_t *)0xfe051cc0) +//Bit 31:0 reg_aa_coef_addr //unsigned, default = 0; +#define P_AUDIO_RSAMP_AA_COEF_DATA ((volatile uint32_t *)0xfe051cc4) +//Bit 31:0 reg_aa_coef_data //signed , default = 0; +#define P_AUDIO_RSAMP_SINC_COEF_ADDR ((volatile uint32_t *)0xfe051d00) +//Bit 31:0 reg_sinc_coef_addr //unsigned, default = 0; +#define P_AUDIO_RSAMP_SINC_COEF_DATA ((volatile uint32_t *)0xfe051d04) +//Bit 31:0 reg_sinc_coef_data //signed , default = 0; +// +// Closing file: RESAMPLE.h +// +//======================================================================== +// AUDIO TOP_VAD - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe054800 +// ----------------------------------------------- +#define P_EE_AUDIO2_CLK81_CTRL ((volatile uint32_t *)0xfe054800) +#define P_EE_AUDIO2_CLK81_EN ((volatile uint32_t *)0xfe054804) +#define P_EE_AUDIO2_SW_RESET0 ((volatile uint32_t *)0xfe054808) +#define P_EE_AUDIO2_CLK_GATE_EN0 ((volatile uint32_t *)0xfe05480c) +#define P_EE_AUDIO2_SECURITY_CTRL0 ((volatile uint32_t *)0xfe054810) +#define P_EE_AUDIO2_MCLK_VAD_CTRL ((volatile uint32_t *)0xfe054840) +#define P_EE_AUDIO2_VAD_CLK_CTRL ((volatile uint32_t *)0xfe054844) +#define P_EE_AUDIO2_MST_DLY_CTRL0 ((volatile uint32_t *)0xfe054848) +#define P_EE_AUDIO2_MST_VAD_SCLK_CTRL0 ((volatile uint32_t *)0xfe05484c) +#define P_EE_AUDIO2_MST_VAD_SCLK_CTRL1 ((volatile uint32_t *)0xfe054850) +#define P_EE_AUDIO2_CLK_TDMIN_VAD_CTRL ((volatile uint32_t *)0xfe054854) +#define P_EE_AUDIO2_CLK_PDMIN_CTRL0 ((volatile uint32_t *)0xfe054858) +#define P_EE_AUDIO2_CLK_PDMIN_CTRL1 ((volatile uint32_t *)0xfe05485c) +#define P_EE_AUDIO2_TOVAD_CTRL0 ((volatile uint32_t *)0xfe054880) +#define P_EE_AUDIO2_TODDR_VAD_CTRL0 ((volatile uint32_t *)0xfe0548c0) +#define P_EE_AUDIO2_TODDR_VAD_CTRL1 ((volatile uint32_t *)0xfe0548c4) +#define P_EE_AUDIO2_TODDR_VAD_CTRL2 ((volatile uint32_t *)0xfe0548c8) +#define P_EE_AUDIO2_TODDR_VAD_START_ADDR ((volatile uint32_t *)0xfe0548cc) +#define P_EE_AUDIO2_TODDR_VAD_INIT_ADDR ((volatile uint32_t *)0xfe0548d0) +#define P_EE_AUDIO2_TODDR_VAD_FINISH_ADDR ((volatile uint32_t *)0xfe0548d4) +#define P_EE_AUDIO2_TODDR_VAD_START_ADDRB ((volatile uint32_t *)0xfe0548d8) +#define P_EE_AUDIO2_TODDR_VAD_FINISH_ADDRB ((volatile uint32_t *)0xfe0548dc) +#define P_EE_AUDIO2_TODDR_VAD_INT_ADDR ((volatile uint32_t *)0xfe0548e0) +#define P_EE_AUDIO2_TODDR_VAD_STATUS1 ((volatile uint32_t *)0xfe0548e4) +#define P_EE_AUDIO2_TODDR_VAD_STATUS2 ((volatile uint32_t *)0xfe0548e8) +#define P_EE_AUDIO2_TDMIN_VAD_CTRL ((volatile uint32_t *)0xfe054900) +#define P_EE_AUDIO2_TDMIN_VAD_SWAP0 ((volatile uint32_t *)0xfe054904) +#define P_EE_AUDIO2_TDMIN_VAD_SWAP1 ((volatile uint32_t *)0xfe054908) +#define P_EE_AUDIO2_TDMIN_VAD_MUTE_VAL ((volatile uint32_t *)0xfe05490c) +#define P_EE_AUDIO2_TDMIN_VAD_STAT ((volatile uint32_t *)0xfe054910) +#define P_EE_AUDIO2_TDMIN_VAD_MUTE0 ((volatile uint32_t *)0xfe054940) +#define P_EE_AUDIO2_TDMIN_VAD_MUTE1 ((volatile uint32_t *)0xfe054944) +#define P_EE_AUDIO2_TDMIN_VAD_MUTE2 ((volatile uint32_t *)0xfe054948) +#define P_EE_AUDIO2_TDMIN_VAD_MUTE3 ((volatile uint32_t *)0xfe05494c) +#define P_EE_AUDIO2_TDMIN_VAD_MUTE4 ((volatile uint32_t *)0xfe054950) +#define P_EE_AUDIO2_TDMIN_VAD_MUTE5 ((volatile uint32_t *)0xfe054954) +#define P_EE_AUDIO2_TDMIN_VAD_MUTE6 ((volatile uint32_t *)0xfe054958) +#define P_EE_AUDIO2_TDMIN_VAD_MUTE7 ((volatile uint32_t *)0xfe05495c) +#define P_EE_AUDIO2_TDMIN_VAD_MASK0 ((volatile uint32_t *)0xfe054960) +#define P_EE_AUDIO2_TDMIN_VAD_MASK1 ((volatile uint32_t *)0xfe054964) +#define P_EE_AUDIO2_TDMIN_VAD_MASK2 ((volatile uint32_t *)0xfe054968) +#define P_EE_AUDIO2_TDMIN_VAD_MASK3 ((volatile uint32_t *)0xfe05496c) +#define P_EE_AUDIO2_TDMIN_VAD_MASK4 ((volatile uint32_t *)0xfe054970) +#define P_EE_AUDIO2_TDMIN_VAD_MASK5 ((volatile uint32_t *)0xfe054974) +#define P_EE_AUDIO2_TDMIN_VAD_MASK6 ((volatile uint32_t *)0xfe054978) +#define P_EE_AUDIO2_TDMIN_VAD_MASK7 ((volatile uint32_t *)0xfe05497c) +// +// Closing file: REG_LIST_AUDIO_RTL.h +// +// +// Reading file: ../spifc/rtl/spifc_reg.vh +// +//`ifdef SPIFC_REG_DEFINE +//`else +//`define SPIFC_REG_DEFINE +//`define SPIFC BASE ADDR 32'hfd000400 +// ----------------------------------------------- +// APB_BASE: APB2_BASE_ADDR = 0xfd000400 +// ----------------------------------------------- +//AHB domain regsiter. +#define P_SPIFC_AHB_CTRL ((volatile uint32_t *)0xfd000400) +//bit 31 AHB BUS enable. 1 enable ahb request. 0: disable ahb request. +//bit 30. decerr_en for (AXI->AHB bridge). +//bit 29. force_incr. for ( AXI->AHB bridge). +//bit 19. critical word first. CWF_EN. 1: enable. 0 : disable. +//bit 18:17 RDBUF_SIZE . 00: 64bytes. 01: 32 bytes. 10: 16 bytes. 11: reserved. +//bit 16 AHB MASTER enable. if enabled, each master use one dedicated HRDATA buffer inside ahb2api model. total 3 HRDATA buffers inside ahb2spi. +//if disabled the 3 HRDATA buffer will random be used for all masters. +//bit 14 write 1 to clean the HRDATA buffer 2. read 0 finished clean operation. +//bit 13 write 1 to clean the HRDATA buffer 1. read 0 finished clean operation. +//bit 12 write 1 to clean the HRDATA buffer 0. read 0 finished clean operation. +//bit 11:0. not used. +#define P_SPIFC_CLK_CTRL ((volatile uint32_t *)0xfd000404) +//bit 14 asynchronous buffer ahb clock disable. 1 = disable. 0 = enable. +//bit 13 ahb2spi ahb clock disable. 1 = disable. 0 = enable. +//bit 12 ahb_arb ahb clock disable. 1 = disable. 0 = enable. +//bit 10 asynchronous buffer ahb clock auto gating enable. 1 = enable. 0 = disable. +//bit 9 ahb2spi ahb clock auto gating enable. 1 = enable. 0 = disable. +//bit 8 ahbarb ahb clock auto gating enable. 1 = enable. 0 = disable. +//bit 2. asynchronous AHB clock domain software reset. 1 = reset. 0 = normal working mode. +//bit 1. ahb2spi ahb clock domain software reset. 1 = reset. 0 = normal working mode. +//bit 0. not used. +#define P_SPIFC_SEC_CTRL ((volatile uint32_t *)0xfd000408) +//bit 31. ADDRESS security range enable. 1 = enable; 0: disable. +//bit 14. range6 enable: 1: enable; 0 : disable. +//bit 13. range5 enable: 1: enable; 0 : disable. +//bit 12. range4 enable: 1: enable; 0 : disable. +//bit 11. range3 enable: 1: enable; 0 : disable. +//bit 10. range2 enable: 1: enable; 0 : disable. +//bit 9. range1 enable: 1: enable; 0 : disable. +//bit 8. range0 enable: 1: enable; 0 : disable. +//bit 7:4 to control spi clock register security. bit 7 = 1, APB bus can access spi clock domain register. bit 7 == 0 : only PPROT[0] == bit 4, the APB can access spic clock domain register. +//bit 3:0 to control ahb clock domain register secruity. bit 3 = 1, APB bus can access ahb clock domain register. bit 3 ==0; only PPROT[0] == bit 0, the APB can access ahb clock domain register. +#define P_SPIFC_RANGE0_STA ((volatile uint32_t *)0xfd000440) +//bit 28 :6. +//AHB security range 0 start address in unit of 64Byte. related to HADDR bit 28:6. +//bit 5:0. always 0. +#define P_SPIFC_RANGE0_EDA ((volatile uint32_t *)0xfd000444) +//bit 28 :6. +//AHB security range 0 end address in unit of 64Byte. related to HADDR bit 28:6. +//bit 5:0. always 0. +#define P_SPIFC_RANGE0_CTRL ((volatile uint32_t *)0xfd000448) +// AHB secruity range 0 control. +//bit 15:8 range 0 access control for DMA access. +//bit 15 range 0 access control for DMA thread 7 +//bit 14 range 0 access control for DMA Thread 6 +//bit 13 range 0 access control for DMA Thread 5. +//bit 12 range 0 access control for DMA Thread 4. +// bit 11. range 0 access control for DMA thread 3 +// bit 10. range 0 access control for DMA Thread 2 +// bit 9. range 0 access control for DMA Thread 1. +// bit 8. range 0 access control for DMA Thread 0. +// bit 7. range 0 access control for HMASTER == 7 Not used. +// bit 6. range 0 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA. +// bit 5. range 0 access control for HMASTER == 5 //DSPB non secure +// bit 4. range 0 access control for HMASTER == 4 //DSPB non secure +// bit 3. range 0 access control for HMASTER == 3 //DSPA secure +// bit 2. range 0 access control for HMASTER == 2 //DSPA non secure +// bit 1. range 0 access control for HMASTER == 1 //CPU secure access +// bit 0. range 0 access control for HMASTER == 0 //CPU non secure. +#define P_SPIFC_RANGE1_STA ((volatile uint32_t *)0xfd00044c) +//bit 28 :6. +//AHB security range 1 start address in unit of 64Byte. related to HADDR bit 28:6. +//bit 5:0. always 0. +#define P_SPIFC_RANGE1_EDA ((volatile uint32_t *)0xfd000450) +//bit 28 :6. +//AHB security range 1 end address in unit of 64Byte. related to HADDR bit 28:6. +//bit 5:0. always 0. +#define P_SPIFC_RANGE1_CTRL ((volatile uint32_t *)0xfd000454) +// AHB secruity range 1 control. +//bit 15:8 range 1 access control for DMA access. +//bit 15 range 1 access control for DMA thread 7 +//bit 14 range 1 access control for DMA Thread 6 +//bit 13 range 1 access control for DMA Thread 5. +//bit 12 range 1 access control for DMA Thread 4. +// bit 11. range 1 access control for DMA thread 3 +// bit 10. range 1 access control for DMA Thread 2 +// bit 9. range 1 access control for DMA Thread 1. +// bit 8. range 1 access control for DMA Thread 0. +// bit 7. range 1 access control for HMASTER == 7 Not used. +// bit 6. range 1 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA. +// bit 5. range 1 access control for HMASTER == 5 //DSPB non secure +// bit 4. range 1 access control for HMASTER == 4 //DSPB non secure +// bit 3. range 1 access control for HMASTER == 3 //DSPA secure +// bit 2. range 1 access control for HMASTER == 2 //DSPA non secure +// bit 1. range 1 access control for HMASTER == 1 //CPU secure access +// bit 0. range 1 access control for HMASTER == 0 //CPU non secure. +#define P_SPIFC_RANGE2_STA ((volatile uint32_t *)0xfd000458) +//bit 28 :6. +//AHB security range 2 start address in unit of 64Byte. related to HADDR bit 28:6. +//bit 5:0. always 0. +#define P_SPIFC_RANGE2_EDA ((volatile uint32_t *)0xfd00045c) +//bit 28 :6. +//AHB security range 2 end address in unit of 64Byte. related to HADDR bit 28:6. +//bit 5:0. always 0. +#define P_SPIFC_RANGE2_CTRL ((volatile uint32_t *)0xfd000460) +// AHB secruity range 2 control. +//bit 15:8 range 2 access control for DMA access. +//bit 15 range 2 access control for DMA thread 7 +//bit 14 range 2 access control for DMA Thread 6 +//bit 13 range 2 access control for DMA Thread 5. +//bit 12 range 2 access control for DMA Thread 4. +// bit 11. range 2 access control for DMA thread 3 +// bit 10. range 2 access control for DMA Thread 2 +// bit 9. range 2 access control for DMA Thread 1. +// bit 8. range 2 access control for DMA Thread 0. +// bit 7. range 2 access control for HMASTER == 7 Not used. +// bit 6. range 2 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA. +// bit 5. range 2 access control for HMASTER == 5 //DSPB non secure +// bit 4. range 2 access control for HMASTER == 4 //DSPB non secure +// bit 3. range 2 access control for HMASTER == 3 //DSPA secure +// bit 2. range 2 access control for HMASTER == 2 //DSPA non secure +// bit 1. range 2 access control for HMASTER == 1 //CPU secure access +// bit 0. range 2 access control for HMASTER == 0 //CPU non secure. +#define P_SPIFC_RANGE3_STA ((volatile uint32_t *)0xfd000464) +//bit 28 :6. +//AHB security range 3 start address in unit of 64Byte. related to HADDR bit 28:6. +//bit 5:0. always 0. +#define P_SPIFC_RANGE3_EDA ((volatile uint32_t *)0xfd000468) +//bit 28 :6. +//AHB security range 3 end address in unit of 64Byte. related to HADDR bit 28:6. +//bit 5:0. always 0. +#define P_SPIFC_RANGE3_CTRL ((volatile uint32_t *)0xfd00046c) +// AHB secruity range 3 control. +//bit 15:8 range 3 access control for DMA access. +//bit 15 range 3 access control for DMA thread 7 +//bit 14 range 3 access control for DMA Thread 6 +//bit 13 range 3 access control for DMA Thread 5. +//bit 12 range 3 access control for DMA Thread 4. +// bit 11. range 3 access control for DMA thread 3 +// bit 10. range 3 access control for DMA Thread 2 +// bit 9. range 3 access control for DMA Thread 1. +// bit 8. range 3 access control for DMA Thread 0. +// bit 7. range 3 access control for HMASTER == 7 Not used. +// bit 6. range 3 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA. +// bit 5. range 3 access control for HMASTER == 5 //DSPB non secure +// bit 4. range 3 access control for HMASTER == 4 //DSPB non secure +// bit 3. range 3 access control for HMASTER == 3 //DSPA secure +// bit 2. range 3 access control for HMASTER == 2 //DSPA non secure +// bit 1. range 3 access control for HMASTER == 1 //CPU secure access +// bit 0. range 3 access control for HMASTER == 0 //CPU non secure. +#define P_SPIFC_RANGE4_STA ((volatile uint32_t *)0xfd000470) +//bit 28 :6. +//AHB security range 4 start address in unit of 64Byte. related to HADDR bit 28:6. +//bit 5:0. always 0. +#define P_SPIFC_RANGE4_EDA ((volatile uint32_t *)0xfd000474) +//bit 28 :6. +//AHB security range 4 end address in unit of 64Byte. related to HADDR bit 28:6. +//bit 5:0. always 0. +#define P_SPIFC_RANGE4_CTRL ((volatile uint32_t *)0xfd000478) +// AHB secruity range 4 control. +//bit 15:8 range 4 access control for DMA access. +//bit 15 range 4 access control for DMA thread 7 +//bit 14 range 4 access control for DMA Thread 6 +//bit 13 range 4 access control for DMA Thread 5. +//bit 12 range 4 access control for DMA Thread 4. +// bit 11. range 4 access control for DMA thread 3 +// bit 10. range 4 access control for DMA Thread 2 +// bit 9. range 4 access control for DMA Thread 1. +// bit 8. range 4 access control for DMA Thread 0. +// bit 7. range 4 access control for HMASTER == 7 Not used. +// bit 6. range 4 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA. +// bit 5. range 4 access control for HMASTER == 5 //DSPB non secure +// bit 4. range 4 access control for HMASTER == 4 //DSPB non secure +// bit 3. range 4 access control for HMASTER == 3 //DSPA secure +// bit 2. range 4 access control for HMASTER == 2 //DSPA non secure +// bit 1. range 4 access control for HMASTER == 1 //CPU secure access +// bit 0. range 4 access control for HMASTER == 0 //CPU non secure. +#define P_SPIFC_RANGE5_STA ((volatile uint32_t *)0xfd00047c) +//bit 28 :6. +//AHB security range 5 start address in unit of 64Byte. related to HADDR bit 28:6. +//bit 5:0. always 0. +#define P_SPIFC_RANGE5_EDA ((volatile uint32_t *)0xfd000484) +//bit 28 :6. +//AHB security range 5 end address in unit of 64Byte. related to HADDR bit 28:6. +//bit 5:0. always 0. +#define P_SPIFC_RANGE5_CTRL ((volatile uint32_t *)0xfd000480) +// AHB secruity range 5 control. +//bit 15:8 range 5 access control for DMA access. +//bit 15 range 5 access control for DMA thread 7 +//bit 14 range 5 access control for DMA Thread 6 +//bit 13 range 5 access control for DMA Thread 5. +//bit 12 range 5 access control for DMA Thread 4. +// bit 11. range 5 access control for DMA thread 3 +// bit 10. range 5 access control for DMA Thread 2 +// bit 9. range 5 access control for DMA Thread 1. +// bit 8. range 5 access control for DMA Thread 0. +// bit 7. range 5 access control for HMASTER == 7 Not used. +// bit 6. range 5 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA. +// bit 5. range 5 access control for HMASTER == 5 //DSPB non secure +// bit 4. range 5 access control for HMASTER == 4 //DSPB non secure +// bit 3. range 5 access control for HMASTER == 3 //DSPA secure +// bit 2. range 5 access control for HMASTER == 2 //DSPA non secure +// bit 1. range 5 access control for HMASTER == 1 //CPU secure access +// bit 0. range 5 access control for HMASTER == 0 //CPU non secure. +#define P_SPIFC_RANGE6_STA ((volatile uint32_t *)0xfd000488) +//bit 28 :6. +//AHB security range 6 start address in unit of 64Byte. related to HADDR bit 28:6. +//bit 5:0. always 0. +#define P_SPIFC_RANGE6_EDA ((volatile uint32_t *)0xfd00048c) +//bit 28 :6. +//AHB security range 6 end address in unit of 64Byte. related to HADDR bit 28:6. +//bit 5:0. always 0. +#define P_SPIFC_RANGE6_CTRL ((volatile uint32_t *)0xfd000490) +// AHB secruity range 6 control. +//bit 15:8 range 6 access control for DMA access. +//bit 15 range 6 access control for DMA thread 7 +//bit 14 range 6 access control for DMA Thread 6 +//bit 13 range 6 access control for DMA Thread 5. +//bit 12 range 6 access control for DMA Thread 4. +// bit 11. range 6 access control for DMA thread 3 +// bit 10. range 6 access control for DMA Thread 2 +// bit 9. range 6 access control for DMA Thread 1. +// bit 8. range 6 access control for DMA Thread 0. +// bit 7. range 6 access control for HMASTER == 7 Not used. +// bit 6. range 6 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA. +// bit 5. range 6 access control for HMASTER == 5 //DSPB non secure +// bit 4. range 6 access control for HMASTER == 4 //DSPB non secure +// bit 3. range 6 access control for HMASTER == 3 //DSPA secure +// bit 2. range 6 access control for HMASTER == 2 //DSPA non secure +// bit 1. range 6 access control for HMASTER == 1 //CPU secure access +// bit 0. range 6 access control for HMASTER == 0 //CPU non secure. +#define P_SPIFC_RANGE7_CTRL ((volatile uint32_t *)0xfd000494) +// AHB secruity range 7( default range) control. +//bit 15:8 range 7 access control for DMA access. +//bit 15 range 7 access control for DMA thread 7 +//bit 14 range 7 access control for DMA Thread 6 +//bit 13 range 7 access control for DMA Thread 5. +//bit 12 range 7 access control for DMA Thread 4. +// bit 11. range 7 access control for DMA thread 3 +// bit 10. range 7 access control for DMA Thread 2 +// bit 9. range 7 access control for DMA Thread 1. +// bit 8. range 7 access control for DMA Thread 0. +// bit 7. range 7 access control for HMASTER == 7 Not used. +// bit 6. range 7 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA. +// bit 5. range 7 access control for HMASTER == 5 //DSPB non secure +// bit 4. range 7 access control for HMASTER == 4 //DSPB non secure +// bit 3. range 7 access control for HMASTER == 3 //DSPA secure +// bit 2. range 7 access control for HMASTER == 2 //DSPA non secure +// bit 1. range 7 access control for HMASTER == 1 //CPU secure access +// bit 0. range 7 access control for HMASTER == 0 //CPU non secure. +#define P_SPIFC_AHB_WTCH_CTRL ((volatile uint32_t *)0xfd000498) +//bit 15:0. ahb bus watch dog timer. if AHB bus not response, the timer over this number, the SPIFC will send back a error response. +#define P_SPIFC_SEC_VIO0 ((volatile uint32_t *)0xfd00049c) +//bit 31:0 VIO ADDR +#define P_SPIFC_SEC_VIO1 ((volatile uint32_t *)0xfd0004a0) +//bit 31. AHB VIO status. write 1 to clear the error info. +//bit 6:5 HMASTER. +//bit 4:2 HPROT. +//bit 1 HNONSEC. +//bit 0 HWRITE. +#define P_SPIFC_AHB_STS ((volatile uint32_t *)0xfd0004a4) +//bit 31. AHB IDLE. when ahb disabled, to show ahb status. 1, no more ahb request or ahb requent is holded. 0, ahb is still busy. +//bit 30. AHB data cycle status, when ahb disabled, to show ahb data cycle status. 1, data cycle is holded, 0 : not in data cycle or data cycle is processing. +//bit 29. AHB bus spi requst status. 1: still waiting for spi data. 0: idle. +//bit 28:0. not used. +//SPI cts_spi_clk domain regsiter. +#define P_SPIFC_USER_CTRL0 ((volatile uint32_t *)0xfd000600) +//bit 31. user request enable. write 1 to enable. read 0, means user command accepted by the SPI_CTRL. +//bit 30. user request finish bit. write 0 when enable user request. read 1 means SPI_CTRL finished this user command. +//bit 0. user data updated. write 0 when enable user request. 1 means there's datas/status read from SPI flash. +#define P_SPIFC_USER_CTRL1 ((volatile uint32_t *)0xfd000604) +//bit 31. not used. +//bit 30. user command cycle enable. 1) enable. 0) don't send command in usr command period. +//bit 29:28. user command mode. 00 = SPI extend mode. 01 : dual mode. 10: quad mode. +//bit 27:20. user command code. the code need to send in command period. +//bit 19. user address cycle enable. +//bit 18:17 user address mode: 00 = SPI extend mode. 01 : dual mode. 10: quad mode. +//bit 16:15 user address Byte length 00 = 1 byte. 01 = 2 bytes. 10 = 3 bytes. 11 = 4bytes. +//bit 14 user datout enable. +//bit 13 user dataout AES enable. 1: dataout through AES describle. 0 : original data. +//bit 12 user data output source. 0: from data buffer. 1: from status register. +//bit 11:10 user dataout mode: 00 SPI extend model. 01 : dual model. 10. quad mode. +//bit 9:0 User data out bytes num. +#define P_SPIFC_USER_CTRL2 ((volatile uint32_t *)0xfd000608) +//bit 31 usr_dummy_en 1: enable dummy cycles. 0 : no dummy cycles. +//bit 30: 29 usr_dummy_mode 2'b00 = SPI extend mode. 01 dual mode. 10 Quad mode. +//bit 28:23 user dummy clock cycle number. +//bit 19:16. user command input/output direction control. 000000: right after the last output. +// 1: after the first cycle of dummy cycle. +// ..... +// 4'hf: right before the datin cycle. +//bit 15:8. data on the dummy cycle after the first byte. +//bit 7:0 The first bytes data showed on dummy cycle. some flash may need special data for enhance performance mode or XIP mode. +#define P_SPIFC_USER_CTRL3 ((volatile uint32_t *)0xfd00060c) +//bit 31 usr_datin_en 1: datain cycle enabled. 0: no datain cycle. +//bit 30: datin_dest. 1: save the input data to STATUS register. 0 save the input data to data buffer. +//bit 29: 1: enable datain data AES describle. 0: not use AES. +//bit 28:27. datin mode. 2'b00 SPI extend mode. 01: dual mode. 10 Quad mode. +//bit 25:16. user data in data bytes. how many bytes of user datain expected. +#define P_SPIFC_USER_ADDR ((volatile uint32_t *)0xfd000610) +//bit 31:0. 32bits user address. +#define P_SPIFC_AHB_REQ_CTRL ((volatile uint32_t *)0xfd000614) +//bit 31. AHB request enable. +//bit 30 AHB cmd_en. command cycle enable. +//bit 29:28. ahb command mode. 2'b00: spi mode. 01: dual mode. 10 Quad mode. +//bit 27:20:.AHB command code. +//bit 19. ahb request address cycle enable. +//bit 18:17 AHB ADDRESS mode. 2'b00: spi mode. 01: dual mode. 10 Quad mode. +//bit 16:15 AHB ADDRESS data width. 2'b00: 1byte. 2'b01 : 2bytes. 2'b10: 3bytes. 2'b11 4bytes. +//bit 13:10 AHB request spi bus input switch time. 0 : after address cycle. 1: the frist dummy cycles. ... 0xf. after dummy cycle. +//bit 9:8 AHB DATAIN mode. 2'b00: spi mode. 01: dual mode. 10 Quad mode. +//bit 7 DATA IN AES enable. 1: enable 0: disable. +//bit 1:0 AHB REQ DATA size. 2'b00: 64bytes. 2'b01: 32 bytes. 2'b10 : 16 bytes. 2'b11: reserved. this bit settign should be same as RDBUF_SIZE setting. +#define P_SPIFC_AHB_REQ_CTRL1 ((volatile uint32_t *)0xfd000618) +//bit 31. ahb Dummy enable. +//bit 30:29. ahb dummy mode. +//bit 28:23. ahb request dummy clock cycles. +//bit 15:0. ahb dummy period output data. +#define P_SPIFC_AHB_REQ_CTRL2 ((volatile uint32_t *)0xfd00061c) +//bit 1:0 AHB address position. this settign depend on SPIFC_AHB_CTRL register CWF_EN bit and RDBUF_SIZE. +// if CWF_EN is enabled. these bit should be set to 2'b10 (16BYTE boundary). +// if CWF_EN is disabled. these bit should be set to same as the RDBUF_SIZE and AHB REQ DATA SIZE. +//00 : 64byte boundary. +//01 : 32byte boundary. +//10 : 16byte boundary. +//11 : reserved. +#define P_SPIFC_ACTIMING0 ((volatile uint32_t *)0xfd000620) +//bit 31:30. tSLCH +//bit 29:28 tCLSH +//bit 20:16 tSHWL +//bit 15:12 tSHSL2 +//bit 11:8 tSHSL1 +//bit 7:0 tWHSL +#define P_SPIFC_ACTIMING1 ((volatile uint32_t *)0xfd000624) +//bit 31. D2 pin WP_n function enable. +//bit 30. D2 Pin value in WP_n fucntion. +//bit 29. D3 Pin HOLD_n function enable. +//bit 8. DTR mode. not support. +//bit 6:4. Clock turn around delay. use it to set the system SPI clock read data delay. +//bit 3:0. not used. +#define P_SPIFC_ACTIMING2 ((volatile uint32_t *)0xfd000628) +//bit 31. spi clock input pin enable. SPIFC controller used this pin as clock to latch the input data. +//bit [3:0] spi clock input pin delay adjustment. +//SPI DATA BUFFER. There's a total 512Byte + 64byte(orgnized as 36x128bits) SRAM . +// since each APB access is 32bits. So we use word address as APB read/write address. +// But for SPI side we have to use 128bit boundary. That's the first Pragram/read SPI with data buffer must start at data buffer 128bit boundary. that means the SPIFC_USE_DBUF_ADDR last 2 bits must be 0. +#define P_SPIFC_DBUF_CTRL ((volatile uint32_t *)0xfd000640) +//bit 31. 1 = write DBUF. 0 : read DBUF. +//bit 30. 1. = auto update address. 0 don't change address. +//bit 7:0 DBUF address unit 32bits. +#define P_SPIFC_DBUF_DATA ((volatile uint32_t *)0xfd000644) +//bit 31:0. if SPIFC_DBUF_CTRL bit 31 = 1. write to this register will trigger one write to DBUF. and the data will be writen to DBUF. +#define P_SPIFC_USER_DBUF_ADDR ((volatile uint32_t *)0xfd000648) +//bit 7:0. the DBUF ADDRESS used to send to or receive from SPI FLASH. the last 2 bits must be 0. +#define P_SPIFC_FLASH_STATUS ((volatile uint32_t *)0xfd000680) +#define P_SPIFC_STATUS ((volatile uint32_t *)0xfd000684) +//bit 1. AES KEY valid. read only 1 : The aes key is ready to use. 0: the aes key is not ready. +//bit 0. SPI CTRL STATE IDLE. read only. 1 = idle; 0 = busy. +#define P_SPIFC_CTRL ((volatile uint32_t *)0xfd000688) +//bit 15:14. mempd for DBUF MEMORY. +//bit 13 spifc asynchronous buffer clock disable. 1 = disable. 0 = enable. +//bit 12. spifc controller clock disable. 1 = disable. 0 = enable. +//bit 9. spifc asynchronous bufer clock auto gate enable. 1 = enable. 0 = disable. +//bit 8. spifc controller clock auto gate enable. 1 = enable. 0 = disable. +//bit 2. spifc interface reset. 1 = RESET. 0 = normal working mode. +//bit 1. spifc asynchronous buffer spi clock side reset. 1 = RESET. 0 : normal working mode. +//bit 0. spifc controller reset. 1 = RESET. 0 : normal working mode. +//`endif +// +// Closing file: ../spifc/rtl/spifc_reg.vh +// +// +// Reading file: ../psram/rtl/psram_reg.vh +// +//`ifdef PSRAM_REG_DEFINE +//`else +//`define PSRAM_REG_DEFINE +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe007400 +// ----------------------------------------------- +#define P_PSRAM_AXI_INTF_CTRL ((volatile uint32_t *)0xfe007400) +//bit 3 axi interface soft reset. 1 = reset AXI interface. 0 = normal. +//bit 2 disable axi interface clock. 1 = disable; 0 = enable. +//bit 1 axi interface auto clock gating enable. 1 = enable; 0 = disable. +//bit 0 axi interface AXI request enable. 1 = enable. 0 = disable. +#define P_PSRAM_DBUF_CTRL ((volatile uint32_t *)0xfe007404) +//bit 16. MWRITE_EN. 1 : enabel mask write(with DM pin). 0 not enable. +//bit 15:0 DBUF AGE to write back to PSRAM if DBUF is dirty. but whole DBUF data is not READ to write.(with MWRITE enabled). +#define P_PSRAM_DBUF_CTRL1 ((volatile uint32_t *)0xfe007408) +//bit 15:0 DBUF AGE to write back to psram if DBUF is dirty and whole DBUF data is ready to write. +#define P_PSRAM_APB_CTRL ((volatile uint32_t *)0xfe00740c) +//7:4 PSRAM PHY register APB secure contrl. +//bit 7, 1: no secure control. 0 : use bit 4 to match PPROT[0] bit. +//bit 4. when bit 7 == 0, bit 4 must match PPROT[0] to access. +//3:0 PCTL_CTRL APB bus control regsiters secure control. +//bit 3, 1: no secure control. 0 : use bit 0 to match PPROT[0] bit. +//bit 0. when bit 3 == 0, bit 0 must match PPROT[0] to access. +#define P_PSRAM_SEC_CTRL ((volatile uint32_t *)0xfe007410) +//bit 31. ADDRESS security range enable. 1 = enable; 0: disable. +//if scruity range disabled, but AXI data describle enabled key0 is selected. +//bit 23 range 7 des key selection 0 : key0; 1: key1; +//bit 22 range 6 des key selection 0 : key0; 1: key1; +//bit 21 range 5 des key selection 0 : key0; 1: key1; +//bit 20 range 4 des key selection 0 : key0; 1: key1; +//bit 19 range 3 des key selection 0 : key0; 1: key1; +//bit 18 range 2 des key selection 0 : key0; 1: key1; +//bit 17 range 1 des key selection 0 : key0; 1: key1; +//bit 16 range0 des key selection 0 : key0; 1: key1; +//bit 6. range6 enable: 1: enable; 0 : disable. +//bit 5. range5 enable: 1: enable; 0 : disable. +//bit 4. range4 enable: 1: enable; 0 : disable. +//bit 3. range3 enable: 1: enable; 0 : disable. +//bit 2. range2 enable: 1: enable; 0 : disable. +//bit 1. range1 enable: 1: enable; 0 : disable. +//bit 0. range0 enable: 1: enable; 0 : disable. +#define P_PSRAM_DES_PADDING ((volatile uint32_t *)0xfe007414) +//bit 31 :0 Padding, with address together to generate describle 64 bits input. +#define P_PSRAM_RANGE0_STA ((volatile uint32_t *)0xfe007440) +//bit 22 :0. +//AXI security range 0 start address in unit of 64Byte. related to HADDR bit 28:6. +#define P_PSRAM_RANGE0_EDA ((volatile uint32_t *)0xfe007444) +//bit 22 :0. +//AXI security range 0 end address in unit of 64Byte. related to HADDR bit 28:6. +#define P_PSRAM_RANGE0_CTRL0 ((volatile uint32_t *)0xfe007448) +// AXI secruity range 0 control. +#define P_PSRAM_RANGE0_CTRL1 ((volatile uint32_t *)0xfe00744c) +// AXI secruity range 0 control. +#define P_PSRAM_RANGE1_STA ((volatile uint32_t *)0xfe007450) +//bit 22 :0. +//AXI security range 1 start address in unit of 64Byte. related to HADDR bit 28:6. +#define P_PSRAM_RANGE1_EDA ((volatile uint32_t *)0xfe007454) +//bit 22 :0. +//AXI security range 1 end address in unit of 64Byte. related to HADDR bit 28:6. +#define P_PSRAM_RANGE1_CTRL0 ((volatile uint32_t *)0xfe007458) +// AXI secruity range 1 control. +#define P_PSRAM_RANGE1_CTRL1 ((volatile uint32_t *)0xfe00745c) +// AXI secruity range 1 control. +#define P_PSRAM_RANGE2_STA ((volatile uint32_t *)0xfe007460) +//bit 31 : 6. +//AXI security range 2 start address in unit of 64Byte. related to HADDR bit 28:6. +#define P_PSRAM_RANGE2_EDA ((volatile uint32_t *)0xfe007464) +//bit 31 :6. +//AXI security range 2 end address in unit of 64Byte. related to HADDR bit 28:6. +#define P_PSRAM_RANGE2_CTRL0 ((volatile uint32_t *)0xfe007468) +#define P_PSRAM_RANGE2_CTRL1 ((volatile uint32_t *)0xfe00746c) +#define P_PSRAM_RANGE3_STA ((volatile uint32_t *)0xfe007470) +//bit 31 : 6. +//AXI security range 3 start address in unit of 64Byte. related to HADDR bit 28:6. +#define P_PSRAM_RANGE3_EDA ((volatile uint32_t *)0xfe007474) +//bit 31 :6. +//AXI security range 3 end address in unit of 64Byte. related to HADDR bit 28:6. +#define P_PSRAM_RANGE3_CTRL0 ((volatile uint32_t *)0xfe007478) +// AXI secruity range 3 control. +#define P_PSRAM_RANGE3_CTRL1 ((volatile uint32_t *)0xfe00747c) +// AXI secruity range 3 control. +#define P_PSRAM_RANGE4_STA ((volatile uint32_t *)0xfe007480) +//bit 31 :6. +//AXI security range 4 start address in unit of 64Byte. related to HADDR bit 28:6. +#define P_PSRAM_RANGE4_EDA ((volatile uint32_t *)0xfe007484) +//bit 31 :6. +//AXI security range 4 end address in unit of 64Byte. related to HADDR bit 28:6. +#define P_PSRAM_RANGE4_CTRL0 ((volatile uint32_t *)0xfe007488) +// AXI secruity range 4 control. +#define P_PSRAM_RANGE4_CTRL1 ((volatile uint32_t *)0xfe00748c) +#define P_PSRAM_RANGE5_STA ((volatile uint32_t *)0xfe007490) +//bit 22 :0. +//AXI security range 5 start address in unit of 64Byte. related to HADDR bit 28:6. +#define P_PSRAM_RANGE5_EDA ((volatile uint32_t *)0xfe007494) +//bit 22 :0. +//AXI security range 5 end address in unit of 64Byte. related to HADDR bit 28:6. +#define P_PSRAM_RANGE5_CTRL0 ((volatile uint32_t *)0xfe007498) +// AXI secruity range 5 control. +#define P_PSRAM_RANGE5_CTRL1 ((volatile uint32_t *)0xfe00749c) +// AXI secruity range 5 control. +#define P_PSRAM_RANGE6_STA ((volatile uint32_t *)0xfe0074a0) +//bit 22 :0. +//AXI security range 6 start address in unit of 64Byte. related to HADDR bit 28:6. +#define P_PSRAM_RANGE6_EDA ((volatile uint32_t *)0xfe0074a4) +//bit 22 :0. +//AXI security range 6 end address in unit of 64Byte. related to HADDR bit 28:6. +#define P_PSRAM_RANGE6_CTRL0 ((volatile uint32_t *)0xfe0074a8) +// AXI secruity range 6 control. +#define P_PSRAM_RANGE6_CTRL1 ((volatile uint32_t *)0xfe0074ac) +// AXI secruity range 6 control. +#define P_PSRAM_RANGE7_CTRL0 ((volatile uint32_t *)0xfe0074b0) +#define P_PSRAM_RANGE7_CTRL1 ((volatile uint32_t *)0xfe0074b4) +#define P_PSRAM_VIO_STATUS ((volatile uint32_t *)0xfe0074b8) +//bit 31: security violation. write 1 to clean security violation status. +//bit 30. 1 : AXI write violation. 0 : axi read violation. +//bit 18:16. AXI ARPROT/AWPROT> +//bit 11:0. AXI violation ID. +#define P_PSRAM_VIO_ADDR ((volatile uint32_t *)0xfe0074bc) +//read only +//31:0 AXI violation address. +#define P_PSRAM_USER_CTRL0 ((volatile uint32_t *)0xfe007600) +//bit 31. user request enable. write 1 to enable. read 0, means user command accepted by the SPI_CTRL. +//bit 30. usr request done. after user command done. this bit set to 1. +//bit 29. USR COMMAND enable. +//bit 28. command type0. 1 READ command. 0 write command. +//bit 27. command type1. 1 for register. 0 : for memory. +//bit 21~16. USR command clock cycles +//bit 15~0. USR COMMAND CODE. +#define P_PSRAM_USER_CTRL1 ((volatile uint32_t *)0xfe007604) +//bit 31. USR_ADDR_EN +//bit 30:29. USR_ADDR_DW +//bit 28~20. USR address clock cycle number. +//bit 19:16 USR data output/input switch postion +//bit 15. USR DUMMY ENABLE +//bit 13~8. USR DUMMY clock cycles. +//bit 5:0 USR data DQS read enable postion. +#define P_PSRAM_USER_CTRL2 ((volatile uint32_t *)0xfe007608) +//bit 31 usr des key selection. 1 : key 1; 0 : key 0. +//bit 30. usr check latency. for Winbond PSRAM data read/write, DQS input indentify the latency is doubled or not. +//bit 29. usr data des enable. +//bit 28 usr datain enable. +//bit 27. usr datain destination. 1 : write to CFG_STS register. 0 : write to DATA REGISTERs. +//bit 26~16 usr data in clock cycle number. +//bit 15. usr datout enable. +//bit 14. usr data out source 1 : from CFG_STS register. 0 from DATA register. +//bit 13~11. not used. +//bit 10~0. usr dataout clock cycles. +#define P_PSRAM_USER_CTRL3 ((volatile uint32_t *)0xfe00760c) +//bit 17:16. which cycle to ask phy to check read/write latency at PSRAM SEND COMMOND stage. +//since PSRAM send command stage only 3 clock cycle. So this number only can chose 0, 1, 2. +//bit 15:0. user dummy data when output in dummy cycle. +#define P_PSRAM_USER_ADDR ((volatile uint32_t *)0xfe007610) +//bit 31:0. 32bits user address. +#define P_PSRAM_AXI_REQ_CTRL0 ((volatile uint32_t *)0xfe007614) +//bit 31. AXI request enable. +//bit 30 AXI cmd_en. command cycle enable. +//bit 29:24. AXI request command cycle clock numbers. +//bit 22. AXI request address cycle enable. +//bit 21:16. AXI request address cycle clock number. +//bit 15:14. AXI address cycle data width. +//bit 13:12. at which clock cycle to send signal to phy to check latency flag for WINBOND PSRAM flexible latency. +//since PSRAM send command stage only 3 clock cycle. So this number only can chose 0, 1, 2. +//bit 6 // AXI Write dummy enable. +//bit 5:0 // axi write dummy clock cycle number. +#define P_PSRAM_AXI_REQ_CTRL1 ((volatile uint32_t *)0xfe007618) +//bit 31:16. AXI request psram READ command code. +//bit 15:0. AXI request psram write command code. +#define P_PSRAM_AXI_REQ_CTRL2 ((volatile uint32_t *)0xfe00761c) +//bit 31. AXI read request Dummy enable. +//bit 30. Check latency enable for WINBOND PSRAM flexible latency. +//bit 27:22. clock cycles in dummy stage to eanble PSRAM PHY reading logic. +//bit 21:16. axi_read dummy clock cycles number. +//bit 15:0. dummy data if output in dummy cycles. +#define P_PSRAM_AXI_REQ_CTRL3 ((volatile uint32_t *)0xfe007620) +//bit 31 des enable. +//bit 26:16. DATA input clock cycles. +//bit 10:0. DATA output clock cycles. +#define P_PSRAM_ACTIMING0 ((volatile uint32_t *)0xfe007624) +//bit 31:30. tSLCH +//bit 29:28 tCLSH +//bit 20:16 tSHWL +//bit 15:12 tSHSL2 +//bit 11:8 tSHSL1 +//bit 7:0 tWHSL +#define P_PSRAM_ACTIMING1 ((volatile uint32_t *)0xfe007628) +//bit 7:0 tRWR for winbond PSRAM, = tRWR -3. Winbond PSRAM include one CS cycle and 2 command cycle. +//for APMEMORY should be same value of tCPH +#define P_PSRAM_ACTIMING2 ((volatile uint32_t *)0xfe00762c) +#define P_PSRAM_WDG_CTRL ((volatile uint32_t *)0xfe007630) +//bit [31] 1: force to reset PSRAM PCTL and PHY logic. 0: normal. +//bit [30] 1: automatic reset PSRAM PCTL and PHY logic if watch dog triggered. +//bit 12:0. watch dog timer. for Winbond PSRAM should be 1us for tRC. for APMEMORY should be 1us for tCEM. +//SPI DATA BUFFER. There's a total 512KByte + 64byte(orgnized as 36x128bits) SRAM . +// since each APB access is 32bits. So we use word address as APB read/write address. +// But for SPI side we have to use 128bit boundary. That's the first Pragram/read SPI with data buffer must start at data buffer 128bit boundary. that means the PSRAM_USE_DBUF_ADDR last 2 bits must be 0. +#define P_PSRAM_DBUF_0 ((volatile uint32_t *)0xfe007640) +#define P_PSRAM_DBUF_1 ((volatile uint32_t *)0xfe007644) +#define P_PSRAM_DBUF_2 ((volatile uint32_t *)0xfe007648) +#define P_PSRAM_DBUF_3 ((volatile uint32_t *)0xfe00764c) +#define P_PSRAM_DBUF_4 ((volatile uint32_t *)0xfe007650) +#define P_PSRAM_DBUF_5 ((volatile uint32_t *)0xfe007654) +#define P_PSRAM_DBUF_6 ((volatile uint32_t *)0xfe007658) +#define P_PSRAM_DBUF_7 ((volatile uint32_t *)0xfe00765c) +#define P_PSRAM_DBUF_8 ((volatile uint32_t *)0xfe007660) +#define P_PSRAM_DBUF_9 ((volatile uint32_t *)0xfe007664) +#define P_PSRAM_DBUF_A ((volatile uint32_t *)0xfe007668) +#define P_PSRAM_DBUF_B ((volatile uint32_t *)0xfe00766c) +#define P_PSRAM_DBUF_C ((volatile uint32_t *)0xfe007670) +#define P_PSRAM_DBUF_D ((volatile uint32_t *)0xfe007674) +#define P_PSRAM_DBUF_E ((volatile uint32_t *)0xfe007678) +#define P_PSRAM_DBUF_F ((volatile uint32_t *)0xfe00767c) +#define P_PSRAM_CFG_STS ((volatile uint32_t *)0xfe007680) +//32bits register to save the USR read command read back values. +#define P_PSRAM_STATUS ((volatile uint32_t *)0xfe007684) +//bit 31. usr_req_done flag. 1 : user request done . write 1 to clean. +//bit 30~11. +//bit 10:8 +//bit 7:3. +//bit 2. axi_data buffer idle bit. 1 : idle. 0 : working. +//bit 1. axi interface idle bit. 1 : idle. 0 : working. +//bit 0. psram ctrl idle bit. 1 : idle. 0 : working. +#define P_PSRAM_CTRL ((volatile uint32_t *)0xfe007688) +//bit 31. PSRAM in DTR mode. +//bit 30. psram input data latch clock select. 1: from clock input pin. 0: from DQS +//if use clock input pin as data input latch clock, bit 13:12 should select 01. +//bit 29:27. PSRAM mode. +//'b000 : STR SPI mode. +//'b001 : STR QPI mode. +//'b010 : DTR QPI mode. +//'b011 : DTR OPI FLASH. +//'b100 : APmemory PSRAM mode. +//'b101 : Winbond PSRAM mode. +//bit 26. enable to generation interruption after usr request done. 1: enable. 0: disable. +//bit 25. to enable APMEMORY 2 command cycle mode. 1 : enable : 0: 3 command cycles. +//bit 24. to enable the psram clock output always enable. 1 : enable. 0: disable. +//bit 23. to enable the psram clock output extend mode to cover APMEMORY tCPI. +//bit 22. to disable the CKN output. 1: disable PSRAM CK_N pin output. 0: CK_N working normal. +//bit 21. PSRAM DATA IN/OUT high 8bit and low 8 bit endian. 1 : rising edge is low byte. falling edge data is high byte. 0 : rising edge is high byte. falling edge data is low byte. +//bit 20. PSRAM ADDRESS unit. 1: Byte. 0 : word. +// APMEMORY used byte address. Winbond use word address. +//bit 19. DQSEN generation. if use dqs to latch input data, this bit should be set to 1 to ask DMC generate ENABLE singal in dummy stage. 0: not generate DQS_EN. +//bit 18. PSRAM RESET I/O oe_n value. if need RESET pin. +//bit 17. PSRAM RESET I/O output vale. if need reset pin. +//bit 16. force CS output low. for APMEMORY exit DPPD mode. 1: to force cs output low : 0 output normal working mode. +//bit 13:12. psram data in clock enable selection. 00: use DQSEN. 01: use clkin cnt. +//bit 11. DM Disable. 1: disable DM output. 0: with dmoutput. +//bit 9. psram pctl auto clock gating enable. 1: enable. 0 : disable. +//bit 8. psram pctl clock disable. 1: disable. 0 : enable. +//bit 2 PSRAM SPI mode, DQ2 works as WP(write protection mode). +//bit 1. DQ2 WP mode value. +//bit 0. PSRAM SPI mode, DQ3 works as HOLD function. +#define P_PSRAM_PIN_CTRL ((volatile uint32_t *)0xfe00768c) +//bit 30:28 DATA 6 DQ pin selection. +//bit 27:24 DATA 6 DQ pin selection. +//bit 22:20 DATA 5 DQ pin selection. +//bit 18:16 DATA 4 DQ pin selection. +//bit 14:12 DATA 3 DQ pin selection. +//bit 10:8 DATA 2 DQ pin selection. +//bit 6:4 DATA 1 DQ pin selection. +//bit 2:0 DATA 0 DQ pin selection. +//0 : from DQ[0] +//1 : from DQ[1] +//2 : from DQ[2] +//3 : from DQ[3] +//4 : from DQ[4] +//5 : from DQ[5] +//6 : from DQ[6] +//7 : from DQ[7] +//psram_dly_16 is used for all DQ[0~] in/out/oen delay adjustment. +//psram_dly_16 consists of 15 delay cells, one delay cell is 50ps delay( typical corner). +//psram_dly_16 is control by delay_sel[3:0]. 0 = no delay. 1~15 controls how many delay cells used. +//psram_dly_16 can be controlled by each control register either with real delay mode or VT updated with 4xclock period. +//psram_lcdl is used for DQS/DQSN input and CK/CKN output delay 90degree delay generation and/or delay fine tune. +//psram_lcdl consits of 96 delay cells, same delay cell used in psram_dly_16. +//psram_lcdl should be calibrated with the psram_4xclock. and tracked with psram_4xclock with VT updated. +#define P_PSRAM_DQ0_DIN_DLY ((volatile uint32_t *)0xfe007700) +//bit 6:0. DQ0 DIN delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_DQ1_DIN_DLY ((volatile uint32_t *)0xfe007704) +//bit 6:0. DQ1 input delay control. in DLY16 read mode, only [3:0] is valid. +#define P_PSRAM_DQ2_DIN_DLY ((volatile uint32_t *)0xfe007708) +//bit 6:0. DQ2 input delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_DQ3_DIN_DLY ((volatile uint32_t *)0xfe00770c) +//bit 6:0. DQ3 input delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_DQ4_DIN_DLY ((volatile uint32_t *)0xfe007710) +//bit 6:0. DQ4 input delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_DQ5_DIN_DLY ((volatile uint32_t *)0xfe007714) +//bit 6:0. DQ5 input delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_DQ6_DIN_DLY ((volatile uint32_t *)0xfe007718) +//bit 6:0. DQ6 input delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_DQ7_DIN_DLY ((volatile uint32_t *)0xfe00771c) +//bit 6:0. DQ7 input delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_DQ0_DOUT_DLY ((volatile uint32_t *)0xfe007720) +//bit 6:0. DQ0 DOUT delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_DQ1_DOUT_DLY ((volatile uint32_t *)0xfe007724) +//bit 6:0. DQ1 output delay control. in DLY16 read mode, only [3:0] is valid. +#define P_PSRAM_DQ2_DOUT_DLY ((volatile uint32_t *)0xfe007728) +//bit 6:0. DQ2 output delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_DQ3_DOUT_DLY ((volatile uint32_t *)0xfe00772c) +//bit 6:0. DQ3 output delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_DQ4_DOUT_DLY ((volatile uint32_t *)0xfe007730) +//bit 6:0. DQ4 output delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_DQ5_DOUT_DLY ((volatile uint32_t *)0xfe007734) +//bit 6:0. DQ5 output delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_DQ6_DOUT_DLY ((volatile uint32_t *)0xfe007738) +//bit 6:0. DQ6 output delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_DQ7_DOUT_DLY ((volatile uint32_t *)0xfe00773c) +//bit 6:0. DQ7 output delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_DQ0_OEN_DLY ((volatile uint32_t *)0xfe007740) +//bit 6:0. DQ0 OEN delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_DQ1_OEN_DLY ((volatile uint32_t *)0xfe007744) +//bit 6:0. DQ1 output enable delay control. in DLY16 read mode, only [3:0] is valid. +#define P_PSRAM_DQ2_OEN_DLY ((volatile uint32_t *)0xfe007748) +//bit 6:0. DQ2 output enable delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_DQ3_OEN_DLY ((volatile uint32_t *)0xfe00774c) +//bit 6:0. DQ3 output enable delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_DQ4_OEN_DLY ((volatile uint32_t *)0xfe007750) +//bit 6:0. DQ4 output enable delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_DQ5_OEN_DLY ((volatile uint32_t *)0xfe007754) +//bit 6:0. DQ5 output enable delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_DQ6_OEN_DLY ((volatile uint32_t *)0xfe007758) +//bit 6:0. DQ6 output enable delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_DQ7_OEN_DLY ((volatile uint32_t *)0xfe00775c) +//bit 6:0. DQ7 output enable delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_DM_DOUT_DLY ((volatile uint32_t *)0xfe007760) +//bit 6:0. DM output delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_DM_OEN_DLY ((volatile uint32_t *)0xfe007764) +//bit 6:0. DM output enable delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_CS_DOUT_DLY ((volatile uint32_t *)0xfe007768) +//bit 6:0. CS output delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_DQS_DIN_DLY ((volatile uint32_t *)0xfe00776c) +//bit 6:0. DQS input delay control. unit = 1/64 UI with PSRAM_LCDL_CTRL bit 28 = 0; +// unit = 1 delay cell, with PSRAM_LCDL_CTRL bit 28 = 1; +#define P_PSRAM_DQSN_DIN_DLY ((volatile uint32_t *)0xfe007770) +//bit 6:0. DQSN input delay control. unit = 1/64 UI with PSRAM_LCDL_CTRL bit 28 = 0; +// unit = 1 delay cell, with PSRAM_LCDL_CTRL bit 28 = 1; +#define P_PSRAM_CKN_DOUT_DLY ((volatile uint32_t *)0xfe007774) +//bit 6:0. CKN output delay control. unit = 1/64 UI with PSRAM_LCDL_CTRL bit 28 = 0; +// unit = 1 delay cell, with PSRAM_LCDL_CTRL bit 28 = 1; +#define P_PSRAM_CK_DOUT_DLY ((volatile uint32_t *)0xfe007778) +//bit 6:0. CK output delay control. unit = 1/64 UI with PSRAM_LCDL_CTRL bit 28 = 0; +// unit = 1 delay cell, with PSRAM_LCDL_CTRL bit 28 = 1; +#define P_PSRAM_RDEN_DLY ((volatile uint32_t *)0xfe00777c) +//bit 10:7. READ enable phase delay. unit = 1UI. for AP QPI PSRAM. PSRAM only send one cycle DQS preamble. +// We have to used this UI delay to compensate the whole clock output delay and the DQS input delay. +// if run high frequency, this delay need to be trained. the valid value from 0 ~ 12. Since one UI is 1/4 of PSRAM clock, +// the total delay of the clock output delay + input delay should be less than 3 PSRAM clock. +//bit 6:0. READ enable fine tune delay control. unit = 1/64 UI with PSRAM_LCDL_CTRL bit 28 = 0; +// unit = 1 delay cell, with PSRAM_LCDL_CTRL bit 28 = 1; +#define P_PSRAM_LCDL_CTRL ((volatile uint32_t *)0xfe0077c0) +//bit 31. write 1 to update all delay cell delays control. +//bit 30. write 1 to calibration LCDL. +//bit 29. LCDL track enable. 1: enable LCDL auto track VT changes. +//bit 28. LCDL delay control mode. +//1 : real delay mode. For DQS/DQSN/CKN/CK/RDEN delay control register, one number means one delay cells. +//0 : UI MODE. For DQS/DQSN/CKN/CK/RDEN delay control register, one number means 1/64 psram_4xclk period. +//bit 27. DLY16 ( psram_dly_16 cell) delay control mode. +//1 : real delay mode. For all data delay control register, one number means one delay cells. +//0 : UI MODE. For all data delay control register, one number means 1/64 psram_4xclk period. +//bit 27:24. not used. +//bit 23:0. timer do trigger LCDL track the VT once. each track will compensate the UI with 1/16 delay cell delay. +//LCDL calibration ctroller. +#define P_PSRAM_LCDL_CAL_CTRL1 ((volatile uint32_t *)0xfe0077c4) +//27:24. which LCDL delay line used to run calibration. +//19:16. LCDL calibration loop end position. +//15:12. LCDL calibration loop initial position. +//10:0. LCDL calibration initial phase counter. +#define P_PSRAM_LCDL_CAL_CTRL2 ((volatile uint32_t *)0xfe0077c8) +//26:16 LCDL phase lock limit. if the lcdl phase counter difference between 2 calibration loops is less than this number, The LCDL would be locked and stop the calibration. +//10:0. deta_init. the first loop phase changing number. +#define P_PSRAM_LCDL_CAL_CTRL3 ((volatile uint32_t *)0xfe0077cc) +//29:25 to configure LCDL calibration step 5 position. +//24:20 to configure LCDL calibration step 4 position. +//19:15 to configure LCDL calibration step 3 position. +//14:10 to configure LCDL calibration step 2 position. +//9:5 to configure LCDL calibration step 1 position. +//4:0 to configure LCDL calibration step 0 position. +#define P_PSRAM_LCDL_CAL_CTRL4 ((volatile uint32_t *)0xfe0077d0) +//19:15 to configure LCDL calibration step 9 position. +//14:10 to configure LCDL calibration step 8 position. +//9:5 to configure LCDL calibration step 7 position. +//4:0 to configure LCDL calibration step 6 position. +#define P_PSRAM_CLK_UI ((volatile uint32_t *)0xfe0077d4) +//bit 6:0. 4xCLOCK period delay measured from LCDL calibration. +#define P_PSRAM_LCDL_PH ((volatile uint32_t *)0xfe0077d8) +//10:0 LCDL phase counter after calibration. +#define P_PSRAM_LCDL_STATUS ((volatile uint32_t *)0xfe0077dc) +//bit 31. LCDL lock status. 1: LCDL locked to 4x clock. +//`endif +// +// Closing file: ../psram/rtl/psram_reg.vh +// +// +// Reading file: ../mmc_lp4/dmc/rtl/dmc_sec.vh +// +//`ifdef DMC_SEC_REG_DEFINE +//`else +//`define DMC_SEC_REG_DEFINE +// ----------------------------------------------- +// APB_BASE: APB1_BASE_ADDR = 0xfd021000 +// ----------------------------------------------- +//`define DMC_SEC_REG_BASE 32'hfd021000 +// ID assignment inside DMC.. +// id[12 :0] total 13 bit ID. +// id[12] == 1: for DMC internal TEST module. +// id[12] == 0: for AXI port input. +// id[11:0] == AXI port ID. +// id[2:0] == 0 : A55 CPU. +// id[2:0] == 1 : DSPA +// id[2:0] == 2 : DSPB +// id[2:0] == 3 : Not used. +// id[2:0] == 4 : for Device. +//Device sublevel ID. +//id[9:7] == 5 : for audio. id[3] == 0: audio +//id[9:7] == 6 : for DMA. id[6:4] for DMA thread id. id[3] for DMC security level. +//id[9:7] == others: for device other masters. +// id[2:0] == 5 : for USB device. +// id[2:0] == 6 : for I2C debug input. +// id[2:0] == 7 : for USB host. +#define P_DMC_SEC_RANGE0_STA ((volatile uint32_t *)0xfd021000) +//bit 31:12. range0 start address. in 4KB boundary. +#define P_DMC_SEC_RANGE0_EDA ((volatile uint32_t *)0xfd021004) +//bit 31:12. range0 end address. in 4KB boundary. +#define P_DMC_SEC_RANGE0_RID_CTRL ((volatile uint32_t *)0xfd021008) +//range 0 read access enable based on DMC ID assignments. +//bit 28. for AXI port 3. Not used in A1. should be 0. +//bit 27. for dmc_test. 1 = enable. 0 = disable. +//bit 26. for usbhost. 1 = enable. 0 = disable. +//bit 25. for i2c. 1 = enable. 0 = disable. +//bit 24. for usbdevide. 1 = enable. 0 = disable. +//bit 23. for AXI device sublevel id 7. 1 = enable. 0 = disable. +//bit 22:18.for AXI device sub level id 5 ~ 0. +//bit 17:10.for AXI device DMA thread 7 ~ thread 0.( in A1, DMA only has thread 3 to thread 0). +//bit 9:6. for AXI device audio read subid 3~0. (in A1, audio read only has subid 1 and subid 0). +//bit 5:4. for AXI DSPB. bit 5 for security access. bit 4 for non secure access. +//bit 3:2. for AXI DSPA. bit 3 for security access. bit 2 for non secure access. +//bit 1:0. for AXI A55 CPU. bit 1 for security access. bit 0 for non secure access. +#define P_DMC_SEC_RANGE0_WID_CTRL ((volatile uint32_t *)0xfd02100c) +//range 0 write access enable based on DMC ID assignments. +//bit 28. for AXI port 3. Not used in A1. should be 0. +//bit 27. for dmc_test. 1 = enable. 0 = disable. +//bit 26. for usbhost. 1 = enable. 0 = disable. +//bit 25. for i2c. 1 = enable. 0 = disable. +//bit 24. for usbdevide. 1 = enable. 0 = disable. +//bit 23. for AXI device sublevel id 7. 1 = enable. 0 = disable. +//bit 22:18.for AXI device sub level id 5 ~ 0. +//bit 17:10.for AXI device DMA thread 7 ~ thread 0.( in A1, DMA only 4 threads from thread 3 to thread 0). +//bit 9:6. for AXI device audio write subid 7~4. (in A1, audio write only 2 masters usey subid 4 and subid 5). +//bit 5:4. for AXI DSPB. bit 5 for security access. bit 4 for non secure access. +//bit 3:2. for AXI DSPA. bit 3 for security access. bit 2 for non secure access. +//bit 1:0. for AXI A55 CPU. bit 1 for security access. bit 0 for non secure access. +#define P_DMC_SEC_RANGE1_STA ((volatile uint32_t *)0xfd021010) +//bit 31:12. range1 start address. in 4KB boundary. +#define P_DMC_SEC_RANGE1_EDA ((volatile uint32_t *)0xfd021014) +//bit 31:12. range0 end address. in 4KB boundary. +#define P_DMC_SEC_RANGE1_RID_CTRL ((volatile uint32_t *)0xfd021018) +//range 1 read access enable based on DMC ID assignments. +//bit 28. for AXI port 3. Not used in A1. should be 0. +//bit 27. for dmc_test. 1 = enable. 0 = disable. +//bit 26. for usbhost. 1 = enable. 0 = disable. +//bit 25. for i2c. 1 = enable. 0 = disable. +//bit 24. for usbdevide. 1 = enable. 0 = disable. +//bit 23. for AXI device sublevel id 7. 1 = enable. 0 = disable. +//bit 22:18.for AXI device sub level id 5 ~ 0. +//bit 17:10.for AXI device DMA thread 7 ~ thread 0.( in A1, DMA only has thread 3 to thread 0). +//bit 9:6. for AXI device audio read subid 3~0. (in A1, audio read only has subid 1 and subid 0). +//bit 5:4. for AXI DSPB. bit 5 for security access. bit 4 for non secure access. +//bit 3:2. for AXI DSPA. bit 3 for security access. bit 2 for non secure access. +//bit 1:0. for AXI A55 CPU. bit 1 for security access. bit 0 for non secure access. +#define P_DMC_SEC_RANGE1_WID_CTRL ((volatile uint32_t *)0xfd02101c) +//range 1 write access enable based on DMC ID assignments. +//bit 28. for AXI port 3. Not used in A1. should be 0. +//bit 27. for dmc_test. 1 = enable. 0 = disable. +//bit 26. for usbhost. 1 = enable. 0 = disable. +//bit 25. for i2c. 1 = enable. 0 = disable. +//bit 24. for usbdevide. 1 = enable. 0 = disable. +//bit 23. for AXI device sublevel id 7. 1 = enable. 0 = disable. +//bit 22:18.for AXI device sub level id 5 ~ 0. +//bit 17:10.for AXI device DMA thread 7 ~ thread 0.( in A1, DMA only 4 threads from thread 3 to thread 0). +//bit 9:6. for AXI device audio write subid 7~4. (in A1, audio write only 2 masters usey subid 4 and subid 5). +//bit 5:4. for AXI DSPB. bit 5 for security access. bit 4 for non secure access. +//bit 3:2. for AXI DSPA. bit 3 for security access. bit 2 for non secure access. +//bit 1:0. for AXI A55 CPU. bit 1 for security access. bit 0 for non secure access. +#define P_DMC_SEC_RANGE2_STA ((volatile uint32_t *)0xfd021020) +//bit 31:12. range2 start address. in 4KB boundary. +#define P_DMC_SEC_RANGE2_EDA ((volatile uint32_t *)0xfd021024) +//bit 31:12. range2 end address. in 4KB boundary. +#define P_DMC_SEC_RANGE2_RID_CTRL ((volatile uint32_t *)0xfd021028) +//range 2 read access enable based on DMC ID assignments. +//bit 28. for AXI port 3. Not used in A1. should be 0. +//bit 27. for dmc_test. 1 = enable. 0 = disable. +//bit 26. for usbhost. 1 = enable. 0 = disable. +//bit 25. for i2c. 1 = enable. 0 = disable. +//bit 24. for usbdevide. 1 = enable. 0 = disable. +//bit 23. for AXI device sublevel id 7. 1 = enable. 0 = disable. +//bit 22:18.for AXI device sub level id 5 ~ 0. +//bit 17:10.for AXI device DMA thread 7 ~ thread 0.( in A1, DMA only has thread 3 to thread 0). +//bit 9:6. for AXI device audio read subid 3~0. (in A1, audio read only has subid 1 and subid 0). +//bit 5:4. for AXI DSPB. bit 5 for security access. bit 4 for non secure access. +//bit 3:2. for AXI DSPA. bit 3 for security access. bit 2 for non secure access. +//bit 1:0. for AXI A55 CPU. bit 1 for security access. bit 0 for non secure access. +#define P_DMC_SEC_RANGE2_WID_CTRL ((volatile uint32_t *)0xfd02102c) +//range 2 write access enable based on DMC ID assignments. +//bit 28. for AXI port 3. Not used in A1. should be 0. +//bit 27. for dmc_test. 1 = enable. 0 = disable. +//bit 26. for usbhost. 1 = enable. 0 = disable. +//bit 25. for i2c. 1 = enable. 0 = disable. +//bit 24. for usbdevide. 1 = enable. 0 = disable. +//bit 23. for AXI device sublevel id 7. 1 = enable. 0 = disable. +//bit 22:18.for AXI device sub level id 5 ~ 0. +//bit 17:10.for AXI device DMA thread 7 ~ thread 0.( in A1, DMA only 4 threads from thread 3 to thread 0). +//bit 9:6. for AXI device audio write subid 7~4. (in A1, audio write only 2 masters usey subid 4 and subid 5). +//bit 5:4. for AXI DSPB. bit 5 for security access. bit 4 for non secure access. +//bit 3:2. for AXI DSPA. bit 3 for security access. bit 2 for non secure access. +//bit 1:0. for AXI A55 CPU. bit 1 for security access. bit 0 for non secure access. +#define P_DMC_SEC_RANGE3_STA ((volatile uint32_t *)0xfd021030) +//bit 31:12. range3 start address. in 4KB boundary. +#define P_DMC_SEC_RANGE3_EDA ((volatile uint32_t *)0xfd021034) +//bit 31:12. range3 end address. in 4KB boundary. +#define P_DMC_SEC_RANGE3_RID_CTRL ((volatile uint32_t *)0xfd021038) +//range 3 read access enable based on DMC ID assignments. +//check DMC_SEC_RANGE0_RID_CTRL for each bit define. +#define P_DMC_SEC_RANGE3_WID_CTRL ((volatile uint32_t *)0xfd02103c) +//range 3 write access enable based on DMC ID assignments. +//check DMC_SEC_RANGE0_WID_CTRL for each bit define. +#define P_DMC_SEC_RANGE4_STA ((volatile uint32_t *)0xfd021040) +//bit 31:12. range4 start address. in 4KB boundary. +#define P_DMC_SEC_RANGE4_EDA ((volatile uint32_t *)0xfd021044) +//bit 31:12. range4 end address. in 4KB boundary. +#define P_DMC_SEC_RANGE4_RID_CTRL ((volatile uint32_t *)0xfd021048) +//range 4 read access enable based on DMC ID assignments. +//check DMC_SEC_RANGE0_RID_CTRL for each bit define. +#define P_DMC_SEC_RANGE4_WID_CTRL ((volatile uint32_t *)0xfd02104c) +//range 4 write access enable based on DMC ID assignments. +//check DMC_SEC_RANGE0_WID_CTRL for each bit define. +#define P_DMC_SEC_RANGE5_STA ((volatile uint32_t *)0xfd021050) +//bit 31:12. range5 start address. in 4KB boundary. +#define P_DMC_SEC_RANGE5_EDA ((volatile uint32_t *)0xfd021054) +//bit 31:12. range5 end address. in 4KB boundary. +#define P_DMC_SEC_RANGE5_RID_CTRL ((volatile uint32_t *)0xfd021058) +//range 5 read access enable based on DMC ID assignments. +//check DMC_SEC_RANGE0_RID_CTRL for each bit define. +#define P_DMC_SEC_RANGE5_WID_CTRL ((volatile uint32_t *)0xfd02105c) +//range 5 write access enable based on DMC ID assignments. +//check DMC_SEC_RANGE0_WID_CTRL for each bit define. +#define P_DMC_SEC_RANGE6_STA ((volatile uint32_t *)0xfd021060) +//bit 31:12. range5 start address. in 4KB boundary. +#define P_DMC_SEC_RANGE6_EDA ((volatile uint32_t *)0xfd021064) +//bit 31:12. range6 end address. in 4KB boundary. +#define P_DMC_SEC_RANGE6_RID_CTRL ((volatile uint32_t *)0xfd021068) +//range 6 read access enable based on DMC ID assignments. +//check DMC_SEC_RANGE0_RID_CTRL for each bit define. +#define P_DMC_SEC_RANGE6_WID_CTRL ((volatile uint32_t *)0xfd02106c) +//range 6 write access enable based on DMC ID assignments. +//check DMC_SEC_RANGE0_WID_CTRL for each bit define. +//range 7 is default range if the access not hit any of the previous 7 range, if would hit range 7. +#define P_DMC_SEC_RANGE7_RID_CTRL ((volatile uint32_t *)0xfd021070) +//range 7 read access enable based on DMC ID assignments. +//check DMC_SEC_RANGE0_RID_CTRL for each bit define. +#define P_DMC_SEC_RANGE7_WID_CTRL ((volatile uint32_t *)0xfd021074) +//range 7 write access enable based on DMC ID assignments. +//check DMC_SEC_RANGE0_WID_CTRL for each bit define. +#define P_DMC_SEC_RANGE_CTRL ((volatile uint32_t *)0xfd021078) +//bit 23:16 8 range security level. to chosse with DES KEY to use data describle. +//bit 7:0 8 range enable. each bit for one range to indentify the range is enabled or not. +//registers to check the security protection and watch point error information. +#define P_DMC_DES_CTRL ((volatile uint32_t *)0xfd021080) +//bit 1 data describle enable. +//bit 0 wirte 1 to block DES CTRL and DES PADDING read/write. +#define P_DMC_DES_PADDING ((volatile uint32_t *)0xfd021084) +#define P_DMC_SEC_STATUS ((volatile uint32_t *)0xfd0212e0) +//bit 31~2. not used. +//bit 1 write security violation. +//bit 0. read security violation. +#define P_DMC_VIO_ADDR0 ((volatile uint32_t *)0xfd0212e4) +//ddr0 write secure violation address. +#define P_DMC_VIO_ADDR1 ((volatile uint32_t *)0xfd0212e8) +//bit 31:18 . not used. always 0. +//17 ddr0 secure check violation. +//16 ddr0 write address overflow. write out of DDR size. +//15:13. ddr0 write violation AWPROT bits. +//12:0 ddr0_write violation ID. Please check ID assignment for ID bit defines. +#define P_DMC_VIO_ADDR2 ((volatile uint32_t *)0xfd0212ec) +//ddr0 write secure violation address. +#define P_DMC_VIO_ADDR3 ((volatile uint32_t *)0xfd0212f0) +//bit 31:18 . not used. always 0. +//17 ddr0 secure check violation. +//16 ddr0 read address overflow. write out of DDR size. +//15:13. ddr0 read violation AWPROT bits. +//12:0 ddr0_read violation ID. please ID assignment for ID bit defines. +//DDR0_ADDRMAP is used for RANK0 bank, row, col address mapping from AXI 32bits linear address. +#define P_DDR0_ADDRMAP_0 ((volatile uint32_t *)0xfd021340) +//29:25 ca8. +//24:20 ca7. +//19:15 ca6. +//14:10 ca5. +//9:5 ca4. +//4:0 ca3. +#define P_DDR0_ADDRMAP_1 ((volatile uint32_t *)0xfd021344) +//29:25 ra2. +//24:20 ra1. +//19:15 ra0. +//14:10 ca11. +//9:5 ca10. +//4:0 ca9. +#define P_DDR0_ADDRMAP_2 ((volatile uint32_t *)0xfd021348) +//29:25 ra8. +//24:20 ra7. +//19:15 ra6. +//14:10 ra5. +//9:5 ra4. +//4:0 ra3. +#define P_DDR0_ADDRMAP_3 ((volatile uint32_t *)0xfd02134c) +//29:25 ra14. +//24:20 ra13. +//19:15 ra12. +//14:10 ra11. +//9:5 ra10. +//4:0 ra9. +#define P_DDR0_ADDRMAP_4 ((volatile uint32_t *)0xfd021350) +//29:25 ra16 for DDR4 SDRAM +//24:20 bg1 for DDR4 SDRAM. +//19:15 ba2. or bg0 for DDR4. +//14:10 ba1. +//9:5 ba0. +//4:0 ra15. +#define P_DMC_DDR_CTRL ((volatile uint32_t *)0xfd021368) +// DDR PHY and DMC only supports 16bits and rank0 only. +//bit 24:22 3'b000 : ddr3 mode. +//3'b001 : ddr4 mode. +//3'b010 : lpddr3 mode. +//3'b011 : lpddr4 mode. +//bit 20 DDR4 BG1 enable bit. +//bit 3:0 : DDR rank 0 size bit [2:0]. +//4'b0000 : DDR rank 0 is 128Mbyte. +//4'b0001 : DDR rank 0 is 256Mbyte. +//4'b0010 : DDR rank 0 is 512Mbyte. +//4'b0011 : DDR rank 0 is 1Gbyte. +//4'b0100 : DDR rank 0 is 2Gbyte. +//4'b0101 : DDR rank 0 is 4Gbyte. +//4'b1000 : DDR rank 0 is 4Gbyte. +//4'b1001 : DDR rank 0 is 4Gbyte. +//others : reserved. +#define P_DMC_APB_SEC_CTRL ((volatile uint32_t *)0xfd02136c) +//bit 19:16. DMC normal APB register secure control. +//bit 19: 1: all can write those register. 0: the APB_PROT[0] must match the bit 16 to access those regsiter. +//Bit15:12. DMC sticky APB regsiter secure control. +//bit 15. 1: All APB bus can write those registers. 0: The APB_PROT[0] must match the bit 12 to access those register. +//bit 11:8. not used. +//Bit 7:4. DMC DDR SDRAM protocal contorl register contorl +//bit 11. 1: All APB bus can write those registers. 0: The APB_PROT[0] must match the bit 4 to access those register. +//bit 3:0. PHY APB regsiter secure control. +//bit 3. 1: All APB bus can write those registers. 0: The APB_PROT[0] must match the bit 0 to access those register. +#define P_DMC_DDR_PHY_CTRL ((volatile uint32_t *)0xfd0212fc) +//bit 4 PwrOkIn +//bit 3. PHY APB soft reset_n +//bit 2. PHY soft reset_n +//bit 1. PHY DfiClk enable. +//bit 0. PHY DfiCtlClk enable. +// ----------------------------------------------- +// APB_BASE: APB1_BASE_ADDR = 0xfd021400 +// ----------------------------------------------- +//`define DMC_TEST_REG_BASE 32'hfd021400 +#define P_DMC_TEST_WRCMD_ADDR ((volatile uint32_t *)0xfd021770) +// the current write cmd address. +#define P_DMC_TEST_RDRSP_ADDR ((volatile uint32_t *)0xfd021774) +// the failed read response address(for error data ) +#define P_DMC_TEST_RDCMD_ADDR ((volatile uint32_t *)0xfd021778) +// the current read command address. +#define P_DMC_TEST_WDG ((volatile uint32_t *)0xfd02177c) +//31:16. write response watch dog. +//15:0. read response watch dog. +#define P_DMC_TEST_STA ((volatile uint32_t *)0xfd021780) +//test start address. for non-sha mode, the last 5 bits would be ignored. the test address at 32bytes boundary. +// for sha mode, address must be in 64 bytes boundary. that mean the last 6 bits must be 0. +#define P_DMC_TEST_EDA ((volatile uint32_t *)0xfd021784) +//test end address. for non-sha mode, the last 5 bits would be ignored. the test address at 32bytes boundary. +// for sha mode, address must be in 64 bytes boundary. that mean the last 6bits must be 1. +#define P_DMC_TEST_CTRL ((volatile uint32_t *)0xfd021788) +//bit 31. enable test. +//bit 30. when enable test, enable the write to DDR function. +//bit 29. when enable test, enable the read from DDR function. +//bit 28. Not used. +//bit 27. enabe to compare data. when do the read enable to enable the error comparaion. suppose the read data should be same as the data in the write buffer. +//bit 26. Not used. +//bit 25. address generation type. 0: continuous increase the address in the range of test start address and test end address. +// 1: test module would pick the random address from test start address and test end address. +//bit 24. done type. 0 : use the DMC_TEST_NUM register as the counter of test numbers. +// for write if the write command number == the DMC_TEST_NUM, the write is done. +// for read if the read command number == the DMC TEST_num, the read id done. for one read command can be repeated repeat number times. +// 1 : finshed at end address. +//bit 23. wdata type. 1 : the first write is {WD3, WD2,WD1,WD0}, then the latter is the previous data plus a pattern.( { + WD7, + WD6, + WD5, + WD4}). +// 0 : the WDATA is the data in write register. +//bit 23. Not used. +//bit 22:20. read repeat times. for non-sha function, we can define multi times of the read. the test module would repeat the same adddress repeat times. +//bit 19. limit write. 0: no outstanding write request limitation. +// 1: limit the outstanding write commands to the number of bits [15:8] +//bit 18. limit read. 0. no outstanding read request limitation. +// 1. limit the read outstanding request to the number of bits[7:0]. +//bit 17:16. Not used. +//bit 15:8. write outstanding commands limit. +//bit 7:0. read outstanding commands limit. +#define P_DMC_TEST_NUM ((volatile uint32_t *)0xfd02178c) +// how many test command for the test if the DMC_TEST_CTRL bit 24 is 0. +#define P_DMC_TEST_WD0 ((volatile uint32_t *)0xfd021790) +// write data 0 for write command. also for read back data comparision. +#define P_DMC_TEST_WD1 ((volatile uint32_t *)0xfd021794) +// write data 1 for write command. also for read back data comparision. +#define P_DMC_TEST_WD2 ((volatile uint32_t *)0xfd021798) +// write data 2 for write command. also for read back data comparision. +#define P_DMC_TEST_WD3 ((volatile uint32_t *)0xfd02179c) +// write data 3 for write command. also for read back data comparision. +#define P_DMC_TEST_WD4 ((volatile uint32_t *)0xfd0217a0) +// write data 4 for write command. also for read back data comparision. +#define P_DMC_TEST_WD5 ((volatile uint32_t *)0xfd0217a4) +// write data 5 for write command. also for read back data comparision. +#define P_DMC_TEST_WD6 ((volatile uint32_t *)0xfd0217a8) +// write data 6 for write command. also for read back data comparision. +#define P_DMC_TEST_WD7 ((volatile uint32_t *)0xfd0217ac) +// write data 7 for write command. also for read back data comparision. +#define P_DMC_TEST_RD0 ((volatile uint32_t *)0xfd0217b0) +// the read back data 0. if error happens, it would capture the first error data. +#define P_DMC_TEST_RD1 ((volatile uint32_t *)0xfd0217b4) +// the read back data 1. if error happens, it would capture the first error data. +#define P_DMC_TEST_RD2 ((volatile uint32_t *)0xfd0217b8) +// the read back data 2. if error happens, it would capture the first error data. +#define P_DMC_TEST_RD3 ((volatile uint32_t *)0xfd0217bc) +// the read back data 3. if error happens, it would capture the first error data. +#define P_DMC_TEST_RD4 ((volatile uint32_t *)0xfd0217c0) +// the read back data 4. if error happens, it would capture the first error data. +#define P_DMC_TEST_RD5 ((volatile uint32_t *)0xfd0217c4) +// the read back data 5. if error happens, it would capture the first error data. +#define P_DMC_TEST_RD6 ((volatile uint32_t *)0xfd0217c8) +// the read back data 6. if error happens, it would capture the first error data. +#define P_DMC_TEST_RD7 ((volatile uint32_t *)0xfd0217cc) +// the read back data 7. if error happens, it would capture the first error data. +#define P_DMC_TEST_ERR_ADDR ((volatile uint32_t *)0xfd0217d0) +// it capature the first error address. +#define P_DMC_TEST_ERR_CNT ((volatile uint32_t *)0xfd0217d4) +// how many data error happens in the whole test period. +#define P_DMC_TEST_STS ((volatile uint32_t *)0xfd0217d8) +//bit 31, test done bit. write 1 to clean. +//bit 30, indicate address err +//bit 29~7. not used. +//bit 6. read data resp error(caused by security or rd latency). +//bit 5. test MRR/MPR rd latency error. write 1 clear +//bit 4, sha done. write 1 to clean. +//bit 3, write done. write 1 to clean. +//bit 2, read done. write 1 to clean +//bit 1, write watchdog triggered. write 1 to clean +//bit 0, read watchdog triggered. write 1 to clean. +#define P_DMC_TEST_COMP_MASK ((volatile uint32_t *)0xfd0214cc) +//32bits for DMC TEST COMPARE bit enable. +//1 : to MASK this bit. 0: compare this bit. +#define P_DMC_TEST_RDBI0 ((volatile uint32_t *)0xfd0214d0) +//MPC RD FIFO command DBI read back data +//bit 31:16 the second cycle. +//bit 15:0 the first cycle. +#define P_DMC_TEST_RDBI1 ((volatile uint32_t *)0xfd0214d4) +//MPC RD FIFO command DBI read back data +//bit 31:16. the Forth cycle. +//bit 15:0. the third cycle. +#define P_DMC_TEST_WSTRB0 ((volatile uint32_t *)0xfd0214d8) +//MPC WR FIFO command DM bit write data +//bit 31:16 the second cycle. +//bit 15:0 the first cycle. +#define P_DMC_TEST_DRAM_CMD ((volatile uint32_t *)0xfd0214e0) +//bit 31. cmd done. write 0 to clean. +//bit 30. data done. write 0 to clean. +//bit 4:0. only one bit can be 1. read data stored in DMC_TEST_RD* write data from DMC_TEST_W +//bit 4. LPDDR4 MPC write data command( MPC WR FIFO). Not support LPDDR4 in A1. +//bit 3. LPDDR4 MPC read data command (MPC RD Calibration and RD FIFO).Not support LPDDR4 in A1. +//bit 2. LPDDR4 MPC-1 command ( NOP, Start DQS interval ....)Not support LPDDR4 in A1. +//bit 1. mrr comand. +//bit 0. mrw command. +#define P_DMC_TEST_DRAM_CMD_CODE ((volatile uint32_t *)0xfd0214e4) +//bit 27:26. 128bits data cycles . 0: 1 clock cycles; 1: 2 clock cycles; 2: 3 clock cycles; 3:4 clock cycles. +// LPDDR4 32bits: 4 clock cycles; LPDDR4 16bits: 2 clock cycles; +// DDR3/4/LPDDR3 32 bits : 2 clock cycles. DDR3/4 16bits: 1 cycles. +//bit 25 MRW/MRR/MPC command rank 1 select. 1: select. 0: not select. In A1, only rank0 supported. +//bit 24. MRW/MRR/MPC command rank 0 select. 1: select. 0: not select.In A1, only rank0 supported. +//bit 23:16 MR addr. DDR4 case : 18:16 ba[2:0]. 20:19 BG[1:0]. +//bit 15:0 opcode. +#define P_DMC_TEST_DRAM_CMD_TIME ((volatile uint32_t *)0xfd0214e8) +//bit 31:16 PRE CMD timer. //delay how many cycle to start the command. +//bit 15:0 POST CMD timer //delay how many cycle after the command execute. +//`endif +// +// Closing file: ../mmc_lp4/dmc/rtl/dmc_sec.vh +// +// +// Reading file: ../mmc_lp4/dmc/rtl/dmc_reg.vh +// +//`ifdef DMC_REG_DEFINE +//`else +//`define DMC_REG_DEFINE +// ----------------------------------------------- +// APB_BASE: APB1_BASE_ADDR = 0xfd020000 +// ----------------------------------------------- +//`define DMC_REG_BASE 32'hfd020000 +#define P_DMC_SOFT_RST2 ((volatile uint32_t *)0xfd02000c) +//bit 31~11. reserved for future. +//bit 10 DMC DFI cmd soft reset_n +//bit 9 DMC DFI MISC soft reset_n +//bit 8 DMC DFI data soft reset_n +//bit 7 DMC DFI dcu soft reset_n +//bit 6 DMC siu soft reset_n +//bit 5. DMC test soft reset_n. 0 : reset. 1 : normal working mode. +//bit 4. DMC low power control moudle soft reset_n. 0 : reset. 1 : normal working mode. +//bit 3. DMC QOS monitor module soft reset_n. 0 : reset. 1 : normal working mode. +//bit 2. DMC register modle soft reset_n. 0 : reset. 1 : normal working mode. +//bit 1. DMC canvas transfer module soft reset_n. 0 : reset. 1 : normal working mode. +//bit 0. DMC command buffers and command generation modules soft reset. 0 = reset. 1: +#define P_DMC_VERSION ((volatile uint32_t *)0xfd020014) +//read only 32'h000b0000. for A1 +#define P_DMC_MON_CTRL0 ((volatile uint32_t *)0xfd020080) +//bit 31. qos_mon_en. write 1 to trigger the enable. polling this bit 0, means finished. or use interrupt to check finish. +//bit 30. qos_mon interrupt clear. clear the qos monitor result. read 1 = qos mon finish interrupt. +//bit 1. qos monitor 1 enable. +//bit 0. qos monitor 0 enable. +#define P_DMC_MON_CTRL1 ((volatile uint32_t *)0xfd020084) +//bit 8:0. qos monitor 0 channel select. +//bit 8 to select DMC TEST +//bit 7:0 each bit enable one AXI subID. +#define P_DMC_MON_CTRL2 ((volatile uint32_t *)0xfd020088) +//bit 8. to enabe monitor 0 second level subID selection for example device. +//bit 7:0 each bit to enable one second level subID inside device. +#define P_DMC_MON_CTRL3 ((volatile uint32_t *)0xfd02008c) +//bit 8:0. qos monitor 1 channel select. +//bit 8 to select DMC TEST +//bit 7:0 each bit enable one AXI subID. +#define P_DMC_MON_CTRL4 ((volatile uint32_t *)0xfd020090) +//bit 8. to enabe monitor 1 second level subID selection for example device. +//bit 7:0 each bit to enable one second level subID inside device. +#define P_DMC_MON_ALL_REQ_CNT ((volatile uint32_t *)0xfd0200a4) +// at the test period, the whole MMC request time. +#define P_DMC_MON_ALL_GRANT_CNT ((volatile uint32_t *)0xfd0200a8) +// at the test period, the whole MMC granted data cycles. 64bits unit. +#define P_DMC_MON_ONE_GRANT_CNT ((volatile uint32_t *)0xfd0200ac) +// at the test period, the granted data cycles for the selected channel and ports. +#define P_DMC_MON_SEC_GRANT_CNT ((volatile uint32_t *)0xfd0200b0) +// at the test period, the granted data cycles for the selected channel and ports. +#define P_DMC_MON_TIMER ((volatile uint32_t *)0xfd0200bc) +// timer for the monitor period. +#define P_DMC_CLKG_CTRL2 ((volatile uint32_t *)0xfd0200c8) +//bit 10 enable auto clock gating for dfi command generation +//bit 9 enable auto clock gating for dram cntroller +//bit 8 enable auto clock gating for dfi data path. +//bit 7. enalbe auto clock gating for write rsp generation. +//bit 6. enalbe auto clock gating for read rsp generation. +//bit 5. enalbe auto clock gating for ddr0 command filter. +//bit 4. enalbe auto clock gating for ddr0 write reorder buffer. +//bit 3. enalbe auto clock gating for ddr0 write data buffer. +//bit 2. enalbe auto clock gating for ddr0 read reorder buffer. +//bit 1. reserved +//bit 0. reserved +#define P_DMC_CLKG_CTRL3 ((volatile uint32_t *)0xfd0200cc) +//bit 10 force to disable the clock of dfi command generation +//bit 9 force to disable the clock of dram cntroller +//bit 8 force to disable the clock of dfi data path. +//bit 7. force to disalbe the clock of write rsp generation. +//bit 6. force to disalbe the clock of read rsp generation. +//bit 5. force to disalbe the clock of command filter. +//bit 4. force to disalbe the clock of write reorder buffer. +//bit 3. force to disalbe the clock of write data buffer. +//bit 2. force to disalbe the clock of read reorder buffer. +//bit 1. reserved. +//bit 0. reserved. +#define P_DMC_CHAN_STS ((volatile uint32_t *)0xfd0200d8) +//bit 4 always 1 +//bit 3 ddr0 write data buffer idle. 1 : idle 0: busy. +//bit 2 always 1. +//bit 1 ddr0 wbuf idle. 1 : idle 0: busy. +//bit 0. axi0 channel idle. 1 : idle 0: busy. +#define P_DMC_CMD_FILTER_CTRL3 ((volatile uint32_t *)0xfd020108) +//bit 31. force wbuf empty. +//bit 30:26 wbuf high level number +//bit 25:21 wbuf mid level number +//bit 20:16 wbuf low level number +//bit 14:10 rbuf high level number +//bit 9:5 rbuf middle level number +//bit 4:0 rbuf low level number +#define P_DMC_CMD_FILTER_CTRL4 ((volatile uint32_t *)0xfd02010c) +//bit 29:25. tITW.long +//bit 24:20. tITW. short +//bit 19:12 tAP auto precharge the bank not used if idle that long time. +//bit 11:6 write to read accesses if there write hit request. +//bit 5:0 read to write accesses if there write hit request. +#define P_DMC_CMD_FILTER_CTRL5 ((volatile uint32_t *)0xfd020110) +//bit 31:24 Once ddr data bus switch to read, the maxmum read command number to give up the bus when there's write request pending for write buffer. +//bit 23:16 Once ddr data bus switch to write, the maxmum write command number to give up the bus when there's read request pending too long. +//bit 15:8. Once ddr data bus switch to read, the minimum read command number to transfer back to write stage if there's still pending read request. +//bit 7:0. Once ddr data bus switch to write, the minimum write command number to transfer back to read stage if there's still pending write request. +#define P_DMC_CMD_FILTER_CTRL6 ((volatile uint32_t *)0xfd020114) +//bit 31:24 write urgent 3 request pending hold num. +//bit 23:16 write urgent 2 request pending hold num. +//bit 15:8. write urgent 1 request pending hold num. +//bit 7:0. write urgent 0 request pending hold num. +#define P_DMC_CMD_FILTER_CTRL7 ((volatile uint32_t *)0xfd020118) +//bit 15:8 write to read waiting cycles if there write hit request. +//bit 7:0 read to write waiting cycles if there write hit request. +#define P_DMC_CMD_BUFFER_CTRL ((volatile uint32_t *)0xfd02011c) +//bit 31:26 total write buffer number. default 32. +//bit 25:20 total read buffer number. default 32. +//bit 19:8 reserved. +//bit 7:0 aw_pending_inc_num. incease write ugent level 1 when write command waiting to in write buffer that long. +#define P_DMC_CMD_BUFFER_CTRL1 ((volatile uint32_t *)0xfd020120) +//bit 29:24 read buffer number in non-urgent request. +//bit 23:16 read buffer bank miss watch dog threshold. +//bit 15:12 read buffer urgent level 3 counter inc weight. +//bit 11:8 read buffer urgent level 2 counter inc weight. +//bit 7:4 read buffer urgent level 1 counter inc weight. +//bit 3:0 read buffer urgent level 0 counter inc weight. +#define P_DMC_AXI0_CHAN_CTRL ((volatile uint32_t *)0xfd020200) +//bit 31 AXI interface request enable. +//bit 19 AXI interface auto clock gating enable. 1: enable; 0 disable. +//bit 18 AXI interface clock disable. 1 : disable clock. 0 enable clock. +//bit 17 AXI interface dmc clock domain soft reset. 0 : reset. 1 : normal working mode. +//bit 16 AXI interface s0 clock domain soft reset. 0 : reset. 1 : normal working mode. +//bit 15:12 ugt3 QOS level. +//bit 11:8 ugt2 QOS level. +//bit 7:4 ugt1 QOS level. +//bit 3:0 not used. +#define P_DMC_AXI0_HOLD_CTRL ((volatile uint32_t *)0xfd020204) +//31:24 write hold num. max outstanding request number. +//23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request. +//15:8 read hold num. max outstanding request number. +//7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request. +#define P_DMC_AXI5_HOLD_CTRL ((volatile uint32_t *)0xfd020254) +//31:24 write hold num. max outstanding request number. +//23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request. +//15:8 read hold num. max outstanding request number. +//7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request. +//`endif +// +// Closing file: ../mmc_lp4/dmc/rtl/dmc_reg.vh +// +// +// Reading file: ../mmc_lp4/dmc/rtl/dmc_siu_reg.vh +// +//`ifdef DMC_SIU_REG_DEFINE +//`else +//`define DMC_SIU_REG_DEFINE +// ----------------------------------------------- +// APB_BASE: APB1_BASE_ADDR = 0xfd020400 +// ----------------------------------------------- +//`define DMC_DRAM_REG_BASE 32'hfd020400 +//in A1 project, don't support hardware controlled frequency change. +#define P_DMC_DRAM_TMRD ((volatile uint32_t *)0xfd020400) +//bit 3:0. tMRD. +#define P_DMC_DRAM_TRFC ((volatile uint32_t *)0xfd020404) +//bit 9:0 tRFC +#define P_DMC_DRAM_TRP ((volatile uint32_t *)0xfd020408) +//bit 21:16. tRP for precharge all banks. +//bit 5:0. tRP for precharge one bank. +#define P_DMC_DRAM_TRTW ((volatile uint32_t *)0xfd02040c) +//bit 5:0 tRTW +#define P_DMC_DRAM_TCL ((volatile uint32_t *)0xfd020410) +//bit 5:0 tCL/tRL. read latency. +#define P_DMC_DRAM_TCWL ((volatile uint32_t *)0xfd020414) +//bit 5:0. CWL: write latency. +#define P_DMC_DRAM_TRAS ((volatile uint32_t *)0xfd020418) +//bit 7:0. tRAS. minimum active to precharge time for same bank. +#define P_DMC_DRAM_TRC ((volatile uint32_t *)0xfd02041c) +//bit 7:0. tRC. minimum active to active time for same bank. +#define P_DMC_DRAM_TRCD ((volatile uint32_t *)0xfd020420) +//bit 7:0 tRCD active to read/write timing for same bank. +#define P_DMC_DRAM_TRRD ((volatile uint32_t *)0xfd020424) +//bit 21:16. tRRD_l active bank A to active B in same band group for DDR4. +//bit 5:0. tRRD/tRRD_s active bank A to active bank b time. +//tRRD_s: active bank A to active bank b in different bank grousp for DDR4. +#define P_DMC_DRAM_TFAW ((volatile uint32_t *)0xfd020428) +//bit 8:0 tFAW. four active command windows +#define P_DMC_DRAM_TRTP ((volatile uint32_t *)0xfd02042c) +//bit 5:0 tRTP. +#define P_DMC_DRAM_TWR ((volatile uint32_t *)0xfd020430) +//bit 5:0 tWR. +#define P_DMC_DRAM_TWTR ((volatile uint32_t *)0xfd020434) +//bit 5:0 tWTR. +#define P_DMC_DRAM_TCCD ((volatile uint32_t *)0xfd020438) +//bit 19:16. tCCD/tCCD_l. +//bit 3:0 tCCD/tCCD_s read to read command time or write to write command time. +#define P_DMC_DRAM_TEXSR ((volatile uint32_t *)0xfd02043c) +//bit 9:0. tEXSR. EXIT SELF-REFRESH to read/write command. +#define P_DMC_DRAM_TXS ((volatile uint32_t *)0xfd020440) +//bit 9:0 tXS. EXIT SELF_REFRESH to other command time +#define P_DMC_DRAM_TXP ((volatile uint32_t *)0xfd020444) +//bit 3:0. tXP. EXIT power down to other command time +#define P_DMC_DRAM_TXPDLL ((volatile uint32_t *)0xfd020448) +//bit 9:0. tXPDLL, EXIT power down to read/write command time(need to relock PLL). +#define P_DMC_DRAM_TZQCS ((volatile uint32_t *)0xfd02044c) +//bit 11:0. ZQCS command to other command time. +#define P_DMC_DRAM_TCKSRE ((volatile uint32_t *)0xfd020450) +//bit 4:0. enter self refresh to disable clock time. +#define P_DMC_DRAM_TCKSRX ((volatile uint32_t *)0xfd020454) +//bit 4:0. enable clock to exit self refresh time. +#define P_DMC_DRAM_TCKE ((volatile uint32_t *)0xfd020458) +//bit 4:0. CKE high or low minimum time. +#define P_DMC_DRAM_TMOD ((volatile uint32_t *)0xfd02045c) +//bit 4:0 tMOD. MRR/MRW to other command time. +#define P_DMC_DRAM_TDQS ((volatile uint32_t *)0xfd020460) +//bit 3:0 tDQS. the delay to access different rank. +#define P_DMC_DRAM_TRSTL ((volatile uint32_t *)0xfd020464) +//not used. +#define P_DMC_DRAM_TZQLAT ((volatile uint32_t *)0xfd020468) +//bit 5:0 ZQ LATCH command to other comand timing in LPDDR4 mode. +#define P_DMC_DRAM_TMRR ((volatile uint32_t *)0xfd02046c) +//bit 7:0 tMRR not used in DMC. not support MR READ. +#define P_DMC_DRAM_TCKESR ((volatile uint32_t *)0xfd020470) +//bit 9:0 tCKESR. CKE low minimum pulse in self refresh mode. +#define P_DMC_DRAM_TDPD ((volatile uint32_t *)0xfd020474) +//not support. +#define P_DMC_DRAM_DFITCTRLDELAY ((volatile uint32_t *)0xfd020478) +//bit 3:0. DFI_t_ctrldealy +#define P_DMC_DRAM_DFITPHYWRDATA ((volatile uint32_t *)0xfd02047c) +//bit 5:0. dfi_t_phy_wrdata. +#define P_DMC_DRAM_DFITPHYWRLAT ((volatile uint32_t *)0xfd020480) +//bit 5:0. dfi_t_phy_wrlat. in DDR3/4/LPDDR3 mode: WL -5. in LPDDR4 mode: WL -5 + 2. +#define P_DMC_DRAM_DFITRDDATAEN ((volatile uint32_t *)0xfd020484) +//bit 5:0. dfi_t_rddata_en. in DDR3/4/LPDDR3 mode: RL -5. in LPDDR4 mode : RL -5 + 1. +#define P_DMC_DRAM_DFITPHYRDLAT ((volatile uint32_t *)0xfd020488) +//bit 5:0. dfi_t_rdlat. +#define P_DMC_DRAM_DFITCTRLUPDMIN ((volatile uint32_t *)0xfd02048c) +//bit 7:0. CTRLUPD_MIN minimux clock cycle to maintain CTRLUPD_REQ. +#define P_DMC_DRAM_DFITCTRLUPDMAX ((volatile uint32_t *)0xfd020490) +//bit 7:0 CTRLUPD_MAX. maxmum clock cycle to maintain CTRLUPD_REQ if no CTRLUPD_ACK response. +#define P_DMC_DRAM_DFITMSTRRESP ((volatile uint32_t *)0xfd020494) +//not used. +#define P_DMC_DRAM_DFITREFMSKI ((volatile uint32_t *)0xfd020498) +//not used. +#define P_DMC_DRAM_DFITCTRLUPDI ((volatile uint32_t *)0xfd02049c) +//not used. +#define P_DMC_DRAM_DFITDRAMCLK ((volatile uint32_t *)0xfd0204a0) +//bit 17 dram clk1 enable. +//bit 16 dram clk0 enable. +//bit 15:8 DRAM CLK disable waiting time +//bit 7:0 DRAM CLK enable enable timer +#define P_DMC_DRAM_DFITLPRESP ((volatile uint32_t *)0xfd0204a8) +//bit 3:0. dfi_lp_ctrl_req response time. after dfi_lp_ctrl_req asserted, and after response time if there's still no dfi_lp_ack respone, then drop the dfi_lp_ctrl_req. +#define P_DMC_DRAM_DFITPHYMSTR ((volatile uint32_t *)0xfd0204ac) +//bit 15 1: enable DFIPHYMASTER INTERFACE 0 disable DFIPHYMSTR en response. +// always 0 we would use DFI_RETRAIN function for PHY retrain required from LPDDR4. +#define P_DMC_DRAM_TCKECK ((volatile uint32_t *)0xfd0204b0) +//bit 4:0. tCKECK from CKE low to assert dfi_dram_clk_disable time. this time + dfi_t_ctrl_delay +#define P_DMC_DRAM_TREFI ((volatile uint32_t *)0xfd0204b4) +//write this register will update the auto refresh related register to the auto refresh control logic. +//bit 31:24: tZQCI dmc send zqci period. unit is how much auto refresh period. +//bit 23:16 pvti dmc send dfi_ctrlupd_req period. unit is one auto refresh period. +//bit 15:8. tREFI.dmc send auto refresh command period. unit is 100ns. +//bit 7:0. t100ns period. unit is dmc clock cycles +#define P_DMC_DRAM_TSR ((volatile uint32_t *)0xfd0204b8) +//bit 5:0 tSR. self resfresh enter to exit time. +#define P_DMC_DRAM_TCCDMW ((volatile uint32_t *)0xfd0204bc) +//bit 5:0. 4*tCCD in LPDDR4 mask write. +#define P_DMC_DRAM_TESCKE ((volatile uint32_t *)0xfd0204c0) +//bit 5:0 tESCKE. enter self refresh to power time for LPDDR4. +#define P_DMC_DRAM_TREFI_DDR3 ((volatile uint32_t *)0xfd0204c4) +//7:0. 8*DDR3 SDRAM tREFI time . the unit is t100ns. use this to check in 8*tREFI time, the DMC should sent more than 16 auto REFRESH command. +#define P_DMC_DRAM_TZQCAL ((volatile uint32_t *)0xfd0204c8) +//7:0. ZQCAL for LPDDR4. +#define P_DMC_DRAM_T10US ((volatile uint32_t *)0xfd0204cc) +//10us clock cycle number used for LP2 mode. +#define P_DMC_DRAM_TMRRI ((volatile uint32_t *)0xfd0204d0) +//bit 7:0 tMRRI for MRR +#define P_DMC_DRAM_DFITPHYUPDTYPE0 ((volatile uint32_t *)0xfd020600) +//dfi_phyupd_ack hold time for dfi_phyupd_req type = 0. +#define P_DMC_DRAM_DFITPHYUPDTYPE1 ((volatile uint32_t *)0xfd020604) +//dfi_phyupd_ack hold time for dfi_phyupd_req type = 1. +#define P_DMC_DRAM_DFITPHYUPDTYPE2 ((volatile uint32_t *)0xfd020608) +//dfi_phyupd_ack hold time for dfi_phyupd_req type = 2. +#define P_DMC_DRAM_DFITPHYUPDTYPE3 ((volatile uint32_t *)0xfd02060c) +//dfi_phyupd_ack hold time for dfi_phyupd_req type = 3. +#define P_DMC_DRAM_DFIODTCFG ((volatile uint32_t *)0xfd020610) +//bit 12. rank1 ODT default. default vulue for ODT[1] pins if theres no read/write activity. +//bit 11. rank1 ODT write sel. enable ODT[1] if there's write occur in rank1. +//bit 10. rank1 ODT write nsel. enable ODT[1] if theres's write occur in rank0. +//bit 9. rank1 odt read sel. enable ODT[1] if there's read occur in rank1. +//bit 8. rank1 odt read nsel. enable ODT[1] if there's read occure in rank0. +//bit 4. rank0 ODT default. default vulue for ODT[0] pins if theres no read/write activity. +//bit 3. rank0 ODT write sel. enable ODT[0] if there's write occur in rank0. +//bit 2. rank0 ODT write nsel. enable ODT[0] if theres's write occur in rank1. +//bit 1. rank0 odt read sel. enable ODT[0] if there's read occur in rank0. +//bit 0. rank0 odt read nsel. enable ODT[0] if there's read occure in rank1. +#define P_DMC_DRAM_DFIODTCFG1 ((volatile uint32_t *)0xfd020614) +//bit 27:24 ODT length for BL8 read transfer. +//bit 19:16. ODT length for BL8 write transfer. +//bit 12:8. ODT latency for reads. suppose to be 0. +//bit 4:0. ODT latency for writes. suppose to be 0. +#define P_DMC_DRAM_MCFG ((volatile uint32_t *)0xfd020618) +//bit 14. 1: cke init low. 0 : cke init high. +//bit 13 1: dbi write enable only for LPDDR4. +//bit 12. 1: dbi read inversion. 0: dbi read high inversion. +//bit 11. 1: dbi read enable. 0: dbi not enabled. +//bit 10 1: enable staggered chip select for 2 ranks DRAM. +//bit 9 1: enable send auto refresh command to DDR SDRAM when PCTL is in CFG/STOP state. +//bit 8 send auto refr cmd before enter register triggered self refresh +//bit 7 send auto refr cmd after exit regsiter triggered self refresh mode. +//bit 6 disable dram clock after enter register triggered self refresh. +//bit 5 send DFI_LP_REQ to PHY after enter register triggered elf refresh mode. +//bit 4 send DRAM to power down mode after enter self refresh. ONLY for LPDDR4. +//bit 3 send DFI_CTRLUPD_REQ after exit register triggered self refresh. +//bit 2 send ZQCS command after exit register triggered self refresh. +//bit 1 enable PHY triggered DFI_PHYUPD_REQ. +//bit 0 2T mode. always 1 in DDR3/4 mode. +#define P_DMC_DRAM_DFI_CTRL ((volatile uint32_t *)0xfd020624) +//bit 31 siu_dfi_lat err generation enable. 1: if dfi read latency violation, generate data error. 0 : disable. +//bit 30:0. not used. +#define P_DMC_DRAM_DFIINITCFG ((volatile uint32_t *)0xfd020628) +//bit 31. dfi_init_complete status. read only. +//bit 15:14. Frequency set 1 dfi_freq_ratio value. Not used in A1 +//bit 12:8 Frequency set 1 dfi_freq value. Not used in A1 +//bit 7:6 Frequency set 0 dfi_freq_ratio value. +//bit 5:1 Frequency set 0 dfi_freq value. +//bit 0. dfi_init_start value can be use manually config dfi_init_start signal. +#define P_DMC_DRAM_ZQ_CTRL ((volatile uint32_t *)0xfd02062c) +// only bit 0 can be enable in A1. +//bit 2 send ZQCS command to RANK0 then send comand to RANK1. +//bit 1. send ZQCS command to both RANK0 and RANK1 together. +//bit 0. send ZQCS command to only rank0. +#define P_DMC_DRAM_APD_CTRL ((volatile uint32_t *)0xfd020630) +//bit 19:16 DFI_LP_WAKEUP value in APD DFI_LP_REQ mode +//bit 12 1: exit power down slow mode(waiting PLL LOCK). 0 : fast mode. +//bit 11 enable DFI_LP_REQ when enter Auto power down mode. +//bit 10 disable DFI_clk_disable when enter auto power down mode. +//bit 9:0 0 disable auto power down mode. +//non zero value to enable auto power down when DMC is in idle state for this number of clock cycles. +#define P_DMC_DRAM_ASR_CTRL ((volatile uint32_t *)0xfd020634) +//bit [25] LP2 mode PHYCLK enable. 1 : keep PHY clock enable after enter LP2 mode. 0 : shutdown PHY clock after enter LP2 mode. +//bit [24] LP2 mode SRX waiting enable. if Self refresh too long, waiting 10us for the PHY stable before DDR SDRAM exit from self refresh state. +//bit [23:20] DFI_LP_WAKEUP value in self refresh DFI_LP_REQ mode. +//bit 17 : send REFRESH command after exit from auto self refersh mode(ASR). +//bit 16 : send REFERSH command before enter to Auto self refresh mode(ASR). +//bit 15 : send ZQCS command after exit from Auto self refresh mode(ASR). +//bit 14 : send dfi_ctrl_upd after exit from ASR mode +//bit 13 : send power down command when enter ASR mode. //for LPDDR4 only. +//bit 12 : set the PHY enter LP2 mode after enter ASR mode. +//bit 11 : send DFI_LP_REQ after enter ASR mode. +//bit 10 : set DFI_CLK_DISABLE after enter ASR mode. +//bit 9:0. 0 disable auto ASR mode. +// Non-zero valule enable ASR mode. when DMC is in idle state for this number of clock cycles, the DMC will enter ASR mode. +#define P_DMC_DRAM_PHYMSTR_CTRL ((volatile uint32_t *)0xfd020640) +//not used in A1. should be all 0. +#define P_DMC_DRAM_DFIODTRANKMAP ((volatile uint32_t *)0xfd020644) +//not used in A1. +#define P_DMC_DRAM_REFR_CTRL ((volatile uint32_t *)0xfd020648) +//bit 17:8 auto refresh request pending cnt if there's page hit request. +//bit 6 Disabled auto refresh command if over 16 auto refresh command sent in 2 TREFI_DDR3 period +//bit 5 enable dmc send ZQCS command . +//bit 4. enable dmc send DFI_CTRUPD_REQ. +//bit 3:1. how many refresh command send for one period. = this number + 1 +//bit 0. enable dmc send auto refresh command. +#define P_DMC_DRAM_FREQ_CTRL ((volatile uint32_t *)0xfd02064c) +//bit 31 . wiret 1 to change freqency read 0: finished. +//bit 30:9. not used. +//bit 9. 1 : FREQ MRW done. let FREQ change machine continue. +//bit 8 FREQ WAIT. 1 when freq change finishes, state machine stop at self refresh state in case there's something need to handle. +// 0 after freq change finishes the state machine go back to access state. +//bit 7 when change PLL setting, disable dmc clock +//bit 6 when change PLL setting, disable PHY DfiClk and DfiCtlClk. +//bit 5 check vpu_sleep_en ==1 when do FREQ change. if vpu_sleep_en == 0, just wait. +//bit 4 nxt frequency selection. 1 = freq1. 0 = freq0. +//bit 3:1. not used. +//bit 0. current frequency selection. +#define P_DMC_DRAM_SCFG ((volatile uint32_t *)0xfd020650) +// bit 2:0 only one bit can be high at same time. +// bit 2 1 : to ask PCTL enter ACCESS STATE. 0 : deassert the request. +// bit 1 1 : to ask PCTL enter SELF REFRESH STATE. 0 : deassert the request. +// bit 0 1 : to ask PCTL enter STOP/CONFIG STATE . 0 : deassert the request. +#define P_DMC_DRAM_STAT ((volatile uint32_t *)0xfd020654) +//bit 31 rd latency error. 1: means after dfiphytrdlat cycles, the read data still not back. +//bit 28:24 dram_sr_state +//bit 23:20 stop_st +//bit 19:15 sleep_st +//bit 14:12 ACCESS STATUS 0 : ACCESS is in normal working mode. +//1 : ACCESS sending precharege command. +//2 : ACCESS sending AUTO REFESH command. +//3 : ACCESS sending DIF_CTRLUPD_REQ command. +//4 : ACCESS sending ZQCS command to DDR DRAM(ZQCAL for LPDDR4). +//5 : ACCESS sending ZQLATCH command to LPDDR4 only. +//bit 11:8 APD STATUS: 0 : APD_IDLE +//1 : APD sending PRECHARGE command +//2 : APD sending CKE low command +//3 : APD sending DISABLE DRAM CLOCK command +//4 : APD sending DFI_LP_CTRL_REQ +//5 : APD in Auto Power down mode. +//6 : APD deassert DFI_LP_CTRL_REQ +//7 : APD sending enable DRAM CLOCK command +//8 : APD sending out CKE high command. +//bit 7:4: DRAM_STATUS: 0 : DRAM IDLE +//1 : DRAM_STOP/DRAM_CFG +//2 : DRAM_ACCESS +//3 : DRAM_SLEEP +//4 : DRAM APD(AUTO POWER DOWN). +//5 : IDLE -> STOP/CONFIG +//6 : STOP -> SLEEP +//7 : STOP -> ACCESS +//8 : ACCESS -> SLEEP. +//9 : ACCESS -> STOP +//A : ACCESS -> APD +//B : SLEEP -> STOP +//C : SLEEP -> ACCESS +//D : APD -> ACCESS +//bit 3 reserved. +//bit 2 1 : DRAM enter normal working state. +//bit 1 1 : DRAM enter sleep state. self refresh state. +//bit 0 1 : dram enter cfg state. +#define P_DMC_DRAM_STAT1 ((volatile uint32_t *)0xfd020658) +//bit 11:8 freq_st. +//bit 7:5 train_st +//bit 4:0 dram_phy_st +#define P_DMC_PHY_RETRAINING_CTRL ((volatile uint32_t *)0xfd02065c) +// A1 not support LPDDR4 so this register is not used in A1. +//bit 31 : phy_retraining enable. +//bit 30 : check vpu sleep_en. +//bit 25:24 : retraining dfi_freq[4:3], the [2:0] bit still use the dfi_freq bits to keep the frequency. +//bit 23:0: retraining period unit : 100ns. +#define P_DMC_DFI_ERR_STAT ((volatile uint32_t *)0xfd020660) +//LPDDR4 PHY DFI error infomation. +//bit 31:20. not used. +//bit 9. ddr0_dfi_error +//bit 8:5 ddr0_dfi_error_info. +//bit 4. ddr1_dfi_error. +//bit 3:0. ddr1_dfi_error_info. +#define P_DMC_LP2_TIMER ((volatile uint32_t *)0xfd020668) +//bit 15:0. timer setting to measure how long the chip is entered LP2 mode. +//this timer is 40bits counter with DMC PCLK. +//we use the high 16bits to compare this register. if the counter is large than this number, that means the PHY need addition 10us after wakeup the PHY and before exit self_refresh mode. +#define P_DMC_DRAM_DFI_SWAP_0 ((volatile uint32_t *)0xfd020680) +//bit 5:0. dfi_act_n function select +// 6'h00 : the function itself. +// 6'h01 : act_n. +// 6'h02 : ras_n. +// 6'h03 : cas_n. +// 6'h04 : we_n. +// 6'h05 : bg[0]. +// 6'h06 : bg[1]. +// 6'h07 : ba[0]. +// 6'h08 : ba[1]. +// 6'h09 : ba[2]. +// 6'h0a : a[0]. +// 6'h0b : a[1]. +// 6'h0c : a[2]. +// 6'h0d : a[3]. +// 6'h0e : a[4]. +// 6'h0f : a[5]. +// 6'h10 : a[6]. +// 6'h11 : a[7]. +// 6'h12 : a[8]. +// 6'h13 : a[9]. +// 6'h14 : a[10]. +// 6'h15 : a[11]. +// 6'h16 : a[12]. +// 6'h17 : a[13]. +// 6'h18 : a[14]. +// 6'h19 : a[15]. +// 6'h1a : a[16]. +// 6'h1b : a[17]. +#define P_DMC_DRAM_DFI_SWAP_1 ((volatile uint32_t *)0xfd020684) +//bit 5:0. dfi_ras_n function select +// 6'h00 : the function itself. +// 6'h01 : act_n. +// 6'h02 : ras_n. +// 6'h03 : cas_n. +// 6'h04 : we_n. +// 6'h05 : bg[0]. +// 6'h06 : bg[1]. +// 6'h07 : ba[0]. +// 6'h08 : ba[1]. +// 6'h09 : ba[2]. +// 6'h0a : a[0]. +// 6'h0b : a[1]. +// 6'h0c : a[2]. +// 6'h0d : a[3]. +// 6'h0e : a[4]. +// 6'h0f : a[5]. +// 6'h10 : a[6]. +// 6'h11 : a[7]. +// 6'h12 : a[8]. +// 6'h13 : a[9]. +// 6'h14 : a[10]. +// 6'h15 : a[11]. +// 6'h16 : a[12]. +// 6'h17 : a[13]. +// 6'h18 : a[14]. +// 6'h19 : a[15]. +// 6'h1a : a[16]. +// 6'h1b : a[17]. +#define P_DMC_DRAM_DFI_SWAP_2 ((volatile uint32_t *)0xfd020688) +//bit 5:0. dfi_cas_n function select +// 6'h00 : the function itself. +// 6'h01 : act_n. +// 6'h02 : ras_n. +// 6'h03 : cas_n. +// 6'h04 : we_n. +// 6'h05 : bg[0]. +// 6'h06 : bg[1]. +// 6'h07 : ba[0]. +// 6'h08 : ba[1]. +// 6'h09 : ba[2]. +// 6'h0a : a[0]. +// 6'h0b : a[1]. +// 6'h0c : a[2]. +// 6'h0d : a[3]. +// 6'h0e : a[4]. +// 6'h0f : a[5]. +// 6'h10 : a[6]. +// 6'h11 : a[7]. +// 6'h12 : a[8]. +// 6'h13 : a[9]. +// 6'h14 : a[10]. +// 6'h15 : a[11]. +// 6'h16 : a[12]. +// 6'h17 : a[13]. +// 6'h18 : a[14]. +// 6'h19 : a[15]. +// 6'h1a : a[16]. +// 6'h1b : a[17]. +#define P_DMC_DRAM_DFI_SWAP_3 ((volatile uint32_t *)0xfd02068c) +//bit 5:0. dfi_we_n function select +// 6'h00 : the function itself. +// 6'h01 : act_n. +// 6'h02 : ras_n. +// 6'h03 : cas_n. +// 6'h04 : we_n. +// 6'h05 : bg[0]. +// 6'h06 : bg[1]. +// 6'h07 : ba[0]. +// 6'h08 : ba[1]. +// 6'h09 : ba[2]. +// 6'h0a : a[0]. +// 6'h0b : a[1]. +// 6'h0c : a[2]. +// 6'h0d : a[3]. +// 6'h0e : a[4]. +// 6'h0f : a[5]. +// 6'h10 : a[6]. +// 6'h11 : a[7]. +// 6'h12 : a[8]. +// 6'h13 : a[9]. +// 6'h14 : a[10]. +// 6'h15 : a[11]. +// 6'h16 : a[12]. +// 6'h17 : a[13]. +// 6'h18 : a[14]. +// 6'h19 : a[15]. +// 6'h1a : a[16]. +// 6'h1b : a[17]. +#define P_DMC_DRAM_DFI_SWAP_4 ((volatile uint32_t *)0xfd020690) +//bit 5:0. dfi_bg0 function select +// 6'h00 : the function itself. +// 6'h01 : act_n. +// 6'h02 : ras_n. +// 6'h03 : cas_n. +// 6'h04 : we_n. +// 6'h05 : bg[0]. +// 6'h06 : bg[1]. +// 6'h07 : ba[0]. +// 6'h08 : ba[1]. +// 6'h09 : ba[2]. +// 6'h0a : a[0]. +// 6'h0b : a[1]. +// 6'h0c : a[2]. +// 6'h0d : a[3]. +// 6'h0e : a[4]. +// 6'h0f : a[5]. +// 6'h10 : a[6]. +// 6'h11 : a[7]. +// 6'h12 : a[8]. +// 6'h13 : a[9]. +// 6'h14 : a[10]. +// 6'h15 : a[11]. +// 6'h16 : a[12]. +// 6'h17 : a[13]. +// 6'h18 : a[14]. +// 6'h19 : a[15]. +// 6'h1a : a[16]. +// 6'h1b : a[17]. +#define P_DMC_DRAM_DFI_SWAP_5 ((volatile uint32_t *)0xfd020694) +//bit 5:0. dfi_bg[1] function select +// 6'h00 : the function itself. +// 6'h01 : act_n. +// 6'h02 : ras_n. +// 6'h03 : cas_n. +// 6'h04 : we_n. +// 6'h05 : bg[0]. +// 6'h06 : bg[1]. +// 6'h07 : ba[0]. +// 6'h08 : ba[1]. +// 6'h09 : ba[2]. +// 6'h0a : a[0]. +// 6'h0b : a[1]. +// 6'h0c : a[2]. +// 6'h0d : a[3]. +// 6'h0e : a[4]. +// 6'h0f : a[5]. +// 6'h10 : a[6]. +// 6'h11 : a[7]. +// 6'h12 : a[8]. +// 6'h13 : a[9]. +// 6'h14 : a[10]. +// 6'h15 : a[11]. +// 6'h16 : a[12]. +// 6'h17 : a[13]. +// 6'h18 : a[14]. +// 6'h19 : a[15]. +// 6'h1a : a[16]. +// 6'h1b : a[17]. +#define P_DMC_DRAM_DFI_SWAP_6 ((volatile uint32_t *)0xfd020698) +//bit 5:0. dfi_ba[0] function select +// 6'h00 : the function itself. +// 6'h01 : act_n. +// 6'h02 : ras_n. +// 6'h03 : cas_n. +// 6'h04 : we_n. +// 6'h05 : bg[0]. +// 6'h06 : bg[1]. +// 6'h07 : ba[0]. +// 6'h08 : ba[1]. +// 6'h09 : ba[2]. +// 6'h0a : a[0]. +// 6'h0b : a[1]. +// 6'h0c : a[2]. +// 6'h0d : a[3]. +// 6'h0e : a[4]. +// 6'h0f : a[5]. +// 6'h10 : a[6]. +// 6'h11 : a[7]. +// 6'h12 : a[8]. +// 6'h13 : a[9]. +// 6'h14 : a[10]. +// 6'h15 : a[11]. +// 6'h16 : a[12]. +// 6'h17 : a[13]. +// 6'h18 : a[14]. +// 6'h19 : a[15]. +// 6'h1a : a[16]. +// 6'h1b : a[17]. +#define P_DMC_DRAM_DFI_SWAP_7 ((volatile uint32_t *)0xfd02069c) +//bit 5:0. dfi_ba[1] function select +// 6'h00 : the function itself. +// 6'h01 : act_n. +// 6'h02 : ras_n. +// 6'h03 : cas_n. +// 6'h04 : we_n. +// 6'h05 : bg[0]. +// 6'h06 : bg[1]. +// 6'h07 : ba[0]. +// 6'h08 : ba[1]. +// 6'h09 : ba[2]. +// 6'h0a : a[0]. +// 6'h0b : a[1]. +// 6'h0c : a[2]. +// 6'h0d : a[3]. +// 6'h0e : a[4]. +// 6'h0f : a[5]. +// 6'h10 : a[6]. +// 6'h11 : a[7]. +// 6'h12 : a[8]. +// 6'h13 : a[9]. +// 6'h14 : a[10]. +// 6'h15 : a[11]. +// 6'h16 : a[12]. +// 6'h17 : a[13]. +// 6'h18 : a[14]. +// 6'h19 : a[15]. +// 6'h1a : a[16]. +// 6'h1b : a[17]. +#define P_DMC_DRAM_DFI_SWAP_8 ((volatile uint32_t *)0xfd0206a0) +//bit 5:0. dfi_ba[2] function select +// 6'h00 : the function itself. +// 6'h01 : act_n. +// 6'h02 : ras_n. +// 6'h03 : cas_n. +// 6'h04 : we_n. +// 6'h05 : bg[0]. +// 6'h06 : bg[1]. +// 6'h07 : ba[0]. +// 6'h08 : ba[1]. +// 6'h09 : ba[2]. +// 6'h0a : a[0]. +// 6'h0b : a[1]. +// 6'h0c : a[2]. +// 6'h0d : a[3]. +// 6'h0e : a[4]. +// 6'h0f : a[5]. +// 6'h10 : a[6]. +// 6'h11 : a[7]. +// 6'h12 : a[8]. +// 6'h13 : a[9]. +// 6'h14 : a[10]. +// 6'h15 : a[11]. +// 6'h16 : a[12]. +// 6'h17 : a[13]. +// 6'h18 : a[14]. +// 6'h19 : a[15]. +// 6'h1a : a[16]. +// 6'h1b : a[17]. +#define P_DMC_DRAM_DFI_SWAP_9 ((volatile uint32_t *)0xfd0206a4) +//bit 5:0. dfi_a[0] function select +// 6'h00 : the function itself. +// 6'h01 : act_n. +// 6'h02 : ras_n. +// 6'h03 : cas_n. +// 6'h04 : we_n. +// 6'h05 : bg[0]. +// 6'h06 : bg[1]. +// 6'h07 : ba[0]. +// 6'h08 : ba[1]. +// 6'h09 : ba[2]. +// 6'h0a : a[0]. +// 6'h0b : a[1]. +// 6'h0c : a[2]. +// 6'h0d : a[3]. +// 6'h0e : a[4]. +// 6'h0f : a[5]. +// 6'h10 : a[6]. +// 6'h11 : a[7]. +// 6'h12 : a[8]. +// 6'h13 : a[9]. +// 6'h14 : a[10]. +// 6'h15 : a[11]. +// 6'h16 : a[12]. +// 6'h17 : a[13]. +// 6'h18 : a[14]. +// 6'h19 : a[15]. +// 6'h1a : a[16]. +// 6'h1b : a[17]. +#define P_DMC_DRAM_DFI_SWAP_10 ((volatile uint32_t *)0xfd0206a8) +//bit 5:0. dfi_a[1] function select +#define P_DMC_DRAM_DFI_SWAP_11 ((volatile uint32_t *)0xfd0206ac) +//bit 5:0. dfi_a[2] function select +#define P_DMC_DRAM_DFI_SWAP_12 ((volatile uint32_t *)0xfd0206b0) +//bit 5:0. dfi_a[3] function select +#define P_DMC_DRAM_DFI_SWAP_13 ((volatile uint32_t *)0xfd0206b4) +//bit 5:0. dfi_a[4] function select +#define P_DMC_DRAM_DFI_SWAP_14 ((volatile uint32_t *)0xfd0206b8) +//bit 5:0. dfi_a[5] function select +#define P_DMC_DRAM_DFI_SWAP_15 ((volatile uint32_t *)0xfd0206bc) +//bit 5:0. dfi_a[6] function select +#define P_DMC_DRAM_DFI_SWAP_16 ((volatile uint32_t *)0xfd0206c0) +//bit 5:0. dfi_a[7] function select +#define P_DMC_DRAM_DFI_SWAP_17 ((volatile uint32_t *)0xfd0206c4) +//bit 5:0. dfi_a[8] function select +#define P_DMC_DRAM_DFI_SWAP_18 ((volatile uint32_t *)0xfd0206c8) +//bit 5:0. dfi_a[9] function select +#define P_DMC_DRAM_DFI_SWAP_19 ((volatile uint32_t *)0xfd0206cc) +//bit 5:0. dfi_a[10] function select +#define P_DMC_DRAM_DFI_SWAP_20 ((volatile uint32_t *)0xfd0206d0) +//bit 5:0. dfi_a[11] function select +#define P_DMC_DRAM_DFI_SWAP_21 ((volatile uint32_t *)0xfd0206d4) +//bit 5:0. dfi_a[12] function select +#define P_DMC_DRAM_DFI_SWAP_22 ((volatile uint32_t *)0xfd0206d8) +//bit 5:0. dfi_a[13] function select +#define P_DMC_DRAM_DFI_SWAP_23 ((volatile uint32_t *)0xfd0206dc) +//bit 5:0. dfi_a[14] function select +#define P_DMC_DRAM_DFI_SWAP_24 ((volatile uint32_t *)0xfd0206e0) +//bit 5:0. dfi_a[15] function select +#define P_DMC_DRAM_DFI_SWAP_25 ((volatile uint32_t *)0xfd0206e4) +//bit 5:0. dfi_a[16] function select +#define P_DMC_DRAM_DFI_SWAP_26 ((volatile uint32_t *)0xfd0206ec) +//bit 5:0. dfi_a[17] function select +// +// Closing file: ../mmc_lp4/dmc/rtl/dmc_siu_reg.vh +// +// +// Reading file: ../mmc_lp4/dmc/rtl/dmc_sticky_reg.vh +// +//`ifdef DMC_STICKY_REG_DEFINE +//`else +//`define DMC_STICKY_REG_DEFINE +// ----------------------------------------------- +// APB_BASE: APB1_BASE_ADDR = 0xfd020800 +// ----------------------------------------------- +//`define DMC_STICKY_REG_BASE 32'hfd020800 +//those register is for software save some tempary value. and because it's in RAM. it won't lose if DMC get reseted. +#define P_DMC_STICKY_0 ((volatile uint32_t *)0xfd020800) +#define P_DMC_STICKY_1 ((volatile uint32_t *)0xfd020804) +#define P_DMC_STICKY_2 ((volatile uint32_t *)0xfd020808) +#define P_DMC_STICKY_3 ((volatile uint32_t *)0xfd02080c) +#define P_DMC_STICKY_4 ((volatile uint32_t *)0xfd020810) +#define P_DMC_STICKY_5 ((volatile uint32_t *)0xfd020814) +#define P_DMC_STICKY_6 ((volatile uint32_t *)0xfd020818) +#define P_DMC_STICKY_7 ((volatile uint32_t *)0xfd02081c) +#define P_DMC_STICKY_8 ((volatile uint32_t *)0xfd020820) +#define P_DMC_STICKY_9 ((volatile uint32_t *)0xfd020824) +#define P_DMC_STICKY_10 ((volatile uint32_t *)0xfd020828) +#define P_DMC_STICKY_11 ((volatile uint32_t *)0xfd02082c) +#define P_DMC_STICKY_12 ((volatile uint32_t *)0xfd020830) +#define P_DMC_STICKY_13 ((volatile uint32_t *)0xfd020834) +#define P_DMC_STICKY_14 ((volatile uint32_t *)0xfd020838) +#define P_DMC_STICKY_15 ((volatile uint32_t *)0xfd02083c) +#define P_DMC_STICKY_16 ((volatile uint32_t *)0xfd020840) +#define P_DMC_STICKY_17 ((volatile uint32_t *)0xfd020844) +#define P_DMC_STICKY_18 ((volatile uint32_t *)0xfd020848) +#define P_DMC_STICKY_19 ((volatile uint32_t *)0xfd02084c) +#define P_DMC_STICKY_20 ((volatile uint32_t *)0xfd020850) +#define P_DMC_STICKY_21 ((volatile uint32_t *)0xfd020854) +#define P_DMC_STICKY_22 ((volatile uint32_t *)0xfd020858) +#define P_DMC_STICKY_23 ((volatile uint32_t *)0xfd02085c) +#define P_DMC_STICKY_24 ((volatile uint32_t *)0xfd020860) +#define P_DMC_STICKY_25 ((volatile uint32_t *)0xfd020864) +#define P_DMC_STICKY_26 ((volatile uint32_t *)0xfd020868) +#define P_DMC_STICKY_27 ((volatile uint32_t *)0xfd02086c) +#define P_DMC_STICKY_28 ((volatile uint32_t *)0xfd020870) +#define P_DMC_STICKY_29 ((volatile uint32_t *)0xfd020874) +#define P_DMC_STICKY_30 ((volatile uint32_t *)0xfd020878) +#define P_DMC_STICKY_31 ((volatile uint32_t *)0xfd02087c) +#define P_DMC_STICKY_32 ((volatile uint32_t *)0xfd020880) +#define P_DMC_STICKY_33 ((volatile uint32_t *)0xfd020884) +#define P_DMC_STICKY_34 ((volatile uint32_t *)0xfd020888) +#define P_DMC_STICKY_35 ((volatile uint32_t *)0xfd02088c) +#define P_DMC_STICKY_36 ((volatile uint32_t *)0xfd020890) +#define P_DMC_STICKY_37 ((volatile uint32_t *)0xfd020894) +#define P_DMC_STICKY_38 ((volatile uint32_t *)0xfd020898) +#define P_DMC_STICKY_39 ((volatile uint32_t *)0xfd02089c) +#define P_DMC_STICKY_40 ((volatile uint32_t *)0xfd0208a0) +#define P_DMC_STICKY_41 ((volatile uint32_t *)0xfd0208a4) +#define P_DMC_STICKY_42 ((volatile uint32_t *)0xfd0208a8) +#define P_DMC_STICKY_43 ((volatile uint32_t *)0xfd0208ac) +#define P_DMC_STICKY_44 ((volatile uint32_t *)0xfd0208b0) +#define P_DMC_STICKY_45 ((volatile uint32_t *)0xfd0208b4) +#define P_DMC_STICKY_46 ((volatile uint32_t *)0xfd0208b8) +#define P_DMC_STICKY_47 ((volatile uint32_t *)0xfd0208bc) +#define P_DMC_STICKY_48 ((volatile uint32_t *)0xfd0208c0) +#define P_DMC_STICKY_49 ((volatile uint32_t *)0xfd0208c4) +#define P_DMC_STICKY_50 ((volatile uint32_t *)0xfd0208c8) +#define P_DMC_STICKY_51 ((volatile uint32_t *)0xfd0208cc) +#define P_DMC_STICKY_52 ((volatile uint32_t *)0xfd0208d0) +#define P_DMC_STICKY_53 ((volatile uint32_t *)0xfd0208d4) +#define P_DMC_STICKY_54 ((volatile uint32_t *)0xfd0208d8) +#define P_DMC_STICKY_55 ((volatile uint32_t *)0xfd0208dc) +#define P_DMC_STICKY_56 ((volatile uint32_t *)0xfd0208e0) +#define P_DMC_STICKY_57 ((volatile uint32_t *)0xfd0208e4) +#define P_DMC_STICKY_58 ((volatile uint32_t *)0xfd0208e8) +#define P_DMC_STICKY_59 ((volatile uint32_t *)0xfd0208ec) +#define P_DMC_STICKY_60 ((volatile uint32_t *)0xfd0208f0) +#define P_DMC_STICKY_61 ((volatile uint32_t *)0xfd0208f4) +#define P_DMC_STICKY_62 ((volatile uint32_t *)0xfd0208f8) +#define P_DMC_STICKY_63 ((volatile uint32_t *)0xfd0208fc) +//`endif +// +// Closing file: ../mmc_lp4/dmc/rtl/dmc_sticky_reg.vh +// +//======================================================================== +// APB0_RESET_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe000000 +// ----------------------------------------------- +#define P_RESETCTRL_RESET0 ((volatile uint32_t *)0xfe000000) +#define P_RESETCTRL_RESET1 ((volatile uint32_t *)0xfe000004) +#define P_RESETCTRL_RESET2 ((volatile uint32_t *)0xfe000008) +#define P_RESETCTRL_RESET0_LEVEL ((volatile uint32_t *)0xfe000040) +#define P_RESETCTRL_RESET1_LEVEL ((volatile uint32_t *)0xfe000044) +#define P_RESETCTRL_RESET2_LEVEL ((volatile uint32_t *)0xfe000048) +#define P_RESETCTRL_RESET0_MASK ((volatile uint32_t *)0xfe000080) +#define P_RESETCTRL_RESET1_MASK ((volatile uint32_t *)0xfe000084) +#define P_RESETCTRL_RESET2_MASK ((volatile uint32_t *)0xfe000088) +#define P_RESETCTRL_RESET_HOLD_CYC ((volatile uint32_t *)0xfe0000c0) +#define P_RESETCTRL_WATCHDOG_CTRL0 ((volatile uint32_t *)0xfe000100) +#define P_RESETCTRL_WATCHDOG_CTRL1 ((volatile uint32_t *)0xfe000104) +#define P_RESETCTRL_WATCHDOG_CNT ((volatile uint32_t *)0xfe000108) +#define P_RESETCTRL_WATCHDOG_CLR ((volatile uint32_t *)0xfe00010c) +#define P_RESETCTRL_SEC_RESET0 ((volatile uint32_t *)0xfe000140) +#define P_RESETCTRL_SEC_RESET0_LEVEL ((volatile uint32_t *)0xfe000144) +#define P_RESETCTRL_SEC_RESET0_MASK ((volatile uint32_t *)0xfe000148) +//======================================================================== +// APB0_PAD_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe000400 +// ----------------------------------------------- +#define P_PADCTRL_PIN_MUX_REG0 ((volatile uint32_t *)0xfe000400) +#define P_PADCTRL_PIN_MUX_REG1 ((volatile uint32_t *)0xfe000404) +#define P_PADCTRL_PIN_MUX_REG2 ((volatile uint32_t *)0xfe000408) +#define P_PADCTRL_PIN_MUX_REG3 ((volatile uint32_t *)0xfe00040c) +#define P_PADCTRL_PIN_MUX_REG4 ((volatile uint32_t *)0xfe000410) +#define P_PADCTRL_PIN_MUX_REG5 ((volatile uint32_t *)0xfe000414) +#define P_PADCTRL_PIN_MUX_REG6 ((volatile uint32_t *)0xfe000418) +#define P_PADCTRL_PIN_MUX_REG7 ((volatile uint32_t *)0xfe00041c) +#define P_PADCTRL_PIN_MUX_REG8 ((volatile uint32_t *)0xfe000420) +#define P_PADCTRL_PIN_MUX_REG9 ((volatile uint32_t *)0xfe000424) +#define P_PADCTRL_PIN_MUX_REGA ((volatile uint32_t *)0xfe000428) +#define P_PADCTRL_PIN_MUX_REGB ((volatile uint32_t *)0xfe00042c) +#define P_PADCTRL_PIN_MUX_REGC ((volatile uint32_t *)0xfe000430) +#define P_PADCTRL_PIN_MUX_REGD ((volatile uint32_t *)0xfe000434) +#define P_PADCTRL_PIN_MUX_REGE ((volatile uint32_t *)0xfe000438) +#define P_PADCTRL_PIN_MUX_REGF ((volatile uint32_t *)0xfe00043c) +#define P_PADCTRL_GPIO_IRQ_CTRL0 ((volatile uint32_t *)0xfe000440) +#define P_PADCTRL_GPIO_IRQ_CTRL1 ((volatile uint32_t *)0xfe000444) +#define P_PADCTRL_GPIO_IRQ_CTRL2 ((volatile uint32_t *)0xfe000448) +#define P_PADCTRL_GPIO_IRQ_CTRL3 ((volatile uint32_t *)0xfe00044c) +#define P_PADCTRL_GPIO_IRQ_CTRL4 ((volatile uint32_t *)0xfe000450) +#define P_PADCTRL_WORLDSYNC_CTRL0 ((volatile uint32_t *)0xfe000460) +#define P_PADCTRL_GPIO_MSR_CTRL0 ((volatile uint32_t *)0xfe000464) +#define P_PADCTRL_GPIOP_I ((volatile uint32_t *)0xfe000480) +#define P_PADCTRL_GPIOP_O ((volatile uint32_t *)0xfe000484) +#define P_PADCTRL_GPIOP_OEN ((volatile uint32_t *)0xfe000488) +#define P_PADCTRL_GPIOP_PULL_EN ((volatile uint32_t *)0xfe00048c) +#define P_PADCTRL_GPIOP_PULL_UP ((volatile uint32_t *)0xfe000490) +#define P_PADCTRL_GPIOP_DS ((volatile uint32_t *)0xfe000494) +#define P_PADCTRL_GPIOB_I ((volatile uint32_t *)0xfe0004c0) +#define P_PADCTRL_GPIOB_O ((volatile uint32_t *)0xfe0004c4) +#define P_PADCTRL_GPIOB_OEN ((volatile uint32_t *)0xfe0004c8) +#define P_PADCTRL_GPIOB_PULL_EN ((volatile uint32_t *)0xfe0004cc) +#define P_PADCTRL_GPIOB_PULL_UP ((volatile uint32_t *)0xfe0004d0) +#define P_PADCTRL_GPIOB_DS ((volatile uint32_t *)0xfe0004d4) +#define P_PADCTRL_GPIOX_I ((volatile uint32_t *)0xfe000500) +#define P_PADCTRL_GPIOX_O ((volatile uint32_t *)0xfe000504) +#define P_PADCTRL_GPIOX_OEN ((volatile uint32_t *)0xfe000508) +#define P_PADCTRL_GPIOX_PULL_EN ((volatile uint32_t *)0xfe00050c) +#define P_PADCTRL_GPIOX_PULL_UP ((volatile uint32_t *)0xfe000510) +#define P_PADCTRL_GPIOX_DS ((volatile uint32_t *)0xfe000514) +#define P_PADCTRL_GPIOX_DS_EXT ((volatile uint32_t *)0xfe000518) +#define P_PADCTRL_GPIOF_I ((volatile uint32_t *)0xfe000540) +#define P_PADCTRL_GPIOF_O ((volatile uint32_t *)0xfe000544) +#define P_PADCTRL_GPIOF_OEN ((volatile uint32_t *)0xfe000548) +#define P_PADCTRL_GPIOF_PULL_EN ((volatile uint32_t *)0xfe00054c) +#define P_PADCTRL_GPIOF_PULL_UP ((volatile uint32_t *)0xfe000550) +#define P_PADCTRL_GPIOF_DS ((volatile uint32_t *)0xfe000554) +#define P_PADCTRL_GPIOA_I ((volatile uint32_t *)0xfe000580) +#define P_PADCTRL_GPIOA_O ((volatile uint32_t *)0xfe000584) +#define P_PADCTRL_GPIOA_OEN ((volatile uint32_t *)0xfe000588) +#define P_PADCTRL_GPIOA_PULL_EN ((volatile uint32_t *)0xfe00058c) +#define P_PADCTRL_GPIOA_PULL_UP ((volatile uint32_t *)0xfe000590) +#define P_PADCTRL_GPIOA_DS ((volatile uint32_t *)0xfe000594) +#define P_PADCTRL_TESTN_I ((volatile uint32_t *)0xfe0005c0) +#define P_PADCTRL_TESTN_O ((volatile uint32_t *)0xfe0005c4) +#define P_PADCTRL_TESTN_OEN ((volatile uint32_t *)0xfe0005c8) +#define P_PADCTRL_TESTN_PULL_EN ((volatile uint32_t *)0xfe0005cc) +#define P_PADCTRL_TESTN_PULL_UP ((volatile uint32_t *)0xfe0005d0) +#define P_PADCTRL_TESTN_DS ((volatile uint32_t *)0xfe0005d4) +#define P_PADCTRL_MUTE_CTRL ((volatile uint32_t *)0xfe000600) +//======================================================================== +// APB0_CLK_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe000800 +// ----------------------------------------------- +#define P_CLKTREE_SYS_OSCIN_CTRL ((volatile uint32_t *)0xfe000800) +#define P_CLKTREE_RTC_BY_OSCIN_CTRL0 ((volatile uint32_t *)0xfe000804) +#define P_CLKTREE_RTC_BY_OSCIN_CTRL1 ((volatile uint32_t *)0xfe000808) +#define P_CLKTREE_RTC_CTRL ((volatile uint32_t *)0xfe00080c) +#define P_CLKTREE_SYS_CLK_CTRL0 ((volatile uint32_t *)0xfe000810) +#define P_CLKTREE_AXI_CLK_CTRL0 ((volatile uint32_t *)0xfe000814) +#define P_CLKTREE_SYS_CLK_EN0 ((volatile uint32_t *)0xfe00081c) +#define P_CLKTREE_SYS_CLK_EN1 ((volatile uint32_t *)0xfe000820) +#define P_CLKTREE_AXI_CLK_EN ((volatile uint32_t *)0xfe000824) +#define P_CLKTREE_DSPA_CLK_EN ((volatile uint32_t *)0xfe000828) +#define P_CLKTREE_DSPB_CLK_EN ((volatile uint32_t *)0xfe00082c) +#define P_CLKTREE_DSPA_CLK_CTRL0 ((volatile uint32_t *)0xfe000830) +#define P_CLKTREE_DSPB_CLK_CTRL0 ((volatile uint32_t *)0xfe000834) +#define P_CLKTREE_CLK12_24_CTRL ((volatile uint32_t *)0xfe000838) +#define P_CLKTREE_GEN_CLK_CTRL ((volatile uint32_t *)0xfe00083c) +#define P_CLKTREE_TIMESTAMP_CTRL0 ((volatile uint32_t *)0xfe000840) +#define P_CLKTREE_TIMESTAMP_CTRL1 ((volatile uint32_t *)0xfe000844) +#define P_CLKTREE_TIMESTAMP_CTRL2 ((volatile uint32_t *)0xfe000848) +#define P_CLKTREE_TIMESTAMP_VAL0 ((volatile uint32_t *)0xfe00084c) +#define P_CLKTREE_TIMESTAMP_VAL1 ((volatile uint32_t *)0xfe000850) +#define P_CLKTREE_TIMEBASE_CTRL0 ((volatile uint32_t *)0xfe000854) +#define P_CLKTREE_TIMEBASE_CTRL1 ((volatile uint32_t *)0xfe000858) +#define P_CLKTREE_SAR_ADC_CLK_CTRL ((volatile uint32_t *)0xfe0008c0) +#define P_CLKTREE_PWM_CLK_AB_CTRL ((volatile uint32_t *)0xfe0008c4) +#define P_CLKTREE_PWM_CLK_CD_CTRL ((volatile uint32_t *)0xfe0008c8) +#define P_CLKTREE_PWM_CLK_EF_CTRL ((volatile uint32_t *)0xfe0008cc) +#define P_CLKTREE_SPICC_CLK_CTRL ((volatile uint32_t *)0xfe0008d0) +#define P_CLKTREE_TS_CLK_CTRL ((volatile uint32_t *)0xfe0008d4) +#define P_CLKTREE_SPIFC_CLK_CTRL ((volatile uint32_t *)0xfe0008d8) +#define P_CLKTREE_USB_BUSCLK_CTRL ((volatile uint32_t *)0xfe0008dc) +#define P_CLKTREE_SD_EMMC_CLK_CTRL ((volatile uint32_t *)0xfe0008e0) +#define P_CLKTREE_CECA_CLK_CTRL0 ((volatile uint32_t *)0xfe0008e4) +#define P_CLKTREE_CECA_CLK_CTRL1 ((volatile uint32_t *)0xfe0008e8) +#define P_CLKTREE_CECB_CLK_CTRL0 ((volatile uint32_t *)0xfe0008ec) +#define P_CLKTREE_CECB_CLK_CTRL1 ((volatile uint32_t *)0xfe0008f0) +#define P_CLKTREE_PSRAM_CLK_CTRL ((volatile uint32_t *)0xfe0008f4) +#define P_CLKTREE_DMC_CLK_CTRL ((volatile uint32_t *)0xfe0008f8) +#define P_CLKTREE_FCLK_DIV1_SEL ((volatile uint32_t *)0xfe0008fc) +#define P_CLKTREE_TST_CTRL0 ((volatile uint32_t *)0xfe000900) +//======================================================================== +// APB0_CEC - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe000c00 +// ----------------------------------------------- +#define P_CECA_GEN_CNTL ((volatile uint32_t *)0xfe000c00) +#define P_CECA_RW_REG ((volatile uint32_t *)0xfe000c04) +#define P_CECA_INTR_MASKN ((volatile uint32_t *)0xfe000c08) +#define P_CECA_INTR_CLR ((volatile uint32_t *)0xfe000c0c) +#define P_CECA_INTR_STAT ((volatile uint32_t *)0xfe000c10) +#define P_CECB_GEN_CNTL ((volatile uint32_t *)0xfe000c40) +#define P_CECB_RW_REG ((volatile uint32_t *)0xfe000c44) +#define P_CECB_INTR_MASKN ((volatile uint32_t *)0xfe000c48) +#define P_CECB_INTR_CLR ((volatile uint32_t *)0xfe000c4c) +#define P_CECB_INTR_STAT ((volatile uint32_t *)0xfe000c50) +//======================================================================== +// APB0_IR_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe001000 +// ----------------------------------------------- +#define P_IRCTRL_IR_DEC_LDR_ACTIVE ((volatile uint32_t *)0xfe001000) +#define P_IRCTRL_IR_DEC_LDR_IDLE ((volatile uint32_t *)0xfe001004) +#define P_IRCTRL_IR_DEC_LDR_REPEAT ((volatile uint32_t *)0xfe001008) +#define P_IRCTRL_IR_DEC_BIT_0 ((volatile uint32_t *)0xfe00100c) +#define P_IRCTRL_IR_DEC_REG0 ((volatile uint32_t *)0xfe001010) +#define P_IRCTRL_IR_DEC_FRAME ((volatile uint32_t *)0xfe001014) +#define P_IRCTRL_IR_DEC_STATUS ((volatile uint32_t *)0xfe001018) +#define P_IRCTRL_IR_DEC_REG1 ((volatile uint32_t *)0xfe00101c) +#define P_IRCTRL_MF_IR_DEC_LDR_ACTIVE ((volatile uint32_t *)0xfe001040) +#define P_IRCTRL_MF_IR_DEC_LDR_IDLE ((volatile uint32_t *)0xfe001044) +#define P_IRCTRL_MF_IR_DEC_LDR_REPEAT ((volatile uint32_t *)0xfe001048) +#define P_IRCTRL_MF_IR_DEC_BIT_0 ((volatile uint32_t *)0xfe00104c) +#define P_IRCTRL_MF_IR_DEC_REG0 ((volatile uint32_t *)0xfe001050) +#define P_IRCTRL_MF_IR_DEC_FRAME ((volatile uint32_t *)0xfe001054) +#define P_IRCTRL_MF_IR_DEC_STATUS ((volatile uint32_t *)0xfe001058) +#define P_IRCTRL_MF_IR_DEC_REG1 ((volatile uint32_t *)0xfe00105c) +#define P_IRCTRL_MF_IR_DEC_REG2 ((volatile uint32_t *)0xfe001060) +#define P_IRCTRL_MF_IR_DEC_DURATN2 ((volatile uint32_t *)0xfe001064) +#define P_IRCTRL_MF_IR_DEC_DURATN3 ((volatile uint32_t *)0xfe001068) +#define P_IRCTRL_MF_IR_DEC_FRAME1 ((volatile uint32_t *)0xfe00106c) +#define P_IRCTRL_MF_IR_DEC_STATUS1 ((volatile uint32_t *)0xfe001070) +#define P_IRCTRL_MF_IR_DEC_STATUS2 ((volatile uint32_t *)0xfe001074) +#define P_IRCTRL_MF_IR_DEC_REG3 ((volatile uint32_t *)0xfe001078) +#define P_IRCTRL_MF_IR_DEC_FRAME_RSV0 ((volatile uint32_t *)0xfe00107c) +#define P_IRCTRL_MF_IR_DEC_FRAME_RSV1 ((volatile uint32_t *)0xfe001080) +#define P_IRCTRL_MF_IR_DEC_FILTE ((volatile uint32_t *)0xfe001084) +#define P_IRCTRL_MF_IR_DEC_IRQ_CTL ((volatile uint32_t *)0xfe001088) +#define P_IRCTRL_MF_IR_DEC_FIFO_CTL ((volatile uint32_t *)0xfe00108c) +#define P_IRCTRL_MF_IR_DEC_WIDTH_NEW ((volatile uint32_t *)0xfe001090) +#define P_IRCTRL_MF_IR_DEC_REPEAT_DET ((volatile uint32_t *)0xfe001094) +#define P_IRCTRL_IR_DEC_DEMOD_CNTL0 ((volatile uint32_t *)0xfe0010c0) +#define P_IRCTRL_IR_DEC_DEMOD_CNTL1 ((volatile uint32_t *)0xfe0010c4) +#define P_IRCTRL_IR_DEC_DEMOD_IIR_THD ((volatile uint32_t *)0xfe0010c8) +#define P_IRCTRL_IR_DEC_DEMOD_THD0 ((volatile uint32_t *)0xfe0010cc) +#define P_IRCTRL_IR_DEC_DEMOD_THD1 ((volatile uint32_t *)0xfe0010d0) +#define P_IRCTRL_IR_DEC_DEMOD_SUM_CNT0 ((volatile uint32_t *)0xfe0010d4) +#define P_IRCTRL_IR_DEC_DEMOD_SUM_CNT1 ((volatile uint32_t *)0xfe0010d8) +#define P_IRCTRL_IR_DEC_DEMOD_CNT0 ((volatile uint32_t *)0xfe0010dc) +#define P_IRCTRL_IR_DEC_DEMOD_CNT1 ((volatile uint32_t *)0xfe0010e0) +#define P_IRCTRL_IR_BLASTER_ADDR0 ((volatile uint32_t *)0xfe00110c) +#define P_IRCTRL_IR_BLASTER_ADDR1 ((volatile uint32_t *)0xfe001110) +#define P_IRCTRL_IR_BLASTER_ADDR2 ((volatile uint32_t *)0xfe001114) +#define P_IRCTRL_IR_BLASTER_ADDR3 ((volatile uint32_t *)0xfe001118) +//======================================================================== +// APB0_I2C_M - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe001400 +// ----------------------------------------------- +#define P_I2C_M_A_CONTROL_REG ((volatile uint32_t *)0xfe001400) +#define P_I2C_M_A_SLAVE_ADDR ((volatile uint32_t *)0xfe001404) +#define P_I2C_M_A_TOKEN_LIST0 ((volatile uint32_t *)0xfe001408) +#define P_I2C_M_A_TOKEN_LIST1 ((volatile uint32_t *)0xfe00140c) +#define P_I2C_M_A_WDATA_REG0 ((volatile uint32_t *)0xfe001410) +#define P_I2C_M_A_WDATA_REG1 ((volatile uint32_t *)0xfe001414) +#define P_I2C_M_A_RDATA_REG0 ((volatile uint32_t *)0xfe001418) +#define P_I2C_M_A_RDATA_REG1 ((volatile uint32_t *)0xfe00141c) +#define P_I2C_M_A_TIMEOUT_TH ((volatile uint32_t *)0xfe001420) +//======================================================================== +// APB0_I2C_S - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe001800 +// ----------------------------------------------- +#define P_I2C_S_A_CONTROL_REG ((volatile uint32_t *)0xfe001800) +#define P_I2C_S_A_SEND_REG ((volatile uint32_t *)0xfe001804) +#define P_I2C_S_A_RECV_REG ((volatile uint32_t *)0xfe001808) +#define P_I2C_S_A_CNTL1_REG ((volatile uint32_t *)0xfe00180c) +//======================================================================== +// APB0_UART_A - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe001c00 +// ----------------------------------------------- +#define P_UART_A_WFIFO ((volatile uint32_t *)0xfe001c00) +#define P_UART_A_RFIFO ((volatile uint32_t *)0xfe001c04) +#define P_UART_A_CONTROL ((volatile uint32_t *)0xfe001c08) +#define P_UART_A_STATUS ((volatile uint32_t *)0xfe001c0c) +#define P_UART_A_MISC ((volatile uint32_t *)0xfe001c10) +#define P_UART_A_REG5 ((volatile uint32_t *)0xfe001c14) +//======================================================================== +// APB0_UART_B - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe002000 +// ----------------------------------------------- +#define P_UART_B_WFIFO ((volatile uint32_t *)0xfe002000) +#define P_UART_B_RFIFO ((volatile uint32_t *)0xfe002004) +#define P_UART_B_CONTROL ((volatile uint32_t *)0xfe002008) +#define P_UART_B_STATUS ((volatile uint32_t *)0xfe00200c) +#define P_UART_B_MISC ((volatile uint32_t *)0xfe002010) +#define P_UART_B_REG5 ((volatile uint32_t *)0xfe002014) +//======================================================================== +// APB0_PWM_AB - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe002400 +// ----------------------------------------------- +#define P_PWMAB_PWM_A ((volatile uint32_t *)0xfe002400) +#define P_PWMAB_PWM_B ((volatile uint32_t *)0xfe002404) +#define P_PWMAB_MISC_REG_AB ((volatile uint32_t *)0xfe002408) +#define P_PWMAB_DELTA_SIGMA_AB ((volatile uint32_t *)0xfe00240c) +#define P_PWMAB_TIME_AB ((volatile uint32_t *)0xfe002410) +#define P_PWMAB_A2 ((volatile uint32_t *)0xfe002414) +#define P_PWMAB_B2 ((volatile uint32_t *)0xfe002418) +#define P_PWMAB_BLINK_AB ((volatile uint32_t *)0xfe00241c) +#define P_PWMAB_LOCK_AB ((volatile uint32_t *)0xfe002420) +//======================================================================== +// APB0_PWM_CD - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe002800 +// ----------------------------------------------- +#define P_PWMCD_PWM_C ((volatile uint32_t *)0xfe002800) +#define P_PWMCD_PWM_D ((volatile uint32_t *)0xfe002804) +#define P_PWMCD_MISC_REG_CD ((volatile uint32_t *)0xfe002808) +#define P_PWMCD_DELTA_SIGMA_CD ((volatile uint32_t *)0xfe00280c) +#define P_PWMCD_TIME_CD ((volatile uint32_t *)0xfe002810) +#define P_PWMCD_C2 ((volatile uint32_t *)0xfe002814) +#define P_PWMCD_D2 ((volatile uint32_t *)0xfe002818) +#define P_PWMCD_BLINK_CD ((volatile uint32_t *)0xfe00281c) +#define P_PWMCD_LOCK_CD ((volatile uint32_t *)0xfe002820) +//======================================================================== +// APB0_SARADC - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe002c00 +// ----------------------------------------------- +#define P_SAR_ADC_REG0 ((volatile uint32_t *)0xfe002c00) +#define P_SAR_ADC_CHAN_LIST ((volatile uint32_t *)0xfe002c04) +#define P_SAR_ADC_AVG_CNTL ((volatile uint32_t *)0xfe002c08) +#define P_SAR_ADC_REG3 ((volatile uint32_t *)0xfe002c0c) +#define P_SAR_ADC_DELAY ((volatile uint32_t *)0xfe002c10) +#define P_SAR_ADC_LAST_RD ((volatile uint32_t *)0xfe002c14) +#define P_SAR_ADC_FIFO_RD ((volatile uint32_t *)0xfe002c18) +#define P_SAR_ADC_AUX_SW ((volatile uint32_t *)0xfe002c1c) +#define P_SAR_ADC_CHAN_10_SW ((volatile uint32_t *)0xfe002c20) +#define P_SAR_ADC_DETECT_IDLE_SW ((volatile uint32_t *)0xfe002c24) +#define P_SAR_ADC_DELTA_10 ((volatile uint32_t *)0xfe002c28) +#define P_SAR_ADC_REG11 ((volatile uint32_t *)0xfe002c2c) +#define P_SAR_ADC_REG12 ((volatile uint32_t *)0xfe002c30) +#define P_SAR_ADC_REG13 ((volatile uint32_t *)0xfe002c34) +#define P_SAR_ADC_CHNL01 ((volatile uint32_t *)0xfe002c38) +#define P_SAR_ADC_CHNL23 ((volatile uint32_t *)0xfe002c3c) +#define P_SAR_ADC_CHNL45 ((volatile uint32_t *)0xfe002c40) +#define P_SAR_ADC_CHNL67 ((volatile uint32_t *)0xfe002c44) +//======================================================================== +// JTAGCTRL_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe003000 +// ----------------------------------------------- +#define P_JTAGCTRL_CTRL0 ((volatile uint32_t *)0xfe003000) +#define P_JTAGCTRL_PWD_CTRL0 ((volatile uint32_t *)0xfe003004) +#define P_JTAGCTRL_PWD_ADDR0 ((volatile uint32_t *)0xfe003008) +#define P_JTAGCTRL_PWD_ADDR1 ((volatile uint32_t *)0xfe00300c) +#define P_JTAGCTRL_PWD_ADDR2 ((volatile uint32_t *)0xfe003010) +#define P_JTAGCTRL_PWD_ADDR3 ((volatile uint32_t *)0xfe003014) +#define P_JTAGCTRL_PWD_VALUE0 ((volatile uint32_t *)0xfe003018) +#define P_JTAGCTRL_PWD_VALUE1 ((volatile uint32_t *)0xfe00301c) +#define P_JTAGCTRL_PWD_VALUE2 ((volatile uint32_t *)0xfe003020) +#define P_JTAGCTRL_PWD_VALUE3 ((volatile uint32_t *)0xfe003024) +#define P_JTAGCTRL_PWD_STS ((volatile uint32_t *)0xfe003028) +//======================================================================== +// APB0_MSR_CLK - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe003400 +// ----------------------------------------------- +#define P_MSR_CLK_REG0 ((volatile uint32_t *)0xfe003400) +#define P_MSR_CLK_REG1 ((volatile uint32_t *)0xfe003404) +#define P_MSR_CLK_REG2 ((volatile uint32_t *)0xfe003408) +#define P_MSR_CLK_REG3 ((volatile uint32_t *)0xfe00340c) +#define P_MSR_CLK_REG4 ((volatile uint32_t *)0xfe003410) +#define P_MSR_CLK_REG5 ((volatile uint32_t *)0xfe003414) +#define P_MSR_CLK_DUTY ((volatile uint32_t *)0xfe003418) +//======================================================================== +// APB0_SPICCA_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe003800 +// ----------------------------------------------- +#define P_SPICC_A_RXDATA ((volatile uint32_t *)0xfe003800) +#define P_SPICC_A_TXDATA ((volatile uint32_t *)0xfe003804) +#define P_SPICC_A_CONREG ((volatile uint32_t *)0xfe003808) +#define P_SPICC_A_INTREG ((volatile uint32_t *)0xfe00380c) +#define P_SPICC_A_DMAREG ((volatile uint32_t *)0xfe003810) +#define P_SPICC_A_STATREG ((volatile uint32_t *)0xfe003814) +#define P_SPICC_A_PERIODREG ((volatile uint32_t *)0xfe003818) +#define P_SPICC_A_TESTREG ((volatile uint32_t *)0xfe00381c) +#define P_SPICC_A_DRADDR ((volatile uint32_t *)0xfe003820) +#define P_SPICC_A_DWADDR ((volatile uint32_t *)0xfe003824) +#define P_SPICC_A_LD_CNTL0 ((volatile uint32_t *)0xfe003828) +#define P_SPICC_A_LD_CNTL1 ((volatile uint32_t *)0xfe00382c) +#define P_SPICC_A_LD_RADDR ((volatile uint32_t *)0xfe003830) +#define P_SPICC_A_LD_WADDR ((volatile uint32_t *)0xfe003834) +#define P_SPICC_A_ENHANCE_CNTL ((volatile uint32_t *)0xfe003838) +#define P_SPICC_A_ENHANCE_CNTL1 ((volatile uint32_t *)0xfe00383c) +#define P_SPICC_A_ENHANCE_CNTL2 ((volatile uint32_t *)0xfe003840) +//======================================================================== +// APB0_SPICCB_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe003c00 +// ----------------------------------------------- +#define P_SPICC_B_RXDATA ((volatile uint32_t *)0xfe003c00) +#define P_SPICC_B_TXDATA ((volatile uint32_t *)0xfe003c04) +#define P_SPICC_B_CONREG ((volatile uint32_t *)0xfe003c08) +#define P_SPICC_B_INTREG ((volatile uint32_t *)0xfe003c0c) +#define P_SPICC_B_DMAREG ((volatile uint32_t *)0xfe003c10) +#define P_SPICC_B_STATREG ((volatile uint32_t *)0xfe003c14) +#define P_SPICC_B_PERIODREG ((volatile uint32_t *)0xfe003c18) +#define P_SPICC_B_TESTREG ((volatile uint32_t *)0xfe003c1c) +#define P_SPICC_B_DRADDR ((volatile uint32_t *)0xfe003c20) +#define P_SPICC_B_DWADDR ((volatile uint32_t *)0xfe003c24) +#define P_SPICC_B_LD_CNTL0 ((volatile uint32_t *)0xfe003c28) +#define P_SPICC_B_LD_CNTL1 ((volatile uint32_t *)0xfe003c2c) +#define P_SPICC_B_LD_RADDR ((volatile uint32_t *)0xfe003c30) +#define P_SPICC_B_LD_WADDR ((volatile uint32_t *)0xfe003c34) +#define P_SPICC_B_ENHANCE_CNTL ((volatile uint32_t *)0xfe003c38) +#define P_SPICC_B_ENHANCE_CNTL1 ((volatile uint32_t *)0xfe003c3c) +#define P_SPICC_B_ENHANCE_CNTL2 ((volatile uint32_t *)0xfe003c40) +//======================================================================== +// USBCTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe004000 +// ----------------------------------------------- +#define P_USB_CTRL0 ((volatile uint32_t *)0xfe004000) +#define P_USB_CTRL1 ((volatile uint32_t *)0xfe004004) +#define P_USB_CTRL2 ((volatile uint32_t *)0xfe004008) +#define P_USB_CTRL3 ((volatile uint32_t *)0xfe00400c) +#define P_USB_CTRL4 ((volatile uint32_t *)0xfe004010) +#define P_USB_CTRL5 ((volatile uint32_t *)0xfe004014) +#define P_USB_CTRL6 ((volatile uint32_t *)0xfe004018) +#define P_USB_CTRL7 ((volatile uint32_t *)0xfe00401c) +#define P_USB_CTRL8 ((volatile uint32_t *)0xfe004020) +#define P_USB_CTRL9 ((volatile uint32_t *)0xfe004024) +#define P_USB_CTRL10 ((volatile uint32_t *)0xfe004028) +#define P_USB_CTRL11 ((volatile uint32_t *)0xfe00402c) +#define P_USB_CTRL12 ((volatile uint32_t *)0xfe004030) +#define P_USB_CTRL13 ((volatile uint32_t *)0xfe004034) +#define P_USB_CTRL14 ((volatile uint32_t *)0xfe004038) +#define P_USB_CTRL15 ((volatile uint32_t *)0xfe00403c) +#define P_USB_CTRL16 ((volatile uint32_t *)0xfe004040) +#define P_USB_CTRL17 ((volatile uint32_t *)0xfe004044) +#define P_USB_CTRL18 ((volatile uint32_t *)0xfe004048) +#define P_USB_CTRL19 ((volatile uint32_t *)0xfe00404c) +#define P_USB_CTRL20 ((volatile uint32_t *)0xfe004050) +#define P_USB_CTRL21 ((volatile uint32_t *)0xfe004054) +#define P_USB_CTRL22 ((volatile uint32_t *)0xfe004058) +#define P_USB_CTRL23 ((volatile uint32_t *)0xfe00405c) +#define P_USB_CTRL24 ((volatile uint32_t *)0xfe004060) +#define P_USB_CTRL25 ((volatile uint32_t *)0xfe004064) +#define P_USB_CTRL26 ((volatile uint32_t *)0xfe004068) +#define P_USB_CTRL27 ((volatile uint32_t *)0xfe00406c) +#define P_USB_CTRL28 ((volatile uint32_t *)0xfe004070) +#define P_USB_CTRL29 ((volatile uint32_t *)0xfe004074) +#define P_USB_CTRL30 ((volatile uint32_t *)0xfe004078) +#define P_USB_CTRL31 ((volatile uint32_t *)0xfe00407c) +//======================================================================== +// APB0_ACODEC_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe004800 +// ----------------------------------------------- +#define P_ACODEC_0 ((volatile uint32_t *)0xfe004800) +#define P_ACODEC_1 ((volatile uint32_t *)0xfe004804) +#define P_ACODEC_2 ((volatile uint32_t *)0xfe004808) +#define P_ACODEC_3 ((volatile uint32_t *)0xfe00480c) +#define P_ACODEC_4 ((volatile uint32_t *)0xfe004810) +#define P_ACODEC_5 ((volatile uint32_t *)0xfe004814) +#define P_ACODEC_6 ((volatile uint32_t *)0xfe004818) +#define P_ACODEC_7 ((volatile uint32_t *)0xfe00481c) +#define P_ACODEC_8 ((volatile uint32_t *)0xfe004820) +#define P_ACODEC_9 ((volatile uint32_t *)0xfe004824) +#define P_ACODEC_STS0 ((volatile uint32_t *)0xfe004840) +//======================================================================== +// APB0_TEMP_SENSOR - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe004c00 +// ----------------------------------------------- +#define P_TS_CFG_REG1 ((volatile uint32_t *)0xfe004c04) +#define P_TS_CFG_REG2 ((volatile uint32_t *)0xfe004c08) +#define P_TS_CFG_REG3 ((volatile uint32_t *)0xfe004c0c) +#define P_TS_CFG_REG4 ((volatile uint32_t *)0xfe004c10) +#define P_TS_CFG_REG5 ((volatile uint32_t *)0xfe004c14) +#define P_TS_CFG_REG6 ((volatile uint32_t *)0xfe004c18) +#define P_TS_CFG_REG7 ((volatile uint32_t *)0xfe004c1c) +#define P_TS_STAT0 ((volatile uint32_t *)0xfe004c40) +#define P_TS_STAT1 ((volatile uint32_t *)0xfe004c44) +#define P_TS_STAT2 ((volatile uint32_t *)0xfe004c48) +#define P_TS_STAT3 ((volatile uint32_t *)0xfe004c4c) +#define P_TS_STAT4 ((volatile uint32_t *)0xfe004c50) +#define P_TS_STAT5 ((volatile uint32_t *)0xfe004c54) +#define P_TS_STAT6 ((volatile uint32_t *)0xfe004c58) +#define P_TS_STAT7 ((volatile uint32_t *)0xfe004c5c) +#define P_TS_STAT8 ((volatile uint32_t *)0xfe004c60) +#define P_TS_STAT9 ((volatile uint32_t *)0xfe004c64) +//======================================================================== +// APB0_KL_EFUSE_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe005000 +// ----------------------------------------------- +// +// Reading file: ../crypto/crypto_reg.h +// +#define P_OTP_TEE_RDY ((volatile uint32_t *)0xfe005000) +#define P_OTP_TEE_CHK ((volatile uint32_t *)0xfe005004) +#define P_OTP_TEE_CFG ((volatile uint32_t *)0xfe005008) +#define P_OTP_TEE_WR_DAT0 ((volatile uint32_t *)0xfe005010) +#define P_OTP_TEE_WR_DAT1 ((volatile uint32_t *)0xfe005014) +#define P_OTP_TEE_WR_DAT2 ((volatile uint32_t *)0xfe005018) +#define P_OTP_TEE_WR_DAT3 ((volatile uint32_t *)0xfe00501c) +#define P_OTP_TEE_RD_DAT0 ((volatile uint32_t *)0xfe005020) +#define P_OTP_TEE_RD_DAT1 ((volatile uint32_t *)0xfe005024) +#define P_OTP_TEE_RD_DAT2 ((volatile uint32_t *)0xfe005028) +#define P_OTP_TEE_RD_DAT3 ((volatile uint32_t *)0xfe00502c) +#define P_OTP_RMA_PW0 ((volatile uint32_t *)0xfe005030) +#define P_OTP_RMA_PW1 ((volatile uint32_t *)0xfe005034) +#define P_OTP_RMA_PW2 ((volatile uint32_t *)0xfe005038) +#define P_OTP_RMA_PW3 ((volatile uint32_t *)0xfe00503c) +#define P_OTP_REE_RDY ((volatile uint32_t *)0xfe005040) +#define P_OTP_REE_CHK ((volatile uint32_t *)0xfe005044) +#define P_OTP_REE_CFG ((volatile uint32_t *)0xfe005048) +#define P_OTP_REE_RD_DAT0 ((volatile uint32_t *)0xfe005050) +#define P_OTP_REE_RD_DAT1 ((volatile uint32_t *)0xfe005054) +#define P_OTP_REE_RD_DAT2 ((volatile uint32_t *)0xfe005058) +#define P_OTP_REE_RD_DAT3 ((volatile uint32_t *)0xfe00505c) +#define P_OTP_LIC0 ((volatile uint32_t *)0xfe005060) +#define P_OTP_LIC1 ((volatile uint32_t *)0xfe005064) +#define P_OTP_LIC2 ((volatile uint32_t *)0xfe005068) +#define P_OTP_LIC3 ((volatile uint32_t *)0xfe00506c) +#define P_RNG_SEC_CONFIG_REG1 ((volatile uint32_t *)0xfe005104) +#define P_RNG_SEC_CONFIG_REG2 ((volatile uint32_t *)0xfe005108) +#define P_RNG_SEC_DATA ((volatile uint32_t *)0xfe005110) +#define P_RNG_SEC_STS ((volatile uint32_t *)0xfe005114) +#define P_RNG_USR_DATA ((volatile uint32_t *)0xfe005118) +#define P_RNG_USR_STS ((volatile uint32_t *)0xfe00511c) +#define P_KTE_SLOT0 ((volatile uint32_t *)0xfe005180) +#define P_KTE_SLOT1 ((volatile uint32_t *)0xfe005184) +#define P_KTE_SLOT2 ((volatile uint32_t *)0xfe005188) +#define P_KTE_SLOT3 ((volatile uint32_t *)0xfe00518c) +#define P_KTE_SLOT4 ((volatile uint32_t *)0xfe005190) +#define P_KTE_SLOT5 ((volatile uint32_t *)0xfe005194) +#define P_KTE_SLOT6 ((volatile uint32_t *)0xfe005198) +#define P_KTE_SLOT7 ((volatile uint32_t *)0xfe00519c) +#define P_MKL_TEE_RDY ((volatile uint32_t *)0xfe005200) +#define P_MKL_TEE_CHK ((volatile uint32_t *)0xfe005204) +#define P_MKL_TEE_CFG ((volatile uint32_t *)0xfe005208) +#define P_MKL_TEE_EK ((volatile uint32_t *)0xfe005210) +#define P_MKL_REE_RDY ((volatile uint32_t *)0xfe005280) +#define P_MKL_REE_CHK ((volatile uint32_t *)0xfe005284) +#define P_MKL_REE_CFG ((volatile uint32_t *)0xfe005288) +#define P_MKL_REE_EK ((volatile uint32_t *)0xfe005290) +// +// Closing file: ../crypto/crypto_reg.h +// +//======================================================================== +// APB0_PWM_EF - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe005400 +// ----------------------------------------------- +#define P_PWMEF_PWM_E ((volatile uint32_t *)0xfe005400) +#define P_PWMEF_PWM_F ((volatile uint32_t *)0xfe005404) +#define P_PWMEF_MISC_REG_EF ((volatile uint32_t *)0xfe005408) +#define P_PWMEF_DELTA_SIGMA_EF ((volatile uint32_t *)0xfe00540c) +#define P_PWMEF_TIME_EF ((volatile uint32_t *)0xfe005410) +#define P_PWMEF_E2 ((volatile uint32_t *)0xfe005414) +#define P_PWMEF_F2 ((volatile uint32_t *)0xfe005418) +#define P_PWMEF_BLINK_EF ((volatile uint32_t *)0xfe00541c) +#define P_PWMEF_LOCK_EF ((volatile uint32_t *)0xfe005420) +//======================================================================== +// APB0_SYS_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe005800 +// ----------------------------------------------- +#define P_SYSCTRL_METAL_REV0 ((volatile uint32_t *)0xfe005800) +#define P_SYSCTRL_METAL_REV1 ((volatile uint32_t *)0xfe005804) +//`define SYSCTRL_PROD_ENABLE 8'h0a +#define P_SYSCTRL_CHIP_ID ((volatile uint32_t *)0xfe00582c) +#define P_SYSCTRL_WRITEONCE1_REG0 ((volatile uint32_t *)0xfe005840) +#define P_SYSCTRL_WRITEONCE1_STICKY_REG0 ((volatile uint32_t *)0xfe005844) +#define P_SYSCTRL_WRITEONCE1_SEC_REG0 ((volatile uint32_t *)0xfe005848) +#define P_SYSCTRL_WRITEONCE1_STICKY_SEC_REG0 ((volatile uint32_t *)0xfe00584c) +#define P_SYSCTRL_WRITEONCE_REG0 ((volatile uint32_t *)0xfe005850) +#define P_SYSCTRL_WRITEONCE_REG1 ((volatile uint32_t *)0xfe005854) +#define P_SYSCTRL_WRITEONCE_SEC_REG0 ((volatile uint32_t *)0xfe005858) +#define P_SYSCTRL_WRITEONCE_STICKY_REG0 ((volatile uint32_t *)0xfe00585c) +#define P_SYSCTRL_WRITEONCE_STICKY_REG1 ((volatile uint32_t *)0xfe005860) +#define P_SYSCTRL_WRITEONCE_STICKY_SEC_REG0 ((volatile uint32_t *)0xfe005864) +#define P_SYSCTRL_TIMERA_CTRL ((volatile uint32_t *)0xfe0058c0) +#define P_SYSCTRL_TIMERA ((volatile uint32_t *)0xfe0058c4) +#define P_SYSCTRL_TIMERB_CTRL ((volatile uint32_t *)0xfe0058c8) +#define P_SYSCTRL_TIMERB ((volatile uint32_t *)0xfe0058cc) +#define P_SYSCTRL_TIMERC_CTRL ((volatile uint32_t *)0xfe0058d0) +#define P_SYSCTRL_TIMERC ((volatile uint32_t *)0xfe0058d4) +#define P_SYSCTRL_TIMERD_CTRL ((volatile uint32_t *)0xfe0058d8) +#define P_SYSCTRL_TIMERD ((volatile uint32_t *)0xfe0058dc) +#define P_SYSCTRL_SEC_TIMERA_CTRL ((volatile uint32_t *)0xfe0058e0) +#define P_SYSCTRL_SEC_TIMERA ((volatile uint32_t *)0xfe0058e4) +#define P_SYSCTRL_TIMERE_CTRL ((volatile uint32_t *)0xfe005900) +#define P_SYSCTRL_TIMERE ((volatile uint32_t *)0xfe005904) +#define P_SYSCTRL_TIMERE_HI ((volatile uint32_t *)0xfe005908) +#define P_SYSCTRL_TIMERF_CTRL ((volatile uint32_t *)0xfe00590c) +#define P_SYSCTRL_TIMERF ((volatile uint32_t *)0xfe005910) +#define P_SYSCTRL_TIMERF_HI ((volatile uint32_t *)0xfe005914) +#define P_SYSCTRL_SEC_TIMERE_CTRL ((volatile uint32_t *)0xfe005918) +#define P_SYSCTRL_SEC_TIMERE ((volatile uint32_t *)0xfe00591c) +#define P_SYSCTRL_SEC_TIMERE_HI ((volatile uint32_t *)0xfe005920) +#define P_SYSCTRL_OSC_RING_CTRL0 ((volatile uint32_t *)0xfe005940) +#define P_SYSCTRL_SEC_DDR_AXI_SEL ((volatile uint32_t *)0xfe005944) +#define P_SYSCTRL_AM2AXI_CTRL0 ((volatile uint32_t *)0xfe005948) +#define P_SYSCTRL_AM2AXI_STS ((volatile uint32_t *)0xfe00594c) +#define P_SYSCTRL_POC ((volatile uint32_t *)0xfe005980) +//`define SYSCTRL_PROD_PWD_VALUE0 8'h80 +//`define SYSCTRL_PROD_PWD_VALUE1 8'h81 +//`define SYSCTRL_PROD_PWD_VALUE2 8'h82 +//`define SYSCTRL_PROD_PWD_VALUE3 8'h83 +//`define SYSCTRL_PROD_STATUS 8'h84 +#define P_SYSCTRL_DEBUG_REG0 ((volatile uint32_t *)0xfe005a40) +#define P_SYSCTRL_DEBUG_REG1 ((volatile uint32_t *)0xfe005a44) +#define P_SYSCTRL_DEBUG_REG2 ((volatile uint32_t *)0xfe005a48) +#define P_SYSCTRL_DEBUG_REG3 ((volatile uint32_t *)0xfe005a4c) +#define P_SYSCTRL_DEBUG_REG4 ((volatile uint32_t *)0xfe005a50) +#define P_SYSCTRL_DEBUG_REG5 ((volatile uint32_t *)0xfe005a54) +#define P_SYSCTRL_DEBUG_REG6 ((volatile uint32_t *)0xfe005a58) +#define P_SYSCTRL_DEBUG_REG7 ((volatile uint32_t *)0xfe005a5c) +#define P_SYSCTRL_STATUS_REG0 ((volatile uint32_t *)0xfe005a80) +#define P_SYSCTRL_STATUS_REG1 ((volatile uint32_t *)0xfe005a84) +#define P_SYSCTRL_STATUS_REG2 ((volatile uint32_t *)0xfe005a88) +#define P_SYSCTRL_STATUS_REG3 ((volatile uint32_t *)0xfe005a8c) +#define P_SYSCTRL_STATUS_REG4 ((volatile uint32_t *)0xfe005a90) +#define P_SYSCTRL_STATUS_REG5 ((volatile uint32_t *)0xfe005a94) +#define P_SYSCTRL_STATUS_REG6 ((volatile uint32_t *)0xfe005a98) +#define P_SYSCTRL_STATUS_REG7 ((volatile uint32_t *)0xfe005a9c) +#define P_SYSCTRL_STICKY_REG0 ((volatile uint32_t *)0xfe005ac0) +#define P_SYSCTRL_STICKY_REG1 ((volatile uint32_t *)0xfe005ac4) +#define P_SYSCTRL_STICKY_REG2 ((volatile uint32_t *)0xfe005ac8) +#define P_SYSCTRL_STICKY_REG3 ((volatile uint32_t *)0xfe005acc) +#define P_SYSCTRL_STICKY_REG4 ((volatile uint32_t *)0xfe005ad0) +#define P_SYSCTRL_STICKY_REG5 ((volatile uint32_t *)0xfe005ad4) +#define P_SYSCTRL_STICKY_REG6 ((volatile uint32_t *)0xfe005ad8) +#define P_SYSCTRL_STICKY_REG7 ((volatile uint32_t *)0xfe005adc) +#define P_SYSCTRL_SEC_STATUS_REG0 ((volatile uint32_t *)0xfe005b00) +#define P_SYSCTRL_SEC_STATUS_REG1 ((volatile uint32_t *)0xfe005b04) +#define P_SYSCTRL_SEC_STATUS_REG2 ((volatile uint32_t *)0xfe005b08) +#define P_SYSCTRL_SEC_STATUS_REG3 ((volatile uint32_t *)0xfe005b0c) +#define P_SYSCTRL_SEC_STATUS_REG4 ((volatile uint32_t *)0xfe005b10) +#define P_SYSCTRL_SEC_STATUS_REG5 ((volatile uint32_t *)0xfe005b14) +#define P_SYSCTRL_SEC_STATUS_REG6 ((volatile uint32_t *)0xfe005b18) +#define P_SYSCTRL_SEC_STATUS_REG7 ((volatile uint32_t *)0xfe005b1c) +#define P_SYSCTRL_SEC_STATUS_REG8 ((volatile uint32_t *)0xfe005b20) +#define P_SYSCTRL_SEC_STATUS_REG9 ((volatile uint32_t *)0xfe005b24) +#define P_SYSCTRL_SEC_STATUS_REG10 ((volatile uint32_t *)0xfe005b28) +#define P_SYSCTRL_SEC_STATUS_REG11 ((volatile uint32_t *)0xfe005b2c) +#define P_SYSCTRL_SEC_STATUS_REG12 ((volatile uint32_t *)0xfe005b30) +#define P_SYSCTRL_SEC_STATUS_REG13 ((volatile uint32_t *)0xfe005b34) +#define P_SYSCTRL_SEC_STATUS_REG14 ((volatile uint32_t *)0xfe005b38) +#define P_SYSCTRL_SEC_STATUS_REG15 ((volatile uint32_t *)0xfe005b3c) +#define P_SYSCTRL_SEC_STATUS_REG16 ((volatile uint32_t *)0xfe005b40) +#define P_SYSCTRL_SEC_STATUS_REG17 ((volatile uint32_t *)0xfe005b44) +#define P_SYSCTRL_SEC_STATUS_REG18 ((volatile uint32_t *)0xfe005b48) +#define P_SYSCTRL_SEC_STATUS_REG19 ((volatile uint32_t *)0xfe005b4c) +#define P_SYSCTRL_SEC_STATUS_REG20 ((volatile uint32_t *)0xfe005b50) +#define P_SYSCTRL_SEC_STATUS_REG21 ((volatile uint32_t *)0xfe005b54) +#define P_SYSCTRL_SEC_STATUS_REG22 ((volatile uint32_t *)0xfe005b58) +#define P_SYSCTRL_SEC_STATUS_REG23 ((volatile uint32_t *)0xfe005b5c) +#define P_SYSCTRL_SEC_STICKY_REG0 ((volatile uint32_t *)0xfe005b80) +#define P_SYSCTRL_SEC_STICKY_REG1 ((volatile uint32_t *)0xfe005b84) +#define P_SYSCTRL_SEC_STICKY_REG2 ((volatile uint32_t *)0xfe005b88) +#define P_SYSCTRL_SEC_STICKY_REG3 ((volatile uint32_t *)0xfe005b8c) +#define P_SYSCTRL_SEC_STICKY_REG4 ((volatile uint32_t *)0xfe005b90) +#define P_SYSCTRL_SEC_STICKY_REG5 ((volatile uint32_t *)0xfe005b94) +#define P_SYSCTRL_SEC_STICKY_REG6 ((volatile uint32_t *)0xfe005b98) +#define P_SYSCTRL_SEC_STICKY_REG7 ((volatile uint32_t *)0xfe005b9c) +#define P_SYSCTRL_MSG_INDEX0_STICKY ((volatile uint32_t *)0xfe005bc0) +#define P_SYSCTRL_MSG_INDEX1_STICKY ((volatile uint32_t *)0xfe005bc4) +#define P_SYSCTRL_MSG_INDEX2_STICKY ((volatile uint32_t *)0xfe005bc8) +#define P_SYSCTRL_MSG_INDEX3_STICKY ((volatile uint32_t *)0xfe005bcc) +//======================================================================== +// APB0_I2C_M_B - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe005c00 +// ----------------------------------------------- +#define P_I2C_M_B_CONTROL_REG ((volatile uint32_t *)0xfe005c00) +#define P_I2C_M_B_SLAVE_ADDR ((volatile uint32_t *)0xfe005c04) +#define P_I2C_M_B_TOKEN_LIST0 ((volatile uint32_t *)0xfe005c08) +#define P_I2C_M_B_TOKEN_LIST1 ((volatile uint32_t *)0xfe005c0c) +#define P_I2C_M_B_WDATA_REG0 ((volatile uint32_t *)0xfe005c10) +#define P_I2C_M_B_WDATA_REG1 ((volatile uint32_t *)0xfe005c14) +#define P_I2C_M_B_RDATA_REG0 ((volatile uint32_t *)0xfe005c18) +#define P_I2C_M_B_RDATA_REG1 ((volatile uint32_t *)0xfe005c1c) +#define P_I2C_M_B_TIMEOUT_TH ((volatile uint32_t *)0xfe005c20) +//======================================================================== +// APB0_DMA - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe006000 +// ----------------------------------------------- +//TODO +//======================================================================== +// APB0_IRQ_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe006400 +// ----------------------------------------------- +#define P_IRQCTRL_IRQOUT_MASK0 ((volatile uint32_t *)0xfe006400) +#define P_IRQCTRL_IRQOUT_MASK1 ((volatile uint32_t *)0xfe006404) +#define P_IRQCTRL_IRQOUT_MASK2 ((volatile uint32_t *)0xfe006408) +#define P_IRQCTRL_IRQOUT_MASK3 ((volatile uint32_t *)0xfe00640c) +#define P_IRQCTRL_IRQOUT_INV0 ((volatile uint32_t *)0xfe006440) +#define P_IRQCTRL_IRQOUT_INV1 ((volatile uint32_t *)0xfe006444) +#define P_IRQCTRL_IRQOUT_INV2 ((volatile uint32_t *)0xfe006448) +#define P_IRQCTRL_IRQOUT_INV3 ((volatile uint32_t *)0xfe00644c) +//`define APB0_IRQIN_MASK0_CLK_USB 8'h00 +//`define APB0_IRQIN_MASK0_CLK_CPU 8'h01 +//`define APB0_IRQIN_MASK0_CLK_SYS 8'h02 +//`define APB0_IRQIN_MASK1_CLK_SYS 8'h03 +//`define APB0_IRQIN_MASK0_CLK_DSPA 8'h04 +//`define APB0_IRQIN_MASK0_CLK_DSPB 8'h05 +//`define APB0_IRQIN_CLRLVL_CLK_USB 8'h10 +//`define APB0_IRQIN_CLRLVL_CLK_DSPA 8'h11 +//`define APB0_IRQIN_CLRLVL_CLK_DSPB 8'h12 +//======================================================================== +// APB0_I2C_M - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe006800 +// ----------------------------------------------- +#define P_I2C_M_C_CONTROL_REG ((volatile uint32_t *)0xfe006800) +#define P_I2C_M_C_SLAVE_ADDR ((volatile uint32_t *)0xfe006804) +#define P_I2C_M_C_TOKEN_LIST0 ((volatile uint32_t *)0xfe006808) +#define P_I2C_M_C_TOKEN_LIST1 ((volatile uint32_t *)0xfe00680c) +#define P_I2C_M_C_WDATA_REG0 ((volatile uint32_t *)0xfe006810) +#define P_I2C_M_C_WDATA_REG1 ((volatile uint32_t *)0xfe006814) +#define P_I2C_M_C_RDATA_REG0 ((volatile uint32_t *)0xfe006818) +#define P_I2C_M_C_RDATA_REG1 ((volatile uint32_t *)0xfe00681c) +#define P_I2C_M_C_TIMEOUT_TH ((volatile uint32_t *)0xfe006820) +//======================================================================== +// APB0_I2C_M - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe006c00 +// ----------------------------------------------- +#define P_I2C_M_D_CONTROL_REG ((volatile uint32_t *)0xfe006c00) +#define P_I2C_M_D_SLAVE_ADDR ((volatile uint32_t *)0xfe006c04) +#define P_I2C_M_D_TOKEN_LIST0 ((volatile uint32_t *)0xfe006c08) +#define P_I2C_M_D_TOKEN_LIST1 ((volatile uint32_t *)0xfe006c0c) +#define P_I2C_M_D_WDATA_REG0 ((volatile uint32_t *)0xfe006c10) +#define P_I2C_M_D_WDATA_REG1 ((volatile uint32_t *)0xfe006c14) +#define P_I2C_M_D_RDATA_REG0 ((volatile uint32_t *)0xfe006c18) +#define P_I2C_M_D_RDATA_REG1 ((volatile uint32_t *)0xfe006c1c) +#define P_I2C_M_D_TIMEOUT_TH ((volatile uint32_t *)0xfe006c20) +//======================================================================== +// APB0_UART_C - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe007000 +// ----------------------------------------------- +#define P_UART_C_WFIFO ((volatile uint32_t *)0xfe007000) +#define P_UART_C_RFIFO ((volatile uint32_t *)0xfe007004) +#define P_UART_C_CONTROL ((volatile uint32_t *)0xfe007008) +#define P_UART_C_STATUS ((volatile uint32_t *)0xfe00700c) +#define P_UART_C_MISC ((volatile uint32_t *)0xfe007010) +#define P_UART_C_REG5 ((volatile uint32_t *)0xfe007014) +//======================================================================== +// APB0_PWR_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe007800 +// ----------------------------------------------- +#define P_PWRCTRL_PWR_ACK0 ((volatile uint32_t *)0xfe007800) +#define P_PWRCTRL_ISO_EN0 ((volatile uint32_t *)0xfe007804) +#define P_PWRCTRL_PWR_OFF0 ((volatile uint32_t *)0xfe007808) +#define P_PWRCTRL_SAVE_EN0 ((volatile uint32_t *)0xfe00780c) +#define P_PWRCTRL_RESTORE_EN0 ((volatile uint32_t *)0xfe007810) +#define P_PWRCTRL_MEM_PD0 ((volatile uint32_t *)0xfe007840) +#define P_PWRCTRL_MEM_PD1 ((volatile uint32_t *)0xfe007844) +#define P_PWRCTRL_MEM_PD2 ((volatile uint32_t *)0xfe007848) +#define P_PWRCTRL_MEM_PD3 ((volatile uint32_t *)0xfe00784c) +#define P_PWRCTRL_MEM_PD4 ((volatile uint32_t *)0xfe007850) +#define P_PWRCTRL_R_ISO_EN0 ((volatile uint32_t *)0xfe007880) +#define P_PWRCTRL_R_PWR_OFF0 ((volatile uint32_t *)0xfe007884) +#define P_PWRCTRL_R_MEM_PD0 ((volatile uint32_t *)0xfe007888) +#define P_PWRCTRL_R_MEM_PD1 ((volatile uint32_t *)0xfe00788c) +#define P_PWRCTRL_R_MEM_PD2 ((volatile uint32_t *)0xfe007890) +#define P_PWRCTRL_R_MEM_PD3 ((volatile uint32_t *)0xfe007894) +#define P_PWRCTRL_R_MEM_PD4 ((volatile uint32_t *)0xfe007898) +//`define PWRCTRL_MEM_PD_DSPA 8'h10 +//`define PWRCTRL_MEM_PD_DSPB 8'h11 +//`define PWRCTRL_MEM_PD_RAMA 8'h12 +//`define PWRCTRL_MEM_PD_RAMB 8'h13 +//`define PWRCTRL_MEM_PD_CPU 8'h14 +//`define PWRCTRL_MEM_PD_AUDIO 8'h20 +//`define PWRCTRL_MEM_PD_USBCTRL 8'h21 +//`define PWRCTRL_MEM_PD_SPICC 8'h22 +//`define PWRCTRL_MEM_PD_SPIFC 8'h23 +//`define PWRCTRL_MEM_PD_IR 8'h24 +//`define PWRCTRL_MEM_PD_SDIO 8'h25 +//`define PWRCTRL_MEM_PD_KLEFUSE 8'h26 +//`define PWRCTRL_MEM_PD_PSRAM 8'h27 +//`define PWRCTRL_MEM_PD_DDR 8'h28 +//`define PWRCTRL_MEM_PD_DMC 8'h29 +#define P_PWRCTRL_AUTO_OFF_CTRL ((volatile uint32_t *)0xfe0078c0) +#define P_PWRCTRL_AUTO_OFF ((volatile uint32_t *)0xfe0078c4) +#define P_PWRCTRL_AUTO_OFF_STS ((volatile uint32_t *)0xfe0078c8) +#define P_PWRCTRL_TIMER_TH_01 ((volatile uint32_t *)0xfe0078cc) +#define P_PWRCTRL_TIMER_TH_23 ((volatile uint32_t *)0xfe0078d0) +#define P_PWRCTRL_TIMER_TH_45 ((volatile uint32_t *)0xfe0078d4) +#define P_PWRCTRL_TIMER_TH_67 ((volatile uint32_t *)0xfe0078d8) +#define P_PWRCTRL_MASK_PWR_ACK0 ((volatile uint32_t *)0xfe007900) +#define P_PWRCTRL_MASK_RSTN_OFF0 ((volatile uint32_t *)0xfe007904) +#define P_PWRCTRL_MASK_RSTN_ON0 ((volatile uint32_t *)0xfe007908) +#define P_PWRCTRL_MASK_PWR_OFF0 ((volatile uint32_t *)0xfe00790c) +#define P_PWRCTRL_MASK_PWR_ON0 ((volatile uint32_t *)0xfe007910) +#define P_PWRCTRL_MASK_ISO_OFF0 ((volatile uint32_t *)0xfe007914) +#define P_PWRCTRL_MASK_ISO_ON0 ((volatile uint32_t *)0xfe007918) +#define P_PWRCTRL_MASK_MEM_OFF0 ((volatile uint32_t *)0xfe007940) +#define P_PWRCTRL_MASK_MEM_OFF1 ((volatile uint32_t *)0xfe007944) +#define P_PWRCTRL_MASK_MEM_OFF2 ((volatile uint32_t *)0xfe007948) +#define P_PWRCTRL_MASK_MEM_OFF3 ((volatile uint32_t *)0xfe00794c) +#define P_PWRCTRL_MASK_MEM_OFF4 ((volatile uint32_t *)0xfe007950) +#define P_PWRCTRL_MASK_MEM_ON0 ((volatile uint32_t *)0xfe007960) +#define P_PWRCTRL_MASK_MEM_ON1 ((volatile uint32_t *)0xfe007964) +#define P_PWRCTRL_MASK_MEM_ON2 ((volatile uint32_t *)0xfe007968) +#define P_PWRCTRL_MASK_MEM_ON3 ((volatile uint32_t *)0xfe00796c) +#define P_PWRCTRL_MASK_MEM_ON4 ((volatile uint32_t *)0xfe007970) +//======================================================================== +// APB0_ANA_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe007c00 +// ----------------------------------------------- +#define P_ANACTRL_FIXPLL_CTRL0 ((volatile uint32_t *)0xfe007c80) +#define P_ANACTRL_FIXPLL_CTRL1 ((volatile uint32_t *)0xfe007c84) +#define P_ANACTRL_FIXPLL_CTRL2 ((volatile uint32_t *)0xfe007c88) +#define P_ANACTRL_FIXPLL_CTRL3 ((volatile uint32_t *)0xfe007c8c) +#define P_ANACTRL_FIXPLL_CTRL4 ((volatile uint32_t *)0xfe007c90) +#define P_ANACTRL_FIXPLL_STS ((volatile uint32_t *)0xfe007c94) +#define P_ANACTRL_SYSPLL_CTRL0 ((volatile uint32_t *)0xfe007d00) +#define P_ANACTRL_SYSPLL_CTRL1 ((volatile uint32_t *)0xfe007d04) +#define P_ANACTRL_SYSPLL_CTRL2 ((volatile uint32_t *)0xfe007d08) +#define P_ANACTRL_SYSPLL_CTRL3 ((volatile uint32_t *)0xfe007d0c) +#define P_ANACTRL_SYSPLL_CTRL4 ((volatile uint32_t *)0xfe007d10) +#define P_ANACTRL_SYSPLL_STS ((volatile uint32_t *)0xfe007d14) +#define P_ANACTRL_HIFIPLL_CTRL0 ((volatile uint32_t *)0xfe007d40) +#define P_ANACTRL_HIFIPLL_CTRL1 ((volatile uint32_t *)0xfe007d44) +#define P_ANACTRL_HIFIPLL_CTRL2 ((volatile uint32_t *)0xfe007d48) +#define P_ANACTRL_HIFIPLL_CTRL3 ((volatile uint32_t *)0xfe007d4c) +#define P_ANACTRL_HIFIPLL_CTRL4 ((volatile uint32_t *)0xfe007d50) +#define P_ANACTRL_HIFIPLL_STS ((volatile uint32_t *)0xfe007d54) +#define P_ANACTRL_AUDDDS_CTRL0 ((volatile uint32_t *)0xfe007d80) +#define P_ANACTRL_AUDDDS_CTRL1 ((volatile uint32_t *)0xfe007d84) +#define P_ANACTRL_AUDDDS_CTRL2 ((volatile uint32_t *)0xfe007d88) +#define P_ANACTRL_AUDDDS_CTRL3 ((volatile uint32_t *)0xfe007d8c) +#define P_ANACTRL_AUDDDS_CTRL4 ((volatile uint32_t *)0xfe007d90) +#define P_ANACTRL_AUDDDS_STS ((volatile uint32_t *)0xfe007d94) +#define P_ANACTRL_MISCTOP_CTRL0 ((volatile uint32_t *)0xfe007dc0) +#define P_ANACTRL_POR_CNTL ((volatile uint32_t *)0xfe007e08) +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe020000 +// ----------------------------------------------- +#define P_RSA_BASE ((volatile uint32_t *)0xfe020000) +//======================================================================== +// CPUCTRL_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB1_BASE_ADDR = 0xfd000000 +// ----------------------------------------------- +#define P_CPUCTRL_CTRL0 ((volatile uint32_t *)0xfd000000) +#define P_CPUCTRL_CTRL1 ((volatile uint32_t *)0xfd000004) +#define P_CPUCTRL_CTRL2 ((volatile uint32_t *)0xfd000008) +#define P_CPUCTRL_CTRL3 ((volatile uint32_t *)0xfd00000c) +#define P_CPUCTRL_CTRL4 ((volatile uint32_t *)0xfd000010) +#define P_CPUCTRL_CTRL5 ((volatile uint32_t *)0xfd000014) +#define P_CPUCTRL_CTRL6 ((volatile uint32_t *)0xfd000018) +#define P_CPUCTRL_CTRL7 ((volatile uint32_t *)0xfd00001c) +#define P_CPUCTRL_CTRL8 ((volatile uint32_t *)0xfd000020) +#define P_CPUCTRL_CTRL9 ((volatile uint32_t *)0xfd000024) +#define P_CPUCTRL_CTRL10 ((volatile uint32_t *)0xfd000028) +#define P_CPUCTRL_CTRL11 ((volatile uint32_t *)0xfd00002c) +#define P_CPUCTRL_CTRL12 ((volatile uint32_t *)0xfd000030) +#define P_CPUCTRL_CTRL13 ((volatile uint32_t *)0xfd000034) +#define P_CPUCTRL_CTRL14 ((volatile uint32_t *)0xfd000038) +#define P_CPUCTRL_CTRL15 ((volatile uint32_t *)0xfd00003c) +#define P_CPUCTRL_STS0 ((volatile uint32_t *)0xfd000040) +#define P_CPUCTRL_STS1 ((volatile uint32_t *)0xfd000044) +#define P_CPUCTRL_STS2 ((volatile uint32_t *)0xfd000048) +#define P_CPUCTRL_STS3 ((volatile uint32_t *)0xfd00004c) +#define P_CPUCTRL_STS4 ((volatile uint32_t *)0xfd000050) +#define P_CPUCTRL_STS5 ((volatile uint32_t *)0xfd000054) +#define P_CPUCTRL_STS6 ((volatile uint32_t *)0xfd000058) +#define P_CPUCTRL_STS7 ((volatile uint32_t *)0xfd00005c) +#define P_CPUCTRL_STS8 ((volatile uint32_t *)0xfd000060) +#define P_CPUCTRL_STS9 ((volatile uint32_t *)0xfd000064) +#define P_CPUCTRL_CLK_CTRL0 ((volatile uint32_t *)0xfd000080) +#define P_CPUCTRL_CLK_CTRL1 ((volatile uint32_t *)0xfd000084) +#define P_CPUCTRL_CLK_CTRL2 ((volatile uint32_t *)0xfd000088) +#define P_CPUCTRL_CLK_CTRL3 ((volatile uint32_t *)0xfd00008c) +#define P_CPUCTRL_CLK_CTRL4 ((volatile uint32_t *)0xfd000090) +#define P_CPUCTRL_CLK_CTRL5 ((volatile uint32_t *)0xfd000094) +#define P_CPUCTRL_CLK_CTRL6 ((volatile uint32_t *)0xfd000098) +#define P_CPUCTRL_CLK_CTRL7 ((volatile uint32_t *)0xfd00009c) +#define P_CPUCTRL_RESET_CTRL ((volatile uint32_t *)0xfd0000c0) +#define P_CPUCTRL_ROM_DISABLE ((volatile uint32_t *)0xfd0000c4) +//======================================================================== +// RAMA_SEC_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB1_BASE_ADDR = 0xfd000800 +// ----------------------------------------------- +#define P_SRAM_RANGE0_STA ((volatile uint32_t *)0xfd000800) +#define P_SRAM_RANGE1_STA ((volatile uint32_t *)0xfd000804) +#define P_SRAM_RANGE2_STA ((volatile uint32_t *)0xfd000808) +#define P_SRAM_RANGE3_STA ((volatile uint32_t *)0xfd00080c) +#define P_SRAM_RANGE4_STA ((volatile uint32_t *)0xfd000810) +#define P_SRAM_RANGE5_STA ((volatile uint32_t *)0xfd000814) +#define P_SRAM_RANGE6_STA ((volatile uint32_t *)0xfd000818) +#define P_SRAM_RANGE0_EDA ((volatile uint32_t *)0xfd00081c) +#define P_SRAM_RANGE1_EDA ((volatile uint32_t *)0xfd000820) +#define P_SRAM_RANGE2_EDA ((volatile uint32_t *)0xfd000824) +#define P_SRAM_RANGE3_EDA ((volatile uint32_t *)0xfd000828) +#define P_SRAM_RANGE4_EDA ((volatile uint32_t *)0xfd00082c) +#define P_SRAM_RANGE5_EDA ((volatile uint32_t *)0xfd000830) +#define P_SRAM_RANGE6_EDA ((volatile uint32_t *)0xfd000834) +#define P_SRAM_RANGE0_CTRL0 ((volatile uint32_t *)0xfd000838) +#define P_SRAM_RANGE1_CTRL0 ((volatile uint32_t *)0xfd00083c) +#define P_SRAM_RANGE2_CTRL0 ((volatile uint32_t *)0xfd000840) +#define P_SRAM_RANGE3_CTRL0 ((volatile uint32_t *)0xfd000844) +#define P_SRAM_RANGE4_CTRL0 ((volatile uint32_t *)0xfd000848) +#define P_SRAM_RANGE5_CTRL0 ((volatile uint32_t *)0xfd00084c) +#define P_SRAM_RANGE6_CTRL0 ((volatile uint32_t *)0xfd000850) +#define P_SRAM_RANGE7_CTRL0 ((volatile uint32_t *)0xfd000854) +#define P_SRAM_RANGE0_CTRL1 ((volatile uint32_t *)0xfd000858) +#define P_SRAM_RANGE1_CTRL1 ((volatile uint32_t *)0xfd00085c) +#define P_SRAM_RANGE2_CTRL1 ((volatile uint32_t *)0xfd000860) +#define P_SRAM_RANGE3_CTRL1 ((volatile uint32_t *)0xfd000864) +#define P_SRAM_RANGE4_CTRL1 ((volatile uint32_t *)0xfd000868) +#define P_SRAM_RANGE5_CTRL1 ((volatile uint32_t *)0xfd00086c) +#define P_SRAM_RANGE6_CTRL1 ((volatile uint32_t *)0xfd000870) +#define P_SRAM_RANGE7_CTRL1 ((volatile uint32_t *)0xfd000874) +#define P_SRAM_SEC_CTRL0 ((volatile uint32_t *)0xfd000878) +#define P_SRAM_REG_LOCK ((volatile uint32_t *)0xfd00087c) +//======================================================================== +// RAMB_SEC_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB1_BASE_ADDR = 0xfd000c00 +// ----------------------------------------------- +#define P_SRAM_RANGE0_STA_B ((volatile uint32_t *)0xfd000c00) +#define P_SRAM_RANGE1_STA_B ((volatile uint32_t *)0xfd000c04) +#define P_SRAM_RANGE2_STA_B ((volatile uint32_t *)0xfd000c08) +#define P_SRAM_RANGE3_STA_B ((volatile uint32_t *)0xfd000c0c) +#define P_SRAM_RANGE4_STA_B ((volatile uint32_t *)0xfd000c10) +#define P_SRAM_RANGE5_STA_B ((volatile uint32_t *)0xfd000c14) +#define P_SRAM_RANGE6_STA_B ((volatile uint32_t *)0xfd000c18) +#define P_SRAM_RANGE0_EDA_B ((volatile uint32_t *)0xfd000c1c) +#define P_SRAM_RANGE1_EDA_B ((volatile uint32_t *)0xfd000c20) +#define P_SRAM_RANGE2_EDA_B ((volatile uint32_t *)0xfd000c24) +#define P_SRAM_RANGE3_EDA_B ((volatile uint32_t *)0xfd000c28) +#define P_SRAM_RANGE4_EDA_B ((volatile uint32_t *)0xfd000c2c) +#define P_SRAM_RANGE5_EDA_B ((volatile uint32_t *)0xfd000c30) +#define P_SRAM_RANGE6_EDA_B ((volatile uint32_t *)0xfd000c34) +#define P_SRAM_RANGE0_CTRL0_B ((volatile uint32_t *)0xfd000c38) +#define P_SRAM_RANGE1_CTRL0_B ((volatile uint32_t *)0xfd000c3c) +#define P_SRAM_RANGE2_CTRL0_B ((volatile uint32_t *)0xfd000c40) +#define P_SRAM_RANGE3_CTRL0_B ((volatile uint32_t *)0xfd000c44) +#define P_SRAM_RANGE4_CTRL0_B ((volatile uint32_t *)0xfd000c48) +#define P_SRAM_RANGE5_CTRL0_B ((volatile uint32_t *)0xfd000c4c) +#define P_SRAM_RANGE6_CTRL0_B ((volatile uint32_t *)0xfd000c50) +#define P_SRAM_RANGE7_CTRL0_B ((volatile uint32_t *)0xfd000c54) +#define P_SRAM_RANGE0_CTRL1_B ((volatile uint32_t *)0xfd000c58) +#define P_SRAM_RANGE1_CTRL1_B ((volatile uint32_t *)0xfd000c5c) +#define P_SRAM_RANGE2_CTRL1_B ((volatile uint32_t *)0xfd000c60) +#define P_SRAM_RANGE3_CTRL1_B ((volatile uint32_t *)0xfd000c64) +#define P_SRAM_RANGE4_CTRL1_B ((volatile uint32_t *)0xfd000c68) +#define P_SRAM_RANGE5_CTRL1_B ((volatile uint32_t *)0xfd000c6c) +#define P_SRAM_RANGE6_CTRL1_B ((volatile uint32_t *)0xfd000c70) +#define P_SRAM_RANGE7_CTRL1_B ((volatile uint32_t *)0xfd000c74) +#define P_SRAM_SEC_CTRL0_B ((volatile uint32_t *)0xfd000c78) +#define P_SRAM_REG_LOCK_B ((volatile uint32_t *)0xfd000c7c) +// +// Reading file: REG_LIST_DSP_RTL.h +// +// synopsys translate_off +// synopsys translate_on +//======================================================================== +// DSPA - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe030000 +// ----------------------------------------------- +#define P_DSP_CFG0 ((volatile uint32_t *)0xfe030000) +#define P_DSP_CFG1 ((volatile uint32_t *)0xfe030004) +#define P_DSP_CFG2 ((volatile uint32_t *)0xfe030008) +#define P_DSP_IMPWIRE ((volatile uint32_t *)0xfe03000c) +#define P_DSP_RESET_VEC ((volatile uint32_t *)0xfe030010) +#define P_DSP_SEC_CFG0 ((volatile uint32_t *)0xfe030018) +#define P_DSP_SEC_CFG1 ((volatile uint32_t *)0xfe03001c) +#define P_DSP_IRQ_CTRL0 ((volatile uint32_t *)0xfe030040) +#define P_DSP_IRQ_CTRL1 ((volatile uint32_t *)0xfe030044) +#define P_DSP_IRQ_CTRL2 ((volatile uint32_t *)0xfe030048) +#define P_DSP_IRQ_CTRL3 ((volatile uint32_t *)0xfe03004c) +#define P_DSP_IRQ_CTRL4 ((volatile uint32_t *)0xfe030050) +#define P_DSP_IRQ_CTRL5 ((volatile uint32_t *)0xfe030054) +#define P_DSP_IRQ_CTRL6 ((volatile uint32_t *)0xfe030058) +#define P_DSP_IRQ_CTRL7 ((volatile uint32_t *)0xfe03005c) +#define P_DSP_IRQ_CTRL8 ((volatile uint32_t *)0xfe030060) +#define P_DSP_IRQ_STS ((volatile uint32_t *)0xfe03007c) +#define P_DSP_REMAP0 ((volatile uint32_t *)0xfe030080) +#define P_DSP_REMAP1 ((volatile uint32_t *)0xfe030084) +#define P_DSP_REMAP2 ((volatile uint32_t *)0xfe030088) +#define P_DSP_STS0 ((volatile uint32_t *)0xfe030100) +#define P_DSP_STS1 ((volatile uint32_t *)0xfe030104) +#define P_DSP_STS2 ((volatile uint32_t *)0xfe030108) +#define P_DSP_STS3 ((volatile uint32_t *)0xfe03010c) +#define P_DSP_STS4 ((volatile uint32_t *)0xfe030110) +#define P_DSP_STS5 ((volatile uint32_t *)0xfe030114) +#define P_DSP_MAILBOX_SET_0 ((volatile uint32_t *)0xfe030140) +#define P_DSP_MAILBOX_SET_1 ((volatile uint32_t *)0xfe030144) +#define P_DSP_MAILBOX_SET_2 ((volatile uint32_t *)0xfe030148) +#define P_DSP_MAILBOX_SET_3 ((volatile uint32_t *)0xfe03014c) +#define P_DSP_MAILBOX_SET_4 ((volatile uint32_t *)0xfe030150) +#define P_DSP_MAILBOX_SET_5 ((volatile uint32_t *)0xfe030154) +#define P_DSP_MAILBOX_SET_6 ((volatile uint32_t *)0xfe030158) +#define P_DSP_MAILBOX_SET_7 ((volatile uint32_t *)0xfe03015c) +#define P_DSP_MAILBOX_SET_8 ((volatile uint32_t *)0xfe030160) +#define P_DSP_MAILBOX_SET_9 ((volatile uint32_t *)0xfe030164) +#define P_DSP_MAILBOX_SET_10 ((volatile uint32_t *)0xfe030168) +#define P_DSP_MAILBOX_SET_11 ((volatile uint32_t *)0xfe03016c) +#define P_DSP_MAILBOX_CLR_0 ((volatile uint32_t *)0xfe030180) +#define P_DSP_MAILBOX_CLR_1 ((volatile uint32_t *)0xfe030184) +#define P_DSP_MAILBOX_CLR_2 ((volatile uint32_t *)0xfe030188) +#define P_DSP_MAILBOX_CLR_3 ((volatile uint32_t *)0xfe03018c) +#define P_DSP_MAILBOX_CLR_4 ((volatile uint32_t *)0xfe030190) +#define P_DSP_MAILBOX_CLR_5 ((volatile uint32_t *)0xfe030194) +#define P_DSP_MAILBOX_CLR_6 ((volatile uint32_t *)0xfe030198) +#define P_DSP_MAILBOX_CLR_7 ((volatile uint32_t *)0xfe03019c) +#define P_DSP_MAILBOX_CLR_8 ((volatile uint32_t *)0xfe0301a0) +#define P_DSP_MAILBOX_CLR_9 ((volatile uint32_t *)0xfe0301a4) +#define P_DSP_MAILBOX_CLR_10 ((volatile uint32_t *)0xfe0301a8) +#define P_DSP_MAILBOX_CLR_11 ((volatile uint32_t *)0xfe0301ac) +#define P_DSP_MAILBOX_STAT_0 ((volatile uint32_t *)0xfe0301c0) +#define P_DSP_MAILBOX_STAT_1 ((volatile uint32_t *)0xfe0301c4) +#define P_DSP_MAILBOX_STAT_2 ((volatile uint32_t *)0xfe0301c8) +#define P_DSP_MAILBOX_STAT_3 ((volatile uint32_t *)0xfe0301cc) +#define P_DSP_MAILBOX_STAT_4 ((volatile uint32_t *)0xfe0301d0) +#define P_DSP_MAILBOX_STAT_5 ((volatile uint32_t *)0xfe0301d4) +#define P_DSP_MAILBOX_STAT_6 ((volatile uint32_t *)0xfe0301d8) +#define P_DSP_MAILBOX_STAT_7 ((volatile uint32_t *)0xfe0301dc) +#define P_DSP_MAILBOX_STAT_8 ((volatile uint32_t *)0xfe0301e0) +#define P_DSP_MAILBOX_STAT_9 ((volatile uint32_t *)0xfe0301e4) +#define P_DSP_MAILBOX_STAT_10 ((volatile uint32_t *)0xfe0301e8) +#define P_DSP_MAILBOX_STAT_11 ((volatile uint32_t *)0xfe0301ec) +#define P_DSP_QIF_CTRL ((volatile uint32_t *)0xfe030200) +#define P_DSP_QIF_STS ((volatile uint32_t *)0xfe030204) +#define P_DSP_WRFIFO_TOCPUA ((volatile uint32_t *)0xfe030208) +#define P_DSP_WRFIFO_TOCPUB ((volatile uint32_t *)0xfe03020c) +#define P_DSP_WRFIFO_TODSP ((volatile uint32_t *)0xfe030210) +#define P_DSP_RDFIFO_FRCPUA ((volatile uint32_t *)0xfe030220) +#define P_DSP_RDFIFO_FRCPUB ((volatile uint32_t *)0xfe030224) +#define P_DSP_RDFIFO_FRDSP ((volatile uint32_t *)0xfe030228) +//======================================================================== +// DSPB - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe040000 +// ----------------------------------------------- +#define P_DSPB_CFG0 ((volatile uint32_t *)0xfe040000) +#define P_DSPB_CFG1 ((volatile uint32_t *)0xfe040004) +#define P_DSPB_CFG2 ((volatile uint32_t *)0xfe040008) +#define P_DSPB_IMPWIRE ((volatile uint32_t *)0xfe04000c) +#define P_DSPB_RESET_VEC ((volatile uint32_t *)0xfe040010) +#define P_DSPB_SEC_CFG0 ((volatile uint32_t *)0xfe040018) +#define P_DSPB_SEC_CFG1 ((volatile uint32_t *)0xfe04001c) +#define P_DSPB_IRQ_CTRL0 ((volatile uint32_t *)0xfe040040) +#define P_DSPB_IRQ_CTRL1 ((volatile uint32_t *)0xfe040044) +#define P_DSPB_IRQ_CTRL2 ((volatile uint32_t *)0xfe040048) +#define P_DSPB_IRQ_CTRL3 ((volatile uint32_t *)0xfe04004c) +#define P_DSPB_IRQ_CTRL4 ((volatile uint32_t *)0xfe040050) +#define P_DSPB_IRQ_CTRL5 ((volatile uint32_t *)0xfe040054) +#define P_DSPB_IRQ_CTRL6 ((volatile uint32_t *)0xfe040058) +#define P_DSPB_IRQ_CTRL7 ((volatile uint32_t *)0xfe04005c) +#define P_DSPB_IRQ_CTRL8 ((volatile uint32_t *)0xfe040060) +#define P_DSPB_IRQ_STS ((volatile uint32_t *)0xfe04007c) +#define P_DSPB_REMAP0 ((volatile uint32_t *)0xfe040080) +#define P_DSPB_REMAP1 ((volatile uint32_t *)0xfe040084) +#define P_DSPB_REMAP2 ((volatile uint32_t *)0xfe040088) +#define P_DSPB_STS0 ((volatile uint32_t *)0xfe040100) +#define P_DSPB_STS1 ((volatile uint32_t *)0xfe040104) +#define P_DSPB_STS2 ((volatile uint32_t *)0xfe040108) +#define P_DSPB_STS3 ((volatile uint32_t *)0xfe04010c) +#define P_DSPB_STS4 ((volatile uint32_t *)0xfe040110) +#define P_DSPB_STS5 ((volatile uint32_t *)0xfe040114) +#define P_DSPB_MAILBOX_SET_0 ((volatile uint32_t *)0xfe040140) +#define P_DSPB_MAILBOX_SET_1 ((volatile uint32_t *)0xfe040144) +#define P_DSPB_MAILBOX_SET_2 ((volatile uint32_t *)0xfe040148) +#define P_DSPB_MAILBOX_SET_3 ((volatile uint32_t *)0xfe04014c) +#define P_DSPB_MAILBOX_SET_4 ((volatile uint32_t *)0xfe040150) +#define P_DSPB_MAILBOX_SET_5 ((volatile uint32_t *)0xfe040154) +#define P_DSPB_MAILBOX_SET_6 ((volatile uint32_t *)0xfe040158) +#define P_DSPB_MAILBOX_SET_7 ((volatile uint32_t *)0xfe04015c) +#define P_DSPB_MAILBOX_SET_8 ((volatile uint32_t *)0xfe040160) +#define P_DSPB_MAILBOX_SET_9 ((volatile uint32_t *)0xfe040164) +#define P_DSPB_MAILBOX_SET_10 ((volatile uint32_t *)0xfe040168) +#define P_DSPB_MAILBOX_SET_11 ((volatile uint32_t *)0xfe04016c) +#define P_DSPB_MAILBOX_CLR_0 ((volatile uint32_t *)0xfe040180) +#define P_DSPB_MAILBOX_CLR_1 ((volatile uint32_t *)0xfe040184) +#define P_DSPB_MAILBOX_CLR_2 ((volatile uint32_t *)0xfe040188) +#define P_DSPB_MAILBOX_CLR_3 ((volatile uint32_t *)0xfe04018c) +#define P_DSPB_MAILBOX_CLR_4 ((volatile uint32_t *)0xfe040190) +#define P_DSPB_MAILBOX_CLR_5 ((volatile uint32_t *)0xfe040194) +#define P_DSPB_MAILBOX_CLR_6 ((volatile uint32_t *)0xfe040198) +#define P_DSPB_MAILBOX_CLR_7 ((volatile uint32_t *)0xfe04019c) +#define P_DSPB_MAILBOX_CLR_8 ((volatile uint32_t *)0xfe0401a0) +#define P_DSPB_MAILBOX_CLR_9 ((volatile uint32_t *)0xfe0401a4) +#define P_DSPB_MAILBOX_CLR_10 ((volatile uint32_t *)0xfe0401a8) +#define P_DSPB_MAILBOX_CLR_11 ((volatile uint32_t *)0xfe0401ac) +#define P_DSPB_MAILBOX_STAT_0 ((volatile uint32_t *)0xfe0401c0) +#define P_DSPB_MAILBOX_STAT_1 ((volatile uint32_t *)0xfe0401c4) +#define P_DSPB_MAILBOX_STAT_2 ((volatile uint32_t *)0xfe0401c8) +#define P_DSPB_MAILBOX_STAT_3 ((volatile uint32_t *)0xfe0401cc) +#define P_DSPB_MAILBOX_STAT_4 ((volatile uint32_t *)0xfe0401d0) +#define P_DSPB_MAILBOX_STAT_5 ((volatile uint32_t *)0xfe0401d4) +#define P_DSPB_MAILBOX_STAT_6 ((volatile uint32_t *)0xfe0401d8) +#define P_DSPB_MAILBOX_STAT_7 ((volatile uint32_t *)0xfe0401dc) +#define P_DSPB_MAILBOX_STAT_8 ((volatile uint32_t *)0xfe0401e0) +#define P_DSPB_MAILBOX_STAT_9 ((volatile uint32_t *)0xfe0401e4) +#define P_DSPB_MAILBOX_STAT_10 ((volatile uint32_t *)0xfe0401e8) +#define P_DSPB_MAILBOX_STAT_11 ((volatile uint32_t *)0xfe0401ec) +#define P_DSPB_QIF_CTRL ((volatile uint32_t *)0xfe040200) +#define P_DSPB_QIF_STS ((volatile uint32_t *)0xfe040204) +#define P_DSPB_WRFIFO_TOCPUA ((volatile uint32_t *)0xfe040208) +#define P_DSPB_WRFIFO_TOCPUB ((volatile uint32_t *)0xfe04020c) +#define P_DSPB_WRFIFO_TODSP ((volatile uint32_t *)0xfe040210) +#define P_DSPB_RDFIFO_FRCPUA ((volatile uint32_t *)0xfe040220) +#define P_DSPB_RDFIFO_FRCPUB ((volatile uint32_t *)0xfe040224) +#define P_DSPB_RDFIFO_FRDSP ((volatile uint32_t *)0xfe040228) +// synopsys translate_off +// synopsys translate_on +// +// Closing file: REG_LIST_DSP_RTL.h +// +// synopsys translate_off +// synopsys translate_on +// +// Closing file: ./REG_LIST_RTL.h +// + +#endif // P_REGISTER_H +
diff --git a/arch/arm/include/asm/arch-c1/pinctrl_init.h b/arch/arm/include/asm/arch-c1/pinctrl_init.h new file mode 100644 index 0000000..cfbc42a --- /dev/null +++ b/arch/arm/include/asm/arch-c1/pinctrl_init.h
@@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef _MESON_PINCTRL_INIT_H_ +#define _MESON_PINCTRL_INIT_H_ + +#define PIN_CONTROLLER_NUM 2 +extern int pinctrl_devices_active(int pinctrl_num); + +#endif /* _MESON_PINCTRL_INIT_H_ */
diff --git a/arch/arm/include/asm/arch-c1/pll.h b/arch/arm/include/asm/arch-c1/pll.h new file mode 100644 index 0000000..5821c3c --- /dev/null +++ b/arch/arm/include/asm/arch-c1/pll.h
@@ -0,0 +1,133 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __PLL_H +#define __PLL_H + +#define PLL_TEST_SYS_TOTAL 8 +#define PLL_TEST_HDMI_TOTAL 3 + +typedef struct sys_pll_set_s { + unsigned int cpu_clk; + unsigned int pll_cntl0; + unsigned int pll_cntl1; + unsigned int pll_cntl2; + unsigned int pll_cntl3; + unsigned int pll_cntl4; +}sys_pll_set_t; + +typedef struct sys_pll_cfg_s { + sys_pll_set_t sys_pll[PLL_TEST_SYS_TOTAL]; +}sys_pll_cfg_t; + +typedef struct hifi_pll_set_s { + unsigned int pll_clk; + unsigned int pll_cntl0; + unsigned int pll_cntl1; + unsigned int pll_cntl2; + unsigned int pll_cntl3; + unsigned int pll_cntl4; +}hifi_pll_set_t; + + +#if 0 +unsigned int fix_pll_cfg[6] = { + /* CNTL, CNTL2, CNTL3, CNTL4, CNTL5, CNTL6*/ + /*2G*/ 0x600006FA, 0x59C80000, 0xCA753822, 0x00010006, 0x95520E1A, 0xFC454545, +}; + +unsigned int ddr_pll_cfg[][6] = { + {0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0}, +}; +#endif + +typedef struct hifipll_rate_table_s { + unsigned int rate; + unsigned int m; + unsigned int n; + unsigned int od; +}hifipll_rate_table_t; + +typedef struct gpll_rate_table_s { + unsigned int rate; + unsigned int m; + unsigned int n; + unsigned int od; +}gpll_rate_table_t; + +typedef struct ddspll_rate_table_t { + unsigned int RATE; + unsigned int CTS; + unsigned int N; +}ddspll_rate_table_t; + +typedef struct gp_pll_set_s { + unsigned int pll_clk; + unsigned int pll_cntl0; + unsigned int pll_cntl1; + unsigned int pll_cntl2; + unsigned int pll_cntl3; + unsigned int pll_cntl4; + unsigned int pll_cntl5; +}gp_pll_set_t; + +typedef struct dds_pll_set_s { + unsigned int pll_clk; + unsigned int misctop_cntl0; + unsigned int pll_cntl0; + unsigned int pll_cntl1; + unsigned int pll_cntl2; + unsigned int pll_cntl3; + unsigned int pll_cntl4; +}dds_pll_set_t; + +typedef struct usbphy_pll_set_s { + unsigned int pll_clk; + unsigned int pll_cntl0; + unsigned int pll_cntl1; + unsigned int pll_cntl2; +}usbphy_pll_set_t; + +typedef struct ethphy_pll_set_s { + unsigned int pll_clk; + unsigned int pll_cntl0; + unsigned int pll_cntl1; + unsigned int pll_cntl2; +}ethphy_pll_set_t; + +#if 0 +unsigned int hdmi_pll_cfg[][7] = { + /* get from enc_clk_config.c */ + /* freq, cntl, cntl1, cntl2, cntl3, cntl4, cntl5 */ + {5940000, 0x4000027b, 0x800cb300, 0xc60f30e0, 0x0c8e0000, 0x001fa729, 0x01a31500}, + {5405400, 0x400002e1, 0x800cb0e6, 0x860f30c4, 0x0c8e0000, 0x001fa729, 0x01a31500}, + {4455000, 0x400002b9, 0x800cb280, 0x860f30c4, 0x0c8e0000, 0x001fa729, 0x01a31500}, + {4324320, 0x400002b4, 0x800cb0b8, 0x860f30c4, 0x0c8e0000, 0x001fa729, 0x01a31500}, + {3712500, 0x4000029a, 0x800cb2c0, 0x860f30c4, 0x0c8e0000, 0x001fa729, 0x01a31500}, + {3450000, 0x4000028f, 0x800cb300, 0x860f30c4, 0x0c8e0000, 0x001fa729, 0x01a31500}, + {3243240, 0x40000287, 0x800cb08a, 0x860f30c4, 0x0c8e0000, 0x001fa729, 0x01a31500}, + {2970000, 0x4000027b, 0x800cb300, 0x860f30c4, 0x0c8e0000, 0x001fa729, 0x01a31500}, +}; +#endif + +enum pll_enum { + PLL_SYS = 0, + PLL_FIX, + PLL_DDR, + PLL_HIFI, + PLL_GP, + PLL_DDS, + PLL_USBPHY, + PLL_ETHPHY, + PLL_ENUM, +}; +int pll_test(int argc, char * const argv[]); + +#endif /* __PLL_H */ \ No newline at end of file
diff --git a/arch/arm/include/asm/arch-c1/pwr_ctrl.h b/arch/arm/include/asm/arch-c1/pwr_ctrl.h new file mode 100644 index 0000000..15d4baa --- /dev/null +++ b/arch/arm/include/asm/arch-c1/pwr_ctrl.h
@@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#define PWR_ON 1 +#define PWR_OFF 0 + +enum pm_e { + PM_CPU_PWR0, + PM_CPU_CORE0, + PM_CPU_CORE1, + PM_DSP_A = 8, + PM_DSP_B, + PM_UART, + PM_DMC, + PM_I2C, + PM_SDEMMC_B, + PM_ACODEC, + PM_AUDIO, + PM_MKL_OTP, + PM_DMA, + PM_SDEMMC_A, + PM_SRAM_A, + PM_SRAM_B, + PM_IR, + PM_SPICC, + PM_SPIFC, + PM_USB, + PM_NIC, + PM_PDM, + PM_RSA, + PM_MIPI_ISP, + PM_HCODEC, + PM_WAVE, + PM_SDEMMC_C, + PM_SRAM_C, + PM_GDC, + PM_GE2D, + PM_NNA, + PM_ETH, + PM_GIC, + PM_DDR, + PM_SPICC_B +}; + +unsigned long pwr_ctrl_psci_smc(unsigned int power_domain, bool power_control); \ No newline at end of file
diff --git a/arch/arm/include/asm/arch-c1/register.h b/arch/arm/include/asm/arch-c1/register.h new file mode 100644 index 0000000..34a8114 --- /dev/null +++ b/arch/arm/include/asm/arch-c1/register.h
@@ -0,0 +1,7225 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifdef REGISTER_H +#else +#define REGISTER_H + +// +// Reading file: ./REG_LIST_RTL.h +// +// synopsys translate_off +// synopsys translate_on +// +// Reading file: REG_LIST_AUDIO_RTL.h +// +//======================================================================== +// AUDIO - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe050000 +// ----------------------------------------------- +#define EE_AUDIO_CLK_GATE_EN0 ((0x0000 << 2) + 0xfe050000) +#define EE_AUDIO_CLK_GATE_EN1 ((0x0001 << 2) + 0xfe050000) +#define EE_AUDIO_MCLK_A_CTRL ((0x0002 << 2) + 0xfe050000) +#define EE_AUDIO_MCLK_B_CTRL ((0x0003 << 2) + 0xfe050000) +#define EE_AUDIO_MCLK_C_CTRL ((0x0004 << 2) + 0xfe050000) +#define EE_AUDIO_MCLK_D_CTRL ((0x0005 << 2) + 0xfe050000) +#define EE_AUDIO_MCLK_E_CTRL ((0x0006 << 2) + 0xfe050000) +#define EE_AUDIO_MCLK_F_CTRL ((0x0007 << 2) + 0xfe050000) +#define EE_AUDIO_PAD_CTRL0 ((0x0008 << 2) + 0xfe050000) +#define EE_AUDIO_PAD_CTRL1 ((0x0009 << 2) + 0xfe050000) +#define EE_AUDIO_SW_RESET0 ((0x000a << 2) + 0xfe050000) +#define EE_AUDIO_SW_RESET1 ((0x000b << 2) + 0xfe050000) +#define EE_AUDIO_CLK81_CTRL ((0x000c << 2) + 0xfe050000) +#define EE_AUDIO_CLK81_EN ((0x000d << 2) + 0xfe050000) +#define EE_AUDIO_MST_A_SCLK_CTRL0 ((0x0010 << 2) + 0xfe050000) +#define EE_AUDIO_MST_A_SCLK_CTRL1 ((0x0011 << 2) + 0xfe050000) +#define EE_AUDIO_MST_B_SCLK_CTRL0 ((0x0012 << 2) + 0xfe050000) +#define EE_AUDIO_MST_B_SCLK_CTRL1 ((0x0013 << 2) + 0xfe050000) +#define EE_AUDIO_MST_C_SCLK_CTRL0 ((0x0014 << 2) + 0xfe050000) +#define EE_AUDIO_MST_C_SCLK_CTRL1 ((0x0015 << 2) + 0xfe050000) +#define EE_AUDIO_MST_D_SCLK_CTRL0 ((0x0016 << 2) + 0xfe050000) +#define EE_AUDIO_MST_D_SCLK_CTRL1 ((0x0017 << 2) + 0xfe050000) +#define EE_AUDIO_MST_E_SCLK_CTRL0 ((0x0018 << 2) + 0xfe050000) +#define EE_AUDIO_MST_E_SCLK_CTRL1 ((0x0019 << 2) + 0xfe050000) +#define EE_AUDIO_MST_F_SCLK_CTRL0 ((0x001a << 2) + 0xfe050000) +#define EE_AUDIO_MST_F_SCLK_CTRL1 ((0x001b << 2) + 0xfe050000) +#define EE_AUDIO_MST_DLY_CTRL0 ((0x001c << 2) + 0xfe050000) +#define EE_AUDIO_MST_DLY_CTRL1 ((0x001d << 2) + 0xfe050000) +#define EE_AUDIO_CLK_TDMIN_A_CTRL ((0x0020 << 2) + 0xfe050000) +#define EE_AUDIO_CLK_TDMIN_B_CTRL ((0x0021 << 2) + 0xfe050000) +#define EE_AUDIO_CLK_TDMIN_C_CTRL ((0x0022 << 2) + 0xfe050000) +#define EE_AUDIO_CLK_TDMIN_LB_CTRL ((0x0023 << 2) + 0xfe050000) +#define EE_AUDIO_CLK_TDMOUT_A_CTRL ((0x0024 << 2) + 0xfe050000) +#define EE_AUDIO_CLK_TDMOUT_B_CTRL ((0x0025 << 2) + 0xfe050000) +#define EE_AUDIO_CLK_TDMOUT_C_CTRL ((0x0026 << 2) + 0xfe050000) +#define EE_AUDIO_CLK_SPDIFIN_CTRL ((0x0027 << 2) + 0xfe050000) +#define EE_AUDIO_CLK_SPDIFOUT_CTRL ((0x0028 << 2) + 0xfe050000) +#define EE_AUDIO_CLK_RESAMPLEA_CTRL ((0x0029 << 2) + 0xfe050000) +#define EE_AUDIO_CLK_LOCKER_CTRL ((0x002a << 2) + 0xfe050000) +#define EE_AUDIO_CLK_PDMIN_CTRL0 ((0x002b << 2) + 0xfe050000) +#define EE_AUDIO_CLK_PDMIN_CTRL1 ((0x002c << 2) + 0xfe050000) +#define EE_AUDIO_CLK_SPDIFOUT_B_CTRL ((0x002d << 2) + 0xfe050000) +#define EE_AUDIO_CLK_RESAMPLEB_CTRL ((0x002e << 2) + 0xfe050000) +#define EE_AUDIO_CLK_SPDIFIN_LB_CTRL ((0x002f << 2) + 0xfe050000) +#define EE_AUDIO_CLK_EQDRC_CTRL0 ((0x0030 << 2) + 0xfe050000) +#define EE_AUDIO_VAD_CLK_CTRL ((0x0031 << 2) + 0xfe050000) +#define EE_AUDIO_EARCTX_CMDC_CLK_CTRL ((0x0032 << 2) + 0xfe050000) +#define EE_AUDIO_EARCTX_DMAC_CLK_CTRL ((0x0033 << 2) + 0xfe050000) +#define EE_AUDIO_EARCRX_CMDC_CLK_CTRL ((0x0034 << 2) + 0xfe050000) +#define EE_AUDIO_EARCRX_DMAC_CLK_CTRL ((0x0035 << 2) + 0xfe050000) +#define EE_AUDIO_CLK_LOCKERB_CTRL ((0x0036 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_A_CTRL0 ((0x0040 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_A_CTRL1 ((0x0041 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_A_START_ADDR ((0x0042 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_A_FINISH_ADDR ((0x0043 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_A_INT_ADDR ((0x0044 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_A_STATUS1 ((0x0045 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_A_STATUS2 ((0x0046 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_A_START_ADDRB ((0x0047 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_A_FINISH_ADDRB ((0x0048 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_A_INIT_ADDR ((0x0049 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_A_CTRL2 ((0x004a << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_B_CTRL0 ((0x0050 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_B_CTRL1 ((0x0051 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_B_START_ADDR ((0x0052 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_B_FINISH_ADDR ((0x0053 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_B_INT_ADDR ((0x0054 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_B_STATUS1 ((0x0055 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_B_STATUS2 ((0x0056 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_B_START_ADDRB ((0x0057 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_B_FINISH_ADDRB ((0x0058 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_B_INIT_ADDR ((0x0059 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_B_CTRL2 ((0x005a << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_C_CTRL0 ((0x0060 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_C_CTRL1 ((0x0061 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_C_START_ADDR ((0x0062 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_C_FINISH_ADDR ((0x0063 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_C_INT_ADDR ((0x0064 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_C_STATUS1 ((0x0065 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_C_STATUS2 ((0x0066 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_C_START_ADDRB ((0x0067 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_C_FINISH_ADDRB ((0x0068 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_C_INIT_ADDR ((0x0069 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_C_CTRL2 ((0x006a << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_A_CTRL0 ((0x0070 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_A_CTRL1 ((0x0071 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_A_START_ADDR ((0x0072 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_A_FINISH_ADDR ((0x0073 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_A_INT_ADDR ((0x0074 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_A_STATUS1 ((0x0075 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_A_STATUS2 ((0x0076 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_A_START_ADDRB ((0x0077 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_A_FINISH_ADDRB ((0x0078 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_A_INIT_ADDR ((0x0079 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_A_CTRL2 ((0x007a << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_B_CTRL0 ((0x0080 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_B_CTRL1 ((0x0081 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_B_START_ADDR ((0x0082 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_B_FINISH_ADDR ((0x0083 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_B_INT_ADDR ((0x0084 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_B_STATUS1 ((0x0085 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_B_STATUS2 ((0x0086 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_B_START_ADDRB ((0x0087 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_B_FINISH_ADDRB ((0x0088 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_B_INIT_ADDR ((0x0089 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_B_CTRL2 ((0x008a << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_C_CTRL0 ((0x0090 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_C_CTRL1 ((0x0091 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_C_START_ADDR ((0x0092 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_C_FINISH_ADDR ((0x0093 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_C_INT_ADDR ((0x0094 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_C_STATUS1 ((0x0095 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_C_STATUS2 ((0x0096 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_C_START_ADDRB ((0x0097 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_C_FINISH_ADDRB ((0x0098 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_C_INIT_ADDR ((0x0099 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_C_CTRL2 ((0x009a << 2) + 0xfe050000) +#define EE_AUDIO_ARB_CTRL ((0x00a0 << 2) + 0xfe050000) +#define EE_AUDIO_LB_A_CTRL0 ((0x00b0 << 2) + 0xfe050000) +#define EE_AUDIO_LB_A_CTRL1 ((0x00b1 << 2) + 0xfe050000) +#define EE_AUDIO_LB_A_CTRL2 ((0x00b2 << 2) + 0xfe050000) +#define EE_AUDIO_LB_A_CTRL3 ((0x00b3 << 2) + 0xfe050000) +#define EE_AUDIO_LB_A_DAT_CH_ID0 ((0x00b4 << 2) + 0xfe050000) +#define EE_AUDIO_LB_A_DAT_CH_ID1 ((0x00b5 << 2) + 0xfe050000) +#define EE_AUDIO_LB_A_DAT_CH_ID2 ((0x00b6 << 2) + 0xfe050000) +#define EE_AUDIO_LB_A_DAT_CH_ID3 ((0x00b7 << 2) + 0xfe050000) +#define EE_AUDIO_LB_A_LB_CH_ID0 ((0x00b8 << 2) + 0xfe050000) +#define EE_AUDIO_LB_A_LB_CH_ID1 ((0x00b9 << 2) + 0xfe050000) +#define EE_AUDIO_LB_A_LB_CH_ID2 ((0x00ba << 2) + 0xfe050000) +#define EE_AUDIO_LB_A_LB_CH_ID3 ((0x00bb << 2) + 0xfe050000) +#define EE_AUDIO_LB_A_STS ((0x00bc << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_A_CTRL ((0x00c0 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_A_SWAP0 ((0x00c1 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_A_MASK0 ((0x00c2 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_A_MASK1 ((0x00c3 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_A_MASK2 ((0x00c4 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_A_MASK3 ((0x00c5 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_A_STAT ((0x00c6 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_A_MUTE_VAL ((0x00c7 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_A_MUTE0 ((0x00c8 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_A_MUTE1 ((0x00c9 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_A_MUTE2 ((0x00ca << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_A_MUTE3 ((0x00cb << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_B_CTRL ((0x00d0 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_B_SWAP0 ((0x00d1 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_B_MASK0 ((0x00d2 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_B_MASK1 ((0x00d3 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_B_MASK2 ((0x00d4 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_B_MASK3 ((0x00d5 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_B_STAT ((0x00d6 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_B_MUTE_VAL ((0x00d7 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_B_MUTE0 ((0x00d8 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_B_MUTE1 ((0x00d9 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_B_MUTE2 ((0x00da << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_B_MUTE3 ((0x00db << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_C_CTRL ((0x00e0 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_C_SWAP0 ((0x00e1 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_C_MASK0 ((0x00e2 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_C_MASK1 ((0x00e3 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_C_MASK2 ((0x00e4 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_C_MASK3 ((0x00e5 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_C_STAT ((0x00e6 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_C_MUTE_VAL ((0x00e7 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_C_MUTE0 ((0x00e8 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_C_MUTE1 ((0x00e9 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_C_MUTE2 ((0x00ea << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_C_MUTE3 ((0x00eb << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_LB_CTRL ((0x00f0 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_LB_SWAP0 ((0x00f1 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_LB_MASK0 ((0x00f2 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_LB_MASK1 ((0x00f3 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_LB_MASK2 ((0x00f4 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_LB_MASK3 ((0x00f5 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_LB_STAT ((0x00f6 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_LB_MUTE_VAL ((0x00f7 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_LB_MUTE0 ((0x00f8 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_LB_MUTE1 ((0x00f9 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_LB_MUTE2 ((0x00fa << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_LB_MUTE3 ((0x00fb << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFIN_CTRL0 ((0x0100 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFIN_CTRL1 ((0x0101 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFIN_CTRL2 ((0x0102 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFIN_CTRL3 ((0x0103 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFIN_CTRL4 ((0x0104 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFIN_CTRL5 ((0x0105 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFIN_CTRL6 ((0x0106 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFIN_STAT0 ((0x0107 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFIN_STAT1 ((0x0108 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFIN_STAT2 ((0x0109 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFIN_MUTE_VAL ((0x010a << 2) + 0xfe050000) +#define EE_AUDIO_RESAMPLEA_CTRL0 ((0x0110 << 2) + 0xfe050000) +#define EE_AUDIO_RESAMPLEA_CTRL1 ((0x0111 << 2) + 0xfe050000) +#define EE_AUDIO_RESAMPLEA_CTRL2 ((0x0112 << 2) + 0xfe050000) +#define EE_AUDIO_RESAMPLEA_CTRL3 ((0x0113 << 2) + 0xfe050000) +#define EE_AUDIO_RESAMPLEA_COEF0 ((0x0114 << 2) + 0xfe050000) +#define EE_AUDIO_RESAMPLEA_COEF1 ((0x0115 << 2) + 0xfe050000) +#define EE_AUDIO_RESAMPLEA_COEF2 ((0x0116 << 2) + 0xfe050000) +#define EE_AUDIO_RESAMPLEA_COEF3 ((0x0117 << 2) + 0xfe050000) +#define EE_AUDIO_RESAMPLEA_COEF4 ((0x0118 << 2) + 0xfe050000) +#define EE_AUDIO_RESAMPLEA_STATUS1 ((0x0119 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_STAT ((0x0120 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_GAIN0 ((0x0121 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_GAIN1 ((0x0122 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_CTRL0 ((0x0123 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_CTRL1 ((0x0124 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_PREAMB ((0x0125 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_SWAP ((0x0126 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_CHSTS0 ((0x0127 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_CHSTS1 ((0x0128 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_CHSTS2 ((0x0129 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_CHSTS3 ((0x012a << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_CHSTS4 ((0x012b << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_CHSTS5 ((0x012c << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_CHSTS6 ((0x012d << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_CHSTS7 ((0x012e << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_CHSTS8 ((0x012f << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_CHSTS9 ((0x0130 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_CHSTSA ((0x0131 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_CHSTSB ((0x0132 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_MUTE_VAL ((0x0133 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_CTRL0 ((0x0140 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_CTRL1 ((0x0141 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_SWAP0 ((0x0142 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_MASK0 ((0x0143 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_MASK1 ((0x0144 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_MASK2 ((0x0145 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_MASK3 ((0x0146 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_STAT ((0x0147 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_GAIN0 ((0x0148 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_GAIN1 ((0x0149 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_MUTE_VAL ((0x014a << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_MUTE0 ((0x014b << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_MUTE1 ((0x014c << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_MUTE2 ((0x014d << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_MUTE3 ((0x014e << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_MASK_VAL ((0x014f << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_CTRL0 ((0x0150 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_CTRL1 ((0x0151 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_SWAP0 ((0x0152 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_MASK0 ((0x0153 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_MASK1 ((0x0154 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_MASK2 ((0x0155 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_MASK3 ((0x0156 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_STAT ((0x0157 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_GAIN0 ((0x0158 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_GAIN1 ((0x0159 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_MUTE_VAL ((0x015a << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_MUTE0 ((0x015b << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_MUTE1 ((0x015c << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_MUTE2 ((0x015d << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_MUTE3 ((0x015e << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_MASK_VAL ((0x015f << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_CTRL0 ((0x0160 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_CTRL1 ((0x0161 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_SWAP0 ((0x0162 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_MASK0 ((0x0163 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_MASK1 ((0x0164 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_MASK2 ((0x0165 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_MASK3 ((0x0166 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_STAT ((0x0167 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_GAIN0 ((0x0168 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_GAIN1 ((0x0169 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_MUTE_VAL ((0x016a << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_MUTE0 ((0x016b << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_MUTE1 ((0x016c << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_MUTE2 ((0x016d << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_MUTE3 ((0x016e << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_MASK_VAL ((0x016f << 2) + 0xfe050000) +//`define EE_AUDIO_POW_DET_CTRL0 10'h180 +//`define EE_AUDIO_POW_DET_CTRL1 10'h181 +//`define EE_AUDIO_POW_DET_TH_HI 10'h182 +//`define EE_AUDIO_POW_DET_TH_LO 10'h183 +//`define EE_AUDIO_POW_DET_VALUE 10'h184 +#define EE_AUDIO_SECURITY_CTRL0 ((0x0190 << 2) + 0xfe050000) +#define EE_AUDIO_SECURITY_CTRL1 ((0x0191 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_B_STAT ((0x01a0 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_B_GAIN0 ((0x01a1 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_B_GAIN1 ((0x01a2 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_B_CTRL0 ((0x01a3 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_B_CTRL1 ((0x01a4 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_B_PREAMB ((0x01a5 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_B_SWAP ((0x01a6 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_B_CHSTS0 ((0x01a7 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_B_CHSTS1 ((0x01a8 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_B_CHSTS2 ((0x01a9 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_B_CHSTS3 ((0x01aa << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_B_CHSTS4 ((0x01ab << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_B_CHSTS5 ((0x01ac << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_B_CHSTS6 ((0x01ad << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_B_CHSTS7 ((0x01ae << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_B_CHSTS8 ((0x01af << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_B_CHSTS9 ((0x01b0 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_B_CHSTSA ((0x01b1 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_B_CHSTSB ((0x01b2 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_B_MUTE_VAL ((0x01b3 << 2) + 0xfe050000) +#define EE_AUDIO_TORAM_CTRL0 ((0x01c0 << 2) + 0xfe050000) +#define EE_AUDIO_TORAM_CTRL1 ((0x01c1 << 2) + 0xfe050000) +#define EE_AUDIO_TORAM_START_ADDR ((0x01c2 << 2) + 0xfe050000) +#define EE_AUDIO_TORAM_FINISH_ADDR ((0x01c3 << 2) + 0xfe050000) +#define EE_AUDIO_TORAM_INT_ADDR ((0x01c4 << 2) + 0xfe050000) +#define EE_AUDIO_TORAM_STATUS1 ((0x01c5 << 2) + 0xfe050000) +#define EE_AUDIO_TORAM_STATUS2 ((0x01c6 << 2) + 0xfe050000) +#define EE_AUDIO_TORAM_INIT_ADDR ((0x01c7 << 2) + 0xfe050000) +#define EE_AUDIO_TOACODEC_CTRL0 ((0x01d0 << 2) + 0xfe050000) +#define EE_AUDIO_TOHDMITX_CTRL0 ((0x01d1 << 2) + 0xfe050000) +#define EE_AUDIO_TOVAD_CTRL0 ((0x01d2 << 2) + 0xfe050000) +#define EE_AUDIO_FRATV_CTRL0 ((0x01d3 << 2) + 0xfe050000) +#define EE_AUDIO_RESAMPLEB_CTRL0 ((0x01e0 << 2) + 0xfe050000) +#define EE_AUDIO_RESAMPLEB_CTRL1 ((0x01e1 << 2) + 0xfe050000) +#define EE_AUDIO_RESAMPLEB_CTRL2 ((0x01e2 << 2) + 0xfe050000) +#define EE_AUDIO_RESAMPLEB_CTRL3 ((0x01e3 << 2) + 0xfe050000) +#define EE_AUDIO_RESAMPLEB_COEF0 ((0x01e4 << 2) + 0xfe050000) +#define EE_AUDIO_RESAMPLEB_COEF1 ((0x01e5 << 2) + 0xfe050000) +#define EE_AUDIO_RESAMPLEB_COEF2 ((0x01e6 << 2) + 0xfe050000) +#define EE_AUDIO_RESAMPLEB_COEF3 ((0x01e7 << 2) + 0xfe050000) +#define EE_AUDIO_RESAMPLEB_COEF4 ((0x01e8 << 2) + 0xfe050000) +#define EE_AUDIO_RESAMPLEB_STATUS1 ((0x01e9 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFIN_LB_CTRL0 ((0x01f0 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFIN_LB_CTRL1 ((0x01f1 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFIN_LB_CTRL6 ((0x01f6 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFIN_LB_STAT0 ((0x01f7 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFIN_LB_STAT1 ((0x01f8 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFIN_LB_MUTE_VAL ((0x01fa << 2) + 0xfe050000) +#define EE_AUDIO_FRHDMIRX_CTRL0 ((0x0200 << 2) + 0xfe050000) +#define EE_AUDIO_FRHDMIRX_CTRL1 ((0x0201 << 2) + 0xfe050000) +#define EE_AUDIO_FRHDMIRX_CTRL2 ((0x0202 << 2) + 0xfe050000) +#define EE_AUDIO_FRHDMIRX_CTRL3 ((0x0203 << 2) + 0xfe050000) +#define EE_AUDIO_FRHDMIRX_CTRL4 ((0x0204 << 2) + 0xfe050000) +#define EE_AUDIO_FRHDMIRX_CTRL5 ((0x0205 << 2) + 0xfe050000) +#define EE_AUDIO_FRHDMIRX_STAT0 ((0x020a << 2) + 0xfe050000) +#define EE_AUDIO_FRHDMIRX_STAT1 ((0x020b << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_D_CTRL0 ((0x0210 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_D_CTRL1 ((0x0211 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_D_START_ADDR ((0x0212 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_D_FINISH_ADDR ((0x0213 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_D_INT_ADDR ((0x0214 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_D_STATUS1 ((0x0215 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_D_STATUS2 ((0x0216 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_D_START_ADDRB ((0x0217 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_D_FINISH_ADDRB ((0x0218 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_D_INIT_ADDR ((0x0219 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_D_CTRL2 ((0x021a << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_D_CTRL0 ((0x0220 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_D_CTRL1 ((0x0221 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_D_START_ADDR ((0x0222 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_D_FINISH_ADDR ((0x0223 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_D_INT_ADDR ((0x0224 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_D_STATUS1 ((0x0225 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_D_STATUS2 ((0x0226 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_D_START_ADDRB ((0x0227 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_D_FINISH_ADDRB ((0x0228 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_D_INIT_ADDR ((0x0229 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_D_CTRL2 ((0x022a << 2) + 0xfe050000) +#define EE_AUDIO_LB_B_CTRL0 ((0x0230 << 2) + 0xfe050000) +#define EE_AUDIO_LB_B_CTRL1 ((0x0231 << 2) + 0xfe050000) +#define EE_AUDIO_LB_B_CTRL2 ((0x0232 << 2) + 0xfe050000) +#define EE_AUDIO_LB_B_CTRL3 ((0x0233 << 2) + 0xfe050000) +#define EE_AUDIO_LB_B_DAT_CH_ID0 ((0x0234 << 2) + 0xfe050000) +#define EE_AUDIO_LB_B_DAT_CH_ID1 ((0x0235 << 2) + 0xfe050000) +#define EE_AUDIO_LB_B_DAT_CH_ID2 ((0x0236 << 2) + 0xfe050000) +#define EE_AUDIO_LB_B_DAT_CH_ID3 ((0x0237 << 2) + 0xfe050000) +#define EE_AUDIO_LB_B_LB_CH_ID0 ((0x0238 << 2) + 0xfe050000) +#define EE_AUDIO_LB_B_LB_CH_ID1 ((0x0239 << 2) + 0xfe050000) +#define EE_AUDIO_LB_B_LB_CH_ID2 ((0x023a << 2) + 0xfe050000) +#define EE_AUDIO_LB_B_LB_CH_ID3 ((0x023b << 2) + 0xfe050000) +#define EE_AUDIO_LB_B_STS ((0x023c << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_E_CTRL0 ((0x0240 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_E_CTRL1 ((0x0241 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_E_START_ADDR ((0x0242 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_E_FINISH_ADDR ((0x0243 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_E_INT_ADDR ((0x0244 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_E_STATUS1 ((0x0245 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_E_STATUS2 ((0x0246 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_E_START_ADDRB ((0x0247 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_E_FINISH_ADDRB ((0x0248 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_E_INIT_ADDR ((0x0249 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_E_CTRL2 ((0x024a << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_E_CTRL0 ((0x0250 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_E_CTRL1 ((0x0251 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_E_START_ADDR ((0x0252 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_E_FINISH_ADDR ((0x0253 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_E_INT_ADDR ((0x0254 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_E_STATUS1 ((0x0255 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_E_STATUS2 ((0x0256 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_E_START_ADDRB ((0x0257 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_E_FINISH_ADDRB ((0x0258 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_E_INIT_ADDR ((0x0259 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_E_CTRL2 ((0x025a << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_A_SWAP1 ((0x0260 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_A_MASK4 ((0x0261 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_A_MASK5 ((0x0262 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_A_MASK6 ((0x0263 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_A_MASK7 ((0x0264 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_A_MUTE4 ((0x0265 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_A_MUTE5 ((0x0266 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_A_MUTE6 ((0x0267 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_A_MUTE7 ((0x0268 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_B_SWAP1 ((0x0270 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_B_MASK4 ((0x0271 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_B_MASK5 ((0x0272 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_B_MASK6 ((0x0273 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_B_MASK7 ((0x0274 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_B_MUTE4 ((0x0275 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_B_MUTE5 ((0x0276 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_B_MUTE6 ((0x0277 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_B_MUTE7 ((0x0278 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_C_SWAP1 ((0x0280 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_C_MASK4 ((0x0281 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_C_MASK5 ((0x0282 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_C_MASK6 ((0x0283 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_C_MASK7 ((0x0284 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_C_MUTE4 ((0x0285 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_C_MUTE5 ((0x0286 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_C_MUTE6 ((0x0287 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_C_MUTE7 ((0x0288 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_LB_SWAP1 ((0x0290 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_LB_MASK4 ((0x0291 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_LB_MASK5 ((0x0292 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_LB_MASK6 ((0x0293 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_LB_MASK7 ((0x0294 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_LB_MUTE4 ((0x0295 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_LB_MUTE5 ((0x0296 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_LB_MUTE6 ((0x0297 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_LB_MUTE7 ((0x0298 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_CTRL2 ((0x02a0 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_SWAP1 ((0x02a1 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_GAIN2 ((0x02a2 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_GAIN3 ((0x02a3 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_MASK4 ((0x02a4 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_MASK5 ((0x02a5 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_MASK6 ((0x02a6 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_MASK7 ((0x02a7 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_MUTE4 ((0x02a8 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_MUTE5 ((0x02a9 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_MUTE6 ((0x02aa << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_MUTE7 ((0x02ab << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_CTRL2 ((0x02b0 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_SWAP1 ((0x02b1 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_GAIN2 ((0x02b2 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_GAIN3 ((0x02b3 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_MASK4 ((0x02b4 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_MASK5 ((0x02b5 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_MASK6 ((0x02b6 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_MASK7 ((0x02b7 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_MUTE4 ((0x02b8 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_MUTE5 ((0x02b9 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_MUTE6 ((0x02ba << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_MUTE7 ((0x02bb << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_CTRL2 ((0x02c0 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_SWAP1 ((0x02c1 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_GAIN2 ((0x02c2 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_GAIN3 ((0x02c3 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_MASK4 ((0x02c4 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_MASK5 ((0x02c5 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_MASK6 ((0x02c6 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_MASK7 ((0x02c7 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_MUTE4 ((0x02c8 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_MUTE5 ((0x02c9 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_MUTE6 ((0x02ca << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_MUTE7 ((0x02cb << 2) + 0xfe050000) +//======================================================================== +// PDM - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe051000 +// ----------------------------------------------- +#define PDM_CTRL ((0x0000 << 2) + 0xfe051000) + //bit 31: PDM enable. + //bit 30: invert the PDM_DCLK. + //bit 29: output mode: 1: 24bits. 0: 32 bits. + //bit 28: bypass mode. 1: bypass all filter. directly output the PDM input to DDR. 0: normal mode. + //bit 27~9: not used. + //bit 16:. PDM Asynchronous FIFO soft reset. write 1 to soft reset AFIFO. + //bit 15:8 PDM channel reset. 0: to reset each PDM channel. 1: normal mode. + //bit 7:0. PDM channel enable. each bit for one channel. +#define PDM_HCIC_CTRL1 ((0x0001 << 2) + 0xfe051000) + //bit 31 hcic filter enable. 1 use sinc filter. 0 bypass input to output. + //bit 29:24. hcic final gain shift parameter. + //bit 23:16 hcic final gain multiplier. + //bit 8:4 hcic down sample rate. + //bit 3:0 hcic stage number. must be between 3 to 9. +#define PDM_HCIC_CTRL2 ((0x0002 << 2) + 0xfe051000) + //Not used. +#define PDM_F1_CTRL ((0x0003 << 2) + 0xfe051000) + //bit 31 . filter 1 enable. + //bit 16:15. f1 round mode. 2'b00 : sign bit at bit 49. 28bits output [49:22] round at bit 21. 32bits output [49:18]. 24bits output [49:26] + // 2'b01 : sign bit at bit 50. 28bits output [50:23] round at bit 22. 32bits output [49:18]. 24bits output [49:26] + // 2'b10 : sign bit at bit 51. 28bits output [51:24] round at bit 23 32bits output [49:18]. 24bits output [49:26]. + //bit 15:12. filter 1 down sample rate. + //bit 8:0. filter 1 stage number. +#define PDM_F2_CTRL ((0x0004 << 2) + 0xfe051000) + //bit 31 . filter 2 enable. + //bit 16:15. f2 round mode. 2'b00 : round at bit 21. 2'b01 : round at bit 22. 2'b10 : round at bit 23. + //bit 15:12. filter 2 down sample rate. + //bit 8:0. filter 2 stage number. +#define PDM_F3_CTRL ((0x0005 << 2) + 0xfe051000) + //bit 31 . filter 3 enable. + //bit 16:15. f3 round mode. 2'b00 : round at bit 21. 2'b01 : round at bit 22. 2'b10 : round at bit 23. + //bit 15:12. filter 3 down sample rate. + //bit 8:0. filter 3 stage number. +#define PDM_HPF_CTRL ((0x0006 << 2) + 0xfe051000) + //bit 31 High pass filter enable. + //bit 20:16 high pass filter shift steps. 6~19 steps. + //bit 15:0 high pass filter output factor. +#define PDM_CHAN_CTRL ((0x0007 << 2) + 0xfe051000) + //bit 31:24. chan3 data sample pointer vs edge of the PDM_DCLK. + //bit 23:16 chan2 data sample pointer vs edge of the PDM_DCLK. + //bit 15:8. chan1 data sample pointer vs edge of the PDM_DCLK. + //bit 7:0 chan0 data sample pointer vs edge of the PDM_DCLK. +#define PDM_CHAN_CTRL1 ((0x0008 << 2) + 0xfe051000) + //bit 31:24. chan7 data sample pointer vs edge of the PDM_DCLK. + //bit 23:16 chan6 data sample pointer vs edge of the PDM_DCLK. + //bit 15:8. chan5 data sample pointer vs edge of the PDM_DCLK. + //bit 7:0 chan4 data sample pointer vs edge of the PDM_DCLK. +#define PDM_COEFF_ADDR ((0x0009 << 2) + 0xfe051000) + // address of the write/read of coeff data. +#define PDM_COEFF_DATA ((0x000a << 2) + 0xfe051000) + //write/read data to coeff memory. +#define PDM_CLKG_CTRL ((0x000b << 2) + 0xfe051000) + // auto clock gating control. 1: disable the clock gating function. the clock will awlays enabled. 0 : use RTL auto clock gating. + //31:7 not used. + //bit 6 filt_ctrl module auto clock gating control. + //bit 5 sinc fifo module auto clock gating control. + //bit 4 filter module auto clock gating control. + //bit 3 apb module auto clock gating control. + //bit 2 coeff memory module auto clock gating control. + //bit 1 each channel module auto clock gating control. + //bit 0 cts_pdm_clk auto clock gating control. +#define PDM_STS ((0x000c << 2) + 0xfe051000) +//bit 1 HPF filter output overflow. means the PCLK is too slow. +//bit 0 HCIC filter output overflow. means the CTS_PDM_CLK is too slow. can't finished the filter function. +#define PDM_MUTE_VALUE ((0x000d << 2) + 0xfe051000) +#define PDM_MASK_NUM ((0x000e << 2) + 0xfe051000) +//======================================================================== +// EQ DRC - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe052000 +// ----------------------------------------------- +#define AED_COEF_RAM_CNTL ((0x0000 << 2) + 0xfe052000) +#define AED_COEF_RAM_DATA ((0x0001 << 2) + 0xfe052000) +#define AED_EQ_EN ((0x0002 << 2) + 0xfe052000) +#define AED_EQ_TAP_CNTL ((0x0003 << 2) + 0xfe052000) +#define AED_EQ_VOLUME ((0x0004 << 2) + 0xfe052000) +#define AED_EQ_VOLUME_SLEW_CNT ((0x0005 << 2) + 0xfe052000) +#define AED_MUTE ((0x0006 << 2) + 0xfe052000) +#define AED_DRC_CNTL ((0x0007 << 2) + 0xfe052000) +#define AED_DRC_RMS_COEF0 ((0x0008 << 2) + 0xfe052000) +#define AED_DRC_RMS_COEF1 ((0x0009 << 2) + 0xfe052000) +#define AED_DRC_THD0 ((0x000a << 2) + 0xfe052000) +#define AED_DRC_THD1 ((0x000b << 2) + 0xfe052000) +#define AED_DRC_THD2 ((0x000c << 2) + 0xfe052000) +#define AED_DRC_THD3 ((0x000d << 2) + 0xfe052000) +#define AED_DRC_THD4 ((0x000e << 2) + 0xfe052000) +#define AED_DRC_K0 ((0x000f << 2) + 0xfe052000) +#define AED_DRC_K1 ((0x0010 << 2) + 0xfe052000) +#define AED_DRC_K2 ((0x0011 << 2) + 0xfe052000) +#define AED_DRC_K3 ((0x0012 << 2) + 0xfe052000) +#define AED_DRC_K4 ((0x0013 << 2) + 0xfe052000) +#define AED_DRC_K5 ((0x0014 << 2) + 0xfe052000) +#define AED_DRC_THD_OUT0 ((0x0015 << 2) + 0xfe052000) +#define AED_DRC_THD_OUT1 ((0x0016 << 2) + 0xfe052000) +#define AED_DRC_THD_OUT2 ((0x0017 << 2) + 0xfe052000) +#define AED_DRC_THD_OUT3 ((0x0018 << 2) + 0xfe052000) +#define AED_DRC_OFFSET ((0x0019 << 2) + 0xfe052000) +#define AED_DRC_RELEASE_COEF00 ((0x001a << 2) + 0xfe052000) +#define AED_DRC_RELEASE_COEF01 ((0x001b << 2) + 0xfe052000) +#define AED_DRC_RELEASE_COEF10 ((0x001c << 2) + 0xfe052000) +#define AED_DRC_RELEASE_COEF11 ((0x001d << 2) + 0xfe052000) +#define AED_DRC_RELEASE_COEF20 ((0x001e << 2) + 0xfe052000) +#define AED_DRC_RELEASE_COEF21 ((0x001f << 2) + 0xfe052000) +#define AED_DRC_RELEASE_COEF30 ((0x0020 << 2) + 0xfe052000) +#define AED_DRC_RELEASE_COEF31 ((0x0021 << 2) + 0xfe052000) +#define AED_DRC_RELEASE_COEF40 ((0x0022 << 2) + 0xfe052000) +#define AED_DRC_RELEASE_COEF41 ((0x0023 << 2) + 0xfe052000) +#define AED_DRC_RELEASE_COEF50 ((0x0024 << 2) + 0xfe052000) +#define AED_DRC_RELEASE_COEF51 ((0x0025 << 2) + 0xfe052000) +#define AED_DRC_ATTACK_COEF00 ((0x0026 << 2) + 0xfe052000) +#define AED_DRC_ATTACK_COEF01 ((0x0027 << 2) + 0xfe052000) +#define AED_DRC_ATTACK_COEF10 ((0x0028 << 2) + 0xfe052000) +#define AED_DRC_ATTACK_COEF11 ((0x0029 << 2) + 0xfe052000) +#define AED_DRC_ATTACK_COEF20 ((0x002a << 2) + 0xfe052000) +#define AED_DRC_ATTACK_COEF21 ((0x002b << 2) + 0xfe052000) +#define AED_DRC_ATTACK_COEF30 ((0x002c << 2) + 0xfe052000) +#define AED_DRC_ATTACK_COEF31 ((0x002d << 2) + 0xfe052000) +#define AED_DRC_ATTACK_COEF40 ((0x002e << 2) + 0xfe052000) +#define AED_DRC_ATTACK_COEF41 ((0x002f << 2) + 0xfe052000) +#define AED_DRC_ATTACK_COEF50 ((0x0030 << 2) + 0xfe052000) +#define AED_DRC_ATTACK_COEF51 ((0x0031 << 2) + 0xfe052000) +#define AED_DRC_LOOPBACK_CNTL ((0x0032 << 2) + 0xfe052000) +#define AED_MDRC_CNTL ((0x0033 << 2) + 0xfe052000) +#define AED_MDRC_RMS_COEF00 ((0x0034 << 2) + 0xfe052000) +#define AED_MDRC_RMS_COEF01 ((0x0035 << 2) + 0xfe052000) +#define AED_MDRC_RELEASE_COEF00 ((0x0036 << 2) + 0xfe052000) +#define AED_MDRC_RELEASE_COEF01 ((0x0037 << 2) + 0xfe052000) +#define AED_MDRC_ATTACK_COEF00 ((0x0038 << 2) + 0xfe052000) +#define AED_MDRC_ATTACK_COEF01 ((0x0039 << 2) + 0xfe052000) +#define AED_MDRC_THD0 ((0x003a << 2) + 0xfe052000) +#define AED_MDRC_K0 ((0x003b << 2) + 0xfe052000) +#define AED_MDRC_LOW_GAIN ((0x003c << 2) + 0xfe052000) +#define AED_MDRC_OFFSET0 ((0x003d << 2) + 0xfe052000) +#define AED_MDRC_RMS_COEF10 ((0x003e << 2) + 0xfe052000) +#define AED_MDRC_RMS_COEF11 ((0x003f << 2) + 0xfe052000) +#define AED_MDRC_RELEASE_COEF10 ((0x0040 << 2) + 0xfe052000) +#define AED_MDRC_RELEASE_COEF11 ((0x0041 << 2) + 0xfe052000) +#define AED_MDRC_ATTACK_COEF10 ((0x0042 << 2) + 0xfe052000) +#define AED_MDRC_ATTACK_COEF11 ((0x0043 << 2) + 0xfe052000) +#define AED_MDRC_THD1 ((0x0044 << 2) + 0xfe052000) +#define AED_MDRC_K1 ((0x0045 << 2) + 0xfe052000) +#define AED_MDRC_OFFSET1 ((0x0046 << 2) + 0xfe052000) +#define AED_MDRC_MID_GAIN ((0x0047 << 2) + 0xfe052000) +#define AED_MDRC_RMS_COEF20 ((0x0048 << 2) + 0xfe052000) +#define AED_MDRC_RMS_COEF21 ((0x0049 << 2) + 0xfe052000) +#define AED_MDRC_RELEASE_COEF20 ((0x004a << 2) + 0xfe052000) +#define AED_MDRC_RELEASE_COEF21 ((0x004b << 2) + 0xfe052000) +#define AED_MDRC_ATTACK_COEF20 ((0x004c << 2) + 0xfe052000) +#define AED_MDRC_ATTACK_COEF21 ((0x004d << 2) + 0xfe052000) +#define AED_MDRC_THD2 ((0x004e << 2) + 0xfe052000) +#define AED_MDRC_K2 ((0x004f << 2) + 0xfe052000) +#define AED_MDRC_OFFSET2 ((0x0050 << 2) + 0xfe052000) +#define AED_MDRC_HIGH_GAIN ((0x0051 << 2) + 0xfe052000) +#define AED_ED_CNTL ((0x0052 << 2) + 0xfe052000) +#define AED_DC_EN ((0x0053 << 2) + 0xfe052000) +#define AED_ND_LOW_THD ((0x0054 << 2) + 0xfe052000) +#define AED_ND_HIGH_THD ((0x0055 << 2) + 0xfe052000) +#define AED_ND_CNT_THD ((0x0056 << 2) + 0xfe052000) +#define AED_ND_SUM_NUM ((0x0057 << 2) + 0xfe052000) +#define AED_ND_CZ_NUM ((0x0058 << 2) + 0xfe052000) +#define AED_ND_SUM_THD0 ((0x0059 << 2) + 0xfe052000) +#define AED_ND_SUM_THD1 ((0x005a << 2) + 0xfe052000) +#define AED_ND_CZ_THD0 ((0x005b << 2) + 0xfe052000) +#define AED_ND_CZ_THD1 ((0x005c << 2) + 0xfe052000) +#define AED_ND_COND_CNTL ((0x005d << 2) + 0xfe052000) +#define AED_ND_RELEASE_COEF0 ((0x005e << 2) + 0xfe052000) +#define AED_ND_RELEASE_COEF1 ((0x005f << 2) + 0xfe052000) +#define AED_ND_ATTACK_COEF0 ((0x0060 << 2) + 0xfe052000) +#define AED_ND_ATTACK_COEF1 ((0x0061 << 2) + 0xfe052000) +#define AED_ND_CNTL ((0x0062 << 2) + 0xfe052000) +#define AED_MIX0_LL ((0x0063 << 2) + 0xfe052000) +#define AED_MIX0_RL ((0x0064 << 2) + 0xfe052000) +#define AED_MIX0_LR ((0x0065 << 2) + 0xfe052000) +#define AED_MIX0_RR ((0x0066 << 2) + 0xfe052000) +#define AED_CLIP_THD ((0x0067 << 2) + 0xfe052000) +#define AED_CH1_ND_SUM_OUT ((0x0068 << 2) + 0xfe052000) +#define AED_CH2_ND_SUM_OUT ((0x0069 << 2) + 0xfe052000) +#define AED_CH1_ND_CZ_OUT ((0x006a << 2) + 0xfe052000) +#define AED_CH2_ND_CZ_OUT ((0x006b << 2) + 0xfe052000) +#define AED_NOISE_STATUS ((0x006c << 2) + 0xfe052000) +#define AED_POW_CURRENT_S0 ((0x006d << 2) + 0xfe052000) +#define AED_POW_CURRENT_S1 ((0x006e << 2) + 0xfe052000) +#define AED_POW_CURRENT_S2 ((0x006f << 2) + 0xfe052000) +#define AED_POW_OUT0 ((0x0070 << 2) + 0xfe052000) +#define AED_POW_OUT1 ((0x0071 << 2) + 0xfe052000) +#define AED_POW_OUT2 ((0x0072 << 2) + 0xfe052000) +#define AED_POW_ADJ_INDEX0 ((0x0073 << 2) + 0xfe052000) +#define AED_POW_ADJ_INDEX1 ((0x0074 << 2) + 0xfe052000) +#define AED_POW_ADJ_INDEX2 ((0x0075 << 2) + 0xfe052000) +#define AED_DRC_GAIN_INDEX0 ((0x0076 << 2) + 0xfe052000) +#define AED_DRC_GAIN_INDEX1 ((0x0077 << 2) + 0xfe052000) +#define AED_DRC_GAIN_INDEX2 ((0x0078 << 2) + 0xfe052000) +#define AED_CH1_VOLUME_STATE ((0x0079 << 2) + 0xfe052000) +#define AED_CH2_VOLUME_STATE ((0x007a << 2) + 0xfe052000) +#define AED_CH1_VOLUME_GAIN ((0x007b << 2) + 0xfe052000) +#define AED_CH2_VOLUME_GAIN ((0x007c << 2) + 0xfe052000) +#define AED_FULL_POW_CURRENT ((0x007d << 2) + 0xfe052000) +#define AED_FULL_POW_OUT ((0x007e << 2) + 0xfe052000) +#define AED_FULL_POW_ADJ ((0x007f << 2) + 0xfe052000) +#define AED_FULL_DRC_GAIN ((0x0080 << 2) + 0xfe052000) +#define AED_MASTER_VOLUME_STATE ((0x0081 << 2) + 0xfe052000) +#define AED_MASTER_VOLUME_GAIN ((0x0082 << 2) + 0xfe052000) +#define AED_TOP_CTL0 ((0x0083 << 2) + 0xfe052000) +#define AED_TOP_CTL1 ((0x0084 << 2) + 0xfe052000) +#define AED_TOP_CTL2 ((0x0085 << 2) + 0xfe052000) +//======================================================================== +// AUDIO locker - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe051400 +// ----------------------------------------------- +#define AUD_LOCK_EN ((0x0000 << 2) + 0xfe051400) +#define AUD_LOCK_SW_RESET ((0x0001 << 2) + 0xfe051400) +#define AUD_LOCK_SW_LATCH ((0x0002 << 2) + 0xfe051400) +#define AUD_LOCK_HW_LATCH ((0x0003 << 2) + 0xfe051400) +#define AUD_LOCK_REFCLK_SRC ((0x0004 << 2) + 0xfe051400) +#define AUD_LOCK_REFCLK_LAT_INT ((0x0005 << 2) + 0xfe051400) +#define AUD_LOCK_IMCLK_LAT_INT ((0x0006 << 2) + 0xfe051400) +#define AUD_LOCK_OMCLK_LAT_INT ((0x0007 << 2) + 0xfe051400) +#define AUD_LOCK_REFCLK_DS_INT ((0x0008 << 2) + 0xfe051400) +#define AUD_LOCK_IMCLK_DS_INT ((0x0009 << 2) + 0xfe051400) +#define AUD_LOCK_OMCLK_DS_INT ((0x000a << 2) + 0xfe051400) +#define AUD_LOCK_INT_CLR ((0x000b << 2) + 0xfe051400) +#define AUD_LOCK_GCLK_CTRL ((0x000c << 2) + 0xfe051400) +#define AUD_LOCK_INT_CTRL ((0x000d << 2) + 0xfe051400) +#define RO_REF2IMCLK_CNT_L ((0x0010 << 2) + 0xfe051400) +#define RO_REF2IMCLK_CNT_H ((0x0011 << 2) + 0xfe051400) +#define RO_REF2OMCLK_CNT_L ((0x0012 << 2) + 0xfe051400) +#define RO_REF2OMCLK_CNT_H ((0x0013 << 2) + 0xfe051400) +#define RO_IMCLK2REF_CNT_L ((0x0014 << 2) + 0xfe051400) +#define RO_IMCLK2REF_CNT_H ((0x0015 << 2) + 0xfe051400) +#define RO_OMCLK2REF_CNT_L ((0x0016 << 2) + 0xfe051400) +#define RO_OMCLK2REF_CNT_H ((0x0017 << 2) + 0xfe051400) +#define RO_REFCLK_PKG_CNT ((0x0018 << 2) + 0xfe051400) +#define RO_IMCLK_PKG_CNT ((0x0019 << 2) + 0xfe051400) +#define RO_OMCLK_PKG_CNT ((0x001a << 2) + 0xfe051400) +#define RO_AUD_LOCK_INT_STATUS ((0x001b << 2) + 0xfe051400) +//======================================================================== +// AUDIO VAD - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe051800 +// ----------------------------------------------- +// +// Reading file: VAD_REG.h +// +#define VAD_TOP_CTRL0 ((0x0000 << 2) + 0xfe051800) +#define VAD_TOP_CTRL1 ((0x0001 << 2) + 0xfe051800) +#define VAD_TOP_CTRL2 ((0x0002 << 2) + 0xfe051800) +#define VAD_FIR_CTRL ((0x0003 << 2) + 0xfe051800) +#define VAD_FIR_EMP ((0x0004 << 2) + 0xfe051800) +#define VAD_FIR_COEF0 ((0x0005 << 2) + 0xfe051800) +#define VAD_FIR_COEF1 ((0x0006 << 2) + 0xfe051800) +#define VAD_FIR_COEF2 ((0x0007 << 2) + 0xfe051800) +#define VAD_FIR_COEF3 ((0x0008 << 2) + 0xfe051800) +#define VAD_FIR_COEF4 ((0x0009 << 2) + 0xfe051800) +#define VAD_FIR_COEF5 ((0x000a << 2) + 0xfe051800) +#define VAD_FIR_COEF6 ((0x000b << 2) + 0xfe051800) +#define VAD_FIR_COEF7 ((0x000c << 2) + 0xfe051800) +#define VAD_FIR_COEF8 ((0x000d << 2) + 0xfe051800) +#define VAD_FIR_COEF9 ((0x000e << 2) + 0xfe051800) +#define VAD_FIR_COEF10 ((0x000f << 2) + 0xfe051800) +#define VAD_FIR_COEF11 ((0x0010 << 2) + 0xfe051800) +#define VAD_FIR_COEF12 ((0x0011 << 2) + 0xfe051800) +#define VAD_FRAME_CTRL0 ((0x0012 << 2) + 0xfe051800) +#define VAD_FRAME_CTRL1 ((0x0013 << 2) + 0xfe051800) +#define VAD_FRAME_CTRL2 ((0x0014 << 2) + 0xfe051800) +#define VAD_CEP_CTRL0 ((0x0015 << 2) + 0xfe051800) +#define VAD_CEP_CTRL1 ((0x0016 << 2) + 0xfe051800) +#define VAD_CEP_CTRL2 ((0x0017 << 2) + 0xfe051800) +#define VAD_CEP_CTRL3 ((0x0018 << 2) + 0xfe051800) +#define VAD_CEP_CTRL4 ((0x0019 << 2) + 0xfe051800) +#define VAD_CEP_CTRL5 ((0x001a << 2) + 0xfe051800) +#define VAD_DEC_CTRL ((0x001b << 2) + 0xfe051800) +#define VAD_TOP_STS0 ((0x001c << 2) + 0xfe051800) +#define VAD_TOP_STS1 ((0x001d << 2) + 0xfe051800) +#define VAD_TOP_STS2 ((0x001e << 2) + 0xfe051800) +#define VAD_FIR_STS0 ((0x001f << 2) + 0xfe051800) +#define VAD_FIR_STS1 ((0x0020 << 2) + 0xfe051800) +#define VAD_POW_STS0 ((0x0021 << 2) + 0xfe051800) +#define VAD_POW_STS1 ((0x0022 << 2) + 0xfe051800) +#define VAD_POW_STS2 ((0x0023 << 2) + 0xfe051800) +#define VAD_FFT_STS0 ((0x0024 << 2) + 0xfe051800) +#define VAD_FFT_STS1 ((0x0025 << 2) + 0xfe051800) +#define VAD_SPE_STS0 ((0x0026 << 2) + 0xfe051800) +#define VAD_SPE_STS1 ((0x0027 << 2) + 0xfe051800) +#define VAD_SPE_STS2 ((0x0028 << 2) + 0xfe051800) +#define VAD_SPE_STS3 ((0x0029 << 2) + 0xfe051800) +#define VAD_DEC_STS0 ((0x002a << 2) + 0xfe051800) +#define VAD_DEC_STS1 ((0x002b << 2) + 0xfe051800) +#define VAD_LUT_CTRL ((0x002c << 2) + 0xfe051800) +#define VAD_LUT_WR ((0x002d << 2) + 0xfe051800) +#define VAD_LUT_RD ((0x002e << 2) + 0xfe051800) +#define VAD_IN_SEL0 ((0x002f << 2) + 0xfe051800) +#define VAD_IN_SEL1 ((0x0030 << 2) + 0xfe051800) +#define VAD_TO_DDR ((0x0031 << 2) + 0xfe051800) +// +// Closing file: VAD_REG.h +// +//======================================================================== +// AUDIO RESAMPLEA - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe051c00 +// ----------------------------------------------- +// +// Reading file: RESAMPLE.h +// +#define AUDIO_RSAMP_CTRL0 ((0x0000 << 2) + 0xfe051c00) +//Bit 31:3 reserved +//Bit 2 reg_lock_rst //unsigned , default =0; +//Bit 1 reg_rsamp_rst //unsigned , default =0; +//Bit 0 reg_sw_rst //unsigned , default =0; +#define AUDIO_RSAMP_CTRL1 ((0x0001 << 2) + 0xfe051c00) +//Bit 31:26 reserved //unsigned , default =0; +//Bit 25 reg_rsamp_rst_sel //unsigned , default =0; +//Bit 24 reg_module_bypas //unsigned , default =0; +//Bit 23:18 reg_gclk_ctrl //unsigned , default =0; +//Bit 17:13 reg_in_msb //unsigned , default =23; +//Bit 12 reg_output_en //unsigned , default =0; +//Bit 11 reg_rsamp_en //unsigned , default =0; +//Bit 10 reg_filt_en //unsigned , default =0; +//Bit 9 reg_post_en //unsigned , default =0; +//Bit 8 reg_inp_mux_mode //unsigned , default =0; +//Bit 7:4 reserved //unsigned , default =2; +//Bit 3:0 reg_inp_mux //unsigned , default =0; +#define AUDIO_RSAMP_CTRL2 ((0x0002 << 2) + 0xfe051c00) +//Bit 31:30 reserved //unsigned , default =0; +//Bit 29:24 reg_chx_size //unsigned , default =2; +//Bit 23:18 reserved //unsigned , default =0; +//Bit 17:16 reg_scl_step //unsigned , default =0; 0: 1/1 1: 1/2 2: 1/4 +//Bit 15:8 reg_filt_tap //unsigned , default =63; +//Bit 7:0 reg_intp_tap //unsigned , default =63; +#define AUDIO_RSAMP_PHSINIT ((0x0003 << 2) + 0xfe051c00) +//Bit 31:28 reserved //unsigned , default = 0; +//Bit 27:0 reg_init_phs //unsigned , default = 0; +#define AUDIO_RSAMP_PHSSTEP ((0x0004 << 2) + 0xfe051c00) +//Bit 31 reserved //unsigned , default = 0; +//Bit 30:0 reg_rsamp_step //unsigned , default = 134217728;//'h800_0000 +#define AUDIO_RSAMP_SHIFT ((0x0005 << 2) + 0xfe051c00) +//Bit 31:24 reg_rsft_iir //unsigned , default = 23; +//Bit 23:16 reg_rsft_blnd //unsigned , default = 21; +//Bit 15:8 reg_rsft_sinc //unsigned , default = 31; +//Bit 7:0 reg_rsft_aa //unsigned , default = 31; +#define AUDIO_RSAMP_ADJ_CTRL0 ((0x0006 << 2) + 0xfe051c00) +//Bit 31:3 reserved //unsigned +//Bit 2 reg_rsamp_adj_out_inv //unsigned , default = 0; +//Bit 1 reg_rsamp_adj_force_en //unsigned , default = 0; +//Bit 0 reg_rsamp_adj_en //unsigned , default = 0; +#define AUDIO_RSAMP_ADJ_CTRL1 ((0x0007 << 2) + 0xfe051c00) +//Bit 31:16 reg_rsamp_adj_odet_step //unsigned , default = 8; +//Bit 15:0 reg_rsamp_adj_kmax //unsigned , default = 32768; +#define AUDIO_RSAMP_ADJ_SFT ((0x0008 << 2) + 0xfe051c00) +//Bit 31:30 reserved //unsigned , default = 0; +//Bit 29 reg_rsamp_adj_dif_sel //unsigned , default = 0; +//Bit 28:24 reg_rsamp_adj_ki //unsigned , default = 9; +//Bit 23:21 reserved //unsigned , default = 0; +//Bit 20:16 reg_rsamp_adj_kp //unsigned , default = 1; +//Bit 15:13 reserved //unsigned , default = 0; +//Bit 12:8 reg_rsamp_adj_ki_sft //unsigned , default = 6; +//Bit 7:6 reserved //unsigned , default = 0; +//Bit 5:0 reg_rsamp_adj_out_sft //unsigned , default = 12; +#define AUDIO_RSAMP_ADJ_IDET_LEN ((0x0009 << 2) + 0xfe051c00) +//Bit 31:0 reg_rsamp_adj_idet_len //unsigned , default = 10000; +#define AUDIO_RSAMP_ADJ_FORCE ((0x000a << 2) + 0xfe051c00) +//Bit 31:0 reg_rsamp_adj_force_err //signed , default = 8; +#define AUDIO_RSAMP_ADJ_KI_FORCE ((0x000b << 2) + 0xfe051c00) +//Bit 31:0 reg_rsamp_adj_ki_force //signed , default = 0; +#define AUDIO_RSAMP_RO_STATUS ((0x0010 << 2) + 0xfe051c00) +//Bit 31:0 ro_rsamp_stat //{din_chx_chk_err,is_idle_st,rsamp_fifo_over_cnt[7:0]} +#define AUDIO_RSAMP_RO_ADJ_FREQ ((0x0011 << 2) + 0xfe051c00) +//Bit 31:0 ro_rsamp_adj_freq +#define AUDIO_RSAMP_RO_ADJ_DIFF_BAK ((0x0012 << 2) + 0xfe051c00) +//Bit 31:0 ro_det_diff_bak +#define AUDIO_RSAMP_RO_ADJ_DIFF_DLT ((0x0013 << 2) + 0xfe051c00) +//Bit 31:0 ro_det_diff_dlt +#define AUDIO_RSAMP_RO_ADJ_PHS_ERR ((0x0014 << 2) + 0xfe051c00) +//Bit 31:0 ro_det_phase_err +#define AUDIO_RSAMP_RO_ADJ_KI_OUT ((0x0015 << 2) + 0xfe051c00) +//Bit 31:0 ro_rsamp_ki_out +#define AUDIO_RSAMP_RO_IN_CNT ((0x0016 << 2) + 0xfe051c00) +//Bit 31:0 ro_rsamp_in_cnt +#define AUDIO_RSAMP_RO_OUT_CNT ((0x0017 << 2) + 0xfe051c00) +//Bit 31:0 ro_rsamp_out_cnt +#define AUDIO_RSAMP_RO_ADJ_PHS_ERR_VAR ((0x0018 << 2) + 0xfe051c00) +//Bit 31:0 ro_det_phase_err_var +#define AUDIO_RSAMP_POST_COEF0 ((0x0020 << 2) + 0xfe051c00) +//Bit 31:0 reg_post_coef0 //signed , default = 0; +#define AUDIO_RSAMP_POST_COEF1 ((0x0021 << 2) + 0xfe051c00) +//Bit 31:0 reg_post_coef1 //signed , default = 0; +#define AUDIO_RSAMP_POST_COEF2 ((0x0022 << 2) + 0xfe051c00) +//Bit 31:0 reg_post_coef2 //signed , default = 0; +#define AUDIO_RSAMP_POST_COEF3 ((0x0023 << 2) + 0xfe051c00) +//Bit 31:0 reg_post_coef3 //signed , default = 0; +#define AUDIO_RSAMP_POST_COEF4 ((0x0024 << 2) + 0xfe051c00) +//Bit 31:0 reg_post_coef4 //signed , default = 0; +#define AUDIO_RSAMP_AA_COEF_ADDR ((0x0030 << 2) + 0xfe051c00) +//Bit 31:0 reg_aa_coef_addr //unsigned, default = 0; +#define AUDIO_RSAMP_AA_COEF_DATA ((0x0031 << 2) + 0xfe051c00) +//Bit 31:0 reg_aa_coef_data //signed , default = 0; +#define AUDIO_RSAMP_SINC_COEF_ADDR ((0x0040 << 2) + 0xfe051c00) +//Bit 31:0 reg_sinc_coef_addr //unsigned, default = 0; +#define AUDIO_RSAMP_SINC_COEF_DATA ((0x0041 << 2) + 0xfe051c00) +//Bit 31:0 reg_sinc_coef_data //signed , default = 0; +// +// Closing file: RESAMPLE.h +// +//======================================================================== +// AUDIO TOP_VAD - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe054800 +// ----------------------------------------------- +#define EE_AUDIO2_CLK81_CTRL ((0x0000 << 2) + 0xfe054800) +#define EE_AUDIO2_CLK81_EN ((0x0001 << 2) + 0xfe054800) +#define EE_AUDIO2_SW_RESET0 ((0x0002 << 2) + 0xfe054800) +#define EE_AUDIO2_CLK_GATE_EN0 ((0x0003 << 2) + 0xfe054800) +#define EE_AUDIO2_SECURITY_CTRL0 ((0x0004 << 2) + 0xfe054800) +#define EE_AUDIO2_MCLK_VAD_CTRL ((0x0010 << 2) + 0xfe054800) +#define EE_AUDIO2_VAD_CLK_CTRL ((0x0011 << 2) + 0xfe054800) +#define EE_AUDIO2_MST_DLY_CTRL0 ((0x0012 << 2) + 0xfe054800) +#define EE_AUDIO2_MST_VAD_SCLK_CTRL0 ((0x0013 << 2) + 0xfe054800) +#define EE_AUDIO2_MST_VAD_SCLK_CTRL1 ((0x0014 << 2) + 0xfe054800) +#define EE_AUDIO2_CLK_TDMIN_VAD_CTRL ((0x0015 << 2) + 0xfe054800) +#define EE_AUDIO2_CLK_PDMIN_CTRL0 ((0x0016 << 2) + 0xfe054800) +#define EE_AUDIO2_CLK_PDMIN_CTRL1 ((0x0017 << 2) + 0xfe054800) +#define EE_AUDIO2_TOVAD_CTRL0 ((0x0020 << 2) + 0xfe054800) +#define EE_AUDIO2_TODDR_VAD_CTRL0 ((0x0030 << 2) + 0xfe054800) +#define EE_AUDIO2_TODDR_VAD_CTRL1 ((0x0031 << 2) + 0xfe054800) +#define EE_AUDIO2_TODDR_VAD_CTRL2 ((0x0032 << 2) + 0xfe054800) +#define EE_AUDIO2_TODDR_VAD_START_ADDR ((0x0033 << 2) + 0xfe054800) +#define EE_AUDIO2_TODDR_VAD_INIT_ADDR ((0x0034 << 2) + 0xfe054800) +#define EE_AUDIO2_TODDR_VAD_FINISH_ADDR ((0x0035 << 2) + 0xfe054800) +#define EE_AUDIO2_TODDR_VAD_START_ADDRB ((0x0036 << 2) + 0xfe054800) +#define EE_AUDIO2_TODDR_VAD_FINISH_ADDRB ((0x0037 << 2) + 0xfe054800) +#define EE_AUDIO2_TODDR_VAD_INT_ADDR ((0x0038 << 2) + 0xfe054800) +#define EE_AUDIO2_TODDR_VAD_STATUS1 ((0x0039 << 2) + 0xfe054800) +#define EE_AUDIO2_TODDR_VAD_STATUS2 ((0x003a << 2) + 0xfe054800) +#define EE_AUDIO2_TDMIN_VAD_CTRL ((0x0040 << 2) + 0xfe054800) +#define EE_AUDIO2_TDMIN_VAD_SWAP0 ((0x0041 << 2) + 0xfe054800) +#define EE_AUDIO2_TDMIN_VAD_SWAP1 ((0x0042 << 2) + 0xfe054800) +#define EE_AUDIO2_TDMIN_VAD_MUTE_VAL ((0x0043 << 2) + 0xfe054800) +#define EE_AUDIO2_TDMIN_VAD_STAT ((0x0044 << 2) + 0xfe054800) +#define EE_AUDIO2_TDMIN_VAD_MUTE0 ((0x0050 << 2) + 0xfe054800) +#define EE_AUDIO2_TDMIN_VAD_MUTE1 ((0x0051 << 2) + 0xfe054800)